All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances
@ 2020-07-21  9:01 Jiansong Chen
  2020-07-21  9:20 ` Zhou1, Tao
  2020-07-21  9:53 ` 答复: " Gao, Likun
  0 siblings, 2 replies; 3+ messages in thread
From: Jiansong Chen @ 2020-07-21  9:01 UTC (permalink / raw)
  To: amd-gfx; +Cc: Tao.Zhou1, kenneth.feng, Jiansong Chen

To accommodate VCN instances variance, otherwise it may trigger
smu response error for configuration with less instances.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Change-Id: I0bfe31f1f5638d539ac6ded3bffee8f57574bafa
---
 .../drm/amd/powerplay/sienna_cichlid_ppt.c    | 68 +++++++++++--------
 1 file changed, 38 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 87eedd7c28ec..c8b59a891f5d 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -525,6 +525,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 	struct smu_11_0_dpm_table *dpm_table;
+	struct amdgpu_device *adev = smu->adev;
 	int ret = 0;
 
 	/* socclk dpm table setup */
@@ -617,22 +618,26 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		dpm_table->max = dpm_table->dpm_levels[0].value;
 	}
 
+
 	/* vclk1 dpm table setup */
-	dpm_table = &dpm_context->dpm_tables.vclk1_table;
-	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
-		ret = smu_v11_0_set_single_dpm_table(smu,
-						     SMU_VCLK1,
-						     dpm_table);
-		if (ret)
-			return ret;
-		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
-	} else {
-		dpm_table->count = 1;
-		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
-		dpm_table->dpm_levels[0].enabled = true;
-		dpm_table->min = dpm_table->dpm_levels[0].value;
-		dpm_table->max = dpm_table->dpm_levels[0].value;
+	if (adev->vcn.num_vcn_inst > 1) {
+		dpm_table = &dpm_context->dpm_tables.vclk1_table;
+		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+			ret = smu_v11_0_set_single_dpm_table(smu,
+							     SMU_VCLK1,
+							     dpm_table);
+			if (ret)
+				return ret;
+			dpm_table->is_fine_grained =
+				!driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
+		} else {
+			dpm_table->count = 1;
+			dpm_table->dpm_levels[0].value =
+				smu->smu_table.boot_values.vclk / 100;
+			dpm_table->dpm_levels[0].enabled = true;
+			dpm_table->min = dpm_table->dpm_levels[0].value;
+			dpm_table->max = dpm_table->dpm_levels[0].value;
+		}
 	}
 
 	/* dclk0 dpm table setup */
@@ -654,21 +659,24 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 	}
 
 	/* dclk1 dpm table setup */
-	dpm_table = &dpm_context->dpm_tables.dclk1_table;
-	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
-		ret = smu_v11_0_set_single_dpm_table(smu,
-						     SMU_DCLK1,
-						     dpm_table);
-		if (ret)
-			return ret;
-		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
-	} else {
-		dpm_table->count = 1;
-		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
-		dpm_table->dpm_levels[0].enabled = true;
-		dpm_table->min = dpm_table->dpm_levels[0].value;
-		dpm_table->max = dpm_table->dpm_levels[0].value;
+	if (adev->vcn.num_vcn_inst > 1) {
+		dpm_table = &dpm_context->dpm_tables.dclk1_table;
+		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+			ret = smu_v11_0_set_single_dpm_table(smu,
+							     SMU_DCLK1,
+							     dpm_table);
+			if (ret)
+				return ret;
+			dpm_table->is_fine_grained =
+				!driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
+		} else {
+			dpm_table->count = 1;
+			dpm_table->dpm_levels[0].value =
+				smu->smu_table.boot_values.dclk / 100;
+			dpm_table->dpm_levels[0].enabled = true;
+			dpm_table->min = dpm_table->dpm_levels[0].value;
+			dpm_table->max = dpm_table->dpm_levels[0].value;
+		}
 	}
 
 	/* dcefclk dpm table setup */
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* RE: [PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances
  2020-07-21  9:01 [PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances Jiansong Chen
@ 2020-07-21  9:20 ` Zhou1, Tao
  2020-07-21  9:53 ` 答复: " Gao, Likun
  1 sibling, 0 replies; 3+ messages in thread
From: Zhou1, Tao @ 2020-07-21  9:20 UTC (permalink / raw)
  To: Chen, Jiansong (Simon), amd-gfx; +Cc: Feng, Kenneth, Chen, Jiansong (Simon)

[AMD Official Use Only - Internal Distribution Only]

With my comment below fixed, the patch is:

Reviewed-by: Tao Zhou <tao.zhou1@amd.com>

-----Original Message-----
From: Jiansong Chen <Jiansong.Chen@amd.com>
Sent: Tuesday, July 21, 2020 5:01 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Chen, Jiansong (Simon) <Jiansong.Chen@amd.com>
Subject: [PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances

To accommodate VCN instances variance, otherwise it may trigger smu response error for configuration with less instances.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Change-Id: I0bfe31f1f5638d539ac6ded3bffee8f57574bafa
---
 .../drm/amd/powerplay/sienna_cichlid_ppt.c    | 68 +++++++++++--------
 1 file changed, 38 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 87eedd7c28ec..c8b59a891f5d 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -525,6 +525,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 struct smu_11_0_dpm_table *dpm_table;
+struct amdgpu_device *adev = smu->adev;
 int ret = 0;

 /* socclk dpm table setup */
@@ -617,22 +618,26 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 dpm_table->max = dpm_table->dpm_levels[0].value;
 }

+
[Tao]: Please remove the redundant line.

 /* vclk1 dpm table setup */
-dpm_table = &dpm_context->dpm_tables.vclk1_table;
-if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
-ret = smu_v11_0_set_single_dpm_table(smu,
-     SMU_VCLK1,
-     dpm_table);
-if (ret)
-return ret;
-dpm_table->is_fine_grained =
-!driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
-} else {
-dpm_table->count = 1;
-dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
-dpm_table->dpm_levels[0].enabled = true;
-dpm_table->min = dpm_table->dpm_levels[0].value;
-dpm_table->max = dpm_table->dpm_levels[0].value;
+if (adev->vcn.num_vcn_inst > 1) {
+dpm_table = &dpm_context->dpm_tables.vclk1_table;
+if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ret = smu_v11_0_set_single_dpm_table(smu,
+     SMU_VCLK1,
+     dpm_table);
+if (ret)
+return ret;
+dpm_table->is_fine_grained =
+!driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
+} else {
+dpm_table->count = 1;
+dpm_table->dpm_levels[0].value =
+smu->smu_table.boot_values.vclk / 100;
+dpm_table->dpm_levels[0].enabled = true;
+dpm_table->min = dpm_table->dpm_levels[0].value;
+dpm_table->max = dpm_table->dpm_levels[0].value;
+}
 }

 /* dclk0 dpm table setup */
@@ -654,21 +659,24 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 }

 /* dclk1 dpm table setup */
-dpm_table = &dpm_context->dpm_tables.dclk1_table;
-if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
-ret = smu_v11_0_set_single_dpm_table(smu,
-     SMU_DCLK1,
-     dpm_table);
-if (ret)
-return ret;
-dpm_table->is_fine_grained =
-!driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
-} else {
-dpm_table->count = 1;
-dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
-dpm_table->dpm_levels[0].enabled = true;
-dpm_table->min = dpm_table->dpm_levels[0].value;
-dpm_table->max = dpm_table->dpm_levels[0].value;
+if (adev->vcn.num_vcn_inst > 1) {
+dpm_table = &dpm_context->dpm_tables.dclk1_table;
+if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ret = smu_v11_0_set_single_dpm_table(smu,
+     SMU_DCLK1,
+     dpm_table);
+if (ret)
+return ret;
+dpm_table->is_fine_grained =
+!driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
+} else {
+dpm_table->count = 1;
+dpm_table->dpm_levels[0].value =
+smu->smu_table.boot_values.dclk / 100;
+dpm_table->dpm_levels[0].enabled = true;
+dpm_table->min = dpm_table->dpm_levels[0].value;
+dpm_table->max = dpm_table->dpm_levels[0].value;
+}
 }

 /* dcefclk dpm table setup */
--
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
* 答复: [PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances
  2020-07-21  9:01 [PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances Jiansong Chen
  2020-07-21  9:20 ` Zhou1, Tao
@ 2020-07-21  9:53 ` Gao, Likun
  1 sibling, 0 replies; 3+ messages in thread
From: Gao, Likun @ 2020-07-21  9:53 UTC (permalink / raw)
  To: Chen, Jiansong (Simon), amd-gfx
  Cc: Zhou1, Tao, Feng, Kenneth, Chen, Jiansong (Simon)

Reviewed-by: Likun Gao <Likun.Gao@amd.com>

Regards,
Likun

-----邮件原件-----
发件人: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] 代表 Jiansong Chen
发送时间: 2020年7月21日 17:01
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhou1, Tao <Tao.Zhou1@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Chen, Jiansong (Simon) <Jiansong.Chen@amd.com>
主题: [PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances

To accommodate VCN instances variance, otherwise it may trigger smu response error for configuration with less instances.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Change-Id: I0bfe31f1f5638d539ac6ded3bffee8f57574bafa
---
 .../drm/amd/powerplay/sienna_cichlid_ppt.c    | 68 +++++++++++--------
 1 file changed, 38 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 87eedd7c28ec..c8b59a891f5d 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -525,6 +525,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 	struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 	PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 	struct smu_11_0_dpm_table *dpm_table;
+	struct amdgpu_device *adev = smu->adev;
 	int ret = 0;
 
 	/* socclk dpm table setup */
@@ -617,22 +618,26 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 		dpm_table->max = dpm_table->dpm_levels[0].value;
 	}
 
+
 	/* vclk1 dpm table setup */
-	dpm_table = &dpm_context->dpm_tables.vclk1_table;
-	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
-		ret = smu_v11_0_set_single_dpm_table(smu,
-						     SMU_VCLK1,
-						     dpm_table);
-		if (ret)
-			return ret;
-		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
-	} else {
-		dpm_table->count = 1;
-		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
-		dpm_table->dpm_levels[0].enabled = true;
-		dpm_table->min = dpm_table->dpm_levels[0].value;
-		dpm_table->max = dpm_table->dpm_levels[0].value;
+	if (adev->vcn.num_vcn_inst > 1) {
+		dpm_table = &dpm_context->dpm_tables.vclk1_table;
+		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+			ret = smu_v11_0_set_single_dpm_table(smu,
+							     SMU_VCLK1,
+							     dpm_table);
+			if (ret)
+				return ret;
+			dpm_table->is_fine_grained =
+				!driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
+		} else {
+			dpm_table->count = 1;
+			dpm_table->dpm_levels[0].value =
+				smu->smu_table.boot_values.vclk / 100;
+			dpm_table->dpm_levels[0].enabled = true;
+			dpm_table->min = dpm_table->dpm_levels[0].value;
+			dpm_table->max = dpm_table->dpm_levels[0].value;
+		}
 	}
 
 	/* dclk0 dpm table setup */
@@ -654,21 +659,24 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 	}
 
 	/* dclk1 dpm table setup */
-	dpm_table = &dpm_context->dpm_tables.dclk1_table;
-	if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
-		ret = smu_v11_0_set_single_dpm_table(smu,
-						     SMU_DCLK1,
-						     dpm_table);
-		if (ret)
-			return ret;
-		dpm_table->is_fine_grained =
-			!driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
-	} else {
-		dpm_table->count = 1;
-		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
-		dpm_table->dpm_levels[0].enabled = true;
-		dpm_table->min = dpm_table->dpm_levels[0].value;
-		dpm_table->max = dpm_table->dpm_levels[0].value;
+	if (adev->vcn.num_vcn_inst > 1) {
+		dpm_table = &dpm_context->dpm_tables.dclk1_table;
+		if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+			ret = smu_v11_0_set_single_dpm_table(smu,
+							     SMU_DCLK1,
+							     dpm_table);
+			if (ret)
+				return ret;
+			dpm_table->is_fine_grained =
+				!driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
+		} else {
+			dpm_table->count = 1;
+			dpm_table->dpm_levels[0].value =
+				smu->smu_table.boot_values.dclk / 100;
+			dpm_table->dpm_levels[0].enabled = true;
+			dpm_table->min = dpm_table->dpm_levels[0].value;
+			dpm_table->max = dpm_table->dpm_levels[0].value;
+		}
 	}
 
 	/* dcefclk dpm table setup */
--
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CLikun.Gao%40amd.com%7C3098db7d34c94cebb00608d82d54a738%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637309188916488516&amp;sdata=ECS0UJfx5CCWln%2FG4kec7BeoE3Q3WVUBlq5GVq1q1co%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-07-21  9:53 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-07-21  9:01 [PATCH] drm/amd/powerplay: retrieve VCN dpm table per instances Jiansong Chen
2020-07-21  9:20 ` Zhou1, Tao
2020-07-21  9:53 ` 答复: " Gao, Likun

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.