* [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
@ 2021-02-15 11:43 Christian König
2021-02-15 11:44 ` Christian König
0 siblings, 1 reply; 5+ messages in thread
From: Christian König @ 2021-02-15 11:43 UTC (permalink / raw)
To: amd-gfx, shashank.sharma
From: Shashank Sharma <shashank.sharma@amd.com>
This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input
parameter flag, during object creation of an imported DMA
buffer.
In absence of this flag:
1. Function amdgpu_display_supported_domains() doesn't add
AMDGPU_GEM_DOMAIN_GTT as supported domain.
2. Due to which, Function amdgpu_display_user_framebuffer_create()
refuses to create framebuffer for imported DMA buffers.
3. Due to which, AddFB() IOCTL fails.
4. Due to which, amdgpu_present_check_flip() check fails in DDX
5. Due to which DDX driver doesn't allow flips (goes to blitting)
6. Due to which setting Freesync/VRR property fails for PRIME buffers.
So, this patch finally enables Freesync with PRIME buffer offloading.
v2 (chk): instead of just checking the flag we copy it over if the
exporter is an amdgpu device as well.
Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
index d3727f3ab277..a54a870f006c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
@@ -422,14 +422,22 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
{
struct dma_resv *resv = dma_buf->resv;
struct amdgpu_device *adev = drm_to_adev(dev);
- struct amdgpu_bo *bo;
struct drm_gem_object *gobj;
+ struct amdgpu_bo *bo;
+ uint64_t flags = 0;
int ret;
dma_resv_lock(resv, NULL);
+
+ if (dma_buf->ops == &amdgpu_dmabuf_ops) {
+ struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
+
+ flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
+ }
+
ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_CPU,
- 0, ttm_bo_type_sg, resv, &gobj);
+ AMDGPU_GEM_DOMAIN_CPU, flags,
+ ttm_bo_type_sg, resv, &gobj);
if (ret)
goto error;
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
2021-02-15 11:43 [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2 Christian König
@ 2021-02-15 11:44 ` Christian König
2021-02-15 11:45 ` Sharma, Shashank
2021-02-15 12:27 ` Sharma, Shashank
0 siblings, 2 replies; 5+ messages in thread
From: Christian König @ 2021-02-15 11:44 UTC (permalink / raw)
To: amd-gfx, shashank.sharma
Hi Shashank,
can you give this patch a test round? In theory it should work, but I'm
not 100% sure.
Thanks,
Christian.
Am 15.02.21 um 12:43 schrieb Christian König:
> From: Shashank Sharma <shashank.sharma@amd.com>
>
> This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input
> parameter flag, during object creation of an imported DMA
> buffer.
>
> In absence of this flag:
> 1. Function amdgpu_display_supported_domains() doesn't add
> AMDGPU_GEM_DOMAIN_GTT as supported domain.
> 2. Due to which, Function amdgpu_display_user_framebuffer_create()
> refuses to create framebuffer for imported DMA buffers.
> 3. Due to which, AddFB() IOCTL fails.
> 4. Due to which, amdgpu_present_check_flip() check fails in DDX
> 5. Due to which DDX driver doesn't allow flips (goes to blitting)
> 6. Due to which setting Freesync/VRR property fails for PRIME buffers.
>
> So, this patch finally enables Freesync with PRIME buffer offloading.
>
> v2 (chk): instead of just checking the flag we copy it over if the
> exporter is an amdgpu device as well.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> index d3727f3ab277..a54a870f006c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> @@ -422,14 +422,22 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
> {
> struct dma_resv *resv = dma_buf->resv;
> struct amdgpu_device *adev = drm_to_adev(dev);
> - struct amdgpu_bo *bo;
> struct drm_gem_object *gobj;
> + struct amdgpu_bo *bo;
> + uint64_t flags = 0;
> int ret;
>
> dma_resv_lock(resv, NULL);
> +
> + if (dma_buf->ops == &amdgpu_dmabuf_ops) {
> + struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
> +
> + flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> + }
> +
> ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_CPU,
> - 0, ttm_bo_type_sg, resv, &gobj);
> + AMDGPU_GEM_DOMAIN_CPU, flags,
> + ttm_bo_type_sg, resv, &gobj);
> if (ret)
> goto error;
>
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
2021-02-15 11:44 ` Christian König
@ 2021-02-15 11:45 ` Sharma, Shashank
2021-02-15 12:27 ` Sharma, Shashank
1 sibling, 0 replies; 5+ messages in thread
From: Sharma, Shashank @ 2021-02-15 11:45 UTC (permalink / raw)
To: Christian König, amd-gfx
[AMD Official Use Only - Internal Distribution Only]
Sure, let me try this out,
Regards
Shashank
-----Original Message-----
From: Christian König <ckoenig.leichtzumerken@gmail.com>
Sent: Monday, February 15, 2021 5:15 PM
To: amd-gfx@lists.freedesktop.org; Sharma, Shashank <Shashank.Sharma@amd.com>
Subject: Re: [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
Hi Shashank,
can you give this patch a test round? In theory it should work, but I'm not 100% sure.
Thanks,
Christian.
Am 15.02.21 um 12:43 schrieb Christian König:
> From: Shashank Sharma <shashank.sharma@amd.com>
>
> This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input parameter
> flag, during object creation of an imported DMA buffer.
>
> In absence of this flag:
> 1. Function amdgpu_display_supported_domains() doesn't add
> AMDGPU_GEM_DOMAIN_GTT as supported domain.
> 2. Due to which, Function amdgpu_display_user_framebuffer_create()
> refuses to create framebuffer for imported DMA buffers.
> 3. Due to which, AddFB() IOCTL fails.
> 4. Due to which, amdgpu_present_check_flip() check fails in DDX 5. Due
> to which DDX driver doesn't allow flips (goes to blitting) 6. Due to
> which setting Freesync/VRR property fails for PRIME buffers.
>
> So, this patch finally enables Freesync with PRIME buffer offloading.
>
> v2 (chk): instead of just checking the flag we copy it over if the
> exporter is an amdgpu device as well.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> index d3727f3ab277..a54a870f006c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> @@ -422,14 +422,22 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
> {
> struct dma_resv *resv = dma_buf->resv;
> struct amdgpu_device *adev = drm_to_adev(dev);
> - struct amdgpu_bo *bo;
> struct drm_gem_object *gobj;
> + struct amdgpu_bo *bo;
> + uint64_t flags = 0;
> int ret;
>
> dma_resv_lock(resv, NULL);
> +
> + if (dma_buf->ops == &amdgpu_dmabuf_ops) {
> + struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
> +
> + flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> + }
> +
> ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_CPU,
> - 0, ttm_bo_type_sg, resv, &gobj);
> + AMDGPU_GEM_DOMAIN_CPU, flags,
> + ttm_bo_type_sg, resv, &gobj);
> if (ret)
> goto error;
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
2021-02-15 11:44 ` Christian König
2021-02-15 11:45 ` Sharma, Shashank
@ 2021-02-15 12:27 ` Sharma, Shashank
2021-02-15 13:32 ` Christian König
1 sibling, 1 reply; 5+ messages in thread
From: Sharma, Shashank @ 2021-02-15 12:27 UTC (permalink / raw)
To: Christian König, amd-gfx
[AMD Official Use Only - Internal Distribution Only]
Hello Christian,
I just tested the patch with Xonotic + PRIME,
I confirm that its working same as previous version, for the Freesync scenario, ie:
- With this patch, display framebuffer creation is successful, flips are coming and VRR property is getting set.
Did some negative testing also,
- Without this patch, Fremebuffer creation fails, no flips, and VRR property doesn't set.
Regards
Shashank
-----Original Message-----
From: Christian König <ckoenig.leichtzumerken@gmail.com>
Sent: Monday, February 15, 2021 5:15 PM
To: amd-gfx@lists.freedesktop.org; Sharma, Shashank <Shashank.Sharma@amd.com>
Subject: Re: [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
Hi Shashank,
can you give this patch a test round? In theory it should work, but I'm not 100% sure.
Thanks,
Christian.
Am 15.02.21 um 12:43 schrieb Christian König:
> From: Shashank Sharma <shashank.sharma@amd.com>
>
> This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input parameter
> flag, during object creation of an imported DMA buffer.
>
> In absence of this flag:
> 1. Function amdgpu_display_supported_domains() doesn't add
> AMDGPU_GEM_DOMAIN_GTT as supported domain.
> 2. Due to which, Function amdgpu_display_user_framebuffer_create()
> refuses to create framebuffer for imported DMA buffers.
> 3. Due to which, AddFB() IOCTL fails.
> 4. Due to which, amdgpu_present_check_flip() check fails in DDX 5. Due
> to which DDX driver doesn't allow flips (goes to blitting) 6. Due to
> which setting Freesync/VRR property fails for PRIME buffers.
>
> So, this patch finally enables Freesync with PRIME buffer offloading.
>
> v2 (chk): instead of just checking the flag we copy it over if the
> exporter is an amdgpu device as well.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +++++++++++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> index d3727f3ab277..a54a870f006c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
> @@ -422,14 +422,22 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
> {
> struct dma_resv *resv = dma_buf->resv;
> struct amdgpu_device *adev = drm_to_adev(dev);
> - struct amdgpu_bo *bo;
> struct drm_gem_object *gobj;
> + struct amdgpu_bo *bo;
> + uint64_t flags = 0;
> int ret;
>
> dma_resv_lock(resv, NULL);
> +
> + if (dma_buf->ops == &amdgpu_dmabuf_ops) {
> + struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
> +
> + flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> + }
> +
> ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_CPU,
> - 0, ttm_bo_type_sg, resv, &gobj);
> + AMDGPU_GEM_DOMAIN_CPU, flags,
> + ttm_bo_type_sg, resv, &gobj);
> if (ret)
> goto error;
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
2021-02-15 12:27 ` Sharma, Shashank
@ 2021-02-15 13:32 ` Christian König
0 siblings, 0 replies; 5+ messages in thread
From: Christian König @ 2021-02-15 13:32 UTC (permalink / raw)
To: Sharma, Shashank, amd-gfx, Alex Deucher
Thanks Shashank,
Alex when do we plan the next rebase?
This also depends on upstream code and can't be merged in
amd-staging-drm-next directly.
Regards,
Christian.
Am 15.02.21 um 13:27 schrieb Sharma, Shashank:
> [AMD Official Use Only - Internal Distribution Only]
>
> Hello Christian,
> I just tested the patch with Xonotic + PRIME,
>
> I confirm that its working same as previous version, for the Freesync scenario, ie:
> - With this patch, display framebuffer creation is successful, flips are coming and VRR property is getting set.
>
> Did some negative testing also,
> - Without this patch, Fremebuffer creation fails, no flips, and VRR property doesn't set.
>
> Regards
> Shashank
> -----Original Message-----
> From: Christian König <ckoenig.leichtzumerken@gmail.com>
> Sent: Monday, February 15, 2021 5:15 PM
> To: amd-gfx@lists.freedesktop.org; Sharma, Shashank <Shashank.Sharma@amd.com>
> Subject: Re: [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2
>
> Hi Shashank,
>
> can you give this patch a test round? In theory it should work, but I'm not 100% sure.
>
> Thanks,
> Christian.
>
> Am 15.02.21 um 12:43 schrieb Christian König:
>> From: Shashank Sharma <shashank.sharma@amd.com>
>>
>> This patch sets 'AMDGPU_GEM_CREATE_CPU_GTT_USWC' as input parameter
>> flag, during object creation of an imported DMA buffer.
>>
>> In absence of this flag:
>> 1. Function amdgpu_display_supported_domains() doesn't add
>> AMDGPU_GEM_DOMAIN_GTT as supported domain.
>> 2. Due to which, Function amdgpu_display_user_framebuffer_create()
>> refuses to create framebuffer for imported DMA buffers.
>> 3. Due to which, AddFB() IOCTL fails.
>> 4. Due to which, amdgpu_present_check_flip() check fails in DDX 5. Due
>> to which DDX driver doesn't allow flips (goes to blitting) 6. Due to
>> which setting Freesync/VRR property fails for PRIME buffers.
>>
>> So, this patch finally enables Freesync with PRIME buffer offloading.
>>
>> v2 (chk): instead of just checking the flag we copy it over if the
>> exporter is an amdgpu device as well.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 14 +++++++++++---
>> 1 file changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>> index d3727f3ab277..a54a870f006c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
>> @@ -422,14 +422,22 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
>> {
>> struct dma_resv *resv = dma_buf->resv;
>> struct amdgpu_device *adev = drm_to_adev(dev);
>> - struct amdgpu_bo *bo;
>> struct drm_gem_object *gobj;
>> + struct amdgpu_bo *bo;
>> + uint64_t flags = 0;
>> int ret;
>>
>> dma_resv_lock(resv, NULL);
>> +
>> + if (dma_buf->ops == &amdgpu_dmabuf_ops) {
>> + struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
>> +
>> + flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>> + }
>> +
>> ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
>> - AMDGPU_GEM_DOMAIN_CPU,
>> - 0, ttm_bo_type_sg, resv, &gobj);
>> + AMDGPU_GEM_DOMAIN_CPU, flags,
>> + ttm_bo_type_sg, resv, &gobj);
>> if (ret)
>> goto error;
>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-02-15 13:32 UTC | newest]
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2021-02-15 11:43 [PATCH] drm/amdgpu: Set GTT_USWC flag to enable freesync v2 Christian König
2021-02-15 11:44 ` Christian König
2021-02-15 11:45 ` Sharma, Shashank
2021-02-15 12:27 ` Sharma, Shashank
2021-02-15 13:32 ` Christian König
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