[PATCH] drm/amd/pm: Enable gfx DCS feature

[PATCH] drm/amd/pm: Enable gfx DCS feature

[Kenneth Feng]

Background:
Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
When the current/power/temperature exceeds the limit with the heavy workload,
the gfx core can be shut off and powered on back and forth.
The ON time and OFF time is determined by the firmware according to
the accumulated power credits.
This feature is different from gfxoff.Gfxoff is applied in the idle case
and DCS is applied in the case with heavey workload.There are two types of DCS:
Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D fullscreen
and VR workload.
Since we only supports Async DCS now,disalbe DCS when the 3D fullscreen or
the VR workload type is chosen.

Verification:
The power is lowerer or the perf/watt is increased in the throttling case.
To be simplified, the entry/exit counter can be observed from the firmware.

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
---
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 24f3c96a5e5e..436d94cbb166 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 	}
 
+	if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == CHIP_DIMGREY_CAVEFISH)
+		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
+
 	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 		*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 					| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
@@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
 	smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
 				    1 << workload_type, NULL);
 
+	/* have to disable dcs if it's the 3D fullscreen or VR workload type */
+	if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
+		smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
+		ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
+			WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
+		if (ret)
+			return ret;
+	}
+
 	return ret;
 }
 
-- 
2.17.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Zhou1, Tao]

[AMD Public Use]



> -----Original Message-----
> From: Kenneth Feng <kenneth.feng@amd.com>
> Sent: Wednesday, January 27, 2021 9:42 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Feng, Kenneth
> <Kenneth.Feng@amd.com>
> Subject: [PATCH] drm/amd/pm: Enable gfx DCS feature
> 
> Background:
> Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> When the current/power/temperature exceeds the limit with the heavy
> workload, the gfx core can be shut off and powered on back and forth.
> The ON time and OFF time is determined by the firmware according to the
> accumulated power credits.
> This feature is different from gfxoff.Gfxoff is applied in the idle case and DCS is
> applied in the case with heavey workload.There are two types of DCS:
> Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D fullscreen
> and VR workload.
> Since we only supports Async DCS now,disalbe DCS when the 3D fullscreen or
> the VR workload type is chosen.
> 
> Verification:
> The power is lowerer or the perf/watt is increased in the throttling case.
> To be simplified, the entry/exit counter can be observed from the firmware.
> 
> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> ---
>  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 24f3c96a5e5e..436d94cbb166 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct
> smu_context *smu,
>  		*(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
>  	}
> 
> +	if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type ==
> CHIP_DIMGREY_CAVEFISH)

[Tao]: So DCS is unsupported on SIENNA_CICHLID currently?

> +		*(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> +
>  	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
>  		*(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>  					|
> FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> @@ -1437,6 +1440,15 @@ static int
> sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
>  	smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetWorkloadMask,
>  				    1 << workload_type, NULL);
> 
> +	/* have to disable dcs if it's the 3D fullscreen or VR workload type */
> +	if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> +		smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {

[Tao]: Tab should be replaced with space here.

> +		ret = smu_cmn_feature_set_enabled(smu,
> SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> +			WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT ||
> workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	return ret;
>  }
> 
> --
> 2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Zhang, Hawking]

[AMD Public Use]

+	if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == CHIP_DIMGREY_CAVEFISH)

We shall consider merge the logic to adev->asic_type > CHIP_ SIENNA_CICHLID. I think it is also supported in SIENNA_CICHLID, right? So we haven't verified on SIENNA_CICHLID yet?

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhou1, Tao
Sent: Wednesday, January 27, 2021 12:15
To: Feng, Kenneth <Kenneth.Feng@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth <Kenneth.Feng@amd.com>
Subject: RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[AMD Public Use]



> -----Original Message-----
> From: Kenneth Feng <kenneth.feng@amd.com>
> Sent: Wednesday, January 27, 2021 9:42 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Feng, Kenneth 
> <Kenneth.Feng@amd.com>
> Subject: [PATCH] drm/amd/pm: Enable gfx DCS feature
> 
> Background:
> Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> When the current/power/temperature exceeds the limit with the heavy 
> workload, the gfx core can be shut off and powered on back and forth.
> The ON time and OFF time is determined by the firmware according to 
> the accumulated power credits.
> This feature is different from gfxoff.Gfxoff is applied in the idle 
> case and DCS is applied in the case with heavey workload.There are two types of DCS:
> Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D 
> fullscreen and VR workload.
> Since we only supports Async DCS now,disalbe DCS when the 3D 
> fullscreen or the VR workload type is chosen.
> 
> Verification:
> The power is lowerer or the perf/watt is increased in the throttling case.
> To be simplified, the entry/exit counter can be observed from the firmware.
> 
> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> ---
>  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
> ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 24f3c96a5e5e..436d94cbb166 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct
> smu_context *smu,
>  		*(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
>  	}
> 
> +	if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type ==
> CHIP_DIMGREY_CAVEFISH)

[Tao]: So DCS is unsupported on SIENNA_CICHLID currently?

> +		*(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> +
>  	if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
>  		*(uint64_t *)feature_mask |=
> FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>  					|
> FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> @@ -1437,6 +1440,15 @@ static int
> sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
>  	smu_cmn_send_smc_msg_with_param(smu,
> SMU_MSG_SetWorkloadMask,
>  				    1 << workload_type, NULL);
> 
> +	/* have to disable dcs if it's the 3D fullscreen or VR workload type */
> +	if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> +		smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {

[Tao]: Tab should be replaced with space here.

> +		ret = smu_cmn_feature_set_enabled(smu,
> SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> +			WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT ||
> workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> +		if (ret)
> +			return ret;
> +	}
> +
>  	return ret;
>  }
> 
> --
> 2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Chawking.zhang%40amd.com%7Cebc62214ec3d4a52ea6e08d8c27a2956%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637473177242163482%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=imvlk8AvH7ttaSnLksU0exYYWxyOGh5sXwl%2FcLm7Afg%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Alex Deucher]

On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng <kenneth.feng@amd.com> wrote:
>
> Background:
> Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> When the current/power/temperature exceeds the limit with the heavy workload,
> the gfx core can be shut off and powered on back and forth.
> The ON time and OFF time is determined by the firmware according to
> the accumulated power credits.
> This feature is different from gfxoff.Gfxoff is applied in the idle case
> and DCS is applied in the case with heavey workload.There are two types of DCS:
> Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D fullscreen
> and VR workload.
> Since we only supports Async DCS now,disalbe DCS when the 3D fullscreen or
> the VR workload type is chosen.
>
> Verification:
> The power is lowerer or the perf/watt is increased in the throttling case.
> To be simplified, the entry/exit counter can be observed from the firmware.
>
> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> ---
>  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 24f3c96a5e5e..436d94cbb166 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
>                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
>         }
>
> +       if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == CHIP_DIMGREY_CAVEFISH)
> +               *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> +
>         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
>                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> @@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
>         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
>                                     1 << workload_type, NULL);
>
> +       /* have to disable dcs if it's the 3D fullscreen or VR workload type */
> +       if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> +               smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> +               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> +                       WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> +               if (ret)
> +                       return ret;
> +       }
> +

Since we don't support FA DCS yet, should we just drop this hunk for
now?  I think the workload profile stuff should be independent of FA
DCS.  Also so we want to add a ppfeaturemask flag to easily allow us
to disable this at driver load time?

Alex


>         return ret;
>  }
>
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
Actually the FA DCS is dependent on the workload type.
FA DCS is applied only when there's 3D fullscreen workload or VR workload.
So we need to disable it if there's a request from the sysfs/user to set the workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
By removing this hunk is ok functionally, but the DCS will never kick in though the DCS is enabled. That might be a little bit confusing.
Thanks.
 


-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com> 
Sent: Wednesday, January 27, 2021 12:55 PM
To: Feng, Kenneth <Kenneth.Feng@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhou1, Tao <Tao.Zhou1@amd.com>
Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

[CAUTION: External Email]

On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng <kenneth.feng@amd.com> wrote:
>
> Background:
> Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> When the current/power/temperature exceeds the limit with the heavy 
> workload, the gfx core can be shut off and powered on back and forth.
> The ON time and OFF time is determined by the firmware according to 
> the accumulated power credits.
> This feature is different from gfxoff.Gfxoff is applied in the idle 
> case and DCS is applied in the case with heavey workload.There are two types of DCS:
> Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D 
> fullscreen and VR workload.
> Since we only supports Async DCS now,disalbe DCS when the 3D 
> fullscreen or the VR workload type is chosen.
>
> Verification:
> The power is lowerer or the perf/watt is increased in the throttling case.
> To be simplified, the entry/exit counter can be observed from the firmware.
>
> Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> ---
>  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
> ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 24f3c96a5e5e..436d94cbb166 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
>                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
>         }
>
> +       if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == CHIP_DIMGREY_CAVEFISH)
> +               *(uint64_t *)feature_mask |= 
> + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> +
>         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
>                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
>                                         | 
> FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> @@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
>         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
>                                     1 << workload_type, NULL);
>
> +       /* have to disable dcs if it's the 3D fullscreen or VR workload type */
> +       if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> +               smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> +               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> +                       WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> +               if (ret)
> +                       return ret;
> +       }
> +

Since we don't support FA DCS yet, should we just drop this hunk for now?  I think the workload profile stuff should be independent of FA DCS.  Also so we want to add a ppfeaturemask flag to easily allow us to disable this at driver load time?

Alex


>         return ret;
>  }
>
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cke
> nneth.feng%40amd.com%7C2f961319cdd141723c1808d8c27fb554%7C3dd8961fe488
> 4e608e11a82d994e183d%7C0%7C0%7C637473201048667755%7CUnknown%7CTWFpbGZs
> b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D
> %7C1000&amp;sdata=2%2BC7%2FgINP5n9k2M6lXChHQj3scXU279dp6pR2SdRiq4%3D&a
> mp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Alex Deucher]

On Wed, Jan 27, 2021 at 12:57 AM Feng, Kenneth <Kenneth.Feng@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Actually the FA DCS is dependent on the workload type.
> FA DCS is applied only when there's 3D fullscreen workload or VR workload.
> So we need to disable it if there's a request from the sysfs/user to set the workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
> By removing this hunk is ok functionally, but the DCS will never kick in though the DCS is enabled. That might be a little bit confusing.
> Thanks.

For clarity, does the SMU act differently with regard to DCS when you
set different workloads via the workload interface or is this just
using the assumption that at some point we might dynamically adjust
the workload bits based on hints from userspace?

Alex


>
>
>
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Wednesday, January 27, 2021 12:55 PM
> To: Feng, Kenneth <Kenneth.Feng@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhou1, Tao <Tao.Zhou1@amd.com>
> Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature
>
> [CAUTION: External Email]
>
> On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng <kenneth.feng@amd.com> wrote:
> >
> > Background:
> > Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> > When the current/power/temperature exceeds the limit with the heavy
> > workload, the gfx core can be shut off and powered on back and forth.
> > The ON time and OFF time is determined by the firmware according to
> > the accumulated power credits.
> > This feature is different from gfxoff.Gfxoff is applied in the idle
> > case and DCS is applied in the case with heavey workload.There are two types of DCS:
> > Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D
> > fullscreen and VR workload.
> > Since we only supports Async DCS now,disalbe DCS when the 3D
> > fullscreen or the VR workload type is chosen.
> >
> > Verification:
> > The power is lowerer or the perf/watt is increased in the throttling case.
> > To be simplified, the entry/exit counter can be observed from the firmware.
> >
> > Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12
> > ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 24f3c96a5e5e..436d94cbb166 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
> >                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
> >         }
> >
> > +       if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == CHIP_DIMGREY_CAVEFISH)
> > +               *(uint64_t *)feature_mask |=
> > + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> > +
> >         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> >                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >                                         |
> > FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> > @@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
> >         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> >                                     1 << workload_type, NULL);
> >
> > +       /* have to disable dcs if it's the 3D fullscreen or VR workload type */
> > +       if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > +               smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> > +               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> > +                       WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
>
> Since we don't support FA DCS yet, should we just drop this hunk for now?  I think the workload profile stuff should be independent of FA DCS.  Also so we want to add a ppfeaturemask flag to easily allow us to disable this at driver load time?
>
> Alex
>
>
> >         return ret;
> >  }
> >
> > --
> > 2.17.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cke
> > nneth.feng%40amd.com%7C2f961319cdd141723c1808d8c27fb554%7C3dd8961fe488
> > 4e608e11a82d994e183d%7C0%7C0%7C637473201048667755%7CUnknown%7CTWFpbGZs
> > b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D
> > %7C1000&amp;sdata=2%2BC7%2FgINP5n9k2M6lXChHQj3scXU279dp6pR2SdRiq4%3D&a
> > mp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Quan, Evan]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,

Yes, SMU acts differently with regard to DCS when you set different workloads via the workload interface. So, Kenneth seems right.
But I think the dcs feature disablement needs to be placed before SMU_MSG_SetWorkloadMask(some code as below). Otherwise, it seems the DCS mode switching happens first(during SMU_MSG_SetWorkloadMask) and the disablement comes afterwards.

+/* have to disable dcs if it's the 3D fullscreen or VR workload type */
+if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
+smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
+ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
+WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
+if (ret)
+return ret;
+}
+
smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
     1 << workload_type, NULL);

BR
Evan
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Thursday, January 28, 2021 1:49 AM
To: Feng, Kenneth <Kenneth.Feng@amd.com>
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

On Wed, Jan 27, 2021 at 12:57 AM Feng, Kenneth <Kenneth.Feng@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Actually the FA DCS is dependent on the workload type.
> FA DCS is applied only when there's 3D fullscreen workload or VR workload.
> So we need to disable it if there's a request from the sysfs/user to set the workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
> By removing this hunk is ok functionally, but the DCS will never kick in though the DCS is enabled. That might be a little bit confusing.
> Thanks.

For clarity, does the SMU act differently with regard to DCS when you set different workloads via the workload interface or is this just using the assumption that at some point we might dynamically adjust the workload bits based on hints from userspace?

Alex


>
>
>
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Wednesday, January 27, 2021 12:55 PM
> To: Feng, Kenneth <Kenneth.Feng@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhou1, Tao
> <Tao.Zhou1@amd.com>
> Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature
>
> [CAUTION: External Email]
>
> On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng <kenneth.feng@amd.com> wrote:
> >
> > Background:
> > Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> > When the current/power/temperature exceeds the limit with the heavy
> > workload, the gfx core can be shut off and powered on back and forth.
> > The ON time and OFF time is determined by the firmware according to
> > the accumulated power credits.
> > This feature is different from gfxoff.Gfxoff is applied in the idle
> > case and DCS is applied in the case with heavey workload.There are two types of DCS:
> > Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D
> > fullscreen and VR workload.
> > Since we only supports Async DCS now,disalbe DCS when the 3D
> > fullscreen or the VR workload type is chosen.
> >
> > Verification:
> > The power is lowerer or the perf/watt is increased in the throttling case.
> > To be simplified, the entry/exit counter can be observed from the firmware.
> >
> > Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12
> > ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 24f3c96a5e5e..436d94cbb166 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
> >                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
> >         }
> >
> > +       if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == CHIP_DIMGREY_CAVEFISH)
> > +               *(uint64_t *)feature_mask |=
> > + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> > +
> >         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> >                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >                                         |
> > FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> > @@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
> >         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> >                                     1 << workload_type, NULL);
> >
> > +       /* have to disable dcs if it's the 3D fullscreen or VR workload type */
> > +       if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > +               smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> > +               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> > +                       WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
>
> Since we don't support FA DCS yet, should we just drop this hunk for now?  I think the workload profile stuff should be independent of FA DCS.  Also so we want to add a ppfeaturemask flag to easily allow us to disable this at driver load time?
>
> Alex
>
>
> >         return ret;
> >  }
> >
> > --
> > 2.17.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > st
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7C
> > ke
> > nneth.feng%40amd.com%7C2f961319cdd141723c1808d8c27fb554%7C3dd8961fe4
> > 88
> > 4e608e11a82d994e183d%7C0%7C0%7C637473201048667755%7CUnknown%7CTWFpbG
> > Zs
> > b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > 3D
> > %7C1000&amp;sdata=2%2BC7%2FgINP5n9k2M6lXChHQj3scXU279dp6pR2SdRiq4%3D
> > &a
> > mp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7Cevan.quan%40amd.com%7Cdc140485274e4987f52208d8c2ebcf5f%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637473665346134041%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=F4lLhov5HScYsfrECmUGzqCXRvBc%2FK8EkzrfpX4SLXY%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
Yes, SMU acts differently with regard to DCS when we set different workloads via the workload interface.
The mapping is as below.
Default, power saving, video, custom -> DCS is disabled in SMU firmware internally though it's enabled from driver.
3D fullscreen, VR -> FA DCS
Compute -> Async DCS

-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com> 
Sent: Thursday, January 28, 2021 1:49 AM
To: Feng, Kenneth <Kenneth.Feng@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhou1, Tao <Tao.Zhou1@amd.com>
Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

[CAUTION: External Email]

On Wed, Jan 27, 2021 at 12:57 AM Feng, Kenneth <Kenneth.Feng@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Actually the FA DCS is dependent on the workload type.
> FA DCS is applied only when there's 3D fullscreen workload or VR workload.
> So we need to disable it if there's a request from the sysfs/user to set the workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
> By removing this hunk is ok functionally, but the DCS will never kick in though the DCS is enabled. That might be a little bit confusing.
> Thanks.

For clarity, does the SMU act differently with regard to DCS when you set different workloads via the workload interface or is this just using the assumption that at some point we might dynamically adjust the workload bits based on hints from userspace?

Alex


>
>
>
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Wednesday, January 27, 2021 12:55 PM
> To: Feng, Kenneth <Kenneth.Feng@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhou1, Tao 
> <Tao.Zhou1@amd.com>
> Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature
>
> [CAUTION: External Email]
>
> On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng <kenneth.feng@amd.com> wrote:
> >
> > Background:
> > Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> > When the current/power/temperature exceeds the limit with the heavy 
> > workload, the gfx core can be shut off and powered on back and forth.
> > The ON time and OFF time is determined by the firmware according to 
> > the accumulated power credits.
> > This feature is different from gfxoff.Gfxoff is applied in the idle 
> > case and DCS is applied in the case with heavey workload.There are two types of DCS:
> > Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D 
> > fullscreen and VR workload.
> > Since we only supports Async DCS now,disalbe DCS when the 3D 
> > fullscreen or the VR workload type is chosen.
> >
> > Verification:
> > The power is lowerer or the perf/watt is increased in the throttling case.
> > To be simplified, the entry/exit counter can be observed from the firmware.
> >
> > Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12
> > ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 24f3c96a5e5e..436d94cbb166 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
> >                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
> >         }
> >
> > +       if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == CHIP_DIMGREY_CAVEFISH)
> > +               *(uint64_t *)feature_mask |= 
> > + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> > +
> >         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> >                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> >                                         |
> > FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> > @@ -1437,6 +1440,15 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
> >         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> >                                     1 << workload_type, NULL);
> >
> > +       /* have to disable dcs if it's the 3D fullscreen or VR workload type */
> > +       if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > +               smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> > +               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> > +                       WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> > +               if (ret)
> > +                       return ret;
> > +       }
> > +
>
> Since we don't support FA DCS yet, should we just drop this hunk for now?  I think the workload profile stuff should be independent of FA DCS.  Also so we want to add a ppfeaturemask flag to easily allow us to disable this at driver load time?
>
> Alex
>
>
> >         return ret;
> >  }
> >
> > --
> > 2.17.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fli
> > st 
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=04%7C01%7C
> > ke
> > nneth.feng%40amd.com%7C2f961319cdd141723c1808d8c27fb554%7C3dd8961fe4
> > 88 
> > 4e608e11a82d994e183d%7C0%7C0%7C637473201048667755%7CUnknown%7CTWFpbG
> > Zs 
> > b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > 3D 
> > %7C1000&amp;sdata=2%2BC7%2FgINP5n9k2M6lXChHQj3scXU279dp6pR2SdRiq4%3D
> > &a
> > mp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx