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From: Tian Yunhao <t123yh@outlook.com>
To: Stephen Boyd <sboyd@kernel.org>, "heiko@sntech.de" <heiko@sntech.de>
Cc: "t123yh.xyz@gmail.com" <t123yh.xyz@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-rockchip@lists.infradead.org"
	<linux-rockchip@lists.infradead.org>
Subject: 回复: [PATCH] clk: rk3308: make ddrphy4x clock critical
Date: Tue, 27 Jul 2021 01:22:14 +0000	[thread overview]
Message-ID: <BYAPR20MB248831FE0EE03DD31FB2C08C89E99@BYAPR20MB2488.namprd20.prod.outlook.com> (raw)
In-Reply-To: <162734809017.2368309.7901135942001140161@swboyd.mtv.corp.google.com>

Quoting Stephen Boyd <sboyd@kernel.org>

> Is it not enabled by default?

Indeed it's enabled by default upon power-up, but it's not
called by any clk_enable (if you look at clk_summary, enable
count is 0). The clk framework thinks that it's an unnecessary
clock, and decides the parent, VPLL1, can be shutdown any time.

If you enable and then disable its siblings (like mclk_i2s0_8ch_in),
 the clk framework will think that VPLL1 is no longer necessary, 
thus shutdown this PLL. This will cause DDR to lose clock.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

WARNING: multiple messages have this Message-ID (diff)
From: Tian Yunhao <t123yh@outlook.com>
To: Stephen Boyd <sboyd@kernel.org>, "heiko@sntech.de" <heiko@sntech.de>
Cc: "t123yh.xyz@gmail.com" <t123yh.xyz@gmail.com>,
	Michael Turquette <mturquette@baylibre.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-rockchip@lists.infradead.org"
	<linux-rockchip@lists.infradead.org>
Subject: 回复: [PATCH] clk: rk3308: make ddrphy4x clock critical
Date: Tue, 27 Jul 2021 01:22:14 +0000	[thread overview]
Message-ID: <BYAPR20MB248831FE0EE03DD31FB2C08C89E99@BYAPR20MB2488.namprd20.prod.outlook.com> (raw)
In-Reply-To: <162734809017.2368309.7901135942001140161@swboyd.mtv.corp.google.com>

Quoting Stephen Boyd <sboyd@kernel.org>

> Is it not enabled by default?

Indeed it's enabled by default upon power-up, but it's not
called by any clk_enable (if you look at clk_summary, enable
count is 0). The clk framework thinks that it's an unnecessary
clock, and decides the parent, VPLL1, can be shutdown any time.

If you enable and then disable its siblings (like mclk_i2s0_8ch_in),
 the clk framework will think that VPLL1 is no longer necessary, 
thus shutdown this PLL. This will cause DDR to lose clock.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-07-27  1:22 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-21 12:48 [PATCH] clk: rk3308: make ddrphy4x clock critical Yunhao Tian
2021-07-21 12:48 ` Yunhao Tian
2021-07-27  1:08 ` Stephen Boyd
2021-07-27  1:08   ` Stephen Boyd
2021-07-27  1:08   ` Stephen Boyd
2021-07-27  1:22   ` Tian Yunhao [this message]
2021-07-27  1:22     ` 回复: " Tian Yunhao
2021-07-28  9:53   ` Heiko Stübner
2021-07-28  9:53     ` Heiko Stübner
2021-07-28  9:53     ` Heiko Stübner
2021-07-29 19:06     ` Stephen Boyd
2021-07-29 19:06       ` Stephen Boyd
2021-07-29 19:06       ` Stephen Boyd
2021-08-02 18:24       ` Saravana Kannan
2021-08-02 18:24         ` Saravana Kannan
2021-08-02 18:24         ` Saravana Kannan
2021-08-02 19:25         ` Heiko Stübner
2021-08-02 19:25           ` Heiko Stübner
2021-08-02 19:25           ` Heiko Stübner
2021-08-05 21:51           ` Saravana Kannan
2021-08-05 21:51             ` Saravana Kannan
2021-08-05 21:51             ` Saravana Kannan
2021-08-03  2:23         ` Tian Yunhao
2021-08-03  2:23           ` Tian Yunhao
2021-07-29 13:19 ` Heiko Stuebner
2021-07-29 13:19   ` Heiko Stuebner
2021-07-29 13:19   ` Heiko Stuebner

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