Re: [PATCH v1 4/4] PCI: brcmstb: Augment driver for MIPs SOCs

From: Jim Quinlan <james.quinlan@broadcom.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Jim Quinlan" <jim2101024@gmail.com>,
	"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS"
	<linux-pci@vger.kernel.org>,
	linux-mips@vger.kernel.org,
	"Nicolas Saenz Julienne" <nsaenz@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Kevin Cernekee" <cernekee@gmail.com>,
	"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
	<bcm-kernel-feedback-list@broadcom.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"open list" <linux-kernel@vger.kernel.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-rpi-kernel@lists.infradead.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v1 4/4] PCI: brcmstb: Augment driver for MIPs SOCs
Date: Fri, 8 Jul 2022 09:37:13 -0400	[thread overview]
Message-ID: <CA+-6iNyViHVgdmvhzTEMWDdaP7mm-38iqhdyknyq0z8Au2gWBg@mail.gmail.com> (raw)
In-Reply-To: <20220706214200.GA224369@bhelgaas>

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On Wed, Jul 6, 2022 at 5:42 PM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Thu, Dec 09, 2021 at 03:47:25PM -0500, Jim Quinlan wrote:
> > The current brcmstb driver works for Arm and Arm64.  A few things are
> > modified here for us to support MIPs as well.
> >
> >   o There are four outbound range register groups and each directs a window
> >     of up to 128MB.  Even though there are four 128MB DT "ranges" in the
> >     bmips PCIe DT node, these ranges are contiguous and are collapsed into
> >     a single range by the OF range parser.  Now the driver assumes a single
> >     range -- for MIPs only -- and splits it back into 128MB sizes.
> >
> >   o For bcm7425, the config space accesses must be 32-bit reads or
> >     writes.  In addition, the 4k config space register array is missing
> >     and not used.
> >
> >   o The registers for the upper 32-bits of the outbound window address do
> >     not exist.
> >
> >   o Burst size must be set to 256 (this refers to an internal bus).
> > ...
>
> > @@ -118,6 +118,7 @@
> >  #define PCIE_MISC_HARD_PCIE_HARD_DEBUG                                       0x4204
> >  #define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK     0x2
> >  #define  PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK             0x08000000
> > +#define  PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK               0x00800000
>
> > @@ -883,7 +937,10 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> >       pcie->bridge_sw_init_set(pcie, 0);
> >
> >       tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> > -     tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> > +     if (is_bmips(pcie))
> > +             tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> > +     else
> > +             tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
> >       writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
> >       /* Wait for SerDes to be stable */
> >       usleep_range(100, 200);
>
> brcm_pcie_resume() has similar code that updates
> PCIE_MISC_HARD_PCIE_HARD_DEBUG [1]:
>
>   tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
>   u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
>   writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
>
>   /* wait for serdes to be stable */
>   udelay(100);
>
> This patch didn't change brcm_pcie_resume() to check is_bmips().
> Should it?
>
> If so, it would be nice to use the same method for updating the value
> (either u32p_replace_bits or plain C bitops) in both places.

Will send a patch to fix this, thanks.

Jim Quinlan
Broadcom STB

>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/pci/controller/pcie-brcmstb.c?id=v5.18#n1452

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