[OpenRISC] Nexys4DDR and OpenRISC

[OpenRISC] Nexys4DDR and OpenRISC

[Marcus Swift]

Hi all,

I am new to OpenRISC and have been attempting to use FuseSOC to build a
system for the Nexys4DRR board.

I realize there is not a FuseSOC system set up in the official repository,
but I came across this and it looked promising: https://github.com/
andrzej-r/orpsoc-cores/tree/nexys4ddr/systems/nexys4ddr

I have been attempting to build this and I have run into several problems -
mostly I think with generating the cores using coregen and logicore.

*Error 1 - Using Coregen to generate project nexys4ddr_ddr2.cgp*

INFO:  Using Coregen to generate project nexys4ddr_ddr2.cgp
Release 14.7 - Xilinx CORE Generator P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
All runtime messages will be recorded in
/home/marcus/.cache/fusesoc/nexys4ddr_ddr2/coregen.log
INFO:encore:314 - Created non-GUI application for batch mode execution.
ERROR:sim:879 - Part 'xc6vlx75t-3ff484' is not valid for component
   'xilinx.com:ip:mig_7series:1.9'.
ERROR:sim:918 - Could not create instance of component MIG 7 Series v1.9.
ERROR: "coregen -r -b nexys4ddr_ddr2.xco -p nexys4ddr_ddr2.cgp" exited with
an error code.
ERROR: See stderr for details.


I cannot find the location of 'stderr' (unless it is /dev/stderr) and am
unsure of where to start with solving this error. If I rebuild the system
for a second time, this error does not occur but a new error arises.

*Error 2 - Using Xilinx Vivado to generate LogiCORE(tm) project
xilinx_mii_to_rmii.xci*

INFO:  Preparing xilinx_mii_to_rmii
INFO:  Using Xilinx Vivado to generate LogiCORE(tm) project
xilinx_mii_to_rmii.xci

****** Vivado v2016.2 (64-bit)
  **** SW Build 1577090 on Thu Jun  2 16:32:35 MDT 2016
  **** IP Build 1577682 on Fri Jun  3 12:00:54 MDT 2016
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source xilinx_mii_to_rmii.tcl
# create_project -force -in_memory xilinx_mii_to_rmii
# set_property target_language verilog [current_project]
# set_property part xc7a100tcsg324-1 [current_project]
# read_ip xilinx_mii_to_rmii.xci
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2016.2/data/ip'.
# generate_target -force synthesis [get_files xilinx_mii_to_rmii.xci]
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the
following file is locked: /home/marcus/.cache/fusesoc/
xilinx_mii_to_rmii/xilinx_mii_to_rmii.xci
Locked reason:
* IP definition 'Ethernet PHY MII to Reduced MII (2.0)' for IP
'xilinx_mii_to_rmii' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl
command 'report_ip_status' for more information.
INFO: [Common 17-206] Exiting Vivado at Mon Oct 24 14:11:34 2016...
The text leading up to this was:
--------------------------
|From a32b1c7380893e7ed890c19e8dd25bc66f226cb3 Mon Sep 17 00:00:00 2001
|From: Andrzej <ndrwrdck@gmail.com>
|Date: Thu, 17 Mar 2016 08:30:51 +0000
|Subject: [PATCH] Switched to work library
|
|---
| mii_to_rmii_v2_0/hdl/src/vhdl/mii_to_rmii.vhd      | 12 ++++++------
| mii_to_rmii_v2_0/hdl/src/vhdl/rmii_rx_agile.vhd    |  2 +-
| mii_to_rmii_v2_0/hdl/src/vhdl/rmii_rx_fixed.vhd    |  6 +++---
| mii_to_rmii_v2_0/hdl/src/vhdl/rmii_tx_agile.vhd    |  2 +-
| mii_to_rmii_v2_0/hdl/src/vhdl/rmii_tx_fixed.vhd    |  2 +-
| mii_to_rmii_v2_0/hdl/src/vhdl/rx_fifo.vhd          |  2 +-
| mii_to_rmii_v2_0/hdl/src/vhdl/rx_fifo_disposer.vhd |  2 +-
| mii_to_rmii_v2_0/hdl/src/vhdl/rx_fifo_loader.vhd   |  2 +-
| mii_to_rmii_v2_0/hdl/src/vhdl/srl_fifo.vhd         |  6 +++---
| 9 files changed, 18 insertions(+), 18 deletions(-)
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/mii_to_rmii.vhd
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/
rmii_rx_agile.vhd
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/
rmii_rx_fixed.vhd
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/
rmii_tx_agile.vhd
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/
rmii_tx_fixed.vhd
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/rx_fifo.vhd
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/
rx_fifo_disposer.vhd
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/
rx_fifo_loader.vhd
| mode change 100755 => 100644 mii_to_rmii_v2_0/hdl/src/vhdl/srl_fifo.vhd
|
|diff --git a/mii_to_rmii_v2_0/hdl/src/vhdl/mii_to_rmii.vhd
b/mii_to_rmii_v2_0/hdl/src/vhdl/mii_to_rmii.vhd
|old mode 100755
|new mode 100644
|index f8d34fa..ba59ec0
|--- a/mii_to_rmii_v2_0/hdl/src/vhdl/mii_to_rmii.vhd
|+++ b/mii_to_rmii_v2_0/hdl/src/vhdl/mii_to_rmii.vhd
--------------------------
File to patch:


When building the* '**xilinx_mii_to_rmii' *core, LogiCORE requests many
patches. I gives me the opportunity to enter the location of a file which
is a patch for the core. From looking at the source directory which I
linked to earlier it might be easier to see what is going on: (
https://github.com/andrzej-r/orpsoc-cores/tree/nexys4ddr/
cores/xilinx_mii_to_rmii)

If anyone could point me in the right direction on getting an OpenRISC SOC
to run on the nexys4ddr or in troubleshooting the above problems I would be
very grateful!

Thanks

Marcus
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[OpenRISC] Nexys4DDR and OpenRISC

[Marcus Swift]

Hi all,

I have solved the first problem involving *Coregen to generate rtl from
project nexys4ddr_ddr2.cgp*, The problem was that the .cgp file was
configured for a different board. By changing the file to be as shown below
the problem is overcome.

************************ nexys4ddr_ddr2.cgp ************************
# Date: Mon Nov 7 12:56:53 2016

SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a100t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/

# CRC: 63e6aa3b
**************************************************************************

If anyone knows how to get vivados logicore to create the
*xilinx_mii_to_rmii.xci
*rtl your input would be much appreciated!

Or if anyone could point me in the right direction in terms of how to get
OpenRISC to run on the Nexus4DDR please do get in touch.

Regards,

Marcus​
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[OpenRISC] Nexys4DDR and OpenRISC

[Stefan Wallentowitz]

On 24.10.2016 16:56, Marcus Swift wrote:
> Hi all,
> 
> I am new to OpenRISC and have been attempting to use FuseSOC to build a
> system for the Nexys4DRR board.
> 
> [..]
>
> If anyone could point me in the right direction on getting an OpenRISC
> SOC to run on the nexys4ddr or in troubleshooting the above problems I
> would be very grateful!

Hi,

in OpTiMSoC we used Xilinx Vivado directly to generate the core. In my
humble opinion thats the most sane way. You end up with AXI ports then
unfortunately, but handling that in the proper clock domain is probably
easier than what you are facing and the "user interface" of MIG.

This is the fusesoc core file:
https://github.com/optimsoc/sources/blob/master/external/extra_cores/boards/nexys4ddr/nexys4ddr-ddr.core

The xci is what I generated in Vivado:
https://github.com/optimsoc/sources/blob/master/external/extra_cores/boards/nexys4ddr/ip/mig_7series.xci

And a data file comes along:
https://github.com/optimsoc/sources/blob/master/external/extra_cores/boards/nexys4ddr/ip/mig_config.prj

If anything needs to be changed, you should generate, customize and then
write back to the xci and prj files.

We then have an abstraction layer (sorry, this is something I plan to
extend and standardize for months now):
https://github.com/optimsoc/sources/blob/master/external/extra_cores/boards/nexys4ddr/rtl/verilog/nexys4ddr.sv

You can see the mig instantiated there. Beside that I have written a
very, very, very simple wb2axi, that does not support anything except
two-cycle accesses (no bursts). But that may be a good start and I would
be happy to assist extensions (planned: i. register, ii. bursts).

I hope that helps a little bit.

Cheers,
Stefan

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[OpenRISC] Nexys4DDR and OpenRISC

[Marcus Swift]

Hi Stefan,

Thanks for your reply, my apologies for taking so long to get back to you.
I have been trying to apply your advice, but still have some questions!

My goal is to create a Vivado project which can generate a bitstream of the
OpenRISC SOC. This will then give me a starting point so that I can
hopefully modify and add to the SOC. From examining your 'optimsoc'
repository my understanding is that this is not the route you take. You
manage to create a SOC for the Nexys4DDR in some other way that does not
use the traditional 'fusesoc build (system)' command, and no vivado project
file is produced.

***** My Question*****
Is there any way I could create a Vivado project which contains all of the
necessary components for an OpenRISC SOC on the Nexys4DDR from your
'optimsoc' repository?
-or-
How would I create a fusesoc system which generates a OpenRISC SOC on the
Nexys4DDR Vivado project?
*************************

My attempt at answering this questions is:
- Use 'andrzej-r' fusesoc system description as before.
- Replace the xilinx cores he generates using fusesoc, with cores I
generate manually in vivado as you did.
   -- This will require me to implement your 'axi2wb' adapter

If this is the best way to create a Nexys4DDR system:
- How must I edit the system top core file (
https://github.com/andrzej-r/orpsoc-cores/blob/nexys4ddr/systems/nexys4ddr/nexys4ddr_top/nexys4ddr_top.core
)
- Which Cores will I need to replace with new Cores I generate in Vivado
myself? ("nexys4ddr_clkgen", "nexys4ddr_ddr2_wb", "nexys4ddr_xadc_wb" and
"xilinx_mii_to_rmii")?
- How would I implement the "axi2wb" adapter? Can I add this to the fusesoc
system?

Please let me know if I am on the right track here! Any advice you have for
me would be very helpful! Looking forward to getting a system up and
working!

Thanks,

Marcus
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