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* Re: [PATCH] target/riscv: Exit current TB after an sfence.vma
@ 2022-03-16 17:22 phantom
  2022-03-29 23:15   ` Atish Patra
  0 siblings, 1 reply; 42+ messages in thread
From: phantom @ 2022-03-16 17:22 UTC (permalink / raw)
  To: idan.horowitz; +Cc: qemu-riscv

Here is a test case for this patch. I used to submit this bug on https://bugs.launchpad.net/qemu/+bug/1906516

sfence.vma will flush the tlb, so after this instruction, the translation block should be end. 
The following code will only work in single step mode:
```
relocate:
 li a0, OFFSET

 la t0, 1f
 add t0, t0, a0
 csrw stvec, t0

 la t0, early_pgtbl
 srl t0, t0, PAGE_SHIFT
 li t1, SATP_SV39
 or t0, t1, t0

 csrw satp, t0
1:
 sfence.vma
 la t0, trap_s
 csrw stvec, t0
 ret
```

In this code, I want to relocate pc to virtual address with the OFFSET prefix. 
Before writing to satp, pc run at physic address, stvec has been set to label 1 
with a virtual prefix and virtual address has been mapping in early_pgtbl, 
after writing satp, qemu will throw a page fault, and pc will set to virtual 
address of label 1.

The problem is that, in this situation, the translation block will not end after 
sfence.vma, and stvec will be set to trap_s,

```
----------------
IN:
Priv: 1; Virt: 0
0x00000000800000dc: 00a080b3 add ra,ra,a0
0x00000000800000e0: 00007297 auipc t0,28672 # 0x800070e0
0x00000000800000e4: f2028293 addi t0,t0,-224
0x00000000800000e8: 00c2d293 srli t0,t0,12
0x00000000800000ec: fff0031b addiw t1,zero,-1
0x00000000800000f0: 03f31313 slli t1,t1,63
0x00000000800000f4: 005362b3 or t0,t1,t0
0x00000000800000f8: 18029073 csrrw zero,satp,t0

----------------
IN:
Priv: 1; Virt: 0
0x00000000800000fc: 12000073 sfence.vma zero,zero
0x0000000080000100: 00000297 auipc t0,0 # 0x80000100
0x0000000080000104: 1c828293 addi t0,t0,456
0x0000000080000108: 10529073 csrrw zero,stvec,t0

riscv_raise_exception: 12
riscv_raise_exception: 12
riscv_raise_exception: 12
riscv_raise_exception: 12
...
```

So, the program will crash. And the program will only work in single step mode:
```
----------------
IN:
Priv: 1; Virt: 0
0x00000000800000f8: 18029073 csrrw zero,satp,t0

----------------
IN:
Priv: 1; Virt: 0
0x00000000800000fc: 12000073 sfence.vma zero,zero

riscv_raise_exception: 12
----------------
IN:
Priv: 1; Virt: 0
0xffffffff800000fc: 12000073 sfence.vma zero,zero

----------------
IN:
Priv: 1; Virt: 0
0xffffffff80000100: 00000297 auipc t0,0 # 0xffffffff80000100

```
The pc will set to label 1, instead of trap_s.

^ permalink raw reply	[flat|nested] 42+ messages in thread
* [PATCH] target/riscv: Exit current TB after an sfence.vma
@ 2022-03-15 19:23 ` Idan Horowitz
  0 siblings, 0 replies; 42+ messages in thread
From: Idan Horowitz @ 2022-03-15 19:23 UTC (permalink / raw)
  To: qemu-riscv
  Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-devel, Idan Horowitz

If the pages which control the translation of the currently executing
instructions are changed, and then the TLB is flushed using sfence.vma
we have to exit the current TB early, to ensure we don't execute stale
instructions.

Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
---
 target/riscv/insn_trans/trans_privileged.c.inc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
index 53613682e8..f265e8202d 100644
--- a/target/riscv/insn_trans/trans_privileged.c.inc
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
@@ -114,6 +114,13 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
 {
 #ifndef CONFIG_USER_ONLY
     gen_helper_tlb_flush(cpu_env);
+    /*
+     * The flush might have changed the backing physical memory of
+     * the instructions we're currently executing
+     */
+    gen_set_pc_imm(ctx, ctx->pc_succ_insn);
+    tcg_gen_exit_tb(NULL, 0);
+    ctx->base.is_jmp = DISAS_NORETURN;
     return true;
 #endif
     return false;
-- 
2.35.1



^ permalink raw reply related	[flat|nested] 42+ messages in thread

end of thread, other threads:[~2022-03-31 19:56 UTC | newest]

Thread overview: 42+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-16 17:22 [PATCH] target/riscv: Exit current TB after an sfence.vma phantom
2022-03-29 23:15 ` Atish Patra
2022-03-29 23:15   ` Atish Patra
2022-03-30  6:15   ` Idan Horowitz
2022-03-30  6:15     ` Idan Horowitz
2022-03-30  7:28     ` Atish Patra
2022-03-30  7:28       ` Atish Patra
2022-03-30  7:35       ` Idan Horowitz
2022-03-30  7:35         ` Idan Horowitz
2022-03-30 12:38         ` phantom
2022-03-30 12:38           ` phantom
2022-03-30 16:11           ` Palmer Dabbelt
2022-03-30 16:11             ` Palmer Dabbelt
2022-03-30 16:11             ` Palmer Dabbelt
2022-03-30 17:06             ` Palmer Dabbelt
2022-03-30 17:06               ` Palmer Dabbelt
2022-03-30 17:06               ` Palmer Dabbelt
2022-03-30 17:10             ` Idan Horowitz
2022-03-30 17:10               ` Idan Horowitz
2022-03-30 17:10               ` Idan Horowitz
2022-03-31  3:23               ` Alistair Francis
2022-03-31  3:23                 ` Alistair Francis
2022-03-31  3:23                 ` Alistair Francis
2022-03-31  4:36                 ` Palmer Dabbelt
2022-03-31  4:36                   ` Palmer Dabbelt
2022-03-31  4:36                   ` Palmer Dabbelt
2022-03-31  5:13                   ` Alistair Francis
2022-03-31  5:13                     ` Alistair Francis
2022-03-31  5:13                     ` Alistair Francis
2022-03-31 19:54                     ` Palmer Dabbelt
2022-03-31 19:54                       ` Palmer Dabbelt
2022-03-31 19:54                       ` Palmer Dabbelt
  -- strict thread matches above, loose matches on Subject: below --
2022-03-15 19:23 Idan Horowitz
2022-03-15 19:23 ` Idan Horowitz
2022-03-15 19:37 ` Richard Henderson
2022-03-15 19:37   ` Richard Henderson
2022-03-15 22:52 ` Alistair Francis
2022-03-15 22:52   ` Alistair Francis
2022-03-15 23:42 ` Alistair Francis
2022-03-15 23:42   ` Alistair Francis
2022-03-30  6:09   ` Alistair Francis
2022-03-30  6:09     ` Alistair Francis

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