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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
	 christoph.muellner@vrull.eu, conor@kernel.org,
	philipp.tomsich@vrull.eu,  ajones@ventanamicro.com,
	emil.renner.berthing@canonical.com,
	 Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: Re: [PATCH 5/7] RISC-V: fix auipc-jalr addresses in patched alternatives
Date: Tue, 15 Nov 2022 14:28:27 +0000	[thread overview]
Message-ID: <CA+V-a8v4=vvCMNRfOtgA2LQN+O5S3w6oQJfY5ZdBtSHCKJ=Hcw@mail.gmail.com> (raw)
In-Reply-To: <20221110164924.529386-6-heiko@sntech.de>

Hi Heiko,

Thank you for the patch.

On Thu, Nov 10, 2022 at 4:50 PM Heiko Stuebner <heiko@sntech.de> wrote:
>
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
>
> Alternatives live in a different section, so addresses used by call
> functions will point to wrong locations after the patch got applied.
>
> Similar to arm64, adjust the location to consider that offset.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> ---
>  arch/riscv/kernel/cpufeature.c | 79 +++++++++++++++++++++++++++++++++-
>  1 file changed, 77 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 694267d1fe81..026512ca9c4c 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -298,6 +298,74 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
>         return cpu_req_feature;
>  }
>
> +#include <asm/parse_asm.h>
> +
> +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
> +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
> +
> +static inline bool is_auipc_jalr_pair(long insn1, long insn2)
> +{
> +       return is_auipc_insn(insn1) && is_jalr_insn(insn2);
> +}
> +
> +#define JALR_SIGN_MASK         BIT(I_IMM_SIGN_OPOFF - I_IMM_11_0_OPOFF)
> +#define JALR_OFFSET_MASK       I_IMM_11_0_MASK
> +#define AUIPC_OFFSET_MASK      U_IMM_31_12_MASK
> +#define AUIPC_PAD              (0x00001000)
> +#define JALR_SHIFT             I_IMM_11_0_OPOFF
> +
> +#define to_jalr_imm(offset)                                            \
> +       ((offset & I_IMM_11_0_MASK) << I_IMM_11_0_OPOFF)
> +
> +#define to_auipc_imm(offset)                                           \
> +       ((offset & JALR_SIGN_MASK) ?                                    \
> +       ((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) :    \
> +       (offset & AUIPC_OFFSET_MASK))
> +
> +static void riscv_alternative_fix_auipc_jalr(unsigned int *alt_ptr,
> +                                            unsigned int len, int patch_offset)
> +{

I am yet to test this with my ASM code yet, but maybe can we move this
to [0] so that other erratas can make use of it too?

[0] arch/riscv/kernel/patch.c

Cheers,
Prabhakar

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  parent reply	other threads:[~2022-11-15 14:29 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-10 16:49 [PATCH 0/7] Zbb string optimizations and call support in alternatives Heiko Stuebner
2022-11-10 16:49 ` [PATCH 1/7] efi/riscv: libstub: mark when compiling libstub Heiko Stuebner
2022-11-13 17:16   ` Conor Dooley
2022-11-13 17:20     ` Heiko Stübner
2022-11-13 18:06       ` Conor Dooley
2022-11-10 16:49 ` [PATCH 2/7] RISC-V: add auipc elements to parse_asm header Heiko Stuebner
2022-11-13 17:18   ` Conor Dooley
2022-11-10 16:49 ` [PATCH 3/7] RISC-V: add U-type imm parsing " Heiko Stuebner
2022-11-13 19:06   ` Conor Dooley
2022-11-10 16:49 ` [PATCH 4/7] RISC-V: add rd reg " Heiko Stuebner
2022-11-13 19:08   ` Conor Dooley
2022-11-10 16:49 ` [PATCH 5/7] RISC-V: fix auipc-jalr addresses in patched alternatives Heiko Stuebner
2022-11-13 20:31   ` Conor Dooley
2022-11-14 10:57   ` Emil Renner Berthing
2022-11-14 11:35     ` Andrew Jones
2022-11-14 11:38       ` Emil Renner Berthing
2022-11-14 11:38       ` Heiko Stübner
2022-11-14 12:15         ` Andrew Jones
2022-11-14 12:29           ` Emil Renner Berthing
2022-11-14 12:47         ` Philipp Tomsich
2022-11-15 14:28   ` Lad, Prabhakar [this message]
2022-11-17 11:51     ` Heiko Stübner
2022-11-21  9:50   ` Lad, Prabhakar
2022-11-21 11:27     ` Heiko Stübner
2022-11-21 15:06       ` Lad, Prabhakar
2022-11-21 21:31         ` Lad, Prabhakar
2022-11-21 22:17           ` Heiko Stübner
2022-11-21 22:38             ` Heiko Stübner
2022-11-22  0:16               ` Lad, Prabhakar
2022-11-21 23:59             ` Lad, Prabhakar
2022-11-22 10:59             ` Lad, Prabhakar
2022-11-22 11:19               ` Heiko Stübner
2022-11-22 11:37                 ` Heiko Stübner
2022-11-22 12:28                   ` Lad, Prabhakar
2022-11-10 16:49 ` [PATCH 6/7] RISC-V: add infrastructure to allow different str* implementations Heiko Stuebner
2022-11-13 22:07   ` Conor Dooley
2022-11-10 16:49 ` [PATCH 7/7] RISC-V: add zbb support to string functions Heiko Stuebner
2022-11-13 23:29   ` Conor Dooley
2022-11-13 23:47     ` Heiko Stübner
2022-11-24 22:23     ` Heiko Stübner
2022-11-24 22:32       ` Conor Dooley
2022-11-24 23:51         ` Heiko Stuebner
2022-11-25  7:49           ` Andrew Jones
2022-11-25  8:17             ` Conor.Dooley
     [not found]             ` <CAEg0e7h9skbWPVDsz9CdB8dATN5XM9eT-uPY0A7xRZmX=qTU6A@mail.gmail.com>
2022-11-25 15:28               ` Andrew Jones
2022-11-25 16:35                 ` Christoph Müllner
2022-11-25 16:39                   ` Conor Dooley
2022-11-25 17:02                     ` Christoph Müllner
2022-11-25 17:11                       ` Conor Dooley
2022-11-25 17:42                         ` Christoph Müllner
2022-11-25 16:36                 ` Conor Dooley

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