From: Conor Dooley <conor@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
christoph.muellner@vrull.eu, prabhakar.csengg@gmail.com,
philipp.tomsich@vrull.eu, ajones@ventanamicro.com,
emil.renner.berthing@canonical.com,
Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: Re: [PATCH 5/7] RISC-V: fix auipc-jalr addresses in patched alternatives
Date: Sun, 13 Nov 2022 20:31:55 +0000 [thread overview]
Message-ID: <Y3FUO18N/JC9erY8@spud> (raw)
In-Reply-To: <20221110164924.529386-6-heiko@sntech.de>
On Thu, Nov 10, 2022 at 05:49:22PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner@vrull.eu>
>
> Alternatives live in a different section, so addresses used by call
> functions will point to wrong locations after the patch got applied.
>
> Similar to arm64, adjust the location to consider that offset.
>
> Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
What a lovely function you've got here, seems to make sense though..
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> arch/riscv/kernel/cpufeature.c | 79 +++++++++++++++++++++++++++++++++-
> 1 file changed, 77 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 694267d1fe81..026512ca9c4c 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -298,6 +298,74 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
> return cpu_req_feature;
> }
>
> +#include <asm/parse_asm.h>
> +
> +DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
> +DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
> +
> +static inline bool is_auipc_jalr_pair(long insn1, long insn2)
> +{
> + return is_auipc_insn(insn1) && is_jalr_insn(insn2);
> +}
> +
> +#define JALR_SIGN_MASK BIT(I_IMM_SIGN_OPOFF - I_IMM_11_0_OPOFF)
> +#define JALR_OFFSET_MASK I_IMM_11_0_MASK
> +#define AUIPC_OFFSET_MASK U_IMM_31_12_MASK
> +#define AUIPC_PAD (0x00001000)
> +#define JALR_SHIFT I_IMM_11_0_OPOFF
> +
> +#define to_jalr_imm(offset) \
> + ((offset & I_IMM_11_0_MASK) << I_IMM_11_0_OPOFF)
> +
> +#define to_auipc_imm(offset) \
> + ((offset & JALR_SIGN_MASK) ? \
> + ((offset & AUIPC_OFFSET_MASK) + AUIPC_PAD) : \
> + (offset & AUIPC_OFFSET_MASK))
> +
> +static void riscv_alternative_fix_auipc_jalr(unsigned int *alt_ptr,
> + unsigned int len, int patch_offset)
> +{
> + int num_instr = len / sizeof(u32);
> + unsigned int call[2];
> + int i;
> + int imm1;
> + u32 rd1;
> +
> + for (i = 0; i < num_instr; i++) {
> + /* is there a further instruction? */
> + if (i + 1 >= num_instr)
> + continue;
> +
> + if (!is_auipc_jalr_pair(*(alt_ptr + i), *(alt_ptr + i + 1)))
> + continue;
> +
> + /* call will use ra register */
> + rd1 = EXTRACT_RD_REG(*(alt_ptr + i));
> + if (rd1 != 1)
> + continue;
> +
> + /* get and adjust new target address */
> + imm1 = EXTRACT_UTYPE_IMM(*(alt_ptr + i));
> + imm1 += EXTRACT_ITYPE_IMM(*(alt_ptr + i + 1));
> + imm1 -= patch_offset;
> +
> + /* pick the original auipc + jalr */
> + call[0] = *(alt_ptr + i);
> + call[1] = *(alt_ptr + i + 1);
> +
> + /* drop the old IMMs */
> + call[0] &= ~(U_IMM_31_12_MASK);
> + call[1] &= ~(I_IMM_11_0_MASK << I_IMM_11_0_OPOFF);
> +
> + /* add the adapted IMMs */
> + call[0] |= to_auipc_imm(imm1);
> + call[1] |= to_jalr_imm(imm1);
> +
> + /* patch the call place again */
> + patch_text_nosync(alt_ptr + i * sizeof(u32), call, 8);
> + }
> +}
> +
> void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
> struct alt_entry *end,
> unsigned int stage)
> @@ -316,8 +384,15 @@ void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin,
> }
>
> tmp = (1U << alt->errata_id);
> - if (cpu_req_feature & tmp)
> - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len);
> + if (cpu_req_feature & tmp) {
> + /* do the basic patching */
> + patch_text_nosync(alt->old_ptr, alt->alt_ptr,
> + alt->alt_len);
> +
> + riscv_alternative_fix_auipc_jalr(alt->old_ptr,
> + alt->alt_len,
> + alt->old_ptr - alt->alt_ptr);
> + }
> }
> }
> #endif
> --
> 2.35.1
>
>
> _______________________________________________
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> http://lists.infradead.org/mailman/listinfo/linux-riscv
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next prev parent reply other threads:[~2022-11-13 20:32 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 16:49 [PATCH 0/7] Zbb string optimizations and call support in alternatives Heiko Stuebner
2022-11-10 16:49 ` [PATCH 1/7] efi/riscv: libstub: mark when compiling libstub Heiko Stuebner
2022-11-13 17:16 ` Conor Dooley
2022-11-13 17:20 ` Heiko Stübner
2022-11-13 18:06 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 2/7] RISC-V: add auipc elements to parse_asm header Heiko Stuebner
2022-11-13 17:18 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 3/7] RISC-V: add U-type imm parsing " Heiko Stuebner
2022-11-13 19:06 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 4/7] RISC-V: add rd reg " Heiko Stuebner
2022-11-13 19:08 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 5/7] RISC-V: fix auipc-jalr addresses in patched alternatives Heiko Stuebner
2022-11-13 20:31 ` Conor Dooley [this message]
2022-11-14 10:57 ` Emil Renner Berthing
2022-11-14 11:35 ` Andrew Jones
2022-11-14 11:38 ` Emil Renner Berthing
2022-11-14 11:38 ` Heiko Stübner
2022-11-14 12:15 ` Andrew Jones
2022-11-14 12:29 ` Emil Renner Berthing
2022-11-14 12:47 ` Philipp Tomsich
2022-11-15 14:28 ` Lad, Prabhakar
2022-11-17 11:51 ` Heiko Stübner
2022-11-21 9:50 ` Lad, Prabhakar
2022-11-21 11:27 ` Heiko Stübner
2022-11-21 15:06 ` Lad, Prabhakar
2022-11-21 21:31 ` Lad, Prabhakar
2022-11-21 22:17 ` Heiko Stübner
2022-11-21 22:38 ` Heiko Stübner
2022-11-22 0:16 ` Lad, Prabhakar
2022-11-21 23:59 ` Lad, Prabhakar
2022-11-22 10:59 ` Lad, Prabhakar
2022-11-22 11:19 ` Heiko Stübner
2022-11-22 11:37 ` Heiko Stübner
2022-11-22 12:28 ` Lad, Prabhakar
2022-11-10 16:49 ` [PATCH 6/7] RISC-V: add infrastructure to allow different str* implementations Heiko Stuebner
2022-11-13 22:07 ` Conor Dooley
2022-11-10 16:49 ` [PATCH 7/7] RISC-V: add zbb support to string functions Heiko Stuebner
2022-11-13 23:29 ` Conor Dooley
2022-11-13 23:47 ` Heiko Stübner
2022-11-24 22:23 ` Heiko Stübner
2022-11-24 22:32 ` Conor Dooley
2022-11-24 23:51 ` Heiko Stuebner
2022-11-25 7:49 ` Andrew Jones
2022-11-25 8:17 ` Conor.Dooley
[not found] ` <CAEg0e7h9skbWPVDsz9CdB8dATN5XM9eT-uPY0A7xRZmX=qTU6A@mail.gmail.com>
2022-11-25 15:28 ` Andrew Jones
2022-11-25 16:35 ` Christoph Müllner
2022-11-25 16:39 ` Conor Dooley
2022-11-25 17:02 ` Christoph Müllner
2022-11-25 17:11 ` Conor Dooley
2022-11-25 17:42 ` Christoph Müllner
2022-11-25 16:36 ` Conor Dooley
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