Re: tg3 crashes under high load, when using 100Mbits

* Re: tg3 crashes under high load, when using 100Mbits
@ 2018-03-20  6:12 Satish Baddipadige
  2018-03-20 16:57 ` Kai-Heng Feng
  0 siblings, 1 reply; 7+ messages in thread
From: Satish Baddipadige @ 2018-03-20  6:12 UTC (permalink / raw)
  To: Siva Reddy Kallam
  Cc: Kai Heng Feng, Prashant Sreedharan, Michael Chan,
	Linux Netdev List, Linux Kernel Mailing List, Stanley Hsiao,
	Tim Chen

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On Thu, Feb 15, 2018 at 7:37 PM, Siva Reddy Kallam
<siva.kallam@broadcom.com> wrote:
> On Mon, Feb 12, 2018 at 10:59 AM, Siva Reddy Kallam
> <siva.kallam@broadcom.com> wrote:
>> On Fri, Feb 9, 2018 at 10:41 AM, Kai Heng Feng
>> <kai.heng.feng@canonical.com> wrote:
>>> Hi Broadcom folks,
>>>
>>> We are now enabling a new platform with tg3 nic, unfortunately we observed
>>> the bug [1] that dated back to 2015.
>>> I tried commit 4419bb1cedcd ("tg3: Add workaround to restrict 5762 MRRS to
>>> 2048”) but it does’t work.
>>>
>>> Do you have any idea how to solve the issue?
>>>
>>> [1] https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1447664
>>>
>>> Kai-Heng
>>>
>> Thank you for reporting. We will check and update you.
> With link aware mode, the clock speed could be slow and boot code does not
> complete within the expected time with lower link speeds. Need to override
> and the clock in driver. We are checking the feasibility of adding
> this in driver or firmware.

Hi Kai-Heng,

Can you please test the attached patch?

Thanks,
Satish

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diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index f259397..d27337d 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -9010,6 +9010,7 @@ static void tg3_override_clk(struct tg3 *tp)
 
 	switch (tg3_asic_rev(tp)) {
 	case ASIC_REV_5717:
+	case ASIC_REV_5762:
 		val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
 		tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
 		     TG3_CPMU_MAC_ORIDE_ENABLE);
@@ -9031,6 +9032,7 @@ static void tg3_restore_clk(struct tg3 *tp)
 
 	switch (tg3_asic_rev(tp)) {
 	case ASIC_REV_5717:
+	case ASIC_REV_5762:
 		val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
 		tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
 		     val & ~TG3_CPMU_MAC_ORIDE_ENABLE);

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