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* [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-01-26  7:19 ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
  to fix zero mask problem
- add EOF setting comment for MUTEX sof register

Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=602528
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=602834

Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next

Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue

Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
  such as AAL, COCLOR, CCORR and MUTEX

Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch

Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195

Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init

Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
  rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting

Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
  the lastest patch
- add MERGE define for const varriable 

Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h

Change in v4:
- extract dt-binding patches to another patch series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function

Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order

Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order

jason-jh.lin (12):
  dt-bindings: arm: mediatek: mmsys: add power and gce properties
  dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  dt-bindings: display: mediatek: disp: split each block to individual
    yaml
  dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
  dt-bindings: display: mediatek: merge: add additional prop for mt8195
  dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
  dt-bindings: arm: mediatek: move out common module from display folder
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: add DSC support for mediatek-drm
  drm/mediatek: add MERGE support for mediatek-drm
  drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
 .../display/mediatek/mediatek,disp.txt        | 219 ----------------
 .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
 .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
 .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
 .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
 .../display/mediatek/mediatek,od.yaml         |  53 ++++
 .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
 .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
 .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
 .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
 .../display/mediatek/mediatek,split.yaml      |  58 +++++
 .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
 .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
 .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
 .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
 .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
 .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
 drivers/gpu/drm/mediatek/Makefile             |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246 ++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
 drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
 drivers/soc/mediatek/mtk-mmsys.c              |  11 +
 drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
 include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
 30 files changed, 1832 insertions(+), 233 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-01-26  7:19 ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
  to fix zero mask problem
- add EOF setting comment for MUTEX sof register

Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=602528
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=602834

Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next

Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue

Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
  such as AAL, COCLOR, CCORR and MUTEX

Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch

Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195

Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init

Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
  rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting

Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
  the lastest patch
- add MERGE define for const varriable 

Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h

Change in v4:
- extract dt-binding patches to another patch series
  https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function

Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order

Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order

jason-jh.lin (12):
  dt-bindings: arm: mediatek: mmsys: add power and gce properties
  dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  dt-bindings: display: mediatek: disp: split each block to individual
    yaml
  dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
  dt-bindings: display: mediatek: merge: add additional prop for mt8195
  dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
  dt-bindings: arm: mediatek: move out common module from display folder
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: add DSC support for mediatek-drm
  drm/mediatek: add MERGE support for mediatek-drm
  drm/mediatek: add mediatek-drm of vdosys0 support for mt8195

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
 .../display/mediatek/mediatek,disp.txt        | 219 ----------------
 .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
 .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
 .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
 .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
 .../display/mediatek/mediatek,od.yaml         |  53 ++++
 .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
 .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
 .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
 .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
 .../display/mediatek/mediatek,split.yaml      |  58 +++++
 .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
 .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
 .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
 .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
 .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
 .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
 drivers/gpu/drm/mediatek/Makefile             |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246 ++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
 drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
 drivers/soc/mediatek/mtk-mmsys.c              |  11 +
 drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
 include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
 30 files changed, 1832 insertions(+), 233 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* [PATCH v15 01/12] dt-bindings: arm: mediatek: mmsys: add power and gce properties
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Power:
1. Add description for power-domains property.

GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.yaml | 30 ++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 763c62323a74..474bcf9c250d 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -40,6 +40,30 @@ properties:
   reg:
     maxItems: 1
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier as defined by bindings
+      of the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  mboxes:
+    description:
+      Using mailbox to communicate with GCE, it should have this
+      property and list of phandle, mailbox specifiers. See
+      Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+  mediatek,gce-client-reg:
+    description:
+      The register of client driver can be configured by gce with 4 arguments
+      defined in this property, such as phandle of gce, subsys id,
+      register offset and size.
+      Each subsys id is mapping to a base address of display function blocks
+      register which is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
   "#clock-cells":
     const: 1
 
@@ -57,7 +81,11 @@ examples:
   - |
     mmsys: syscon@14000000 {
         compatible = "mediatek,mt8173-mmsys", "syscon";
-        reg = <0x14000000 0x1000>;
+        reg = <0 0x14000000 0 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
         #clock-cells = <1>;
         #reset-cells = <1>;
+        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
     };
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 01/12] dt-bindings: arm: mediatek: mmsys: add power and gce properties
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Power:
1. Add description for power-domains property.

GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.yaml | 30 ++++++++++++++++++-
 1 file changed, 29 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 763c62323a74..474bcf9c250d 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -40,6 +40,30 @@ properties:
   reg:
     maxItems: 1
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier as defined by bindings
+      of the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  mboxes:
+    description:
+      Using mailbox to communicate with GCE, it should have this
+      property and list of phandle, mailbox specifiers. See
+      Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+  mediatek,gce-client-reg:
+    description:
+      The register of client driver can be configured by gce with 4 arguments
+      defined in this property, such as phandle of gce, subsys id,
+      register offset and size.
+      Each subsys id is mapping to a base address of display function blocks
+      register which is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
   "#clock-cells":
     const: 1
 
@@ -57,7 +81,11 @@ examples:
   - |
     mmsys: syscon@14000000 {
         compatible = "mediatek,mt8173-mmsys", "syscon";
-        reg = <0x14000000 0x1000>;
+        reg = <0 0x14000000 0 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
         #clock-cells = <1>;
         #reset-cells = <1>;
+        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
     };
-- 
2.18.0


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 02/12] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 474bcf9c250d..a978cdd32575 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,8 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8192-mmsys
               - mediatek,mt8365-mmsys
+              - mediatek,mt8195-vdosys0
+              - mediatek,mt8195-vdosys1
           - const: syscon
       - items:
           - const: mediatek,mt7623-mmsys
-- 
2.18.0


_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 02/12] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml        | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 474bcf9c250d..a978cdd32575 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,8 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8192-mmsys
               - mediatek,mt8365-mmsys
+              - mediatek,mt8195-vdosys0
+              - mediatek,mt8195-vdosys1
           - const: syscon
       - items:
           - const: mediatek,mt7623-mmsys
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="y", Size: 50916 bytes --]

1. Remove mediatek,dislpay.txt
2. Split each display function block to individual yaml file.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,aal.yaml        |  76 ++++++
 .../display/mediatek/mediatek,ccorr.yaml      |  71 ++++++
 .../display/mediatek/mediatek,color.yaml      |  85 +++++++
 .../display/mediatek/mediatek,disp.txt        | 219 ------------------
 .../display/mediatek/mediatek,dither.yaml     |  75 ++++++
 .../display/mediatek/mediatek,gamma.yaml      |  76 ++++++
 .../display/mediatek/mediatek,merge.yaml      |  66 ++++++
 .../display/mediatek/mediatek,mutex.yaml      |  82 +++++++
 .../display/mediatek/mediatek,od.yaml         |  53 +++++
 .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
 .../display/mediatek/mediatek,ovl.yaml        |  98 ++++++++
 .../display/mediatek/mediatek,postmask.yaml   |  69 ++++++
 .../display/mediatek/mediatek,rdma.yaml       | 115 +++++++++
 .../display/mediatek/mediatek,split.yaml      |  58 +++++
 .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
 .../display/mediatek/mediatek,wdma.yaml       |  86 +++++++
 16 files changed, 1159 insertions(+), 219 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
new file mode 100644
index 000000000000..044331f5aacb
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display adaptive ambient light processor
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display adaptive ambient light processor, namely AAL,
+  is responsible for backlight power saving and sunlight visibility improving.
+  AAL device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-aal
+      - items:
+          - enum:
+              - mediatek,mt2712-disp-aal
+              - mediatek,mt8183-disp-aal
+              - mediatek,mt8192-disp-aal
+          - enum:
+              - mediatek,mt8173-disp-aal
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: AAL Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    aal@14015000 {
+        compatible = "mediatek,mt8173-disp-aal";
+        reg = <0 0x14015000 0 0x1000>;
+        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_AAL>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
new file mode 100644
index 000000000000..ea45b40edee7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display color correction
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display color correction, namely CCORR, reproduces correct color
+  on panels with different color gamut.
+  CCORR device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-disp-ccorr
+      - items:
+          - const: mediatek,mt8192-disp-ccorr
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: CCORR Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    ccorr0: ccorr@1400f000 {
+        compatible = "mediatek,mt8183-disp-ccorr";
+        reg = <0 0x1400f000 0 0x1000>;
+        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
new file mode 100644
index 000000000000..13628f346718
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display color processor
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display color processor, namely COLOR, provides hue, luma and
+  saturation adjustments to get better picture quality and to have one panel
+  resemble the other in their output characteristics.
+  COLOR device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2701-disp-color
+      - items:
+          - const: mediatek,mt8167-disp-color
+      - items:
+          - const: mediatek,mt8173-disp-color
+      - items:
+          - enum:
+              - mediatek,mt7623-disp-color
+              - mediatek,mt2712-disp-color
+          - enum:
+              - mediatek,mt2701-disp-color
+      - items:
+          - enum:
+              - mediatek,mt8183-disp-color
+              - mediatek,mt8192-disp-color
+          - enum:
+              - mediatek,mt8173-disp-color
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: COLOR Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    color0: color@14013000 {
+        compatible = "mediatek,mt8173-disp-color";
+        reg = <0 0x14013000 0 0x1000>;
+        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
deleted file mode 100644
index 78044c340e20..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ /dev/null
@@ -1,219 +0,0 @@
-Mediatek display subsystem
-==========================
-
-The Mediatek display subsystem consists of various DISP function blocks in the
-MMSYS register space. The connections between them can be configured by output
-and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
-of frame signal are distributed to the other function blocks by a DISP_MUTEX
-function block.
-
-All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
-For a description of the MMSYS_CONFIG binding, see
-Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
-
-DISP function blocks
-====================
-
-A display stream starts at a source function block that reads pixel data from
-memory and ends with a sink function block that drives pixels on a display
-interface, or writes pixels back to memory. All DISP function blocks have
-their own register space, interrupt, and clock gate. The blocks that can
-access memory additionally have to list the IOMMU and local arbiter they are
-connected to.
-
-For a description of the display interface sink function blocks, see
-Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
-Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
-
-Required properties (all function blocks):
-- compatible: "mediatek,<chip>-disp-<function>", one of
-	"mediatek,<chip>-disp-ovl"   		- overlay (4 layers, blending, csc)
-	"mediatek,<chip>-disp-ovl-2l"           - overlay (2 layers, blending, csc)
-	"mediatek,<chip>-disp-rdma"  		- read DMA / line buffer
-	"mediatek,<chip>-disp-wdma"  		- write DMA
-	"mediatek,<chip>-disp-ccorr"            - color correction
-	"mediatek,<chip>-disp-color" 		- color processor
-	"mediatek,<chip>-disp-dither"           - dither
-	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
-	"mediatek,<chip>-disp-gamma" 		- gamma correction
-	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
-	"mediatek,<chip>-disp-postmask" 	- control round corner for display frame
-	"mediatek,<chip>-disp-split" 		- split stream to two encoders
-	"mediatek,<chip>-disp-ufoe"  		- data compression engine
-	"mediatek,<chip>-dsi"        		- DSI controller, see mediatek,dsi.txt
-	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
-	"mediatek,<chip>-disp-mutex" 		- display mutex
-	"mediatek,<chip>-disp-od"    		- overdrive
-  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
-- reg: Physical base address and length of the function block register space
-- interrupts: The interrupt signal from the function block (required, except for
-  merge and split function blocks).
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-  For most function blocks this is just a single clock input. Only the DSI and
-  DPI controller nodes have multiple clock inputs. These are documented in
-  mediatek,dsi.txt and mediatek,dpi.txt, respectively.
-  An exception is that the mt8183 mutex is always free running with no clocks property.
-
-Required properties (DMA function blocks):
-- compatible: Should be one of
-	"mediatek,<chip>-disp-ovl"
-	"mediatek,<chip>-disp-rdma"
-	"mediatek,<chip>-disp-wdma"
-  the supported chips are mt2701, mt8167 and mt8173.
-- larb: Should contain a phandle pointing to the local arbiter device as defined
-  in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
-- iommus: Should point to the respective IOMMU block with master port as
-  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
-  for details.
-
-Optional properties (RDMA function blocks):
-- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
-  property to the corresponding rdma
-  the value is the Max value which defined in hardware data sheet.
-  mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
-  mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
-  mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
-
-Examples:
-
-mmsys: clock-controller@14000000 {
-	compatible = "mediatek,mt8173-mmsys", "syscon";
-	reg = <0 0x14000000 0 0x1000>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	#clock-cells = <1>;
-};
-
-ovl0: ovl@1400c000 {
-	compatible = "mediatek,mt8173-disp-ovl";
-	reg = <0 0x1400c000 0 0x1000>;
-	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_OVL0>;
-	iommus = <&iommu M4U_PORT_DISP_OVL0>;
-	mediatek,larb = <&larb0>;
-};
-
-ovl1: ovl@1400d000 {
-	compatible = "mediatek,mt8173-disp-ovl";
-	reg = <0 0x1400d000 0 0x1000>;
-	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_OVL1>;
-	iommus = <&iommu M4U_PORT_DISP_OVL1>;
-	mediatek,larb = <&larb4>;
-};
-
-rdma0: rdma@1400e000 {
-	compatible = "mediatek,mt8173-disp-rdma";
-	reg = <0 0x1400e000 0 0x1000>;
-	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_RDMA0>;
-	iommus = <&iommu M4U_PORT_DISP_RDMA0>;
-	mediatek,larb = <&larb0>;
-	mediatek,rdma-fifosize = <8192>;
-};
-
-rdma1: rdma@1400f000 {
-	compatible = "mediatek,mt8173-disp-rdma";
-	reg = <0 0x1400f000 0 0x1000>;
-	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_RDMA1>;
-	iommus = <&iommu M4U_PORT_DISP_RDMA1>;
-	mediatek,larb = <&larb4>;
-};
-
-rdma2: rdma@14010000 {
-	compatible = "mediatek,mt8173-disp-rdma";
-	reg = <0 0x14010000 0 0x1000>;
-	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_RDMA2>;
-	iommus = <&iommu M4U_PORT_DISP_RDMA2>;
-	mediatek,larb = <&larb4>;
-};
-
-wdma0: wdma@14011000 {
-	compatible = "mediatek,mt8173-disp-wdma";
-	reg = <0 0x14011000 0 0x1000>;
-	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_WDMA0>;
-	iommus = <&iommu M4U_PORT_DISP_WDMA0>;
-	mediatek,larb = <&larb0>;
-};
-
-wdma1: wdma@14012000 {
-	compatible = "mediatek,mt8173-disp-wdma";
-	reg = <0 0x14012000 0 0x1000>;
-	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_WDMA1>;
-	iommus = <&iommu M4U_PORT_DISP_WDMA1>;
-	mediatek,larb = <&larb4>;
-};
-
-color0: color@14013000 {
-	compatible = "mediatek,mt8173-disp-color";
-	reg = <0 0x14013000 0 0x1000>;
-	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_COLOR0>;
-};
-
-color1: color@14014000 {
-	compatible = "mediatek,mt8173-disp-color";
-	reg = <0 0x14014000 0 0x1000>;
-	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_COLOR1>;
-};
-
-aal@14015000 {
-	compatible = "mediatek,mt8173-disp-aal";
-	reg = <0 0x14015000 0 0x1000>;
-	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_AAL>;
-};
-
-gamma@14016000 {
-	compatible = "mediatek,mt8173-disp-gamma";
-	reg = <0 0x14016000 0 0x1000>;
-	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_GAMMA>;
-};
-
-ufoe@1401a000 {
-	compatible = "mediatek,mt8173-disp-ufoe";
-	reg = <0 0x1401a000 0 0x1000>;
-	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_UFOE>;
-};
-
-dsi0: dsi@1401b000 {
-	/* See mediatek,dsi.txt for details */
-};
-
-dpi0: dpi@1401d000 {
-	/* See mediatek,dpi.txt for details */
-};
-
-mutex: mutex@14020000 {
-	compatible = "mediatek,mt8173-disp-mutex";
-	reg = <0 0x14020000 0 0x1000>;
-	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_MUTEX_32K>;
-};
-
-od@14023000 {
-	compatible = "mediatek,mt8173-disp-od";
-	reg = <0 0x14023000 0 0x1000>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_OD>;
-};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
new file mode 100644
index 000000000000..2c05e3019c75
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display dither processor
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display dither processor, namely DITHER, works by approximating
+  unavailable colors with available colors and by mixing and matching available
+  colors to mimic unavailable ones.
+  DITHER device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-disp-dither
+      - items:
+          - enum:
+              - mediatek,mt8192-disp-dither
+          - enum:
+              - mediatek,mt8183-disp-dither
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: DITHER Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    dither0: dither@14012000 {
+        compatible = "mediatek,mt8183-disp-dither";
+        reg = <0 0x14012000 0 0x1000>;
+        interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
new file mode 100644
index 000000000000..89ccb8dbadd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display gamma correction
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display gamma correction, namely GAMMA, provides a nonlinear
+  operation used to adjust luminance in display system.
+  GAMMA device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-gamma
+      - items:
+          - const: mediatek,mt8183-disp-gamma
+      - items:
+          - enum:
+              - mediatek,mt8192-disp-gamma
+          - enum:
+              - mediatek,mt8183-disp-gamma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: GAMMA Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    gamma@14016000 {
+        compatible = "mediatek,mt8173-disp-gamma";
+        reg = <0 0x14016000 0 0x1000>;
+        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
new file mode 100644
index 000000000000..7aa6974d509d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display merge
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
+  inputs into one side-by-side output.
+  MERGE device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-merge
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: MERGE Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    merge@14017000 {
+        compatible = "mediatek,mt8173-disp-merge";
+        reg = <0 0x14017000 0 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_MERGE>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
new file mode 100644
index 000000000000..90f11e12a55e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display mutex
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
+  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
+  data path or MDP data path.
+  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
+  the shadow register.
+  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2701-disp-mutex
+      - items:
+          - const: mediatek,mt2712-disp-mutex
+      - items:
+          - const: mediatek,mt8167-disp-mutex
+      - items:
+          - const: mediatek,mt8173-disp-mutex
+      - items:
+          - const: mediatek,mt8183-disp-mutex
+      - items:
+          - const: mediatek,mt8192-disp-mutex
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: MUTEX Clock
+
+  mediatek,gce-events:
+    description:
+      The event id which is mapping to the specific hardware event signal
+      to gce. The event id is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h of each chips.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    mutex: mutex@14020000 {
+        compatible = "mediatek,mt8173-disp-mutex";
+        reg = <0 0x14020000 0 0x1000>;
+        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_MUTEX_32K>;
+        mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
+                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
new file mode 100644
index 000000000000..7519db315217
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overdirve
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display overdrive, namely OD, increases the transition values
+  of pixels between consecutive frames to make LCD rotate faster.
+  OD device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2712-disp-od
+      - items:
+          - const: mediatek,mt8173-disp-od
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: OD Clock
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    od@14023000 {
+        compatible = "mediatek,mt8173-disp-od";
+        reg = <0 0x14023000 0 0x1000>;
+        clocks = <&mmsys CLK_MM_DISP_OD>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
new file mode 100644
index 000000000000..611a2dbdefa4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overlay 2 layer
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
+  for OVL.
+  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-disp-ovl-2l
+      - items:
+          - const: mediatek,mt8192-disp-ovl-2l
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: OVL-2L Clock
+
+  iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommus
+
+additionalProperties: false
+
+examples:
+  - |
+
+    ovl_2l0: ovl@14009000 {
+        compatible = "mediatek,mt8183-disp-ovl-2l";
+        reg = <0 0x14009000 0 0x1000>;
+        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+        iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
+        mediatek,larb = <&larb0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
new file mode 100644
index 000000000000..8e4a62cb9c81
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overlay
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display overlay, namely OVL, can do alpha blending from
+  the memory.
+  OVL device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2701-disp-ovl
+      - items:
+          - const: mediatek,mt8173-disp-ovl
+      - items:
+          - const: mediatek,mt8183-disp-ovl
+      - items:
+          - const: mediatek,mt8192-disp-ovl
+      - items:
+          - enum:
+              - mediatek,mt7623-disp-ovl
+              - mediatek,mt2712-disp-ovl
+          - enum:
+              - mediatek,mt2701-disp-ovl
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: OVL Clock
+
+  iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommu
+
+additionalProperties: false
+
+examples:
+  - |
+
+    ovl0: ovl@1400c000 {
+        compatible = "mediatek,mt8173-disp-ovl";
+        reg = <0 0x1400c000 0 0x1000>;
+        interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_OVL0>;
+        iommus = <&iommu M4U_PORT_DISP_OVL0>;
+        mediatek,larb = <&larb0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
new file mode 100644
index 000000000000..6ac1da2e8871
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display postmask
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display postmask, namely POSTMASK, provides round corner pattern
+  generation.
+  POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8192-disp-postmask
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: POSTMASK Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    postmask0: postmask@1400d000 {
+        compatible = "mediatek,mt8192-disp-postmask";
+        reg = <0 0x1400d000 0 0x1000>;
+        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+        power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
new file mode 100644
index 000000000000..a3c5f4c9fbcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Read Direct Memory Access
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek Read Direct Memory Access(RDMA) component used to read the
+  data into DMA. It provides real time data to the back-end panel
+  driver, such as DSI, DPI and DP_INTF.
+  It contains one line buffer to store the sufficient pixel data.
+  RDMA device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2701-disp-rdma
+      - items:
+          - const: mediatek,mt8173-disp-rdma
+      - items:
+          - const: mediatek,mt8183-disp-rdma
+      - items:
+          - enum:
+              - mediatek,mt7623-disp-rdma
+              - mediatek,mt2712-disp-rdma
+          - enum:
+              - mediatek,mt2701-disp-rdma
+      - items:
+          - enum:
+              - mediatek,mt8192-disp-rdma
+          - enum:
+              - mediatek,mt8183-disp-rdma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: RDMA Clock
+
+  iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+  mediatek,rdma-fifo-size:
+    description:
+      rdma fifo size may be different even in same SOC, add this property to the
+      corresponding rdma.
+      The value below is the Max value which defined in hardware data sheet
+      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
+      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
+      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [8192, 5120, 2048]
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommus
+
+additionalProperties: false
+
+examples:
+  - |
+
+    rdma0: rdma@1400e000 {
+        compatible = "mediatek,mt8173-disp-rdma";
+        reg = <0 0x1400e000 0 0x1000>;
+        interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+        mediatek,larb = <&larb0>;
+        mediatek,rdma-fifosize = <8192>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
new file mode 100644
index 000000000000..4f08e89c1067
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display split
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display split, namely SPLIT, is used to split stream to two
+  encoders.
+  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-split
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: SPLIT Clock
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    split0: split@14018000 {
+        compatible = "mediatek,mt8173-disp-split";
+        reg = <0 0x14018000 0 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
new file mode 100644
index 000000000000..6e8748529e73
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display UFOe
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display UFOe stands for Unified Frame Optimization engine.
+  UFOe can cut the data rate for DSI port which may lead to reduce power
+  consumption.
+  UFOe device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-ufoe
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: UFOe Clock
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    ufoe@1401a000 {
+        compatible = "mediatek,mt8173-disp-ufoe";
+        reg = <0 0x1401a000 0 0x1000>;
+        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_UFOE>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
new file mode 100644
index 000000000000..aaf5649b6413
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write Direct Memory Access
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek Write Direct Memory Access(WDMA) component used to write
+  the data into DMA.
+  WDMA device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-wdma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: WDMA Clock
+
+  iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommus
+
+additionalProperties: false
+
+examples:
+  - |
+
+    wdma0: wdma@14011000 {
+        compatible = "mediatek,mt8173-disp-wdma";
+        reg = <0 0x14011000 0 0x1000>;
+        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+        mediatek,larb = <&larb0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+    };
-- 
2.18.0



[-- Attachment #2: Type: text/plain, Size: 170 bytes --]

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^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="y", Size: 50916 bytes --]

1. Remove mediatek,dislpay.txt
2. Split each display function block to individual yaml file.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,aal.yaml        |  76 ++++++
 .../display/mediatek/mediatek,ccorr.yaml      |  71 ++++++
 .../display/mediatek/mediatek,color.yaml      |  85 +++++++
 .../display/mediatek/mediatek,disp.txt        | 219 ------------------
 .../display/mediatek/mediatek,dither.yaml     |  75 ++++++
 .../display/mediatek/mediatek,gamma.yaml      |  76 ++++++
 .../display/mediatek/mediatek,merge.yaml      |  66 ++++++
 .../display/mediatek/mediatek,mutex.yaml      |  82 +++++++
 .../display/mediatek/mediatek,od.yaml         |  53 +++++
 .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
 .../display/mediatek/mediatek,ovl.yaml        |  98 ++++++++
 .../display/mediatek/mediatek,postmask.yaml   |  69 ++++++
 .../display/mediatek/mediatek,rdma.yaml       | 115 +++++++++
 .../display/mediatek/mediatek,split.yaml      |  58 +++++
 .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
 .../display/mediatek/mediatek,wdma.yaml       |  86 +++++++
 16 files changed, 1159 insertions(+), 219 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
new file mode 100644
index 000000000000..044331f5aacb
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display adaptive ambient light processor
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display adaptive ambient light processor, namely AAL,
+  is responsible for backlight power saving and sunlight visibility improving.
+  AAL device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-aal
+      - items:
+          - enum:
+              - mediatek,mt2712-disp-aal
+              - mediatek,mt8183-disp-aal
+              - mediatek,mt8192-disp-aal
+          - enum:
+              - mediatek,mt8173-disp-aal
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: AAL Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    aal@14015000 {
+        compatible = "mediatek,mt8173-disp-aal";
+        reg = <0 0x14015000 0 0x1000>;
+        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_AAL>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
new file mode 100644
index 000000000000..ea45b40edee7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display color correction
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display color correction, namely CCORR, reproduces correct color
+  on panels with different color gamut.
+  CCORR device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-disp-ccorr
+      - items:
+          - const: mediatek,mt8192-disp-ccorr
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: CCORR Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    ccorr0: ccorr@1400f000 {
+        compatible = "mediatek,mt8183-disp-ccorr";
+        reg = <0 0x1400f000 0 0x1000>;
+        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
new file mode 100644
index 000000000000..13628f346718
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display color processor
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display color processor, namely COLOR, provides hue, luma and
+  saturation adjustments to get better picture quality and to have one panel
+  resemble the other in their output characteristics.
+  COLOR device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2701-disp-color
+      - items:
+          - const: mediatek,mt8167-disp-color
+      - items:
+          - const: mediatek,mt8173-disp-color
+      - items:
+          - enum:
+              - mediatek,mt7623-disp-color
+              - mediatek,mt2712-disp-color
+          - enum:
+              - mediatek,mt2701-disp-color
+      - items:
+          - enum:
+              - mediatek,mt8183-disp-color
+              - mediatek,mt8192-disp-color
+          - enum:
+              - mediatek,mt8173-disp-color
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: COLOR Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    color0: color@14013000 {
+        compatible = "mediatek,mt8173-disp-color";
+        reg = <0 0x14013000 0 0x1000>;
+        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
deleted file mode 100644
index 78044c340e20..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ /dev/null
@@ -1,219 +0,0 @@
-Mediatek display subsystem
-==========================
-
-The Mediatek display subsystem consists of various DISP function blocks in the
-MMSYS register space. The connections between them can be configured by output
-and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
-of frame signal are distributed to the other function blocks by a DISP_MUTEX
-function block.
-
-All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
-For a description of the MMSYS_CONFIG binding, see
-Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
-
-DISP function blocks
-====================
-
-A display stream starts at a source function block that reads pixel data from
-memory and ends with a sink function block that drives pixels on a display
-interface, or writes pixels back to memory. All DISP function blocks have
-their own register space, interrupt, and clock gate. The blocks that can
-access memory additionally have to list the IOMMU and local arbiter they are
-connected to.
-
-For a description of the display interface sink function blocks, see
-Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
-Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
-
-Required properties (all function blocks):
-- compatible: "mediatek,<chip>-disp-<function>", one of
-	"mediatek,<chip>-disp-ovl"   		- overlay (4 layers, blending, csc)
-	"mediatek,<chip>-disp-ovl-2l"           - overlay (2 layers, blending, csc)
-	"mediatek,<chip>-disp-rdma"  		- read DMA / line buffer
-	"mediatek,<chip>-disp-wdma"  		- write DMA
-	"mediatek,<chip>-disp-ccorr"            - color correction
-	"mediatek,<chip>-disp-color" 		- color processor
-	"mediatek,<chip>-disp-dither"           - dither
-	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
-	"mediatek,<chip>-disp-gamma" 		- gamma correction
-	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
-	"mediatek,<chip>-disp-postmask" 	- control round corner for display frame
-	"mediatek,<chip>-disp-split" 		- split stream to two encoders
-	"mediatek,<chip>-disp-ufoe"  		- data compression engine
-	"mediatek,<chip>-dsi"        		- DSI controller, see mediatek,dsi.txt
-	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
-	"mediatek,<chip>-disp-mutex" 		- display mutex
-	"mediatek,<chip>-disp-od"    		- overdrive
-  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
-- reg: Physical base address and length of the function block register space
-- interrupts: The interrupt signal from the function block (required, except for
-  merge and split function blocks).
-- clocks: device clocks
-  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-  For most function blocks this is just a single clock input. Only the DSI and
-  DPI controller nodes have multiple clock inputs. These are documented in
-  mediatek,dsi.txt and mediatek,dpi.txt, respectively.
-  An exception is that the mt8183 mutex is always free running with no clocks property.
-
-Required properties (DMA function blocks):
-- compatible: Should be one of
-	"mediatek,<chip>-disp-ovl"
-	"mediatek,<chip>-disp-rdma"
-	"mediatek,<chip>-disp-wdma"
-  the supported chips are mt2701, mt8167 and mt8173.
-- larb: Should contain a phandle pointing to the local arbiter device as defined
-  in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
-- iommus: Should point to the respective IOMMU block with master port as
-  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
-  for details.
-
-Optional properties (RDMA function blocks):
-- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
-  property to the corresponding rdma
-  the value is the Max value which defined in hardware data sheet.
-  mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
-  mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
-  mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
-
-Examples:
-
-mmsys: clock-controller@14000000 {
-	compatible = "mediatek,mt8173-mmsys", "syscon";
-	reg = <0 0x14000000 0 0x1000>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	#clock-cells = <1>;
-};
-
-ovl0: ovl@1400c000 {
-	compatible = "mediatek,mt8173-disp-ovl";
-	reg = <0 0x1400c000 0 0x1000>;
-	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_OVL0>;
-	iommus = <&iommu M4U_PORT_DISP_OVL0>;
-	mediatek,larb = <&larb0>;
-};
-
-ovl1: ovl@1400d000 {
-	compatible = "mediatek,mt8173-disp-ovl";
-	reg = <0 0x1400d000 0 0x1000>;
-	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_OVL1>;
-	iommus = <&iommu M4U_PORT_DISP_OVL1>;
-	mediatek,larb = <&larb4>;
-};
-
-rdma0: rdma@1400e000 {
-	compatible = "mediatek,mt8173-disp-rdma";
-	reg = <0 0x1400e000 0 0x1000>;
-	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_RDMA0>;
-	iommus = <&iommu M4U_PORT_DISP_RDMA0>;
-	mediatek,larb = <&larb0>;
-	mediatek,rdma-fifosize = <8192>;
-};
-
-rdma1: rdma@1400f000 {
-	compatible = "mediatek,mt8173-disp-rdma";
-	reg = <0 0x1400f000 0 0x1000>;
-	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_RDMA1>;
-	iommus = <&iommu M4U_PORT_DISP_RDMA1>;
-	mediatek,larb = <&larb4>;
-};
-
-rdma2: rdma@14010000 {
-	compatible = "mediatek,mt8173-disp-rdma";
-	reg = <0 0x14010000 0 0x1000>;
-	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_RDMA2>;
-	iommus = <&iommu M4U_PORT_DISP_RDMA2>;
-	mediatek,larb = <&larb4>;
-};
-
-wdma0: wdma@14011000 {
-	compatible = "mediatek,mt8173-disp-wdma";
-	reg = <0 0x14011000 0 0x1000>;
-	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_WDMA0>;
-	iommus = <&iommu M4U_PORT_DISP_WDMA0>;
-	mediatek,larb = <&larb0>;
-};
-
-wdma1: wdma@14012000 {
-	compatible = "mediatek,mt8173-disp-wdma";
-	reg = <0 0x14012000 0 0x1000>;
-	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_WDMA1>;
-	iommus = <&iommu M4U_PORT_DISP_WDMA1>;
-	mediatek,larb = <&larb4>;
-};
-
-color0: color@14013000 {
-	compatible = "mediatek,mt8173-disp-color";
-	reg = <0 0x14013000 0 0x1000>;
-	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_COLOR0>;
-};
-
-color1: color@14014000 {
-	compatible = "mediatek,mt8173-disp-color";
-	reg = <0 0x14014000 0 0x1000>;
-	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_COLOR1>;
-};
-
-aal@14015000 {
-	compatible = "mediatek,mt8173-disp-aal";
-	reg = <0 0x14015000 0 0x1000>;
-	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_AAL>;
-};
-
-gamma@14016000 {
-	compatible = "mediatek,mt8173-disp-gamma";
-	reg = <0 0x14016000 0 0x1000>;
-	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_GAMMA>;
-};
-
-ufoe@1401a000 {
-	compatible = "mediatek,mt8173-disp-ufoe";
-	reg = <0 0x1401a000 0 0x1000>;
-	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_UFOE>;
-};
-
-dsi0: dsi@1401b000 {
-	/* See mediatek,dsi.txt for details */
-};
-
-dpi0: dpi@1401d000 {
-	/* See mediatek,dpi.txt for details */
-};
-
-mutex: mutex@14020000 {
-	compatible = "mediatek,mt8173-disp-mutex";
-	reg = <0 0x14020000 0 0x1000>;
-	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_MUTEX_32K>;
-};
-
-od@14023000 {
-	compatible = "mediatek,mt8173-disp-od";
-	reg = <0 0x14023000 0 0x1000>;
-	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-	clocks = <&mmsys CLK_MM_DISP_OD>;
-};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
new file mode 100644
index 000000000000..2c05e3019c75
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display dither processor
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display dither processor, namely DITHER, works by approximating
+  unavailable colors with available colors and by mixing and matching available
+  colors to mimic unavailable ones.
+  DITHER device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-disp-dither
+      - items:
+          - enum:
+              - mediatek,mt8192-disp-dither
+          - enum:
+              - mediatek,mt8183-disp-dither
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: DITHER Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    dither0: dither@14012000 {
+        compatible = "mediatek,mt8183-disp-dither";
+        reg = <0 0x14012000 0 0x1000>;
+        interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
new file mode 100644
index 000000000000..89ccb8dbadd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display gamma correction
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display gamma correction, namely GAMMA, provides a nonlinear
+  operation used to adjust luminance in display system.
+  GAMMA device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-gamma
+      - items:
+          - const: mediatek,mt8183-disp-gamma
+      - items:
+          - enum:
+              - mediatek,mt8192-disp-gamma
+          - enum:
+              - mediatek,mt8183-disp-gamma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: GAMMA Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    gamma@14016000 {
+        compatible = "mediatek,mt8173-disp-gamma";
+        reg = <0 0x14016000 0 0x1000>;
+        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
new file mode 100644
index 000000000000..7aa6974d509d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display merge
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
+  inputs into one side-by-side output.
+  MERGE device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-merge
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: MERGE Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    merge@14017000 {
+        compatible = "mediatek,mt8173-disp-merge";
+        reg = <0 0x14017000 0 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_MERGE>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
new file mode 100644
index 000000000000..90f11e12a55e
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display mutex
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
+  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
+  data path or MDP data path.
+  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
+  the shadow register.
+  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2701-disp-mutex
+      - items:
+          - const: mediatek,mt2712-disp-mutex
+      - items:
+          - const: mediatek,mt8167-disp-mutex
+      - items:
+          - const: mediatek,mt8173-disp-mutex
+      - items:
+          - const: mediatek,mt8183-disp-mutex
+      - items:
+          - const: mediatek,mt8192-disp-mutex
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: MUTEX Clock
+
+  mediatek,gce-events:
+    description:
+      The event id which is mapping to the specific hardware event signal
+      to gce. The event id is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h of each chips.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    mutex: mutex@14020000 {
+        compatible = "mediatek,mt8173-disp-mutex";
+        reg = <0 0x14020000 0 0x1000>;
+        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_MUTEX_32K>;
+        mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
+                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
new file mode 100644
index 000000000000..7519db315217
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overdirve
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display overdrive, namely OD, increases the transition values
+  of pixels between consecutive frames to make LCD rotate faster.
+  OD device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2712-disp-od
+      - items:
+          - const: mediatek,mt8173-disp-od
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: OD Clock
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    od@14023000 {
+        compatible = "mediatek,mt8173-disp-od";
+        reg = <0 0x14023000 0 0x1000>;
+        clocks = <&mmsys CLK_MM_DISP_OD>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
new file mode 100644
index 000000000000..611a2dbdefa4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overlay 2 layer
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
+  for OVL.
+  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-disp-ovl-2l
+      - items:
+          - const: mediatek,mt8192-disp-ovl-2l
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: OVL-2L Clock
+
+  iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommus
+
+additionalProperties: false
+
+examples:
+  - |
+
+    ovl_2l0: ovl@14009000 {
+        compatible = "mediatek,mt8183-disp-ovl-2l";
+        reg = <0 0x14009000 0 0x1000>;
+        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+        iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
+        mediatek,larb = <&larb0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
new file mode 100644
index 000000000000..8e4a62cb9c81
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display overlay
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display overlay, namely OVL, can do alpha blending from
+  the memory.
+  OVL device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2701-disp-ovl
+      - items:
+          - const: mediatek,mt8173-disp-ovl
+      - items:
+          - const: mediatek,mt8183-disp-ovl
+      - items:
+          - const: mediatek,mt8192-disp-ovl
+      - items:
+          - enum:
+              - mediatek,mt7623-disp-ovl
+              - mediatek,mt2712-disp-ovl
+          - enum:
+              - mediatek,mt2701-disp-ovl
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: OVL Clock
+
+  iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommu
+
+additionalProperties: false
+
+examples:
+  - |
+
+    ovl0: ovl@1400c000 {
+        compatible = "mediatek,mt8173-disp-ovl";
+        reg = <0 0x1400c000 0 0x1000>;
+        interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_OVL0>;
+        iommus = <&iommu M4U_PORT_DISP_OVL0>;
+        mediatek,larb = <&larb0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
new file mode 100644
index 000000000000..6ac1da2e8871
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display postmask
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display postmask, namely POSTMASK, provides round corner pattern
+  generation.
+  POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8192-disp-postmask
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: POSTMASK Clock
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    postmask0: postmask@1400d000 {
+        compatible = "mediatek,mt8192-disp-postmask";
+        reg = <0 0x1400d000 0 0x1000>;
+        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+        power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
new file mode 100644
index 000000000000..a3c5f4c9fbcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Read Direct Memory Access
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek Read Direct Memory Access(RDMA) component used to read the
+  data into DMA. It provides real time data to the back-end panel
+  driver, such as DSI, DPI and DP_INTF.
+  It contains one line buffer to store the sufficient pixel data.
+  RDMA device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt2701-disp-rdma
+      - items:
+          - const: mediatek,mt8173-disp-rdma
+      - items:
+          - const: mediatek,mt8183-disp-rdma
+      - items:
+          - enum:
+              - mediatek,mt7623-disp-rdma
+              - mediatek,mt2712-disp-rdma
+          - enum:
+              - mediatek,mt2701-disp-rdma
+      - items:
+          - enum:
+              - mediatek,mt8192-disp-rdma
+          - enum:
+              - mediatek,mt8183-disp-rdma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: RDMA Clock
+
+  iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+  mediatek,rdma-fifo-size:
+    description:
+      rdma fifo size may be different even in same SOC, add this property to the
+      corresponding rdma.
+      The value below is the Max value which defined in hardware data sheet
+      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
+      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
+      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [8192, 5120, 2048]
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommus
+
+additionalProperties: false
+
+examples:
+  - |
+
+    rdma0: rdma@1400e000 {
+        compatible = "mediatek,mt8173-disp-rdma";
+        reg = <0 0x1400e000 0 0x1000>;
+        interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+        mediatek,larb = <&larb0>;
+        mediatek,rdma-fifosize = <8192>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
new file mode 100644
index 000000000000..4f08e89c1067
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display split
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display split, namely SPLIT, is used to split stream to two
+  encoders.
+  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-split
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: SPLIT Clock
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    split0: split@14018000 {
+        compatible = "mediatek,mt8173-disp-split";
+        reg = <0 0x14018000 0 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
new file mode 100644
index 000000000000..6e8748529e73
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek display UFOe
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek display UFOe stands for Unified Frame Optimization engine.
+  UFOe can cut the data rate for DSI port which may lead to reduce power
+  consumption.
+  UFOe device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-ufoe
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: UFOe Clock
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    ufoe@1401a000 {
+        compatible = "mediatek,mt8173-disp-ufoe";
+        reg = <0 0x1401a000 0 0x1000>;
+        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_UFOE>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
new file mode 100644
index 000000000000..aaf5649b6413
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write Direct Memory Access
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  Mediatek Write Direct Memory Access(WDMA) component used to write
+  the data into DMA.
+  WDMA device node must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8173-disp-wdma
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: WDMA Clock
+
+  iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommus
+
+additionalProperties: false
+
+examples:
+  - |
+
+    wdma0: wdma@14011000 {
+        compatible = "mediatek,mt8173-disp-wdma";
+        reg = <0 0x14011000 0 0x1000>;
+        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+        mediatek,larb = <&larb0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+    };
-- 
2.18.0



[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

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^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

1. Add mediatek,dsc.yaml to describe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,dsc.yaml        | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
new file mode 100644
index 000000000000..1ec083eff824
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display DSC controller
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  The DSC standard is a specification of the algorithms used for
+  compressing and decompressing image display streams, including
+  the specification of the syntax and semantics of the compressed
+  video bit stream. DSC is designed for real-time systems with
+  real-time compression, transmission, decompression and Display.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8195-disp-dsc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: DSC Wrapper Clock
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  mediatek,gce-client-reg:
+    description:
+      The register of client driver can be configured by gce with 4 arguments
+      defined in this property, such as phandle of gce, subsys id,
+      register offset and size.
+      Each subsys id is mapping to a base address of display function blocks
+      register which is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    dsc0: disp_dsc_wrap@1c009000 {
+        compatible = "mediatek,mt8195-disp-dsc";
+        reg = <0 0x1c009000 0 0x1000>;
+        interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+        clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+        mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+    };
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

1. Add mediatek,dsc.yaml to describe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,dsc.yaml        | 71 +++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
new file mode 100644
index 000000000000..1ec083eff824
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek display DSC controller
+
+maintainers:
+  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+  - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+  The DSC standard is a specification of the algorithms used for
+  compressing and decompressing image display streams, including
+  the specification of the syntax and semantics of the compressed
+  video bit stream. DSC is designed for real-time systems with
+  real-time compression, transmission, decompression and Display.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: mediatek,mt8195-disp-dsc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: DSC Wrapper Clock
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  mediatek,gce-client-reg:
+    description:
+      The register of client driver can be configured by gce with 4 arguments
+      defined in this property, such as phandle of gce, subsys id,
+      register offset and size.
+      Each subsys id is mapping to a base address of display function blocks
+      register which is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+
+    dsc0: disp_dsc_wrap@1c009000 {
+        compatible = "mediatek,mt8195-disp-dsc";
+        reg = <0 0x1c009000 0 0x1000>;
+        interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+        clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+        mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+    };
-- 
2.18.0


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 05/12] dt-bindings: display: mediatek: merge: add additional prop for mt8195
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

add MERGE additional properties description for mt8195:
1. async clock
2. fifo setting enable
3. reset controller

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,merge.yaml      | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 7aa6974d509d..fae106cf1753 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -36,8 +36,28 @@ properties:
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
   clocks:
+    maxItems: 2
     items:
       - description: MERGE Clock
+      - description: MERGE Async Clock
+          Controlling the synchronous process between MERGE and other display
+          function blocks cross clock domain.
+
+  clock-names:
+    maxItems: 2
+    items:
+      - const: merge
+      - const: merge_async
+
+  mediatek,merge-fifo-en:
+    description:
+      The setting of merge fifo is mainly provided for the display latency
+      buffer to ensure that the back-end panel display data will not be
+      underrun, a little more data is needed in the fifo.
+      According to the merge fifo settings, when the water level is detected
+      to be insufficient, it will trigger RDMA sending ultra and preulra
+      command to SMI to speed up the data rate.
+    type: boolean
 
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
@@ -47,6 +67,11 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  resets:
+    description: reset controller
+      See Documentation/devicetree/bindings/reset/reset.txt for details.
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -64,3 +89,16 @@ examples:
         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
         clocks = <&mmsys CLK_MM_DISP_MERGE>;
     };
+
+    merge5: disp_vpp_merge5@1c110000 {
+        compatible = "mediatek,mt8195-disp-merge";
+        reg = <0 0x1c110000 0 0x1000>;
+        interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+        clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+                 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+        clock-names = "merge","merge_async";
+        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+        mediatek,merge-fifo-en = <1>;
+        resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+    };
-- 
2.18.0


_______________________________________________
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Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 05/12] dt-bindings: display: mediatek: merge: add additional prop for mt8195
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

add MERGE additional properties description for mt8195:
1. async clock
2. fifo setting enable
3. reset controller

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,merge.yaml      | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 7aa6974d509d..fae106cf1753 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -36,8 +36,28 @@ properties:
       Documentation/devicetree/bindings/power/power-domain.yaml for details.
 
   clocks:
+    maxItems: 2
     items:
       - description: MERGE Clock
+      - description: MERGE Async Clock
+          Controlling the synchronous process between MERGE and other display
+          function blocks cross clock domain.
+
+  clock-names:
+    maxItems: 2
+    items:
+      - const: merge
+      - const: merge_async
+
+  mediatek,merge-fifo-en:
+    description:
+      The setting of merge fifo is mainly provided for the display latency
+      buffer to ensure that the back-end panel display data will not be
+      underrun, a little more data is needed in the fifo.
+      According to the merge fifo settings, when the water level is detected
+      to be insufficient, it will trigger RDMA sending ultra and preulra
+      command to SMI to speed up the data rate.
+    type: boolean
 
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
@@ -47,6 +67,11 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
+  resets:
+    description: reset controller
+      See Documentation/devicetree/bindings/reset/reset.txt for details.
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -64,3 +89,16 @@ examples:
         power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
         clocks = <&mmsys CLK_MM_DISP_MERGE>;
     };
+
+    merge5: disp_vpp_merge5@1c110000 {
+        compatible = "mediatek,mt8195-disp-merge";
+        reg = <0 0x1c110000 0 0x1000>;
+        interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+        clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+                 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+        clock-names = "merge","merge_async";
+        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+        mediatek,merge-fifo-en = <1>;
+        resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+    };
-- 
2.18.0


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
MUTEX, OVL and RDMA yaml schema for vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../devicetree/bindings/display/mediatek/mediatek,aal.yaml   | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 5 +++++
 .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
 .../bindings/display/mediatek/mediatek,dither.yaml           | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
 .../devicetree/bindings/display/mediatek/mediatek,mutex.yaml | 5 +++--
 .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 5 +++++
 .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 2 ++
 9 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index 044331f5aacb..225f9dd726d2 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -28,6 +28,7 @@ properties:
               - mediatek,mt2712-disp-aal
               - mediatek,mt8183-disp-aal
               - mediatek,mt8192-disp-aal
+              - mediatek,mt8195-disp-aal
           - enum:
               - mediatek,mt8173-disp-aal
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index ea45b40edee7..6894b6999412 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -25,6 +25,11 @@ properties:
           - const: mediatek,mt8183-disp-ccorr
       - items:
           - const: mediatek,mt8192-disp-ccorr
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-ccorr
+          - enum:
+              - mediatek,mt8192-disp-ccorr
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index 13628f346718..bc83155b3b4c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -38,6 +38,7 @@ properties:
           - enum:
               - mediatek,mt8183-disp-color
               - mediatek,mt8192-disp-color
+              - mediatek,mt8195-disp-color
           - enum:
               - mediatek,mt8173-disp-color
   reg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index 2c05e3019c75..9d89297f5f1d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -27,6 +27,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt8192-disp-dither
+              - mediatek,mt8195-disp-dither
           - enum:
               - mediatek,mt8183-disp-dither
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index 89ccb8dbadd7..247baad147b3 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -28,6 +28,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt8192-disp-gamma
+              - mediatek,mt8195-disp-gamma
           - enum:
               - mediatek,mt8183-disp-gamma
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index fae106cf1753..60b21ef5549b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -23,6 +23,8 @@ properties:
     oneOf:
       - items:
           - const: mediatek,mt8173-disp-merge
+      - items:
+          - const: mediatek,mt8195-disp-merge
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
index 90f11e12a55e..6eca525eced0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Mediatek display mutex
+title: Mediatek mutex
 
 maintainers:
   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
@@ -36,7 +36,8 @@ properties:
           - const: mediatek,mt8183-disp-mutex
       - items:
           - const: mediatek,mt8192-disp-mutex
-
+      - items:
+          - const: mediatek,mt8195-disp-mutex
   reg:
     maxItems: 1
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 8e4a62cb9c81..e71f79bc2dee 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -35,6 +35,11 @@ properties:
               - mediatek,mt2712-disp-ovl
           - enum:
               - mediatek,mt2701-disp-ovl
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-ovl
+          - enum:
+              - mediatek,mt8183-disp-ovl
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index a3c5f4c9fbcd..8ef821641672 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -29,6 +29,8 @@ properties:
           - const: mediatek,mt8173-disp-rdma
       - items:
           - const: mediatek,mt8183-disp-rdma
+      - items:
+          - const: mediatek,mt8195-disp-rdma
       - items:
           - enum:
               - mediatek,mt7623-disp-rdma
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
MUTEX, OVL and RDMA yaml schema for vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../devicetree/bindings/display/mediatek/mediatek,aal.yaml   | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 5 +++++
 .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
 .../bindings/display/mediatek/mediatek,dither.yaml           | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
 .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
 .../devicetree/bindings/display/mediatek/mediatek,mutex.yaml | 5 +++--
 .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 5 +++++
 .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 2 ++
 9 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index 044331f5aacb..225f9dd726d2 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -28,6 +28,7 @@ properties:
               - mediatek,mt2712-disp-aal
               - mediatek,mt8183-disp-aal
               - mediatek,mt8192-disp-aal
+              - mediatek,mt8195-disp-aal
           - enum:
               - mediatek,mt8173-disp-aal
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index ea45b40edee7..6894b6999412 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -25,6 +25,11 @@ properties:
           - const: mediatek,mt8183-disp-ccorr
       - items:
           - const: mediatek,mt8192-disp-ccorr
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-ccorr
+          - enum:
+              - mediatek,mt8192-disp-ccorr
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
index 13628f346718..bc83155b3b4c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
@@ -38,6 +38,7 @@ properties:
           - enum:
               - mediatek,mt8183-disp-color
               - mediatek,mt8192-disp-color
+              - mediatek,mt8195-disp-color
           - enum:
               - mediatek,mt8173-disp-color
   reg:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index 2c05e3019c75..9d89297f5f1d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -27,6 +27,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt8192-disp-dither
+              - mediatek,mt8195-disp-dither
           - enum:
               - mediatek,mt8183-disp-dither
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index 89ccb8dbadd7..247baad147b3 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -28,6 +28,7 @@ properties:
       - items:
           - enum:
               - mediatek,mt8192-disp-gamma
+              - mediatek,mt8195-disp-gamma
           - enum:
               - mediatek,mt8183-disp-gamma
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index fae106cf1753..60b21ef5549b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -23,6 +23,8 @@ properties:
     oneOf:
       - items:
           - const: mediatek,mt8173-disp-merge
+      - items:
+          - const: mediatek,mt8195-disp-merge
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
index 90f11e12a55e..6eca525eced0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Mediatek display mutex
+title: Mediatek mutex
 
 maintainers:
   - Chun-Kuang Hu <chunkuang.hu@kernel.org>
@@ -36,7 +36,8 @@ properties:
           - const: mediatek,mt8183-disp-mutex
       - items:
           - const: mediatek,mt8192-disp-mutex
-
+      - items:
+          - const: mediatek,mt8195-disp-mutex
   reg:
     maxItems: 1
 
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 8e4a62cb9c81..e71f79bc2dee 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -35,6 +35,11 @@ properties:
               - mediatek,mt2712-disp-ovl
           - enum:
               - mediatek,mt2701-disp-ovl
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-ovl
+          - enum:
+              - mediatek,mt8183-disp-ovl
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index a3c5f4c9fbcd..8ef821641672 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -29,6 +29,8 @@ properties:
           - const: mediatek,mt8173-disp-rdma
       - items:
           - const: mediatek,mt8183-disp-rdma
+      - items:
+          - const: mediatek,mt8195-disp-rdma
       - items:
           - enum:
               - mediatek,mt7623-disp-rdma
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 07/12] dt-bindings: arm: mediatek: move out common module from display folder
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

AAL, COLOR, CCORR, MUTEX, WDMA could be used by other modules,
such as MDP, so move their binding document into the common folder.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,ccorr.yaml      | 76 ----------------
 .../display/mediatek/mediatek,wdma.yaml       | 86 -------------------
 .../mediatek/mediatek,aal.yaml                | 13 +--
 .../bindings/soc/mediatek/mediatek,ccorr.yaml | 46 ++++++++--
 .../mediatek/mediatek,color.yaml              | 15 ++--
 .../mediatek/mediatek,mutex.yaml              | 12 +--
 .../bindings/soc/mediatek/mediatek,wdma.yaml  | 47 +++++++++-
 7 files changed, 96 insertions(+), 199 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
 rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,aal.yaml (78%)
 rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,color.yaml (78%)
 rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,mutex.yaml (80%)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
deleted file mode 100644
index 6894b6999412..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ /dev/null
@@ -1,76 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mediatek display color correction
-
-maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
-
-description: |
-  Mediatek display color correction, namely CCORR, reproduces correct color
-  on panels with different color gamut.
-  CCORR device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
-
-properties:
-  compatible:
-    oneOf:
-      - items:
-          - const: mediatek,mt8183-disp-ccorr
-      - items:
-          - const: mediatek,mt8192-disp-ccorr
-      - items:
-          - enum:
-              - mediatek,mt8195-disp-ccorr
-          - enum:
-              - mediatek,mt8192-disp-ccorr
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  power-domains:
-    description: A phandle and PM domain specifier as defined by bindings of
-      the power controller specified by phandle. See
-      Documentation/devicetree/bindings/power/power-domain.yaml for details.
-
-  clocks:
-    items:
-      - description: CCORR Clock
-
-  mediatek,gce-client-reg:
-    description: The register of client driver can be configured by gce with
-      4 arguments defined in this property, such as phandle of gce, subsys id,
-      register offset and size. Each GCE subsys id is mapping to a client
-      defined in the header include/dt-bindings/gce/<chip>-gce.h.
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    maxItems: 1
-
-required:
-  - compatible
-  - reg
-  - interrupts
-  - power-domains
-  - clocks
-
-additionalProperties: false
-
-examples:
-  - |
-
-    ccorr0: ccorr@1400f000 {
-        compatible = "mediatek,mt8183-disp-ccorr";
-        reg = <0 0x1400f000 0 0x1000>;
-        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
-        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
-        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
-        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
-    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
deleted file mode 100644
index aaf5649b6413..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
+++ /dev/null
@@ -1,86 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mediatek Write Direct Memory Access
-
-maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
-
-description: |
-  Mediatek Write Direct Memory Access(WDMA) component used to write
-  the data into DMA.
-  WDMA device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
-
-properties:
-  compatible:
-    oneOf:
-      - items:
-          - const: mediatek,mt8173-disp-wdma
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  power-domains:
-    description: A phandle and PM domain specifier as defined by bindings of
-      the power controller specified by phandle. See
-      Documentation/devicetree/bindings/power/power-domain.yaml for details.
-
-  clocks:
-    items:
-      - description: WDMA Clock
-
-  iommus:
-    description:
-      This property should point to the respective IOMMU block with master port as argument,
-      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
-
-  mediatek,larb:
-    description:
-      This property should contain a phandle pointing to the local arbiter devices defined in
-      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
-      It must sort according to the local arbiter index, like larb0, larb1, larb2...
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    minItems: 1
-    maxItems: 32
-
-  mediatek,gce-client-reg:
-    description: The register of client driver can be configured by gce with
-      4 arguments defined in this property, such as phandle of gce, subsys id,
-      register offset and size. Each GCE subsys id is mapping to a client
-      defined in the header include/dt-bindings/gce/<chip>-gce.h.
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    maxItems: 1
-
-required:
-  - compatible
-  - reg
-  - interrupts
-  - power-domains
-  - clocks
-  - iommus
-
-additionalProperties: false
-
-examples:
-  - |
-
-    wdma0: wdma@14011000 {
-        compatible = "mediatek,mt8173-disp-wdma";
-        reg = <0 0x14011000 0 0x1000>;
-        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
-        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
-        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
-        mediatek,larb = <&larb0>;
-        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
-    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
similarity index 78%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
index 225f9dd726d2..f9f57e073b37 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
@@ -1,22 +1,17 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,aal.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Mediatek display adaptive ambient light processor
+title: Mediatek adaptive ambient light processor
 
 maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
+  - Matthias Brugger <matthias.bgg@gmail.com>
 
 description: |
-  Mediatek display adaptive ambient light processor, namely AAL,
+  Mediatek adaptive ambient light processor, namely AAL,
   is responsible for backlight power saving and sunlight visibility improving.
-  AAL device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
 
 properties:
   compatible:
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
index cf23f4f5bd69..c4db0b42cf86 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
@@ -10,17 +10,40 @@ maintainers:
   - Matthias Brugger <matthias.bgg@gmail.com>
 
 description: |
-  Mediatek color correction with 3X3 matrix.
+  Mediatek color correction, namely CCORR, reproduces correct color
+  on panels with 3X3 matrix of different color gamut.
 
 properties:
   compatible:
-    items:
-      - enum:
-          - mediatek,mt8183-mdp3-ccorr
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-mdp3-ccorr
+      - items:
+          - const: mediatek,mt8183-disp-ccorr
+      - items:
+          - const: mediatek,mt8192-disp-ccorr
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-ccorr
+          - enum:
+              - mediatek,mt8192-disp-ccorr
 
   reg:
     maxItems: 1
 
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: CCORR Clock
+    minItems: 1
+
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
       4 arguments defined in this property, such as phandle of gce, subsys id,
@@ -29,8 +52,10 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
-  clocks:
-    minItems: 1
+required:
+  - compatible
+  - reg
+  - clocks
 
 additionalProperties: false
 
@@ -45,3 +70,12 @@ examples:
       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
       clocks = <&mmsys CLK_MM_MDP_CCORR>;
     };
+
+    ccorr0: ccorr@1400f000 {
+        compatible = "mediatek,mt8183-disp-ccorr";
+        reg = <0 0x1400f000 0 0x1000>;
+        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
similarity index 78%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
index bc83155b3b4c..8f8b048a8407 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
@@ -1,23 +1,18 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,color.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Mediatek display color processor
+title: Mediatek color processor
 
 maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
+  - Matthias Brugger <matthias.bgg@gmail.com>
 
 description: |
-  Mediatek display color processor, namely COLOR, provides hue, luma and
-  saturation adjustments to get better picture quality and to have one panel
+  Mediatek color processor, namely COLOR, provides hue, luma and saturation
+  adjustments to get better picture quality and to have one panel
   resemble the other in their output characteristics.
-  COLOR device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
 
 properties:
   compatible:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
similarity index 80%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index 6eca525eced0..6e1d1ea377c4 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -1,25 +1,19 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mutex.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Mediatek mutex
 
 maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
+  - Matthias Brugger <matthias.bgg@gmail.com>
 
 description: |
   Mediatek mutex, namely MUTEX, is used to send the triggers signals called
-  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
-  data path or MDP data path.
+  Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules on the data path.
   In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
   the shadow register.
-  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
 
 properties:
   compatible:
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
index 4057b5232e45..7e5d1a6a79a9 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
@@ -15,13 +15,18 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - mediatek,mt8183-mdp3-wdma
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-mdp3-wdma
+      - items:
+          - const: mediatek,mt8173-disp-wdma
 
   reg:
     maxItems: 1
 
+  interrupts:
+    maxItems: 1
+
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
       4 arguments defined in this property, such as phandle of gce, subsys id,
@@ -31,14 +36,39 @@ properties:
     maxItems: 1
 
   power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
     maxItems: 1
 
   clocks:
+    items:
+      - description: WDMA Clock
     minItems: 1
 
   iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
     maxItems: 1
 
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommus
+
 additionalProperties: false
 
 examples:
@@ -56,3 +86,14 @@ examples:
       clocks = <&mmsys CLK_MM_MDP_WDMA0>;
       iommus = <&iommu>;
     };
+
+    wdma0: wdma@14011000 {
+        compatible = "mediatek,mt8173-disp-wdma";
+        reg = <0 0x14011000 0 0x1000>;
+        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+        mediatek,larb = <&larb0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+    };
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 07/12] dt-bindings: arm: mediatek: move out common module from display folder
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

AAL, COLOR, CCORR, MUTEX, WDMA could be used by other modules,
such as MDP, so move their binding document into the common folder.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 .../display/mediatek/mediatek,ccorr.yaml      | 76 ----------------
 .../display/mediatek/mediatek,wdma.yaml       | 86 -------------------
 .../mediatek/mediatek,aal.yaml                | 13 +--
 .../bindings/soc/mediatek/mediatek,ccorr.yaml | 46 ++++++++--
 .../mediatek/mediatek,color.yaml              | 15 ++--
 .../mediatek/mediatek,mutex.yaml              | 12 +--
 .../bindings/soc/mediatek/mediatek,wdma.yaml  | 47 +++++++++-
 7 files changed, 96 insertions(+), 199 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
 delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
 rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,aal.yaml (78%)
 rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,color.yaml (78%)
 rename Documentation/devicetree/bindings/{display => soc}/mediatek/mediatek,mutex.yaml (80%)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
deleted file mode 100644
index 6894b6999412..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ /dev/null
@@ -1,76 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mediatek display color correction
-
-maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
-
-description: |
-  Mediatek display color correction, namely CCORR, reproduces correct color
-  on panels with different color gamut.
-  CCORR device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
-
-properties:
-  compatible:
-    oneOf:
-      - items:
-          - const: mediatek,mt8183-disp-ccorr
-      - items:
-          - const: mediatek,mt8192-disp-ccorr
-      - items:
-          - enum:
-              - mediatek,mt8195-disp-ccorr
-          - enum:
-              - mediatek,mt8192-disp-ccorr
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  power-domains:
-    description: A phandle and PM domain specifier as defined by bindings of
-      the power controller specified by phandle. See
-      Documentation/devicetree/bindings/power/power-domain.yaml for details.
-
-  clocks:
-    items:
-      - description: CCORR Clock
-
-  mediatek,gce-client-reg:
-    description: The register of client driver can be configured by gce with
-      4 arguments defined in this property, such as phandle of gce, subsys id,
-      register offset and size. Each GCE subsys id is mapping to a client
-      defined in the header include/dt-bindings/gce/<chip>-gce.h.
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    maxItems: 1
-
-required:
-  - compatible
-  - reg
-  - interrupts
-  - power-domains
-  - clocks
-
-additionalProperties: false
-
-examples:
-  - |
-
-    ccorr0: ccorr@1400f000 {
-        compatible = "mediatek,mt8183-disp-ccorr";
-        reg = <0 0x1400f000 0 0x1000>;
-        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
-        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
-        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
-        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
-    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
deleted file mode 100644
index aaf5649b6413..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
+++ /dev/null
@@ -1,86 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Mediatek Write Direct Memory Access
-
-maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
-
-description: |
-  Mediatek Write Direct Memory Access(WDMA) component used to write
-  the data into DMA.
-  WDMA device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
-
-properties:
-  compatible:
-    oneOf:
-      - items:
-          - const: mediatek,mt8173-disp-wdma
-
-  reg:
-    maxItems: 1
-
-  interrupts:
-    maxItems: 1
-
-  power-domains:
-    description: A phandle and PM domain specifier as defined by bindings of
-      the power controller specified by phandle. See
-      Documentation/devicetree/bindings/power/power-domain.yaml for details.
-
-  clocks:
-    items:
-      - description: WDMA Clock
-
-  iommus:
-    description:
-      This property should point to the respective IOMMU block with master port as argument,
-      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
-
-  mediatek,larb:
-    description:
-      This property should contain a phandle pointing to the local arbiter devices defined in
-      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
-      It must sort according to the local arbiter index, like larb0, larb1, larb2...
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    minItems: 1
-    maxItems: 32
-
-  mediatek,gce-client-reg:
-    description: The register of client driver can be configured by gce with
-      4 arguments defined in this property, such as phandle of gce, subsys id,
-      register offset and size. Each GCE subsys id is mapping to a client
-      defined in the header include/dt-bindings/gce/<chip>-gce.h.
-    $ref: /schemas/types.yaml#/definitions/phandle-array
-    maxItems: 1
-
-required:
-  - compatible
-  - reg
-  - interrupts
-  - power-domains
-  - clocks
-  - iommus
-
-additionalProperties: false
-
-examples:
-  - |
-
-    wdma0: wdma@14011000 {
-        compatible = "mediatek,mt8173-disp-wdma";
-        reg = <0 0x14011000 0 0x1000>;
-        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
-        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
-        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
-        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
-        mediatek,larb = <&larb0>;
-        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
-    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
similarity index 78%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
index 225f9dd726d2..f9f57e073b37 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
@@ -1,22 +1,17 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,aal.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Mediatek display adaptive ambient light processor
+title: Mediatek adaptive ambient light processor
 
 maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
+  - Matthias Brugger <matthias.bgg@gmail.com>
 
 description: |
-  Mediatek display adaptive ambient light processor, namely AAL,
+  Mediatek adaptive ambient light processor, namely AAL,
   is responsible for backlight power saving and sunlight visibility improving.
-  AAL device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
 
 properties:
   compatible:
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
index cf23f4f5bd69..c4db0b42cf86 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
@@ -10,17 +10,40 @@ maintainers:
   - Matthias Brugger <matthias.bgg@gmail.com>
 
 description: |
-  Mediatek color correction with 3X3 matrix.
+  Mediatek color correction, namely CCORR, reproduces correct color
+  on panels with 3X3 matrix of different color gamut.
 
 properties:
   compatible:
-    items:
-      - enum:
-          - mediatek,mt8183-mdp3-ccorr
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-mdp3-ccorr
+      - items:
+          - const: mediatek,mt8183-disp-ccorr
+      - items:
+          - const: mediatek,mt8192-disp-ccorr
+      - items:
+          - enum:
+              - mediatek,mt8195-disp-ccorr
+          - enum:
+              - mediatek,mt8192-disp-ccorr
 
   reg:
     maxItems: 1
 
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  clocks:
+    items:
+      - description: CCORR Clock
+    minItems: 1
+
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
       4 arguments defined in this property, such as phandle of gce, subsys id,
@@ -29,8 +52,10 @@ properties:
     $ref: /schemas/types.yaml#/definitions/phandle-array
     maxItems: 1
 
-  clocks:
-    minItems: 1
+required:
+  - compatible
+  - reg
+  - clocks
 
 additionalProperties: false
 
@@ -45,3 +70,12 @@ examples:
       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
       clocks = <&mmsys CLK_MM_MDP_CCORR>;
     };
+
+    ccorr0: ccorr@1400f000 {
+        compatible = "mediatek,mt8183-disp-ccorr";
+        reg = <0 0x1400f000 0 0x1000>;
+        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+    };
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
similarity index 78%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
index bc83155b3b4c..8f8b048a8407 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
@@ -1,23 +1,18 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,color.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Mediatek display color processor
+title: Mediatek color processor
 
 maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
+  - Matthias Brugger <matthias.bgg@gmail.com>
 
 description: |
-  Mediatek display color processor, namely COLOR, provides hue, luma and
-  saturation adjustments to get better picture quality and to have one panel
+  Mediatek color processor, namely COLOR, provides hue, luma and saturation
+  adjustments to get better picture quality and to have one panel
   resemble the other in their output characteristics.
-  COLOR device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
 
 properties:
   compatible:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
similarity index 80%
rename from Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
rename to Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
index 6eca525eced0..6e1d1ea377c4 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
@@ -1,25 +1,19 @@
 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mutex.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Mediatek mutex
 
 maintainers:
-  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
-  - Philipp Zabel <p.zabel@pengutronix.de>
+  - Matthias Brugger <matthias.bgg@gmail.com>
 
 description: |
   Mediatek mutex, namely MUTEX, is used to send the triggers signals called
-  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
-  data path or MDP data path.
+  Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules on the data path.
   In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
   the shadow register.
-  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
-  For a description of the MMSYS_CONFIG binding, see
-  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
-  for details.
 
 properties:
   compatible:
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
index 4057b5232e45..7e5d1a6a79a9 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
@@ -15,13 +15,18 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - mediatek,mt8183-mdp3-wdma
+    oneOf:
+      - items:
+          - const: mediatek,mt8183-mdp3-wdma
+      - items:
+          - const: mediatek,mt8173-disp-wdma
 
   reg:
     maxItems: 1
 
+  interrupts:
+    maxItems: 1
+
   mediatek,gce-client-reg:
     description: The register of client driver can be configured by gce with
       4 arguments defined in this property, such as phandle of gce, subsys id,
@@ -31,14 +36,39 @@ properties:
     maxItems: 1
 
   power-domains:
+    description: A phandle and PM domain specifier as defined by bindings of
+      the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
     maxItems: 1
 
   clocks:
+    items:
+      - description: WDMA Clock
     minItems: 1
 
   iommus:
+    description:
+      This property should point to the respective IOMMU block with master port as argument,
+      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
     maxItems: 1
 
+  mediatek,larb:
+    description:
+      This property should contain a phandle pointing to the local arbiter devices defined in
+      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+      It must sort according to the local arbiter index, like larb0, larb1, larb2...
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 32
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - power-domains
+  - clocks
+  - iommus
+
 additionalProperties: false
 
 examples:
@@ -56,3 +86,14 @@ examples:
       clocks = <&mmsys CLK_MM_MDP_WDMA0>;
       iommus = <&iommu>;
     };
+
+    wdma0: wdma@14011000 {
+        compatible = "mediatek,mt8173-disp-wdma";
+        reg = <0 0x14011000 0 0x1000>;
+        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+        mediatek,larb = <&larb0>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+    };
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 08/12] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
This patch is base on [1]
[1] soc: mediatek: mmsys: add mt8192 mmsys support
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857

The vdosys1 impelmentation patch [2]
[2] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210906071539.12953-7-nancy.lin@mediatek.com/
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 130 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       |  11 +++
 include/linux/soc/mediatek/mtk-mmsys.h |   9 ++
 3 files changed, 150 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..24a3afe23bc8
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK			GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK			GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK			GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK			GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK			GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK			GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK				GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK				GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK			GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK			GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK			GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK			BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK			GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK			GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK				GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK		GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK			GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK			GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 5f79c7e039ad..5865d268c5b4 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -18,6 +18,7 @@
 #include "mt8167-mmsys.h"
 #include "mt8183-mmsys.h"
 #include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -66,6 +67,12 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
 	.clk_driver = "clk-mt8365-mm",
 	.routes = mt8365_mmsys_routing_table,
@@ -391,6 +398,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt8192-mmsys",
 		.data = &mt8192_mmsys_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &mt8195_vdosys0_driver_data,
+	},
 	{
 		.compatible = "mediatek,mt8365-mmsys",
 		.data = &mt8365_mmsys_driver_data,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 45e77d1cd6c1..c0ba22ad7229 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -23,13 +23,22 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DPI0,
 	DDP_COMPONENT_DPI1,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
 	DDP_COMPONENT_DSI0,
 	DDP_COMPONENT_DSI1,
 	DDP_COMPONENT_DSI2,
 	DDP_COMPONENT_DSI3,
 	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
 	DDP_COMPONENT_OD0,
 	DDP_COMPONENT_OD1,
 	DDP_COMPONENT_OVL0,
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 08/12] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
This patch is base on [1]
[1] soc: mediatek: mmsys: add mt8192 mmsys support
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857

The vdosys1 impelmentation patch [2]
[2] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210906071539.12953-7-nancy.lin@mediatek.com/
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 130 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       |  11 +++
 include/linux/soc/mediatek/mtk-mmsys.h |   9 ++
 3 files changed, 150 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..24a3afe23bc8
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK			GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK			GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK			GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK			GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK			GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK			GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK				GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK				GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK			GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK			GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK			GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK			BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK			GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK			GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK				GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK		GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK			GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK			GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 5f79c7e039ad..5865d268c5b4 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -18,6 +18,7 @@
 #include "mt8167-mmsys.h"
 #include "mt8183-mmsys.h"
 #include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -66,6 +67,12 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
 	.clk_driver = "clk-mt8365-mm",
 	.routes = mt8365_mmsys_routing_table,
@@ -391,6 +398,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
 		.compatible = "mediatek,mt8192-mmsys",
 		.data = &mt8192_mmsys_driver_data,
 	},
+	{
+		.compatible = "mediatek,mt8195-vdosys0",
+		.data = &mt8195_vdosys0_driver_data,
+	},
 	{
 		.compatible = "mediatek,mt8365-mmsys",
 		.data = &mt8365_mmsys_driver_data,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 45e77d1cd6c1..c0ba22ad7229 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -23,13 +23,22 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DPI0,
 	DDP_COMPONENT_DPI1,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
 	DDP_COMPONENT_DSI0,
 	DDP_COMPONENT_DSI1,
 	DDP_COMPONENT_DSI2,
 	DDP_COMPONENT_DSI3,
 	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
 	DDP_COMPONENT_OD0,
 	DDP_COMPONENT_OD1,
 	DDP_COMPONENT_OVL0,
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 09/12] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
This patch is base on [1]

[1] Add mmsys and mutex support for MDP
- https://patchwork.kernel.org/project/linux-mediatek/cover/20220104091712.25670-1-moudy.ho@mediatek.com/
---
 drivers/soc/mediatek/mtk-mutex.c | 103 ++++++++++++++++++++++++++++++-
 1 file changed, 100 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 615c42260a50..5bfea86aa8cf 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -21,6 +21,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -83,6 +86,36 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_OVL1		10
+#define MT8195_MUTEX_MOD_DISP_WDMA1		11
+#define MT8195_MUTEX_MOD_DISP_RDMA1		12
+#define MT8195_MUTEX_MOD_DISP_COLOR1		13
+#define MT8195_MUTEX_MOD_DISP_CCORR1		14
+#define MT8195_MUTEX_MOD_DISP_AAL1		15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
+#define MT8195_MUTEX_MOD_DISP_DITHER1		17
+#define MT8195_MUTEX_MOD_DISP_DSI1		18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+#define MT8195_MUTEX_MOD_DISP_PWM1		28
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -119,9 +152,21 @@
 #define MT8167_MUTEX_SOF_DPI1			3
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
 
 #define MT8183_MUTEX_MDP_START			5
 #define MT8183_MUTEX_MDP_MOD_MASK		0x07FFFFFF
@@ -148,6 +193,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -274,7 +322,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+	[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -284,7 +348,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -292,7 +356,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -306,6 +370,26 @@ static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
 	[MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
 };
 
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -355,6 +439,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
 	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -442,6 +533,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DPI1:
 		sof_id = MUTEX_SOF_DPI1;
 		break;
+	case DDP_COMPONENT_DP_INTF0:
+		sof_id = MUTEX_SOF_DP_INTF0;
+		break;
 	default:
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -481,6 +575,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DSI3:
 	case DDP_COMPONENT_DPI0:
 	case DDP_COMPONENT_DPI1:
+	case DDP_COMPONENT_DP_INTF0:
 		writel_relaxed(MUTEX_SOF_SINGLE_MODE,
 			       mtx->regs +
 			       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -678,6 +773,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8183_mutex_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = &mt8192_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 09/12] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
This patch is base on [1]

[1] Add mmsys and mutex support for MDP
- https://patchwork.kernel.org/project/linux-mediatek/cover/20220104091712.25670-1-moudy.ho@mediatek.com/
---
 drivers/soc/mediatek/mtk-mutex.c | 103 ++++++++++++++++++++++++++++++-
 1 file changed, 100 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 615c42260a50..5bfea86aa8cf 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -21,6 +21,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -83,6 +86,36 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_OVL1		10
+#define MT8195_MUTEX_MOD_DISP_WDMA1		11
+#define MT8195_MUTEX_MOD_DISP_RDMA1		12
+#define MT8195_MUTEX_MOD_DISP_COLOR1		13
+#define MT8195_MUTEX_MOD_DISP_CCORR1		14
+#define MT8195_MUTEX_MOD_DISP_AAL1		15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1		16
+#define MT8195_MUTEX_MOD_DISP_DITHER1		17
+#define MT8195_MUTEX_MOD_DISP_DSI1		18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1	19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0	22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1	23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2	24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3	25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4	26
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+#define MT8195_MUTEX_MOD_DISP_PWM1		28
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -119,9 +152,21 @@
 #define MT8167_MUTEX_SOF_DPI1			3
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
 
 #define MT8183_MUTEX_MDP_START			5
 #define MT8183_MUTEX_MDP_MOD_MASK		0x07FFFFFF
@@ -148,6 +193,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -274,7 +322,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+	[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -284,7 +348,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -292,7 +356,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -306,6 +370,26 @@ static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
 	[MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
 };
 
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -355,6 +439,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
 	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -442,6 +533,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DPI1:
 		sof_id = MUTEX_SOF_DPI1;
 		break;
+	case DDP_COMPONENT_DP_INTF0:
+		sof_id = MUTEX_SOF_DP_INTF0;
+		break;
 	default:
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -481,6 +575,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DSI3:
 	case DDP_COMPONENT_DPI0:
 	case DDP_COMPONENT_DPI1:
+	case DDP_COMPONENT_DP_INTF0:
 		writel_relaxed(MUTEX_SOF_SINGLE_MODE,
 			       mtx->regs +
 			       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -678,6 +773,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8183_mutex_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = &mt8192_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 10/12] drm/mediatek: add DSC support for mediatek-drm
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
rebase on series [1]

[1] drm/mediatek: add support for mediatek SOC MT8192
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b4b682bc1991..90b289b5f9a4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* write with mask to reserve the value set in mtk_dsc_config */
+	mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]		= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 4c6a98662305..5e6ff12f16ad 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 10/12] drm/mediatek: add DSC support for mediatek-drm
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
rebase on series [1]

[1] drm/mediatek: add support for mediatek SOC MT8192
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b4b682bc1991..90b289b5f9a4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* write with mask to reserve the value set in mtk_dsc_config */
+	mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]		= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 4c6a98662305..5e6ff12f16ad 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 11/12] drm/mediatek: add MERGE support for mediatek-drm
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
rebase on series [1]

[1] drm/mediatek: add support for mediatek SOC MT8192
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 246 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 7 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN				1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE				0
+#define FLD_SWAP_MODE				GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE		6
+#define CFG_10_10_2PI_2PO_BUF_MODE		8
+#define FLD_CFG_MERGE_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN				BIT(0)
+#define PREULTRA_EN				BIT(4)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE				3
+#define FLD_BUFFER_MODE				GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW				(6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH				(8 * 594)
+#define FLD_ULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH			GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW				(8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH			(9 * 594)
+#define FLD_PREULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH			GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem			*regs;
+	struct clk			*clk;
+	struct clk			*async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *cmdq_pkt)
+{
+	mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+		      &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+	mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, cmdq_pkt);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "merge clk prepare enable failed\n");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(priv->async_clk);
+	if (ret) {
+		/* should clean up the state of priv->clk */
+		clk_disable_unprepare(priv->clk);
+
+		dev_err(dev, "async clk prepare enable failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(priv->async_clk);
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+	if (IS_ERR(priv->async_clk)) {
+		dev_err(dev, "failed to get merge async clock\n");
+		return PTR_ERR(priv->async_clk);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 90b289b5f9a4..26d197da41c0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]		= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]		= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]		= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]		= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]		= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]		= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -555,6 +570,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 5e6ff12f16ad..221e2e3a3c8d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 56ff8c57ef8f..2f33fe8ad46b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -599,7 +599,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
@@ -607,6 +607,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -708,6 +709,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 11/12] drm/mediatek: add MERGE support for mediatek-drm
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
rebase on series [1]

[1] drm/mediatek: add support for mediatek SOC MT8192
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 246 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 7 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN				1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE				0
+#define FLD_SWAP_MODE				GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE		6
+#define CFG_10_10_2PI_2PO_BUF_MODE		8
+#define FLD_CFG_MERGE_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN				BIT(0)
+#define PREULTRA_EN				BIT(4)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE				3
+#define FLD_BUFFER_MODE				GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW				(6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH				(8 * 594)
+#define FLD_ULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH			GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW				(8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH			(9 * 594)
+#define FLD_PREULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH			GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem			*regs;
+	struct clk			*clk;
+	struct clk			*async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *cmdq_pkt)
+{
+	mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+		      &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+	mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, cmdq_pkt);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "merge clk prepare enable failed\n");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(priv->async_clk);
+	if (ret) {
+		/* should clean up the state of priv->clk */
+		clk_disable_unprepare(priv->clk);
+
+		dev_err(dev, "async clk prepare enable failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(priv->async_clk);
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+	if (IS_ERR(priv->async_clk)) {
+		dev_err(dev, "failed to get merge async clock\n");
+		return PTR_ERR(priv->async_clk);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 90b289b5f9a4..26d197da41c0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]		= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]		= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]		= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]		= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]		= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]		= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -555,6 +570,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 5e6ff12f16ad..221e2e3a3c8d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 56ff8c57ef8f..2f33fe8ad46b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -599,7 +599,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
@@ -607,6 +607,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -708,6 +709,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
2.18.0


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 12/12] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-01-26  7:19   ` jason-jh.lin
  -1 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
rebase on series [1]

[1] drm/mediatek: add support for mediatek SOC MT8192
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index d41a3970b944..77c952bdc88c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -357,6 +357,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -366,6 +370,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8183_rdma_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = &mt8192_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 2f33fe8ad46b..274a5bb10851 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -177,6 +177,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -228,6 +241,11 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -447,12 +465,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8167-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -465,6 +487,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -499,6 +523,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -535,6 +561,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8183_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
+	{.compatible = "mediatek,mt8195-vdosys0",
+	  .data = &mt8195_vdosys0_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* [PATCH v15 12/12] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-01-26  7:19   ` jason-jh.lin
  0 siblings, 0 replies; 65+ messages in thread
From: jason-jh.lin @ 2022-01-26  7:19 UTC (permalink / raw)
  To: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, linux-kernel, CK Hu, moudy.ho, linux-mediatek,
	Daniel Vetter, hsinyi, Enric Balletbo i Serra, nancy.lin,
	linux-stm32, linux-arm-kernel

Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
rebase on series [1]

[1] drm/mediatek: add support for mediatek SOC MT8192
- https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 +++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 28 ++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index d41a3970b944..77c952bdc88c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -357,6 +357,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -366,6 +370,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8183_rdma_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = &mt8192_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 2f33fe8ad46b..274a5bb10851 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -177,6 +177,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -228,6 +241,11 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -447,12 +465,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8167-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -465,6 +487,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -499,6 +523,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -535,6 +561,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8183_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
+	{.compatible = "mediatek,mt8195-vdosys0",
+	  .data = &mt8195_vdosys0_driver_data},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 10/12] drm/mediatek: add DSC support for mediatek-drm
  2022-01-26  7:19   ` jason-jh.lin
  (?)
@ 2022-01-27 10:27     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-27 10:27 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
	Philipp Zabel
  Cc: Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
	Jitao shi, nancy.lin, singo.chang, devicetree, linux-stm32,
	linux-arm-kernel, linux-mediatek, linux-kernel

Il 26/01/22 08:19, jason-jh.lin ha scritto:
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 10/12] drm/mediatek: add DSC support for mediatek-drm
@ 2022-01-27 10:27     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-27 10:27 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
	Philipp Zabel
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	linux-kernel, singo.chang, Alexandre Torgue, roy-cw.yeh,
	Fabien Parent, moudy.ho, linux-mediatek, Daniel Vetter, hsinyi,
	CK Hu, nancy.lin, linux-stm32, linux-arm-kernel

Il 26/01/22 08:19, jason-jh.lin ha scritto:
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 10/12] drm/mediatek: add DSC support for mediatek-drm
@ 2022-01-27 10:27     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-01-27 10:27 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Matthias Brugger, Chun-Kuang Hu,
	Philipp Zabel
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	linux-kernel, singo.chang, Alexandre Torgue, roy-cw.yeh,
	Fabien Parent, moudy.ho, linux-mediatek, Daniel Vetter, hsinyi,
	CK Hu, nancy.lin, linux-stm32, linux-arm-kernel

Il 26/01/22 08:19, jason-jh.lin ha scritto:
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
> 
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

_______________________________________________
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^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
  2022-01-26  7:19   ` jason-jh.lin
@ 2022-01-27 15:46     ` Chun-Kuang Hu
  -1 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-01-27 15:46 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent, DTML,
	Nancy Lin, linux-stm32, roy-cw.yeh, CK Hu, Chun-Kuang Hu,
	Jitao shi, Philipp Zabel, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Maxime Coquelin, Enric Balletbo i Serra

Hi, Rob:

This patch looks good to me, how do you think about it?

Regards,
Chun-Kuang.

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> 1. Remove mediatek,dislpay.txt
> 2. Split each display function block to individual yaml file.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../display/mediatek/mediatek,aal.yaml        |  76 ++++++
>  .../display/mediatek/mediatek,ccorr.yaml      |  71 ++++++
>  .../display/mediatek/mediatek,color.yaml      |  85 +++++++
>  .../display/mediatek/mediatek,disp.txt        | 219 ------------------
>  .../display/mediatek/mediatek,dither.yaml     |  75 ++++++
>  .../display/mediatek/mediatek,gamma.yaml      |  76 ++++++
>  .../display/mediatek/mediatek,merge.yaml      |  66 ++++++
>  .../display/mediatek/mediatek,mutex.yaml      |  82 +++++++
>  .../display/mediatek/mediatek,od.yaml         |  53 +++++
>  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
>  .../display/mediatek/mediatek,ovl.yaml        |  98 ++++++++
>  .../display/mediatek/mediatek,postmask.yaml   |  69 ++++++
>  .../display/mediatek/mediatek,rdma.yaml       | 115 +++++++++
>  .../display/mediatek/mediatek,split.yaml      |  58 +++++
>  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
>  .../display/mediatek/mediatek,wdma.yaml       |  86 +++++++
>  16 files changed, 1159 insertions(+), 219 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
>  delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> new file mode 100644
> index 000000000000..044331f5aacb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display adaptive ambient light processor
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display adaptive ambient light processor, namely AAL,
> +  is responsible for backlight power saving and sunlight visibility improving.
> +  AAL device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-aal
> +      - items:
> +          - enum:
> +              - mediatek,mt2712-disp-aal
> +              - mediatek,mt8183-disp-aal
> +              - mediatek,mt8192-disp-aal
> +          - enum:
> +              - mediatek,mt8173-disp-aal
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: AAL Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    aal@14015000 {
> +        compatible = "mediatek,mt8173-disp-aal";
> +        reg = <0 0x14015000 0 0x1000>;
> +        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_AAL>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> new file mode 100644
> index 000000000000..ea45b40edee7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display color correction
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display color correction, namely CCORR, reproduces correct color
> +  on panels with different color gamut.
> +  CCORR device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8183-disp-ccorr
> +      - items:
> +          - const: mediatek,mt8192-disp-ccorr
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: CCORR Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    ccorr0: ccorr@1400f000 {
> +        compatible = "mediatek,mt8183-disp-ccorr";
> +        reg = <0 0x1400f000 0 0x1000>;
> +        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> new file mode 100644
> index 000000000000..13628f346718
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display color processor
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display color processor, namely COLOR, provides hue, luma and
> +  saturation adjustments to get better picture quality and to have one panel
> +  resemble the other in their output characteristics.
> +  COLOR device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2701-disp-color
> +      - items:
> +          - const: mediatek,mt8167-disp-color
> +      - items:
> +          - const: mediatek,mt8173-disp-color
> +      - items:
> +          - enum:
> +              - mediatek,mt7623-disp-color
> +              - mediatek,mt2712-disp-color
> +          - enum:
> +              - mediatek,mt2701-disp-color
> +      - items:
> +          - enum:
> +              - mediatek,mt8183-disp-color
> +              - mediatek,mt8192-disp-color
> +          - enum:
> +              - mediatek,mt8173-disp-color
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: COLOR Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    color0: color@14013000 {
> +        compatible = "mediatek,mt8173-disp-color";
> +        reg = <0 0x14013000 0 0x1000>;
> +        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> deleted file mode 100644
> index 78044c340e20..000000000000
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ /dev/null
> @@ -1,219 +0,0 @@
> -Mediatek display subsystem
> -==========================
> -
> -The Mediatek display subsystem consists of various DISP function blocks in the
> -MMSYS register space. The connections between them can be configured by output
> -and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
> -of frame signal are distributed to the other function blocks by a DISP_MUTEX
> -function block.
> -
> -All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
> -For a description of the MMSYS_CONFIG binding, see
> -Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
> -
> -DISP function blocks
> -====================
> -
> -A display stream starts at a source function block that reads pixel data from
> -memory and ends with a sink function block that drives pixels on a display
> -interface, or writes pixels back to memory. All DISP function blocks have
> -their own register space, interrupt, and clock gate. The blocks that can
> -access memory additionally have to list the IOMMU and local arbiter they are
> -connected to.
> -
> -For a description of the display interface sink function blocks, see
> -Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
> -Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
> -
> -Required properties (all function blocks):
> -- compatible: "mediatek,<chip>-disp-<function>", one of
> -       "mediatek,<chip>-disp-ovl"              - overlay (4 layers, blending, csc)
> -       "mediatek,<chip>-disp-ovl-2l"           - overlay (2 layers, blending, csc)
> -       "mediatek,<chip>-disp-rdma"             - read DMA / line buffer
> -       "mediatek,<chip>-disp-wdma"             - write DMA
> -       "mediatek,<chip>-disp-ccorr"            - color correction
> -       "mediatek,<chip>-disp-color"            - color processor
> -       "mediatek,<chip>-disp-dither"           - dither
> -       "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
> -       "mediatek,<chip>-disp-gamma"            - gamma correction
> -       "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> -       "mediatek,<chip>-disp-postmask"         - control round corner for display frame
> -       "mediatek,<chip>-disp-split"            - split stream to two encoders
> -       "mediatek,<chip>-disp-ufoe"             - data compression engine
> -       "mediatek,<chip>-dsi"                   - DSI controller, see mediatek,dsi.txt
> -       "mediatek,<chip>-dpi"                   - DPI controller, see mediatek,dpi.txt
> -       "mediatek,<chip>-disp-mutex"            - display mutex
> -       "mediatek,<chip>-disp-od"               - overdrive
> -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> -- reg: Physical base address and length of the function block register space
> -- interrupts: The interrupt signal from the function block (required, except for
> -  merge and split function blocks).
> -- clocks: device clocks
> -  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> -  For most function blocks this is just a single clock input. Only the DSI and
> -  DPI controller nodes have multiple clock inputs. These are documented in
> -  mediatek,dsi.txt and mediatek,dpi.txt, respectively.
> -  An exception is that the mt8183 mutex is always free running with no clocks property.
> -
> -Required properties (DMA function blocks):
> -- compatible: Should be one of
> -       "mediatek,<chip>-disp-ovl"
> -       "mediatek,<chip>-disp-rdma"
> -       "mediatek,<chip>-disp-wdma"
> -  the supported chips are mt2701, mt8167 and mt8173.
> -- larb: Should contain a phandle pointing to the local arbiter device as defined
> -  in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> -- iommus: Should point to the respective IOMMU block with master port as
> -  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> -  for details.
> -
> -Optional properties (RDMA function blocks):
> -- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
> -  property to the corresponding rdma
> -  the value is the Max value which defined in hardware data sheet.
> -  mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> -  mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> -  mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> -
> -Examples:
> -
> -mmsys: clock-controller@14000000 {
> -       compatible = "mediatek,mt8173-mmsys", "syscon";
> -       reg = <0 0x14000000 0 0x1000>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       #clock-cells = <1>;
> -};
> -
> -ovl0: ovl@1400c000 {
> -       compatible = "mediatek,mt8173-disp-ovl";
> -       reg = <0 0x1400c000 0 0x1000>;
> -       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_OVL0>;
> -       iommus = <&iommu M4U_PORT_DISP_OVL0>;
> -       mediatek,larb = <&larb0>;
> -};
> -
> -ovl1: ovl@1400d000 {
> -       compatible = "mediatek,mt8173-disp-ovl";
> -       reg = <0 0x1400d000 0 0x1000>;
> -       interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_OVL1>;
> -       iommus = <&iommu M4U_PORT_DISP_OVL1>;
> -       mediatek,larb = <&larb4>;
> -};
> -
> -rdma0: rdma@1400e000 {
> -       compatible = "mediatek,mt8173-disp-rdma";
> -       reg = <0 0x1400e000 0 0x1000>;
> -       interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> -       iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> -       mediatek,larb = <&larb0>;
> -       mediatek,rdma-fifosize = <8192>;
> -};
> -
> -rdma1: rdma@1400f000 {
> -       compatible = "mediatek,mt8173-disp-rdma";
> -       reg = <0 0x1400f000 0 0x1000>;
> -       interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> -       iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> -       mediatek,larb = <&larb4>;
> -};
> -
> -rdma2: rdma@14010000 {
> -       compatible = "mediatek,mt8173-disp-rdma";
> -       reg = <0 0x14010000 0 0x1000>;
> -       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> -       iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> -       mediatek,larb = <&larb4>;
> -};
> -
> -wdma0: wdma@14011000 {
> -       compatible = "mediatek,mt8173-disp-wdma";
> -       reg = <0 0x14011000 0 0x1000>;
> -       interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> -       iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> -       mediatek,larb = <&larb0>;
> -};
> -
> -wdma1: wdma@14012000 {
> -       compatible = "mediatek,mt8173-disp-wdma";
> -       reg = <0 0x14012000 0 0x1000>;
> -       interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> -       iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> -       mediatek,larb = <&larb4>;
> -};
> -
> -color0: color@14013000 {
> -       compatible = "mediatek,mt8173-disp-color";
> -       reg = <0 0x14013000 0 0x1000>;
> -       interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> -};
> -
> -color1: color@14014000 {
> -       compatible = "mediatek,mt8173-disp-color";
> -       reg = <0 0x14014000 0 0x1000>;
> -       interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> -};
> -
> -aal@14015000 {
> -       compatible = "mediatek,mt8173-disp-aal";
> -       reg = <0 0x14015000 0 0x1000>;
> -       interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_AAL>;
> -};
> -
> -gamma@14016000 {
> -       compatible = "mediatek,mt8173-disp-gamma";
> -       reg = <0 0x14016000 0 0x1000>;
> -       interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> -};
> -
> -ufoe@1401a000 {
> -       compatible = "mediatek,mt8173-disp-ufoe";
> -       reg = <0 0x1401a000 0 0x1000>;
> -       interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_UFOE>;
> -};
> -
> -dsi0: dsi@1401b000 {
> -       /* See mediatek,dsi.txt for details */
> -};
> -
> -dpi0: dpi@1401d000 {
> -       /* See mediatek,dpi.txt for details */
> -};
> -
> -mutex: mutex@14020000 {
> -       compatible = "mediatek,mt8173-disp-mutex";
> -       reg = <0 0x14020000 0 0x1000>;
> -       interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_MUTEX_32K>;
> -};
> -
> -od@14023000 {
> -       compatible = "mediatek,mt8173-disp-od";
> -       reg = <0 0x14023000 0 0x1000>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_OD>;
> -};
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> new file mode 100644
> index 000000000000..2c05e3019c75
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> @@ -0,0 +1,75 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display dither processor
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display dither processor, namely DITHER, works by approximating
> +  unavailable colors with available colors and by mixing and matching available
> +  colors to mimic unavailable ones.
> +  DITHER device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8183-disp-dither
> +      - items:
> +          - enum:
> +              - mediatek,mt8192-disp-dither
> +          - enum:
> +              - mediatek,mt8183-disp-dither
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: DITHER Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    dither0: dither@14012000 {
> +        compatible = "mediatek,mt8183-disp-dither";
> +        reg = <0 0x14012000 0 0x1000>;
> +        interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +        clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> new file mode 100644
> index 000000000000..89ccb8dbadd7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display gamma correction
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display gamma correction, namely GAMMA, provides a nonlinear
> +  operation used to adjust luminance in display system.
> +  GAMMA device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-gamma
> +      - items:
> +          - const: mediatek,mt8183-disp-gamma
> +      - items:
> +          - enum:
> +              - mediatek,mt8192-disp-gamma
> +          - enum:
> +              - mediatek,mt8183-disp-gamma
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: GAMMA Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    gamma@14016000 {
> +        compatible = "mediatek,mt8173-disp-gamma";
> +        reg = <0 0x14016000 0 0x1000>;
> +        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> new file mode 100644
> index 000000000000..7aa6974d509d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display merge
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
> +  inputs into one side-by-side output.
> +  MERGE device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-merge
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: MERGE Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    merge@14017000 {
> +        compatible = "mediatek,mt8173-disp-merge";
> +        reg = <0 0x14017000 0 0x1000>;
> +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_MERGE>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> new file mode 100644
> index 000000000000..90f11e12a55e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display mutex
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
> +  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
> +  data path or MDP data path.
> +  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
> +  the shadow register.
> +  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2701-disp-mutex
> +      - items:
> +          - const: mediatek,mt2712-disp-mutex
> +      - items:
> +          - const: mediatek,mt8167-disp-mutex
> +      - items:
> +          - const: mediatek,mt8173-disp-mutex
> +      - items:
> +          - const: mediatek,mt8183-disp-mutex
> +      - items:
> +          - const: mediatek,mt8192-disp-mutex
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: MUTEX Clock
> +
> +  mediatek,gce-events:
> +    description:
> +      The event id which is mapping to the specific hardware event signal
> +      to gce. The event id is defined in the gce header
> +      include/dt-bindings/gce/<chip>-gce.h of each chips.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    mutex: mutex@14020000 {
> +        compatible = "mediatek,mt8173-disp-mutex";
> +        reg = <0 0x14020000 0 0x1000>;
> +        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_MUTEX_32K>;
> +        mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> +                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> new file mode 100644
> index 000000000000..7519db315217
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display overdirve
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display overdrive, namely OD, increases the transition values
> +  of pixels between consecutive frames to make LCD rotate faster.
> +  OD device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2712-disp-od
> +      - items:
> +          - const: mediatek,mt8173-disp-od
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: OD Clock
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    od@14023000 {
> +        compatible = "mediatek,mt8173-disp-od";
> +        reg = <0 0x14023000 0 0x1000>;
> +        clocks = <&mmsys CLK_MM_DISP_OD>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> new file mode 100644
> index 000000000000..611a2dbdefa4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display overlay 2 layer
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
> +  for OVL.
> +  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8183-disp-ovl-2l
> +      - items:
> +          - const: mediatek,mt8192-disp-ovl-2l
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: OVL-2L Clock
> +
> +  iommus:
> +    description:
> +      This property should point to the respective IOMMU block with master port as argument,
> +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> +  mediatek,larb:
> +    description:
> +      This property should contain a phandle pointing to the local arbiter devices defined in
> +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    ovl_2l0: ovl@14009000 {
> +        compatible = "mediatek,mt8183-disp-ovl-2l";
> +        reg = <0 0x14009000 0 0x1000>;
> +        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +        clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +        iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
> +        mediatek,larb = <&larb0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> new file mode 100644
> index 000000000000..8e4a62cb9c81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display overlay
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display overlay, namely OVL, can do alpha blending from
> +  the memory.
> +  OVL device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2701-disp-ovl
> +      - items:
> +          - const: mediatek,mt8173-disp-ovl
> +      - items:
> +          - const: mediatek,mt8183-disp-ovl
> +      - items:
> +          - const: mediatek,mt8192-disp-ovl
> +      - items:
> +          - enum:
> +              - mediatek,mt7623-disp-ovl
> +              - mediatek,mt2712-disp-ovl
> +          - enum:
> +              - mediatek,mt2701-disp-ovl
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: OVL Clock
> +
> +  iommus:
> +    description:
> +      This property should point to the respective IOMMU block with master port as argument,
> +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> +  mediatek,larb:
> +    description:
> +      This property should contain a phandle pointing to the local arbiter devices defined in
> +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - iommu
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    ovl0: ovl@1400c000 {
> +        compatible = "mediatek,mt8173-disp-ovl";
> +        reg = <0 0x1400c000 0 0x1000>;
> +        interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +        iommus = <&iommu M4U_PORT_DISP_OVL0>;
> +        mediatek,larb = <&larb0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> new file mode 100644
> index 000000000000..6ac1da2e8871
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display postmask
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display postmask, namely POSTMASK, provides round corner pattern
> +  generation.
> +  POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8192-disp-postmask
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: POSTMASK Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    postmask0: postmask@1400d000 {
> +        compatible = "mediatek,mt8192-disp-postmask";
> +        reg = <0 0x1400d000 0 0x1000>;
> +        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> +        power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +        clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> new file mode 100644
> index 000000000000..a3c5f4c9fbcd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Read Direct Memory Access
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek Read Direct Memory Access(RDMA) component used to read the
> +  data into DMA. It provides real time data to the back-end panel
> +  driver, such as DSI, DPI and DP_INTF.
> +  It contains one line buffer to store the sufficient pixel data.
> +  RDMA device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2701-disp-rdma
> +      - items:
> +          - const: mediatek,mt8173-disp-rdma
> +      - items:
> +          - const: mediatek,mt8183-disp-rdma
> +      - items:
> +          - enum:
> +              - mediatek,mt7623-disp-rdma
> +              - mediatek,mt2712-disp-rdma
> +          - enum:
> +              - mediatek,mt2701-disp-rdma
> +      - items:
> +          - enum:
> +              - mediatek,mt8192-disp-rdma
> +          - enum:
> +              - mediatek,mt8183-disp-rdma
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: RDMA Clock
> +
> +  iommus:
> +    description:
> +      This property should point to the respective IOMMU block with master port as argument,
> +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> +  mediatek,larb:
> +    description:
> +      This property should contain a phandle pointing to the local arbiter devices defined in
> +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  mediatek,rdma-fifo-size:
> +    description:
> +      rdma fifo size may be different even in same SOC, add this property to the
> +      corresponding rdma.
> +      The value below is the Max value which defined in hardware data sheet
> +      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> +      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> +      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [8192, 5120, 2048]
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    rdma0: rdma@1400e000 {
> +        compatible = "mediatek,mt8173-disp-rdma";
> +        reg = <0 0x1400e000 0 0x1000>;
> +        interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> +        mediatek,larb = <&larb0>;
> +        mediatek,rdma-fifosize = <8192>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> new file mode 100644
> index 000000000000..4f08e89c1067
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display split
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display split, namely SPLIT, is used to split stream to two
> +  encoders.
> +  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-split
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: SPLIT Clock
> +
> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    split0: split@14018000 {
> +        compatible = "mediatek,mt8173-disp-split";
> +        reg = <0 0x14018000 0 0x1000>;
> +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> new file mode 100644
> index 000000000000..6e8748529e73
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display UFOe
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display UFOe stands for Unified Frame Optimization engine.
> +  UFOe can cut the data rate for DSI port which may lead to reduce power
> +  consumption.
> +  UFOe device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-ufoe
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: UFOe Clock
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    ufoe@1401a000 {
> +        compatible = "mediatek,mt8173-disp-ufoe";
> +        reg = <0 0x1401a000 0 0x1000>;
> +        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_UFOE>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> new file mode 100644
> index 000000000000..aaf5649b6413
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> @@ -0,0 +1,86 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Write Direct Memory Access
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek Write Direct Memory Access(WDMA) component used to write
> +  the data into DMA.
> +  WDMA device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-wdma
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: WDMA Clock
> +
> +  iommus:
> +    description:
> +      This property should point to the respective IOMMU block with master port as argument,
> +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> +  mediatek,larb:
> +    description:
> +      This property should contain a phandle pointing to the local arbiter devices defined in
> +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    wdma0: wdma@14011000 {
> +        compatible = "mediatek,mt8173-disp-wdma";
> +        reg = <0 0x14011000 0 0x1000>;
> +        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> +        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> +        mediatek,larb = <&larb0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> +    };
> --
> 2.18.0
>

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^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
@ 2022-01-27 15:46     ` Chun-Kuang Hu
  0 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-01-27 15:46 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent, DTML,
	Nancy Lin, linux-stm32, roy-cw.yeh, CK Hu, Chun-Kuang Hu,
	Jitao shi, Philipp Zabel, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Maxime Coquelin, Enric Balletbo i Serra

Hi, Rob:

This patch looks good to me, how do you think about it?

Regards,
Chun-Kuang.

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> 1. Remove mediatek,dislpay.txt
> 2. Split each display function block to individual yaml file.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../display/mediatek/mediatek,aal.yaml        |  76 ++++++
>  .../display/mediatek/mediatek,ccorr.yaml      |  71 ++++++
>  .../display/mediatek/mediatek,color.yaml      |  85 +++++++
>  .../display/mediatek/mediatek,disp.txt        | 219 ------------------
>  .../display/mediatek/mediatek,dither.yaml     |  75 ++++++
>  .../display/mediatek/mediatek,gamma.yaml      |  76 ++++++
>  .../display/mediatek/mediatek,merge.yaml      |  66 ++++++
>  .../display/mediatek/mediatek,mutex.yaml      |  82 +++++++
>  .../display/mediatek/mediatek,od.yaml         |  53 +++++
>  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
>  .../display/mediatek/mediatek,ovl.yaml        |  98 ++++++++
>  .../display/mediatek/mediatek,postmask.yaml   |  69 ++++++
>  .../display/mediatek/mediatek,rdma.yaml       | 115 +++++++++
>  .../display/mediatek/mediatek,split.yaml      |  58 +++++
>  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
>  .../display/mediatek/mediatek,wdma.yaml       |  86 +++++++
>  16 files changed, 1159 insertions(+), 219 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
>  delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> new file mode 100644
> index 000000000000..044331f5aacb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display adaptive ambient light processor
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display adaptive ambient light processor, namely AAL,
> +  is responsible for backlight power saving and sunlight visibility improving.
> +  AAL device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-aal
> +      - items:
> +          - enum:
> +              - mediatek,mt2712-disp-aal
> +              - mediatek,mt8183-disp-aal
> +              - mediatek,mt8192-disp-aal
> +          - enum:
> +              - mediatek,mt8173-disp-aal
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: AAL Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    aal@14015000 {
> +        compatible = "mediatek,mt8173-disp-aal";
> +        reg = <0 0x14015000 0 0x1000>;
> +        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_AAL>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> new file mode 100644
> index 000000000000..ea45b40edee7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display color correction
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display color correction, namely CCORR, reproduces correct color
> +  on panels with different color gamut.
> +  CCORR device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8183-disp-ccorr
> +      - items:
> +          - const: mediatek,mt8192-disp-ccorr
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: CCORR Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    ccorr0: ccorr@1400f000 {
> +        compatible = "mediatek,mt8183-disp-ccorr";
> +        reg = <0 0x1400f000 0 0x1000>;
> +        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> new file mode 100644
> index 000000000000..13628f346718
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display color processor
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display color processor, namely COLOR, provides hue, luma and
> +  saturation adjustments to get better picture quality and to have one panel
> +  resemble the other in their output characteristics.
> +  COLOR device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2701-disp-color
> +      - items:
> +          - const: mediatek,mt8167-disp-color
> +      - items:
> +          - const: mediatek,mt8173-disp-color
> +      - items:
> +          - enum:
> +              - mediatek,mt7623-disp-color
> +              - mediatek,mt2712-disp-color
> +          - enum:
> +              - mediatek,mt2701-disp-color
> +      - items:
> +          - enum:
> +              - mediatek,mt8183-disp-color
> +              - mediatek,mt8192-disp-color
> +          - enum:
> +              - mediatek,mt8173-disp-color
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: COLOR Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    color0: color@14013000 {
> +        compatible = "mediatek,mt8173-disp-color";
> +        reg = <0 0x14013000 0 0x1000>;
> +        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> deleted file mode 100644
> index 78044c340e20..000000000000
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ /dev/null
> @@ -1,219 +0,0 @@
> -Mediatek display subsystem
> -==========================
> -
> -The Mediatek display subsystem consists of various DISP function blocks in the
> -MMSYS register space. The connections between them can be configured by output
> -and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
> -of frame signal are distributed to the other function blocks by a DISP_MUTEX
> -function block.
> -
> -All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
> -For a description of the MMSYS_CONFIG binding, see
> -Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
> -
> -DISP function blocks
> -====================
> -
> -A display stream starts at a source function block that reads pixel data from
> -memory and ends with a sink function block that drives pixels on a display
> -interface, or writes pixels back to memory. All DISP function blocks have
> -their own register space, interrupt, and clock gate. The blocks that can
> -access memory additionally have to list the IOMMU and local arbiter they are
> -connected to.
> -
> -For a description of the display interface sink function blocks, see
> -Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
> -Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
> -
> -Required properties (all function blocks):
> -- compatible: "mediatek,<chip>-disp-<function>", one of
> -       "mediatek,<chip>-disp-ovl"              - overlay (4 layers, blending, csc)
> -       "mediatek,<chip>-disp-ovl-2l"           - overlay (2 layers, blending, csc)
> -       "mediatek,<chip>-disp-rdma"             - read DMA / line buffer
> -       "mediatek,<chip>-disp-wdma"             - write DMA
> -       "mediatek,<chip>-disp-ccorr"            - color correction
> -       "mediatek,<chip>-disp-color"            - color processor
> -       "mediatek,<chip>-disp-dither"           - dither
> -       "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
> -       "mediatek,<chip>-disp-gamma"            - gamma correction
> -       "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> -       "mediatek,<chip>-disp-postmask"         - control round corner for display frame
> -       "mediatek,<chip>-disp-split"            - split stream to two encoders
> -       "mediatek,<chip>-disp-ufoe"             - data compression engine
> -       "mediatek,<chip>-dsi"                   - DSI controller, see mediatek,dsi.txt
> -       "mediatek,<chip>-dpi"                   - DPI controller, see mediatek,dpi.txt
> -       "mediatek,<chip>-disp-mutex"            - display mutex
> -       "mediatek,<chip>-disp-od"               - overdrive
> -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> -- reg: Physical base address and length of the function block register space
> -- interrupts: The interrupt signal from the function block (required, except for
> -  merge and split function blocks).
> -- clocks: device clocks
> -  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> -  For most function blocks this is just a single clock input. Only the DSI and
> -  DPI controller nodes have multiple clock inputs. These are documented in
> -  mediatek,dsi.txt and mediatek,dpi.txt, respectively.
> -  An exception is that the mt8183 mutex is always free running with no clocks property.
> -
> -Required properties (DMA function blocks):
> -- compatible: Should be one of
> -       "mediatek,<chip>-disp-ovl"
> -       "mediatek,<chip>-disp-rdma"
> -       "mediatek,<chip>-disp-wdma"
> -  the supported chips are mt2701, mt8167 and mt8173.
> -- larb: Should contain a phandle pointing to the local arbiter device as defined
> -  in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> -- iommus: Should point to the respective IOMMU block with master port as
> -  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> -  for details.
> -
> -Optional properties (RDMA function blocks):
> -- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
> -  property to the corresponding rdma
> -  the value is the Max value which defined in hardware data sheet.
> -  mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> -  mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> -  mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> -
> -Examples:
> -
> -mmsys: clock-controller@14000000 {
> -       compatible = "mediatek,mt8173-mmsys", "syscon";
> -       reg = <0 0x14000000 0 0x1000>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       #clock-cells = <1>;
> -};
> -
> -ovl0: ovl@1400c000 {
> -       compatible = "mediatek,mt8173-disp-ovl";
> -       reg = <0 0x1400c000 0 0x1000>;
> -       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_OVL0>;
> -       iommus = <&iommu M4U_PORT_DISP_OVL0>;
> -       mediatek,larb = <&larb0>;
> -};
> -
> -ovl1: ovl@1400d000 {
> -       compatible = "mediatek,mt8173-disp-ovl";
> -       reg = <0 0x1400d000 0 0x1000>;
> -       interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_OVL1>;
> -       iommus = <&iommu M4U_PORT_DISP_OVL1>;
> -       mediatek,larb = <&larb4>;
> -};
> -
> -rdma0: rdma@1400e000 {
> -       compatible = "mediatek,mt8173-disp-rdma";
> -       reg = <0 0x1400e000 0 0x1000>;
> -       interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> -       iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> -       mediatek,larb = <&larb0>;
> -       mediatek,rdma-fifosize = <8192>;
> -};
> -
> -rdma1: rdma@1400f000 {
> -       compatible = "mediatek,mt8173-disp-rdma";
> -       reg = <0 0x1400f000 0 0x1000>;
> -       interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> -       iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> -       mediatek,larb = <&larb4>;
> -};
> -
> -rdma2: rdma@14010000 {
> -       compatible = "mediatek,mt8173-disp-rdma";
> -       reg = <0 0x14010000 0 0x1000>;
> -       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> -       iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> -       mediatek,larb = <&larb4>;
> -};
> -
> -wdma0: wdma@14011000 {
> -       compatible = "mediatek,mt8173-disp-wdma";
> -       reg = <0 0x14011000 0 0x1000>;
> -       interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> -       iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> -       mediatek,larb = <&larb0>;
> -};
> -
> -wdma1: wdma@14012000 {
> -       compatible = "mediatek,mt8173-disp-wdma";
> -       reg = <0 0x14012000 0 0x1000>;
> -       interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> -       iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> -       mediatek,larb = <&larb4>;
> -};
> -
> -color0: color@14013000 {
> -       compatible = "mediatek,mt8173-disp-color";
> -       reg = <0 0x14013000 0 0x1000>;
> -       interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> -};
> -
> -color1: color@14014000 {
> -       compatible = "mediatek,mt8173-disp-color";
> -       reg = <0 0x14014000 0 0x1000>;
> -       interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> -};
> -
> -aal@14015000 {
> -       compatible = "mediatek,mt8173-disp-aal";
> -       reg = <0 0x14015000 0 0x1000>;
> -       interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_AAL>;
> -};
> -
> -gamma@14016000 {
> -       compatible = "mediatek,mt8173-disp-gamma";
> -       reg = <0 0x14016000 0 0x1000>;
> -       interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> -};
> -
> -ufoe@1401a000 {
> -       compatible = "mediatek,mt8173-disp-ufoe";
> -       reg = <0 0x1401a000 0 0x1000>;
> -       interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_UFOE>;
> -};
> -
> -dsi0: dsi@1401b000 {
> -       /* See mediatek,dsi.txt for details */
> -};
> -
> -dpi0: dpi@1401d000 {
> -       /* See mediatek,dpi.txt for details */
> -};
> -
> -mutex: mutex@14020000 {
> -       compatible = "mediatek,mt8173-disp-mutex";
> -       reg = <0 0x14020000 0 0x1000>;
> -       interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_MUTEX_32K>;
> -};
> -
> -od@14023000 {
> -       compatible = "mediatek,mt8173-disp-od";
> -       reg = <0 0x14023000 0 0x1000>;
> -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> -       clocks = <&mmsys CLK_MM_DISP_OD>;
> -};
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> new file mode 100644
> index 000000000000..2c05e3019c75
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> @@ -0,0 +1,75 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display dither processor
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display dither processor, namely DITHER, works by approximating
> +  unavailable colors with available colors and by mixing and matching available
> +  colors to mimic unavailable ones.
> +  DITHER device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8183-disp-dither
> +      - items:
> +          - enum:
> +              - mediatek,mt8192-disp-dither
> +          - enum:
> +              - mediatek,mt8183-disp-dither
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: DITHER Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    dither0: dither@14012000 {
> +        compatible = "mediatek,mt8183-disp-dither";
> +        reg = <0 0x14012000 0 0x1000>;
> +        interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +        clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> new file mode 100644
> index 000000000000..89ccb8dbadd7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display gamma correction
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display gamma correction, namely GAMMA, provides a nonlinear
> +  operation used to adjust luminance in display system.
> +  GAMMA device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-gamma
> +      - items:
> +          - const: mediatek,mt8183-disp-gamma
> +      - items:
> +          - enum:
> +              - mediatek,mt8192-disp-gamma
> +          - enum:
> +              - mediatek,mt8183-disp-gamma
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: GAMMA Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    gamma@14016000 {
> +        compatible = "mediatek,mt8173-disp-gamma";
> +        reg = <0 0x14016000 0 0x1000>;
> +        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> new file mode 100644
> index 000000000000..7aa6974d509d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display merge
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
> +  inputs into one side-by-side output.
> +  MERGE device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-merge
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: MERGE Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    merge@14017000 {
> +        compatible = "mediatek,mt8173-disp-merge";
> +        reg = <0 0x14017000 0 0x1000>;
> +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_MERGE>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> new file mode 100644
> index 000000000000..90f11e12a55e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> @@ -0,0 +1,82 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display mutex
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
> +  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
> +  data path or MDP data path.
> +  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
> +  the shadow register.
> +  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2701-disp-mutex
> +      - items:
> +          - const: mediatek,mt2712-disp-mutex
> +      - items:
> +          - const: mediatek,mt8167-disp-mutex
> +      - items:
> +          - const: mediatek,mt8173-disp-mutex
> +      - items:
> +          - const: mediatek,mt8183-disp-mutex
> +      - items:
> +          - const: mediatek,mt8192-disp-mutex
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: MUTEX Clock
> +
> +  mediatek,gce-events:
> +    description:
> +      The event id which is mapping to the specific hardware event signal
> +      to gce. The event id is defined in the gce header
> +      include/dt-bindings/gce/<chip>-gce.h of each chips.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    mutex: mutex@14020000 {
> +        compatible = "mediatek,mt8173-disp-mutex";
> +        reg = <0 0x14020000 0 0x1000>;
> +        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_MUTEX_32K>;
> +        mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> +                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> new file mode 100644
> index 000000000000..7519db315217
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display overdirve
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display overdrive, namely OD, increases the transition values
> +  of pixels between consecutive frames to make LCD rotate faster.
> +  OD device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2712-disp-od
> +      - items:
> +          - const: mediatek,mt8173-disp-od
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: OD Clock
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    od@14023000 {
> +        compatible = "mediatek,mt8173-disp-od";
> +        reg = <0 0x14023000 0 0x1000>;
> +        clocks = <&mmsys CLK_MM_DISP_OD>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> new file mode 100644
> index 000000000000..611a2dbdefa4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> @@ -0,0 +1,88 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display overlay 2 layer
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
> +  for OVL.
> +  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8183-disp-ovl-2l
> +      - items:
> +          - const: mediatek,mt8192-disp-ovl-2l
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: OVL-2L Clock
> +
> +  iommus:
> +    description:
> +      This property should point to the respective IOMMU block with master port as argument,
> +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> +  mediatek,larb:
> +    description:
> +      This property should contain a phandle pointing to the local arbiter devices defined in
> +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    ovl_2l0: ovl@14009000 {
> +        compatible = "mediatek,mt8183-disp-ovl-2l";
> +        reg = <0 0x14009000 0 0x1000>;
> +        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +        clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> +        iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
> +        mediatek,larb = <&larb0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> new file mode 100644
> index 000000000000..8e4a62cb9c81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> @@ -0,0 +1,98 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display overlay
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display overlay, namely OVL, can do alpha blending from
> +  the memory.
> +  OVL device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2701-disp-ovl
> +      - items:
> +          - const: mediatek,mt8173-disp-ovl
> +      - items:
> +          - const: mediatek,mt8183-disp-ovl
> +      - items:
> +          - const: mediatek,mt8192-disp-ovl
> +      - items:
> +          - enum:
> +              - mediatek,mt7623-disp-ovl
> +              - mediatek,mt2712-disp-ovl
> +          - enum:
> +              - mediatek,mt2701-disp-ovl
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: OVL Clock
> +
> +  iommus:
> +    description:
> +      This property should point to the respective IOMMU block with master port as argument,
> +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> +  mediatek,larb:
> +    description:
> +      This property should contain a phandle pointing to the local arbiter devices defined in
> +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - iommu
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    ovl0: ovl@1400c000 {
> +        compatible = "mediatek,mt8173-disp-ovl";
> +        reg = <0 0x1400c000 0 0x1000>;
> +        interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_OVL0>;
> +        iommus = <&iommu M4U_PORT_DISP_OVL0>;
> +        mediatek,larb = <&larb0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> new file mode 100644
> index 000000000000..6ac1da2e8871
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> @@ -0,0 +1,69 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display postmask
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display postmask, namely POSTMASK, provides round corner pattern
> +  generation.
> +  POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8192-disp-postmask
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: POSTMASK Clock
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    postmask0: postmask@1400d000 {
> +        compatible = "mediatek,mt8192-disp-postmask";
> +        reg = <0 0x1400d000 0 0x1000>;
> +        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> +        power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> +        clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> new file mode 100644
> index 000000000000..a3c5f4c9fbcd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Read Direct Memory Access
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek Read Direct Memory Access(RDMA) component used to read the
> +  data into DMA. It provides real time data to the back-end panel
> +  driver, such as DSI, DPI and DP_INTF.
> +  It contains one line buffer to store the sufficient pixel data.
> +  RDMA device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt2701-disp-rdma
> +      - items:
> +          - const: mediatek,mt8173-disp-rdma
> +      - items:
> +          - const: mediatek,mt8183-disp-rdma
> +      - items:
> +          - enum:
> +              - mediatek,mt7623-disp-rdma
> +              - mediatek,mt2712-disp-rdma
> +          - enum:
> +              - mediatek,mt2701-disp-rdma
> +      - items:
> +          - enum:
> +              - mediatek,mt8192-disp-rdma
> +          - enum:
> +              - mediatek,mt8183-disp-rdma
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: RDMA Clock
> +
> +  iommus:
> +    description:
> +      This property should point to the respective IOMMU block with master port as argument,
> +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> +  mediatek,larb:
> +    description:
> +      This property should contain a phandle pointing to the local arbiter devices defined in
> +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  mediatek,rdma-fifo-size:
> +    description:
> +      rdma fifo size may be different even in same SOC, add this property to the
> +      corresponding rdma.
> +      The value below is the Max value which defined in hardware data sheet
> +      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> +      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> +      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [8192, 5120, 2048]
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    rdma0: rdma@1400e000 {
> +        compatible = "mediatek,mt8173-disp-rdma";
> +        reg = <0 0x1400e000 0 0x1000>;
> +        interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> +        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> +        mediatek,larb = <&larb0>;
> +        mediatek,rdma-fifosize = <8192>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> new file mode 100644
> index 000000000000..4f08e89c1067
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display split
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display split, namely SPLIT, is used to split stream to two
> +  encoders.
> +  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-split
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: SPLIT Clock
> +
> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    split0: split@14018000 {
> +        compatible = "mediatek,mt8173-disp-split";
> +        reg = <0 0x14018000 0 0x1000>;
> +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> new file mode 100644
> index 000000000000..6e8748529e73
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek display UFOe
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek display UFOe stands for Unified Frame Optimization engine.
> +  UFOe can cut the data rate for DSI port which may lead to reduce power
> +  consumption.
> +  UFOe device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-ufoe
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: UFOe Clock
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    ufoe@1401a000 {
> +        compatible = "mediatek,mt8173-disp-ufoe";
> +        reg = <0 0x1401a000 0 0x1000>;
> +        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_UFOE>;
> +    };
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> new file mode 100644
> index 000000000000..aaf5649b6413
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> @@ -0,0 +1,86 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Write Direct Memory Access
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  Mediatek Write Direct Memory Access(WDMA) component used to write
> +  the data into DMA.
> +  WDMA device node must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8173-disp-wdma
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  clocks:
> +    items:
> +      - description: WDMA Clock
> +
> +  iommus:
> +    description:
> +      This property should point to the respective IOMMU block with master port as argument,
> +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> +
> +  mediatek,larb:
> +    description:
> +      This property should contain a phandle pointing to the local arbiter devices defined in
> +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 1
> +    maxItems: 32
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +  - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    wdma0: wdma@14011000 {
> +        compatible = "mediatek,mt8173-disp-wdma";
> +        reg = <0 0x14011000 0 0x1000>;
> +        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> +        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> +        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> +        mediatek,larb = <&larb0>;
> +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> +    };
> --
> 2.18.0
>

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^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
  2022-01-27 15:46     ` Chun-Kuang Hu
@ 2022-02-07 23:07       ` Chun-Kuang Hu
  -1 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:07 UTC (permalink / raw)
  To: Chun-Kuang Hu
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	Nancy Lin, linux-stm32, roy-cw.yeh, CK Hu, DTML, Jitao shi,
	Maxime Coquelin, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, jason-jh . lin, linux-kernel,
	Moudy Ho, Philipp Zabel, Enric Balletbo i Serra

OK, it seems no one has comment on this patch, so

applied to mediatek-drm-next [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

Chun-Kuang Hu <chunkuang.hu@kernel.org> 於 2022年1月27日 週四 下午11:46寫道：
>
> Hi, Rob:
>
> This patch looks good to me, how do you think about it?
>
> Regards,
> Chun-Kuang.
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
> >
> > 1. Remove mediatek,dislpay.txt
> > 2. Split each display function block to individual yaml file.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > ---
> >  .../display/mediatek/mediatek,aal.yaml        |  76 ++++++
> >  .../display/mediatek/mediatek,ccorr.yaml      |  71 ++++++
> >  .../display/mediatek/mediatek,color.yaml      |  85 +++++++
> >  .../display/mediatek/mediatek,disp.txt        | 219 ------------------
> >  .../display/mediatek/mediatek,dither.yaml     |  75 ++++++
> >  .../display/mediatek/mediatek,gamma.yaml      |  76 ++++++
> >  .../display/mediatek/mediatek,merge.yaml      |  66 ++++++
> >  .../display/mediatek/mediatek,mutex.yaml      |  82 +++++++
> >  .../display/mediatek/mediatek,od.yaml         |  53 +++++
> >  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
> >  .../display/mediatek/mediatek,ovl.yaml        |  98 ++++++++
> >  .../display/mediatek/mediatek,postmask.yaml   |  69 ++++++
> >  .../display/mediatek/mediatek,rdma.yaml       | 115 +++++++++
> >  .../display/mediatek/mediatek,split.yaml      |  58 +++++
> >  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
> >  .../display/mediatek/mediatek,wdma.yaml       |  86 +++++++
> >  16 files changed, 1159 insertions(+), 219 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> >  delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> > new file mode 100644
> > index 000000000000..044331f5aacb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> > @@ -0,0 +1,76 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display adaptive ambient light processor
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display adaptive ambient light processor, namely AAL,
> > +  is responsible for backlight power saving and sunlight visibility improving.
> > +  AAL device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-aal
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt2712-disp-aal
> > +              - mediatek,mt8183-disp-aal
> > +              - mediatek,mt8192-disp-aal
> > +          - enum:
> > +              - mediatek,mt8173-disp-aal
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: AAL Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    aal@14015000 {
> > +        compatible = "mediatek,mt8173-disp-aal";
> > +        reg = <0 0x14015000 0 0x1000>;
> > +        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_AAL>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> > new file mode 100644
> > index 000000000000..ea45b40edee7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display color correction
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display color correction, namely CCORR, reproduces correct color
> > +  on panels with different color gamut.
> > +  CCORR device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8183-disp-ccorr
> > +      - items:
> > +          - const: mediatek,mt8192-disp-ccorr
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: CCORR Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    ccorr0: ccorr@1400f000 {
> > +        compatible = "mediatek,mt8183-disp-ccorr";
> > +        reg = <0 0x1400f000 0 0x1000>;
> > +        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > +        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> > new file mode 100644
> > index 000000000000..13628f346718
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> > @@ -0,0 +1,85 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display color processor
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display color processor, namely COLOR, provides hue, luma and
> > +  saturation adjustments to get better picture quality and to have one panel
> > +  resemble the other in their output characteristics.
> > +  COLOR device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2701-disp-color
> > +      - items:
> > +          - const: mediatek,mt8167-disp-color
> > +      - items:
> > +          - const: mediatek,mt8173-disp-color
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt7623-disp-color
> > +              - mediatek,mt2712-disp-color
> > +          - enum:
> > +              - mediatek,mt2701-disp-color
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8183-disp-color
> > +              - mediatek,mt8192-disp-color
> > +          - enum:
> > +              - mediatek,mt8173-disp-color
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: COLOR Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    color0: color@14013000 {
> > +        compatible = "mediatek,mt8173-disp-color";
> > +        reg = <0 0x14013000 0 0x1000>;
> > +        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > deleted file mode 100644
> > index 78044c340e20..000000000000
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > +++ /dev/null
> > @@ -1,219 +0,0 @@
> > -Mediatek display subsystem
> > -==========================
> > -
> > -The Mediatek display subsystem consists of various DISP function blocks in the
> > -MMSYS register space. The connections between them can be configured by output
> > -and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
> > -of frame signal are distributed to the other function blocks by a DISP_MUTEX
> > -function block.
> > -
> > -All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
> > -For a description of the MMSYS_CONFIG binding, see
> > -Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
> > -
> > -DISP function blocks
> > -====================
> > -
> > -A display stream starts at a source function block that reads pixel data from
> > -memory and ends with a sink function block that drives pixels on a display
> > -interface, or writes pixels back to memory. All DISP function blocks have
> > -their own register space, interrupt, and clock gate. The blocks that can
> > -access memory additionally have to list the IOMMU and local arbiter they are
> > -connected to.
> > -
> > -For a description of the display interface sink function blocks, see
> > -Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
> > -Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
> > -
> > -Required properties (all function blocks):
> > -- compatible: "mediatek,<chip>-disp-<function>", one of
> > -       "mediatek,<chip>-disp-ovl"              - overlay (4 layers, blending, csc)
> > -       "mediatek,<chip>-disp-ovl-2l"           - overlay (2 layers, blending, csc)
> > -       "mediatek,<chip>-disp-rdma"             - read DMA / line buffer
> > -       "mediatek,<chip>-disp-wdma"             - write DMA
> > -       "mediatek,<chip>-disp-ccorr"            - color correction
> > -       "mediatek,<chip>-disp-color"            - color processor
> > -       "mediatek,<chip>-disp-dither"           - dither
> > -       "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
> > -       "mediatek,<chip>-disp-gamma"            - gamma correction
> > -       "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> > -       "mediatek,<chip>-disp-postmask"         - control round corner for display frame
> > -       "mediatek,<chip>-disp-split"            - split stream to two encoders
> > -       "mediatek,<chip>-disp-ufoe"             - data compression engine
> > -       "mediatek,<chip>-dsi"                   - DSI controller, see mediatek,dsi.txt
> > -       "mediatek,<chip>-dpi"                   - DPI controller, see mediatek,dpi.txt
> > -       "mediatek,<chip>-disp-mutex"            - display mutex
> > -       "mediatek,<chip>-disp-od"               - overdrive
> > -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> > -- reg: Physical base address and length of the function block register space
> > -- interrupts: The interrupt signal from the function block (required, except for
> > -  merge and split function blocks).
> > -- clocks: device clocks
> > -  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> > -  For most function blocks this is just a single clock input. Only the DSI and
> > -  DPI controller nodes have multiple clock inputs. These are documented in
> > -  mediatek,dsi.txt and mediatek,dpi.txt, respectively.
> > -  An exception is that the mt8183 mutex is always free running with no clocks property.
> > -
> > -Required properties (DMA function blocks):
> > -- compatible: Should be one of
> > -       "mediatek,<chip>-disp-ovl"
> > -       "mediatek,<chip>-disp-rdma"
> > -       "mediatek,<chip>-disp-wdma"
> > -  the supported chips are mt2701, mt8167 and mt8173.
> > -- larb: Should contain a phandle pointing to the local arbiter device as defined
> > -  in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > -- iommus: Should point to the respective IOMMU block with master port as
> > -  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > -  for details.
> > -
> > -Optional properties (RDMA function blocks):
> > -- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
> > -  property to the corresponding rdma
> > -  the value is the Max value which defined in hardware data sheet.
> > -  mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> > -  mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> > -  mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> > -
> > -Examples:
> > -
> > -mmsys: clock-controller@14000000 {
> > -       compatible = "mediatek,mt8173-mmsys", "syscon";
> > -       reg = <0 0x14000000 0 0x1000>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       #clock-cells = <1>;
> > -};
> > -
> > -ovl0: ovl@1400c000 {
> > -       compatible = "mediatek,mt8173-disp-ovl";
> > -       reg = <0 0x1400c000 0 0x1000>;
> > -       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > -       iommus = <&iommu M4U_PORT_DISP_OVL0>;
> > -       mediatek,larb = <&larb0>;
> > -};
> > -
> > -ovl1: ovl@1400d000 {
> > -       compatible = "mediatek,mt8173-disp-ovl";
> > -       reg = <0 0x1400d000 0 0x1000>;
> > -       interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_OVL1>;
> > -       iommus = <&iommu M4U_PORT_DISP_OVL1>;
> > -       mediatek,larb = <&larb4>;
> > -};
> > -
> > -rdma0: rdma@1400e000 {
> > -       compatible = "mediatek,mt8173-disp-rdma";
> > -       reg = <0 0x1400e000 0 0x1000>;
> > -       interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > -       iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> > -       mediatek,larb = <&larb0>;
> > -       mediatek,rdma-fifosize = <8192>;
> > -};
> > -
> > -rdma1: rdma@1400f000 {
> > -       compatible = "mediatek,mt8173-disp-rdma";
> > -       reg = <0 0x1400f000 0 0x1000>;
> > -       interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > -       iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> > -       mediatek,larb = <&larb4>;
> > -};
> > -
> > -rdma2: rdma@14010000 {
> > -       compatible = "mediatek,mt8173-disp-rdma";
> > -       reg = <0 0x14010000 0 0x1000>;
> > -       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> > -       iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> > -       mediatek,larb = <&larb4>;
> > -};
> > -
> > -wdma0: wdma@14011000 {
> > -       compatible = "mediatek,mt8173-disp-wdma";
> > -       reg = <0 0x14011000 0 0x1000>;
> > -       interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> > -       iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> > -       mediatek,larb = <&larb0>;
> > -};
> > -
> > -wdma1: wdma@14012000 {
> > -       compatible = "mediatek,mt8173-disp-wdma";
> > -       reg = <0 0x14012000 0 0x1000>;
> > -       interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> > -       iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> > -       mediatek,larb = <&larb4>;
> > -};
> > -
> > -color0: color@14013000 {
> > -       compatible = "mediatek,mt8173-disp-color";
> > -       reg = <0 0x14013000 0 0x1000>;
> > -       interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > -};
> > -
> > -color1: color@14014000 {
> > -       compatible = "mediatek,mt8173-disp-color";
> > -       reg = <0 0x14014000 0 0x1000>;
> > -       interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> > -};
> > -
> > -aal@14015000 {
> > -       compatible = "mediatek,mt8173-disp-aal";
> > -       reg = <0 0x14015000 0 0x1000>;
> > -       interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_AAL>;
> > -};
> > -
> > -gamma@14016000 {
> > -       compatible = "mediatek,mt8173-disp-gamma";
> > -       reg = <0 0x14016000 0 0x1000>;
> > -       interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> > -};
> > -
> > -ufoe@1401a000 {
> > -       compatible = "mediatek,mt8173-disp-ufoe";
> > -       reg = <0 0x1401a000 0 0x1000>;
> > -       interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_UFOE>;
> > -};
> > -
> > -dsi0: dsi@1401b000 {
> > -       /* See mediatek,dsi.txt for details */
> > -};
> > -
> > -dpi0: dpi@1401d000 {
> > -       /* See mediatek,dpi.txt for details */
> > -};
> > -
> > -mutex: mutex@14020000 {
> > -       compatible = "mediatek,mt8173-disp-mutex";
> > -       reg = <0 0x14020000 0 0x1000>;
> > -       interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > -};
> > -
> > -od@14023000 {
> > -       compatible = "mediatek,mt8173-disp-od";
> > -       reg = <0 0x14023000 0 0x1000>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_OD>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> > new file mode 100644
> > index 000000000000..2c05e3019c75
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> > @@ -0,0 +1,75 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display dither processor
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display dither processor, namely DITHER, works by approximating
> > +  unavailable colors with available colors and by mixing and matching available
> > +  colors to mimic unavailable ones.
> > +  DITHER device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8183-disp-dither
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8192-disp-dither
> > +          - enum:
> > +              - mediatek,mt8183-disp-dither
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: DITHER Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    dither0: dither@14012000 {
> > +        compatible = "mediatek,mt8183-disp-dither";
> > +        reg = <0 0x14012000 0 0x1000>;
> > +        interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > +        clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> > new file mode 100644
> > index 000000000000..89ccb8dbadd7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> > @@ -0,0 +1,76 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display gamma correction
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display gamma correction, namely GAMMA, provides a nonlinear
> > +  operation used to adjust luminance in display system.
> > +  GAMMA device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-gamma
> > +      - items:
> > +          - const: mediatek,mt8183-disp-gamma
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8192-disp-gamma
> > +          - enum:
> > +              - mediatek,mt8183-disp-gamma
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: GAMMA Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    gamma@14016000 {
> > +        compatible = "mediatek,mt8173-disp-gamma";
> > +        reg = <0 0x14016000 0 0x1000>;
> > +        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> > new file mode 100644
> > index 000000000000..7aa6974d509d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> > @@ -0,0 +1,66 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display merge
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
> > +  inputs into one side-by-side output.
> > +  MERGE device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-merge
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: MERGE Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    merge@14017000 {
> > +        compatible = "mediatek,mt8173-disp-merge";
> > +        reg = <0 0x14017000 0 0x1000>;
> > +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_MERGE>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> > new file mode 100644
> > index 000000000000..90f11e12a55e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> > @@ -0,0 +1,82 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display mutex
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
> > +  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
> > +  data path or MDP data path.
> > +  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
> > +  the shadow register.
> > +  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2701-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt2712-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt8167-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt8173-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt8183-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt8192-disp-mutex
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: MUTEX Clock
> > +
> > +  mediatek,gce-events:
> > +    description:
> > +      The event id which is mapping to the specific hardware event signal
> > +      to gce. The event id is defined in the gce header
> > +      include/dt-bindings/gce/<chip>-gce.h of each chips.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    mutex: mutex@14020000 {
> > +        compatible = "mediatek,mt8173-disp-mutex";
> > +        reg = <0 0x14020000 0 0x1000>;
> > +        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > +        mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> > +                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> > new file mode 100644
> > index 000000000000..7519db315217
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> > @@ -0,0 +1,53 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overdirve
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display overdrive, namely OD, increases the transition values
> > +  of pixels between consecutive frames to make LCD rotate faster.
> > +  OD device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2712-disp-od
> > +      - items:
> > +          - const: mediatek,mt8173-disp-od
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: OD Clock
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    od@14023000 {
> > +        compatible = "mediatek,mt8173-disp-od";
> > +        reg = <0 0x14023000 0 0x1000>;
> > +        clocks = <&mmsys CLK_MM_DISP_OD>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> > new file mode 100644
> > index 000000000000..611a2dbdefa4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> > @@ -0,0 +1,88 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overlay 2 layer
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
> > +  for OVL.
> > +  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8183-disp-ovl-2l
> > +      - items:
> > +          - const: mediatek,mt8192-disp-ovl-2l
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: OVL-2L Clock
> > +
> > +  iommus:
> > +    description:
> > +      This property should point to the respective IOMMU block with master port as argument,
> > +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > +  mediatek,larb:
> > +    description:
> > +      This property should contain a phandle pointing to the local arbiter devices defined in
> > +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +  - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    ovl_2l0: ovl@14009000 {
> > +        compatible = "mediatek,mt8183-disp-ovl-2l";
> > +        reg = <0 0x14009000 0 0x1000>;
> > +        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > +        clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > +        iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
> > +        mediatek,larb = <&larb0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> > new file mode 100644
> > index 000000000000..8e4a62cb9c81
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overlay
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display overlay, namely OVL, can do alpha blending from
> > +  the memory.
> > +  OVL device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2701-disp-ovl
> > +      - items:
> > +          - const: mediatek,mt8173-disp-ovl
> > +      - items:
> > +          - const: mediatek,mt8183-disp-ovl
> > +      - items:
> > +          - const: mediatek,mt8192-disp-ovl
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt7623-disp-ovl
> > +              - mediatek,mt2712-disp-ovl
> > +          - enum:
> > +              - mediatek,mt2701-disp-ovl
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: OVL Clock
> > +
> > +  iommus:
> > +    description:
> > +      This property should point to the respective IOMMU block with master port as argument,
> > +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > +  mediatek,larb:
> > +    description:
> > +      This property should contain a phandle pointing to the local arbiter devices defined in
> > +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +  - iommu
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    ovl0: ovl@1400c000 {
> > +        compatible = "mediatek,mt8173-disp-ovl";
> > +        reg = <0 0x1400c000 0 0x1000>;
> > +        interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > +        iommus = <&iommu M4U_PORT_DISP_OVL0>;
> > +        mediatek,larb = <&larb0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> > new file mode 100644
> > index 000000000000..6ac1da2e8871
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> > @@ -0,0 +1,69 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display postmask
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display postmask, namely POSTMASK, provides round corner pattern
> > +  generation.
> > +  POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8192-disp-postmask
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: POSTMASK Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    postmask0: postmask@1400d000 {
> > +        compatible = "mediatek,mt8192-disp-postmask";
> > +        reg = <0 0x1400d000 0 0x1000>;
> > +        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> > +        power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> > +        clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> > new file mode 100644
> > index 000000000000..a3c5f4c9fbcd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> > @@ -0,0 +1,115 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek Read Direct Memory Access
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek Read Direct Memory Access(RDMA) component used to read the
> > +  data into DMA. It provides real time data to the back-end panel
> > +  driver, such as DSI, DPI and DP_INTF.
> > +  It contains one line buffer to store the sufficient pixel data.
> > +  RDMA device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2701-disp-rdma
> > +      - items:
> > +          - const: mediatek,mt8173-disp-rdma
> > +      - items:
> > +          - const: mediatek,mt8183-disp-rdma
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt7623-disp-rdma
> > +              - mediatek,mt2712-disp-rdma
> > +          - enum:
> > +              - mediatek,mt2701-disp-rdma
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8192-disp-rdma
> > +          - enum:
> > +              - mediatek,mt8183-disp-rdma
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: RDMA Clock
> > +
> > +  iommus:
> > +    description:
> > +      This property should point to the respective IOMMU block with master port as argument,
> > +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > +  mediatek,larb:
> > +    description:
> > +      This property should contain a phandle pointing to the local arbiter devices defined in
> > +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  mediatek,rdma-fifo-size:
> > +    description:
> > +      rdma fifo size may be different even in same SOC, add this property to the
> > +      corresponding rdma.
> > +      The value below is the Max value which defined in hardware data sheet
> > +      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> > +      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> > +      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [8192, 5120, 2048]
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +  - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    rdma0: rdma@1400e000 {
> > +        compatible = "mediatek,mt8173-disp-rdma";
> > +        reg = <0 0x1400e000 0 0x1000>;
> > +        interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> > +        mediatek,larb = <&larb0>;
> > +        mediatek,rdma-fifosize = <8192>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > new file mode 100644
> > index 000000000000..4f08e89c1067
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display split
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display split, namely SPLIT, is used to split stream to two
> > +  encoders.
> > +  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-split
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: SPLIT Clock
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    split0: split@14018000 {
> > +        compatible = "mediatek,mt8173-disp-split";
> > +        reg = <0 0x14018000 0 0x1000>;
> > +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> > new file mode 100644
> > index 000000000000..6e8748529e73
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> > @@ -0,0 +1,61 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display UFOe
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display UFOe stands for Unified Frame Optimization engine.
> > +  UFOe can cut the data rate for DSI port which may lead to reduce power
> > +  consumption.
> > +  UFOe device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-ufoe
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: UFOe Clock
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    ufoe@1401a000 {
> > +        compatible = "mediatek,mt8173-disp-ufoe";
> > +        reg = <0 0x1401a000 0 0x1000>;
> > +        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_UFOE>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> > new file mode 100644
> > index 000000000000..aaf5649b6413
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> > @@ -0,0 +1,86 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek Write Direct Memory Access
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek Write Direct Memory Access(WDMA) component used to write
> > +  the data into DMA.
> > +  WDMA device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-wdma
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: WDMA Clock
> > +
> > +  iommus:
> > +    description:
> > +      This property should point to the respective IOMMU block with master port as argument,
> > +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > +  mediatek,larb:
> > +    description:
> > +      This property should contain a phandle pointing to the local arbiter devices defined in
> > +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +  - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    wdma0: wdma@14011000 {
> > +        compatible = "mediatek,mt8173-disp-wdma";
> > +        reg = <0 0x14011000 0 0x1000>;
> > +        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> > +        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> > +        mediatek,larb = <&larb0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> > +    };
> > --
> > 2.18.0
> >

_______________________________________________
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
@ 2022-02-07 23:07       ` Chun-Kuang Hu
  0 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:07 UTC (permalink / raw)
  To: Chun-Kuang Hu
  Cc: Rob Herring, Matthias Brugger, Philipp Zabel,
	AngeloGioacchino Del Regno, Enric Balletbo i Serra,
	Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, jason-jh . lin,
	CK Hu, Fabien Parent, Jitao shi, Nancy Lin, singo.chang, DTML,
	linux-stm32, Linux ARM, moderated list:ARM/Mediatek SoC support,
	linux-kernel

OK, it seems no one has comment on this patch, so

applied to mediatek-drm-next [1].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

Chun-Kuang Hu <chunkuang.hu@kernel.org> 於 2022年1月27日 週四 下午11:46寫道：
>
> Hi, Rob:
>
> This patch looks good to me, how do you think about it?
>
> Regards,
> Chun-Kuang.
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
> >
> > 1. Remove mediatek,dislpay.txt
> > 2. Split each display function block to individual yaml file.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > ---
> >  .../display/mediatek/mediatek,aal.yaml        |  76 ++++++
> >  .../display/mediatek/mediatek,ccorr.yaml      |  71 ++++++
> >  .../display/mediatek/mediatek,color.yaml      |  85 +++++++
> >  .../display/mediatek/mediatek,disp.txt        | 219 ------------------
> >  .../display/mediatek/mediatek,dither.yaml     |  75 ++++++
> >  .../display/mediatek/mediatek,gamma.yaml      |  76 ++++++
> >  .../display/mediatek/mediatek,merge.yaml      |  66 ++++++
> >  .../display/mediatek/mediatek,mutex.yaml      |  82 +++++++
> >  .../display/mediatek/mediatek,od.yaml         |  53 +++++
> >  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
> >  .../display/mediatek/mediatek,ovl.yaml        |  98 ++++++++
> >  .../display/mediatek/mediatek,postmask.yaml   |  69 ++++++
> >  .../display/mediatek/mediatek,rdma.yaml       | 115 +++++++++
> >  .../display/mediatek/mediatek,split.yaml      |  58 +++++
> >  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
> >  .../display/mediatek/mediatek,wdma.yaml       |  86 +++++++
> >  16 files changed, 1159 insertions(+), 219 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> >  delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> >  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> > new file mode 100644
> > index 000000000000..044331f5aacb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> > @@ -0,0 +1,76 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,aal.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display adaptive ambient light processor
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display adaptive ambient light processor, namely AAL,
> > +  is responsible for backlight power saving and sunlight visibility improving.
> > +  AAL device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-aal
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt2712-disp-aal
> > +              - mediatek,mt8183-disp-aal
> > +              - mediatek,mt8192-disp-aal
> > +          - enum:
> > +              - mediatek,mt8173-disp-aal
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: AAL Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    aal@14015000 {
> > +        compatible = "mediatek,mt8173-disp-aal";
> > +        reg = <0 0x14015000 0 0x1000>;
> > +        interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_AAL>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> > new file mode 100644
> > index 000000000000..ea45b40edee7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ccorr.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display color correction
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display color correction, namely CCORR, reproduces correct color
> > +  on panels with different color gamut.
> > +  CCORR device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8183-disp-ccorr
> > +      - items:
> > +          - const: mediatek,mt8192-disp-ccorr
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: CCORR Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    ccorr0: ccorr@1400f000 {
> > +        compatible = "mediatek,mt8183-disp-ccorr";
> > +        reg = <0 0x1400f000 0 0x1000>;
> > +        interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > +        clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> > new file mode 100644
> > index 000000000000..13628f346718
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> > @@ -0,0 +1,85 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,color.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display color processor
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display color processor, namely COLOR, provides hue, luma and
> > +  saturation adjustments to get better picture quality and to have one panel
> > +  resemble the other in their output characteristics.
> > +  COLOR device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2701-disp-color
> > +      - items:
> > +          - const: mediatek,mt8167-disp-color
> > +      - items:
> > +          - const: mediatek,mt8173-disp-color
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt7623-disp-color
> > +              - mediatek,mt2712-disp-color
> > +          - enum:
> > +              - mediatek,mt2701-disp-color
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8183-disp-color
> > +              - mediatek,mt8192-disp-color
> > +          - enum:
> > +              - mediatek,mt8173-disp-color
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: COLOR Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    color0: color@14013000 {
> > +        compatible = "mediatek,mt8173-disp-color";
> > +        reg = <0 0x14013000 0 0x1000>;
> > +        interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > deleted file mode 100644
> > index 78044c340e20..000000000000
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > +++ /dev/null
> > @@ -1,219 +0,0 @@
> > -Mediatek display subsystem
> > -==========================
> > -
> > -The Mediatek display subsystem consists of various DISP function blocks in the
> > -MMSYS register space. The connections between them can be configured by output
> > -and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
> > -of frame signal are distributed to the other function blocks by a DISP_MUTEX
> > -function block.
> > -
> > -All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
> > -For a description of the MMSYS_CONFIG binding, see
> > -Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml.
> > -
> > -DISP function blocks
> > -====================
> > -
> > -A display stream starts at a source function block that reads pixel data from
> > -memory and ends with a sink function block that drives pixels on a display
> > -interface, or writes pixels back to memory. All DISP function blocks have
> > -their own register space, interrupt, and clock gate. The blocks that can
> > -access memory additionally have to list the IOMMU and local arbiter they are
> > -connected to.
> > -
> > -For a description of the display interface sink function blocks, see
> > -Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
> > -Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
> > -
> > -Required properties (all function blocks):
> > -- compatible: "mediatek,<chip>-disp-<function>", one of
> > -       "mediatek,<chip>-disp-ovl"              - overlay (4 layers, blending, csc)
> > -       "mediatek,<chip>-disp-ovl-2l"           - overlay (2 layers, blending, csc)
> > -       "mediatek,<chip>-disp-rdma"             - read DMA / line buffer
> > -       "mediatek,<chip>-disp-wdma"             - write DMA
> > -       "mediatek,<chip>-disp-ccorr"            - color correction
> > -       "mediatek,<chip>-disp-color"            - color processor
> > -       "mediatek,<chip>-disp-dither"           - dither
> > -       "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
> > -       "mediatek,<chip>-disp-gamma"            - gamma correction
> > -       "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> > -       "mediatek,<chip>-disp-postmask"         - control round corner for display frame
> > -       "mediatek,<chip>-disp-split"            - split stream to two encoders
> > -       "mediatek,<chip>-disp-ufoe"             - data compression engine
> > -       "mediatek,<chip>-dsi"                   - DSI controller, see mediatek,dsi.txt
> > -       "mediatek,<chip>-dpi"                   - DPI controller, see mediatek,dpi.txt
> > -       "mediatek,<chip>-disp-mutex"            - display mutex
> > -       "mediatek,<chip>-disp-od"               - overdrive
> > -  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
> > -- reg: Physical base address and length of the function block register space
> > -- interrupts: The interrupt signal from the function block (required, except for
> > -  merge and split function blocks).
> > -- clocks: device clocks
> > -  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
> > -  For most function blocks this is just a single clock input. Only the DSI and
> > -  DPI controller nodes have multiple clock inputs. These are documented in
> > -  mediatek,dsi.txt and mediatek,dpi.txt, respectively.
> > -  An exception is that the mt8183 mutex is always free running with no clocks property.
> > -
> > -Required properties (DMA function blocks):
> > -- compatible: Should be one of
> > -       "mediatek,<chip>-disp-ovl"
> > -       "mediatek,<chip>-disp-rdma"
> > -       "mediatek,<chip>-disp-wdma"
> > -  the supported chips are mt2701, mt8167 and mt8173.
> > -- larb: Should contain a phandle pointing to the local arbiter device as defined
> > -  in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
> > -- iommus: Should point to the respective IOMMU block with master port as
> > -  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> > -  for details.
> > -
> > -Optional properties (RDMA function blocks):
> > -- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
> > -  property to the corresponding rdma
> > -  the value is the Max value which defined in hardware data sheet.
> > -  mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> > -  mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> > -  mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> > -
> > -Examples:
> > -
> > -mmsys: clock-controller@14000000 {
> > -       compatible = "mediatek,mt8173-mmsys", "syscon";
> > -       reg = <0 0x14000000 0 0x1000>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       #clock-cells = <1>;
> > -};
> > -
> > -ovl0: ovl@1400c000 {
> > -       compatible = "mediatek,mt8173-disp-ovl";
> > -       reg = <0 0x1400c000 0 0x1000>;
> > -       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > -       iommus = <&iommu M4U_PORT_DISP_OVL0>;
> > -       mediatek,larb = <&larb0>;
> > -};
> > -
> > -ovl1: ovl@1400d000 {
> > -       compatible = "mediatek,mt8173-disp-ovl";
> > -       reg = <0 0x1400d000 0 0x1000>;
> > -       interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_OVL1>;
> > -       iommus = <&iommu M4U_PORT_DISP_OVL1>;
> > -       mediatek,larb = <&larb4>;
> > -};
> > -
> > -rdma0: rdma@1400e000 {
> > -       compatible = "mediatek,mt8173-disp-rdma";
> > -       reg = <0 0x1400e000 0 0x1000>;
> > -       interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > -       iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> > -       mediatek,larb = <&larb0>;
> > -       mediatek,rdma-fifosize = <8192>;
> > -};
> > -
> > -rdma1: rdma@1400f000 {
> > -       compatible = "mediatek,mt8173-disp-rdma";
> > -       reg = <0 0x1400f000 0 0x1000>;
> > -       interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> > -       iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> > -       mediatek,larb = <&larb4>;
> > -};
> > -
> > -rdma2: rdma@14010000 {
> > -       compatible = "mediatek,mt8173-disp-rdma";
> > -       reg = <0 0x14010000 0 0x1000>;
> > -       interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> > -       iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> > -       mediatek,larb = <&larb4>;
> > -};
> > -
> > -wdma0: wdma@14011000 {
> > -       compatible = "mediatek,mt8173-disp-wdma";
> > -       reg = <0 0x14011000 0 0x1000>;
> > -       interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> > -       iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> > -       mediatek,larb = <&larb0>;
> > -};
> > -
> > -wdma1: wdma@14012000 {
> > -       compatible = "mediatek,mt8173-disp-wdma";
> > -       reg = <0 0x14012000 0 0x1000>;
> > -       interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> > -       iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> > -       mediatek,larb = <&larb4>;
> > -};
> > -
> > -color0: color@14013000 {
> > -       compatible = "mediatek,mt8173-disp-color";
> > -       reg = <0 0x14013000 0 0x1000>;
> > -       interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> > -};
> > -
> > -color1: color@14014000 {
> > -       compatible = "mediatek,mt8173-disp-color";
> > -       reg = <0 0x14014000 0 0x1000>;
> > -       interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> > -};
> > -
> > -aal@14015000 {
> > -       compatible = "mediatek,mt8173-disp-aal";
> > -       reg = <0 0x14015000 0 0x1000>;
> > -       interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_AAL>;
> > -};
> > -
> > -gamma@14016000 {
> > -       compatible = "mediatek,mt8173-disp-gamma";
> > -       reg = <0 0x14016000 0 0x1000>;
> > -       interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> > -};
> > -
> > -ufoe@1401a000 {
> > -       compatible = "mediatek,mt8173-disp-ufoe";
> > -       reg = <0 0x1401a000 0 0x1000>;
> > -       interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_UFOE>;
> > -};
> > -
> > -dsi0: dsi@1401b000 {
> > -       /* See mediatek,dsi.txt for details */
> > -};
> > -
> > -dpi0: dpi@1401d000 {
> > -       /* See mediatek,dpi.txt for details */
> > -};
> > -
> > -mutex: mutex@14020000 {
> > -       compatible = "mediatek,mt8173-disp-mutex";
> > -       reg = <0 0x14020000 0 0x1000>;
> > -       interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > -};
> > -
> > -od@14023000 {
> > -       compatible = "mediatek,mt8173-disp-od";
> > -       reg = <0 0x14023000 0 0x1000>;
> > -       power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > -       clocks = <&mmsys CLK_MM_DISP_OD>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> > new file mode 100644
> > index 000000000000..2c05e3019c75
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> > @@ -0,0 +1,75 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dither.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display dither processor
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display dither processor, namely DITHER, works by approximating
> > +  unavailable colors with available colors and by mixing and matching available
> > +  colors to mimic unavailable ones.
> > +  DITHER device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8183-disp-dither
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8192-disp-dither
> > +          - enum:
> > +              - mediatek,mt8183-disp-dither
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: DITHER Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    dither0: dither@14012000 {
> > +        compatible = "mediatek,mt8183-disp-dither";
> > +        reg = <0 0x14012000 0 0x1000>;
> > +        interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > +        clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> > new file mode 100644
> > index 000000000000..89ccb8dbadd7
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> > @@ -0,0 +1,76 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,gamma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display gamma correction
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display gamma correction, namely GAMMA, provides a nonlinear
> > +  operation used to adjust luminance in display system.
> > +  GAMMA device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-gamma
> > +      - items:
> > +          - const: mediatek,mt8183-disp-gamma
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8192-disp-gamma
> > +          - enum:
> > +              - mediatek,mt8183-disp-gamma
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: GAMMA Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    gamma@14016000 {
> > +        compatible = "mediatek,mt8173-disp-gamma";
> > +        reg = <0 0x14016000 0 0x1000>;
> > +        interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> > new file mode 100644
> > index 000000000000..7aa6974d509d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> > @@ -0,0 +1,66 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display merge
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display merge, namely MERGE, is used to merge two slice-per-line
> > +  inputs into one side-by-side output.
> > +  MERGE device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-merge
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: MERGE Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    merge@14017000 {
> > +        compatible = "mediatek,mt8173-disp-merge";
> > +        reg = <0 0x14017000 0 0x1000>;
> > +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_MERGE>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> > new file mode 100644
> > index 000000000000..90f11e12a55e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> > @@ -0,0 +1,82 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display mutex
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek mutex, namely MUTEX, is used to send the triggers signals called
> > +  Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display
> > +  data path or MDP data path.
> > +  In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
> > +  the shadow register.
> > +  MUTEX device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2701-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt2712-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt8167-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt8173-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt8183-disp-mutex
> > +      - items:
> > +          - const: mediatek,mt8192-disp-mutex
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: MUTEX Clock
> > +
> > +  mediatek,gce-events:
> > +    description:
> > +      The event id which is mapping to the specific hardware event signal
> > +      to gce. The event id is defined in the gce header
> > +      include/dt-bindings/gce/<chip>-gce.h of each chips.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    mutex: mutex@14020000 {
> > +        compatible = "mediatek,mt8173-disp-mutex";
> > +        reg = <0 0x14020000 0 0x1000>;
> > +        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_MUTEX_32K>;
> > +        mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> > +                              <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> > new file mode 100644
> > index 000000000000..7519db315217
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> > @@ -0,0 +1,53 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,od.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overdirve
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display overdrive, namely OD, increases the transition values
> > +  of pixels between consecutive frames to make LCD rotate faster.
> > +  OD device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2712-disp-od
> > +      - items:
> > +          - const: mediatek,mt8173-disp-od
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: OD Clock
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    od@14023000 {
> > +        compatible = "mediatek,mt8173-disp-od";
> > +        reg = <0 0x14023000 0 0x1000>;
> > +        clocks = <&mmsys CLK_MM_DISP_OD>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> > new file mode 100644
> > index 000000000000..611a2dbdefa4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
> > @@ -0,0 +1,88 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl-2l.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overlay 2 layer
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display overlay 2 layer, namely OVL-2L, provides 2 more layer
> > +  for OVL.
> > +  OVL-2L device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8183-disp-ovl-2l
> > +      - items:
> > +          - const: mediatek,mt8192-disp-ovl-2l
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: OVL-2L Clock
> > +
> > +  iommus:
> > +    description:
> > +      This property should point to the respective IOMMU block with master port as argument,
> > +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > +  mediatek,larb:
> > +    description:
> > +      This property should contain a phandle pointing to the local arbiter devices defined in
> > +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +  - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    ovl_2l0: ovl@14009000 {
> > +        compatible = "mediatek,mt8183-disp-ovl-2l";
> > +        reg = <0 0x14009000 0 0x1000>;
> > +        interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > +        clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> > +        iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
> > +        mediatek,larb = <&larb0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> > new file mode 100644
> > index 000000000000..8e4a62cb9c81
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ovl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display overlay
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display overlay, namely OVL, can do alpha blending from
> > +  the memory.
> > +  OVL device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2701-disp-ovl
> > +      - items:
> > +          - const: mediatek,mt8173-disp-ovl
> > +      - items:
> > +          - const: mediatek,mt8183-disp-ovl
> > +      - items:
> > +          - const: mediatek,mt8192-disp-ovl
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt7623-disp-ovl
> > +              - mediatek,mt2712-disp-ovl
> > +          - enum:
> > +              - mediatek,mt2701-disp-ovl
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: OVL Clock
> > +
> > +  iommus:
> > +    description:
> > +      This property should point to the respective IOMMU block with master port as argument,
> > +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > +  mediatek,larb:
> > +    description:
> > +      This property should contain a phandle pointing to the local arbiter devices defined in
> > +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +  - iommu
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    ovl0: ovl@1400c000 {
> > +        compatible = "mediatek,mt8173-disp-ovl";
> > +        reg = <0 0x1400c000 0 0x1000>;
> > +        interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_OVL0>;
> > +        iommus = <&iommu M4U_PORT_DISP_OVL0>;
> > +        mediatek,larb = <&larb0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> > new file mode 100644
> > index 000000000000..6ac1da2e8871
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
> > @@ -0,0 +1,69 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,postmask.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display postmask
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display postmask, namely POSTMASK, provides round corner pattern
> > +  generation.
> > +  POSTMASK device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8192-disp-postmask
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: POSTMASK Clock
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    postmask0: postmask@1400d000 {
> > +        compatible = "mediatek,mt8192-disp-postmask";
> > +        reg = <0 0x1400d000 0 0x1000>;
> > +        interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
> > +        power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
> > +        clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> > new file mode 100644
> > index 000000000000..a3c5f4c9fbcd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> > @@ -0,0 +1,115 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek Read Direct Memory Access
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek Read Direct Memory Access(RDMA) component used to read the
> > +  data into DMA. It provides real time data to the back-end panel
> > +  driver, such as DSI, DPI and DP_INTF.
> > +  It contains one line buffer to store the sufficient pixel data.
> > +  RDMA device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt2701-disp-rdma
> > +      - items:
> > +          - const: mediatek,mt8173-disp-rdma
> > +      - items:
> > +          - const: mediatek,mt8183-disp-rdma
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt7623-disp-rdma
> > +              - mediatek,mt2712-disp-rdma
> > +          - enum:
> > +              - mediatek,mt2701-disp-rdma
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8192-disp-rdma
> > +          - enum:
> > +              - mediatek,mt8183-disp-rdma
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: RDMA Clock
> > +
> > +  iommus:
> > +    description:
> > +      This property should point to the respective IOMMU block with master port as argument,
> > +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > +  mediatek,larb:
> > +    description:
> > +      This property should contain a phandle pointing to the local arbiter devices defined in
> > +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  mediatek,rdma-fifo-size:
> > +    description:
> > +      rdma fifo size may be different even in same SOC, add this property to the
> > +      corresponding rdma.
> > +      The value below is the Max value which defined in hardware data sheet
> > +      mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
> > +      mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
> > +      mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    enum: [8192, 5120, 2048]
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +  - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    rdma0: rdma@1400e000 {
> > +        compatible = "mediatek,mt8173-disp-rdma";
> > +        reg = <0 0x1400e000 0 0x1000>;
> > +        interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> > +        iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> > +        mediatek,larb = <&larb0>;
> > +        mediatek,rdma-fifosize = <8192>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > new file mode 100644
> > index 000000000000..4f08e89c1067
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,split.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display split
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display split, namely SPLIT, is used to split stream to two
> > +  encoders.
> > +  SPLIT device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-split
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: SPLIT Clock
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    split0: split@14018000 {
> > +        compatible = "mediatek,mt8173-disp-split";
> > +        reg = <0 0x14018000 0 0x1000>;
> > +        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> > new file mode 100644
> > index 000000000000..6e8748529e73
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
> > @@ -0,0 +1,61 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek display UFOe
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek display UFOe stands for Unified Frame Optimization engine.
> > +  UFOe can cut the data rate for DSI port which may lead to reduce power
> > +  consumption.
> > +  UFOe device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-ufoe
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: UFOe Clock
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    ufoe@1401a000 {
> > +        compatible = "mediatek,mt8173-disp-ufoe";
> > +        reg = <0 0x1401a000 0 0x1000>;
> > +        interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_UFOE>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> > new file mode 100644
> > index 000000000000..aaf5649b6413
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
> > @@ -0,0 +1,86 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,wdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Mediatek Write Direct Memory Access
> > +
> > +maintainers:
> > +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> > +  - Philipp Zabel <p.zabel@pengutronix.de>
> > +
> > +description: |
> > +  Mediatek Write Direct Memory Access(WDMA) component used to write
> > +  the data into DMA.
> > +  WDMA device node must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> > +  for details.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - const: mediatek,mt8173-disp-wdma
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    description: A phandle and PM domain specifier as defined by bindings of
> > +      the power controller specified by phandle. See
> > +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> > +
> > +  clocks:
> > +    items:
> > +      - description: WDMA Clock
> > +
> > +  iommus:
> > +    description:
> > +      This property should point to the respective IOMMU block with master port as argument,
> > +      see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
> > +
> > +  mediatek,larb:
> > +    description:
> > +      This property should contain a phandle pointing to the local arbiter devices defined in
> > +      Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> > +      It must sort according to the local arbiter index, like larb0, larb1, larb2...
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    minItems: 1
> > +    maxItems: 32
> > +
> > +  mediatek,gce-client-reg:
> > +    description: The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - power-domains
> > +  - clocks
> > +  - iommus
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +
> > +    wdma0: wdma@14011000 {
> > +        compatible = "mediatek,mt8173-disp-wdma";
> > +        reg = <0 0x14011000 0 0x1000>;
> > +        interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
> > +        power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> > +        clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> > +        iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> > +        mediatek,larb = <&larb0>;
> > +        mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> > +    };
> > --
> > 2.18.0
> >

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
  2022-01-26  7:19   ` jason-jh.lin
  (?)
@ 2022-02-07 23:09     ` Chun-Kuang Hu
  -1 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:09 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent, DTML,
	Nancy Lin, linux-stm32, roy-cw.yeh, CK Hu, Chun-Kuang Hu,
	Jitao shi, Philipp Zabel, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Maxime Coquelin, Enric Balletbo i Serra

 Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> 1. Add mediatek,dsc.yaml to describe DSC module in details.
> 2. Add mt8195 SoC binding to mediatek,dsc.yaml.

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../display/mediatek/mediatek,dsc.yaml        | 71 +++++++++++++++++++
>  1 file changed, 71 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> new file mode 100644
> index 000000000000..1ec083eff824
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek display DSC controller
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  The DSC standard is a specification of the algorithms used for
> +  compressing and decompressing image display streams, including
> +  the specification of the syntax and semantics of the compressed
> +  video bit stream. DSC is designed for real-time systems with
> +  real-time compression, transmission, decompression and Display.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8195-disp-dsc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: DSC Wrapper Clock
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  mediatek,gce-client-reg:
> +    description:
> +      The register of client driver can be configured by gce with 4 arguments
> +      defined in this property, such as phandle of gce, subsys id,
> +      register offset and size.
> +      Each subsys id is mapping to a base address of display function blocks
> +      register which is defined in the gce header
> +      include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    dsc0: disp_dsc_wrap@1c009000 {
> +        compatible = "mediatek,mt8195-disp-dsc";
> +        reg = <0 0x1c009000 0 0x1000>;
> +        interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
> +        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +        clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
> +        mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
> +    };
> --
> 2.18.0
>

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
@ 2022-02-07 23:09     ` Chun-Kuang Hu
  0 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:09 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno, Enric Balletbo i Serra,
	Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
	Fabien Parent, Jitao shi, Nancy Lin, singo.chang, DTML,
	linux-stm32, Linux ARM, moderated list:ARM/Mediatek SoC support,
	linux-kernel

 Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> 1. Add mediatek,dsc.yaml to describe DSC module in details.
> 2. Add mt8195 SoC binding to mediatek,dsc.yaml.

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../display/mediatek/mediatek,dsc.yaml        | 71 +++++++++++++++++++
>  1 file changed, 71 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> new file mode 100644
> index 000000000000..1ec083eff824
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek display DSC controller
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  The DSC standard is a specification of the algorithms used for
> +  compressing and decompressing image display streams, including
> +  the specification of the syntax and semantics of the compressed
> +  video bit stream. DSC is designed for real-time systems with
> +  real-time compression, transmission, decompression and Display.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8195-disp-dsc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: DSC Wrapper Clock
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  mediatek,gce-client-reg:
> +    description:
> +      The register of client driver can be configured by gce with 4 arguments
> +      defined in this property, such as phandle of gce, subsys id,
> +      register offset and size.
> +      Each subsys id is mapping to a base address of display function blocks
> +      register which is defined in the gce header
> +      include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    dsc0: disp_dsc_wrap@1c009000 {
> +        compatible = "mediatek,mt8195-disp-dsc";
> +        reg = <0 0x1c009000 0 0x1000>;
> +        interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
> +        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +        clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
> +        mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
> +    };
> --
> 2.18.0
>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
@ 2022-02-07 23:09     ` Chun-Kuang Hu
  0 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:09 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno, Enric Balletbo i Serra,
	Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
	Fabien Parent, Jitao shi, Nancy Lin, singo.chang, DTML,
	linux-stm32, Linux ARM, moderated list:ARM/Mediatek SoC support,
	linux-kernel

 Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> 1. Add mediatek,dsc.yaml to describe DSC module in details.
> 2. Add mt8195 SoC binding to mediatek,dsc.yaml.

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../display/mediatek/mediatek,dsc.yaml        | 71 +++++++++++++++++++
>  1 file changed, 71 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> new file mode 100644
> index 000000000000..1ec083eff824
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek display DSC controller
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description: |
> +  The DSC standard is a specification of the algorithms used for
> +  compressing and decompressing image display streams, including
> +  the specification of the syntax and semantics of the compressed
> +  video bit stream. DSC is designed for real-time systems with
> +  real-time compression, transmission, decompression and Display.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - const: mediatek,mt8195-disp-dsc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: DSC Wrapper Clock
> +
> +  power-domains:
> +    description: A phandle and PM domain specifier as defined by bindings of
> +      the power controller specified by phandle. See
> +      Documentation/devicetree/bindings/power/power-domain.yaml for details.
> +
> +  mediatek,gce-client-reg:
> +    description:
> +      The register of client driver can be configured by gce with 4 arguments
> +      defined in this property, such as phandle of gce, subsys id,
> +      register offset and size.
> +      Each subsys id is mapping to a base address of display function blocks
> +      register which is defined in the gce header
> +      include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - power-domains
> +  - clocks
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    dsc0: disp_dsc_wrap@1c009000 {
> +        compatible = "mediatek,mt8195-disp-dsc";
> +        reg = <0 0x1c009000 0 0x1000>;
> +        interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
> +        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +        clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
> +        mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
> +    };
> --
> 2.18.0
>

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 05/12] dt-bindings: display: mediatek: merge: add additional prop for mt8195
  2022-01-26  7:19   ` jason-jh.lin
  (?)
@ 2022-02-07 23:09     ` Chun-Kuang Hu
  -1 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:09 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent, DTML,
	Nancy Lin, linux-stm32, roy-cw.yeh, CK Hu, Chun-Kuang Hu,
	Jitao shi, Philipp Zabel, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Maxime Coquelin, Enric Balletbo i Serra

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> add MERGE additional properties description for mt8195:
> 1. async clock
> 2. fifo setting enable
> 3. reset controller

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../display/mediatek/mediatek,merge.yaml      | 38 +++++++++++++++++++
>  1 file changed, 38 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 7aa6974d509d..fae106cf1753 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -36,8 +36,28 @@ properties:
>        Documentation/devicetree/bindings/power/power-domain.yaml for details.
>
>    clocks:
> +    maxItems: 2
>      items:
>        - description: MERGE Clock
> +      - description: MERGE Async Clock
> +          Controlling the synchronous process between MERGE and other display
> +          function blocks cross clock domain.
> +
> +  clock-names:
> +    maxItems: 2
> +    items:
> +      - const: merge
> +      - const: merge_async
> +
> +  mediatek,merge-fifo-en:
> +    description:
> +      The setting of merge fifo is mainly provided for the display latency
> +      buffer to ensure that the back-end panel display data will not be
> +      underrun, a little more data is needed in the fifo.
> +      According to the merge fifo settings, when the water level is detected
> +      to be insufficient, it will trigger RDMA sending ultra and preulra
> +      command to SMI to speed up the data rate.
> +    type: boolean
>
>    mediatek,gce-client-reg:
>      description: The register of client driver can be configured by gce with
> @@ -47,6 +67,11 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/phandle-array
>      maxItems: 1
>
> +  resets:
> +    description: reset controller
> +      See Documentation/devicetree/bindings/reset/reset.txt for details.
> +    maxItems: 1
> +
>  required:
>    - compatible
>    - reg
> @@ -64,3 +89,16 @@ examples:
>          power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
>          clocks = <&mmsys CLK_MM_DISP_MERGE>;
>      };
> +
> +    merge5: disp_vpp_merge5@1c110000 {
> +        compatible = "mediatek,mt8195-disp-merge";
> +        reg = <0 0x1c110000 0 0x1000>;
> +        interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
> +        clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
> +                 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
> +        clock-names = "merge","merge_async";
> +        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
> +        mediatek,merge-fifo-en = <1>;
> +        resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
> +    };
> --
> 2.18.0
>

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 05/12] dt-bindings: display: mediatek: merge: add additional prop for mt8195
@ 2022-02-07 23:09     ` Chun-Kuang Hu
  0 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:09 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno, Enric Balletbo i Serra,
	Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
	Fabien Parent, Jitao shi, Nancy Lin, singo.chang, DTML,
	linux-stm32, Linux ARM, moderated list:ARM/Mediatek SoC support,
	linux-kernel

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> add MERGE additional properties description for mt8195:
> 1. async clock
> 2. fifo setting enable
> 3. reset controller

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../display/mediatek/mediatek,merge.yaml      | 38 +++++++++++++++++++
>  1 file changed, 38 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 7aa6974d509d..fae106cf1753 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -36,8 +36,28 @@ properties:
>        Documentation/devicetree/bindings/power/power-domain.yaml for details.
>
>    clocks:
> +    maxItems: 2
>      items:
>        - description: MERGE Clock
> +      - description: MERGE Async Clock
> +          Controlling the synchronous process between MERGE and other display
> +          function blocks cross clock domain.
> +
> +  clock-names:
> +    maxItems: 2
> +    items:
> +      - const: merge
> +      - const: merge_async
> +
> +  mediatek,merge-fifo-en:
> +    description:
> +      The setting of merge fifo is mainly provided for the display latency
> +      buffer to ensure that the back-end panel display data will not be
> +      underrun, a little more data is needed in the fifo.
> +      According to the merge fifo settings, when the water level is detected
> +      to be insufficient, it will trigger RDMA sending ultra and preulra
> +      command to SMI to speed up the data rate.
> +    type: boolean
>
>    mediatek,gce-client-reg:
>      description: The register of client driver can be configured by gce with
> @@ -47,6 +67,11 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/phandle-array
>      maxItems: 1
>
> +  resets:
> +    description: reset controller
> +      See Documentation/devicetree/bindings/reset/reset.txt for details.
> +    maxItems: 1
> +
>  required:
>    - compatible
>    - reg
> @@ -64,3 +89,16 @@ examples:
>          power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
>          clocks = <&mmsys CLK_MM_DISP_MERGE>;
>      };
> +
> +    merge5: disp_vpp_merge5@1c110000 {
> +        compatible = "mediatek,mt8195-disp-merge";
> +        reg = <0 0x1c110000 0 0x1000>;
> +        interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
> +        clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
> +                 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
> +        clock-names = "merge","merge_async";
> +        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
> +        mediatek,merge-fifo-en = <1>;
> +        resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
> +    };
> --
> 2.18.0
>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 05/12] dt-bindings: display: mediatek: merge: add additional prop for mt8195
@ 2022-02-07 23:09     ` Chun-Kuang Hu
  0 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:09 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno, Enric Balletbo i Serra,
	Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
	Fabien Parent, Jitao shi, Nancy Lin, singo.chang, DTML,
	linux-stm32, Linux ARM, moderated list:ARM/Mediatek SoC support,
	linux-kernel

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> add MERGE additional properties description for mt8195:
> 1. async clock
> 2. fifo setting enable
> 3. reset controller

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../display/mediatek/mediatek,merge.yaml      | 38 +++++++++++++++++++
>  1 file changed, 38 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index 7aa6974d509d..fae106cf1753 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -36,8 +36,28 @@ properties:
>        Documentation/devicetree/bindings/power/power-domain.yaml for details.
>
>    clocks:
> +    maxItems: 2
>      items:
>        - description: MERGE Clock
> +      - description: MERGE Async Clock
> +          Controlling the synchronous process between MERGE and other display
> +          function blocks cross clock domain.
> +
> +  clock-names:
> +    maxItems: 2
> +    items:
> +      - const: merge
> +      - const: merge_async
> +
> +  mediatek,merge-fifo-en:
> +    description:
> +      The setting of merge fifo is mainly provided for the display latency
> +      buffer to ensure that the back-end panel display data will not be
> +      underrun, a little more data is needed in the fifo.
> +      According to the merge fifo settings, when the water level is detected
> +      to be insufficient, it will trigger RDMA sending ultra and preulra
> +      command to SMI to speed up the data rate.
> +    type: boolean
>
>    mediatek,gce-client-reg:
>      description: The register of client driver can be configured by gce with
> @@ -47,6 +67,11 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/phandle-array
>      maxItems: 1
>
> +  resets:
> +    description: reset controller
> +      See Documentation/devicetree/bindings/reset/reset.txt for details.
> +    maxItems: 1
> +
>  required:
>    - compatible
>    - reg
> @@ -64,3 +89,16 @@ examples:
>          power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
>          clocks = <&mmsys CLK_MM_DISP_MERGE>;
>      };
> +
> +    merge5: disp_vpp_merge5@1c110000 {
> +        compatible = "mediatek,mt8195-disp-merge";
> +        reg = <0 0x1c110000 0 0x1000>;
> +        interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
> +        clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
> +                 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
> +        clock-names = "merge","merge_async";
> +        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
> +        mediatek,merge-fifo-en = <1>;
> +        resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
> +    };
> --
> 2.18.0
>

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
  2022-01-26  7:19   ` jason-jh.lin
  (?)
@ 2022-02-07 23:10     ` Chun-Kuang Hu
  -1 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:10 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent, DTML,
	Nancy Lin, linux-stm32, roy-cw.yeh, CK Hu, Chun-Kuang Hu,
	Jitao shi, Philipp Zabel, Rob Herring,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Maxime Coquelin, Enric Balletbo i Serra

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
> MUTEX, OVL and RDMA yaml schema for vdosys0.

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,aal.yaml   | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 5 +++++
>  .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
>  .../bindings/display/mediatek/mediatek,dither.yaml           | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
>  .../devicetree/bindings/display/mediatek/mediatek,mutex.yaml | 5 +++--
>  .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 5 +++++
>  .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 2 ++
>  9 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> index 044331f5aacb..225f9dd726d2 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> @@ -28,6 +28,7 @@ properties:
>                - mediatek,mt2712-disp-aal
>                - mediatek,mt8183-disp-aal
>                - mediatek,mt8192-disp-aal
> +              - mediatek,mt8195-disp-aal
>            - enum:
>                - mediatek,mt8173-disp-aal
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> index ea45b40edee7..6894b6999412 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> @@ -25,6 +25,11 @@ properties:
>            - const: mediatek,mt8183-disp-ccorr
>        - items:
>            - const: mediatek,mt8192-disp-ccorr
> +      - items:
> +          - enum:
> +              - mediatek,mt8195-disp-ccorr
> +          - enum:
> +              - mediatek,mt8192-disp-ccorr
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> index 13628f346718..bc83155b3b4c 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> @@ -38,6 +38,7 @@ properties:
>            - enum:
>                - mediatek,mt8183-disp-color
>                - mediatek,mt8192-disp-color
> +              - mediatek,mt8195-disp-color
>            - enum:
>                - mediatek,mt8173-disp-color
>    reg:
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> index 2c05e3019c75..9d89297f5f1d 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> @@ -27,6 +27,7 @@ properties:
>        - items:
>            - enum:
>                - mediatek,mt8192-disp-dither
> +              - mediatek,mt8195-disp-dither
>            - enum:
>                - mediatek,mt8183-disp-dither
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> index 89ccb8dbadd7..247baad147b3 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> @@ -28,6 +28,7 @@ properties:
>        - items:
>            - enum:
>                - mediatek,mt8192-disp-gamma
> +              - mediatek,mt8195-disp-gamma
>            - enum:
>                - mediatek,mt8183-disp-gamma
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index fae106cf1753..60b21ef5549b 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -23,6 +23,8 @@ properties:
>      oneOf:
>        - items:
>            - const: mediatek,mt8173-disp-merge
> +      - items:
> +          - const: mediatek,mt8195-disp-merge
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> index 90f11e12a55e..6eca525eced0 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> @@ -4,7 +4,7 @@
>  $id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Mediatek display mutex
> +title: Mediatek mutex
>
>  maintainers:
>    - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> @@ -36,7 +36,8 @@ properties:
>            - const: mediatek,mt8183-disp-mutex
>        - items:
>            - const: mediatek,mt8192-disp-mutex
> -
> +      - items:
> +          - const: mediatek,mt8195-disp-mutex
>    reg:
>      maxItems: 1
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> index 8e4a62cb9c81..e71f79bc2dee 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> @@ -35,6 +35,11 @@ properties:
>                - mediatek,mt2712-disp-ovl
>            - enum:
>                - mediatek,mt2701-disp-ovl
> +      - items:
> +          - enum:
> +              - mediatek,mt8195-disp-ovl
> +          - enum:
> +              - mediatek,mt8183-disp-ovl
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> index a3c5f4c9fbcd..8ef821641672 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> @@ -29,6 +29,8 @@ properties:
>            - const: mediatek,mt8173-disp-rdma
>        - items:
>            - const: mediatek,mt8183-disp-rdma
> +      - items:
> +          - const: mediatek,mt8195-disp-rdma
>        - items:
>            - enum:
>                - mediatek,mt7623-disp-rdma
> --
> 2.18.0
>

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
@ 2022-02-07 23:10     ` Chun-Kuang Hu
  0 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:10 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno, Enric Balletbo i Serra,
	Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
	Fabien Parent, Jitao shi, Nancy Lin, singo.chang, DTML,
	linux-stm32, Linux ARM, moderated list:ARM/Mediatek SoC support,
	linux-kernel

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
> MUTEX, OVL and RDMA yaml schema for vdosys0.

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,aal.yaml   | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 5 +++++
>  .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
>  .../bindings/display/mediatek/mediatek,dither.yaml           | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
>  .../devicetree/bindings/display/mediatek/mediatek,mutex.yaml | 5 +++--
>  .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 5 +++++
>  .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 2 ++
>  9 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> index 044331f5aacb..225f9dd726d2 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> @@ -28,6 +28,7 @@ properties:
>                - mediatek,mt2712-disp-aal
>                - mediatek,mt8183-disp-aal
>                - mediatek,mt8192-disp-aal
> +              - mediatek,mt8195-disp-aal
>            - enum:
>                - mediatek,mt8173-disp-aal
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> index ea45b40edee7..6894b6999412 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> @@ -25,6 +25,11 @@ properties:
>            - const: mediatek,mt8183-disp-ccorr
>        - items:
>            - const: mediatek,mt8192-disp-ccorr
> +      - items:
> +          - enum:
> +              - mediatek,mt8195-disp-ccorr
> +          - enum:
> +              - mediatek,mt8192-disp-ccorr
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> index 13628f346718..bc83155b3b4c 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> @@ -38,6 +38,7 @@ properties:
>            - enum:
>                - mediatek,mt8183-disp-color
>                - mediatek,mt8192-disp-color
> +              - mediatek,mt8195-disp-color
>            - enum:
>                - mediatek,mt8173-disp-color
>    reg:
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> index 2c05e3019c75..9d89297f5f1d 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> @@ -27,6 +27,7 @@ properties:
>        - items:
>            - enum:
>                - mediatek,mt8192-disp-dither
> +              - mediatek,mt8195-disp-dither
>            - enum:
>                - mediatek,mt8183-disp-dither
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> index 89ccb8dbadd7..247baad147b3 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> @@ -28,6 +28,7 @@ properties:
>        - items:
>            - enum:
>                - mediatek,mt8192-disp-gamma
> +              - mediatek,mt8195-disp-gamma
>            - enum:
>                - mediatek,mt8183-disp-gamma
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index fae106cf1753..60b21ef5549b 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -23,6 +23,8 @@ properties:
>      oneOf:
>        - items:
>            - const: mediatek,mt8173-disp-merge
> +      - items:
> +          - const: mediatek,mt8195-disp-merge
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> index 90f11e12a55e..6eca525eced0 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> @@ -4,7 +4,7 @@
>  $id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Mediatek display mutex
> +title: Mediatek mutex
>
>  maintainers:
>    - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> @@ -36,7 +36,8 @@ properties:
>            - const: mediatek,mt8183-disp-mutex
>        - items:
>            - const: mediatek,mt8192-disp-mutex
> -
> +      - items:
> +          - const: mediatek,mt8195-disp-mutex
>    reg:
>      maxItems: 1
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> index 8e4a62cb9c81..e71f79bc2dee 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> @@ -35,6 +35,11 @@ properties:
>                - mediatek,mt2712-disp-ovl
>            - enum:
>                - mediatek,mt2701-disp-ovl
> +      - items:
> +          - enum:
> +              - mediatek,mt8195-disp-ovl
> +          - enum:
> +              - mediatek,mt8183-disp-ovl
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> index a3c5f4c9fbcd..8ef821641672 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> @@ -29,6 +29,8 @@ properties:
>            - const: mediatek,mt8173-disp-rdma
>        - items:
>            - const: mediatek,mt8183-disp-rdma
> +      - items:
> +          - const: mediatek,mt8195-disp-rdma
>        - items:
>            - enum:
>                - mediatek,mt7623-disp-rdma
> --
> 2.18.0
>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
@ 2022-02-07 23:10     ` Chun-Kuang Hu
  0 siblings, 0 replies; 65+ messages in thread
From: Chun-Kuang Hu @ 2022-02-07 23:10 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: Rob Herring, Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno, Enric Balletbo i Serra,
	Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
	Fabien Parent, Jitao shi, Nancy Lin, singo.chang, DTML,
	linux-stm32, Linux ARM, moderated list:ARM/Mediatek SoC support,
	linux-kernel

Hi, Jason:

jason-jh.lin <jason-jh.lin@mediatek.com> 於 2022年1月26日 週三 下午3:19寫道：
>
> Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
> MUTEX, OVL and RDMA yaml schema for vdosys0.

Applied to mediatek-drm-next [1], thanks.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang

>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> ---
>  .../devicetree/bindings/display/mediatek/mediatek,aal.yaml   | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 5 +++++
>  .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 +
>  .../bindings/display/mediatek/mediatek,dither.yaml           | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
>  .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 2 ++
>  .../devicetree/bindings/display/mediatek/mediatek,mutex.yaml | 5 +++--
>  .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml   | 5 +++++
>  .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml  | 2 ++
>  9 files changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> index 044331f5aacb..225f9dd726d2 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
> @@ -28,6 +28,7 @@ properties:
>                - mediatek,mt2712-disp-aal
>                - mediatek,mt8183-disp-aal
>                - mediatek,mt8192-disp-aal
> +              - mediatek,mt8195-disp-aal
>            - enum:
>                - mediatek,mt8173-disp-aal
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> index ea45b40edee7..6894b6999412 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
> @@ -25,6 +25,11 @@ properties:
>            - const: mediatek,mt8183-disp-ccorr
>        - items:
>            - const: mediatek,mt8192-disp-ccorr
> +      - items:
> +          - enum:
> +              - mediatek,mt8195-disp-ccorr
> +          - enum:
> +              - mediatek,mt8192-disp-ccorr
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> index 13628f346718..bc83155b3b4c 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml
> @@ -38,6 +38,7 @@ properties:
>            - enum:
>                - mediatek,mt8183-disp-color
>                - mediatek,mt8192-disp-color
> +              - mediatek,mt8195-disp-color
>            - enum:
>                - mediatek,mt8173-disp-color
>    reg:
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> index 2c05e3019c75..9d89297f5f1d 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
> @@ -27,6 +27,7 @@ properties:
>        - items:
>            - enum:
>                - mediatek,mt8192-disp-dither
> +              - mediatek,mt8195-disp-dither
>            - enum:
>                - mediatek,mt8183-disp-dither
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> index 89ccb8dbadd7..247baad147b3 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
> @@ -28,6 +28,7 @@ properties:
>        - items:
>            - enum:
>                - mediatek,mt8192-disp-gamma
> +              - mediatek,mt8195-disp-gamma
>            - enum:
>                - mediatek,mt8183-disp-gamma
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> index fae106cf1753..60b21ef5549b 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
> @@ -23,6 +23,8 @@ properties:
>      oneOf:
>        - items:
>            - const: mediatek,mt8173-disp-merge
> +      - items:
> +          - const: mediatek,mt8195-disp-merge
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> index 90f11e12a55e..6eca525eced0 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.yaml
> @@ -4,7 +4,7 @@
>  $id: http://devicetree.org/schemas/display/mediatek/mediatek,mutex.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: Mediatek display mutex
> +title: Mediatek mutex
>
>  maintainers:
>    - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> @@ -36,7 +36,8 @@ properties:
>            - const: mediatek,mt8183-disp-mutex
>        - items:
>            - const: mediatek,mt8192-disp-mutex
> -
> +      - items:
> +          - const: mediatek,mt8195-disp-mutex
>    reg:
>      maxItems: 1
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> index 8e4a62cb9c81..e71f79bc2dee 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
> @@ -35,6 +35,11 @@ properties:
>                - mediatek,mt2712-disp-ovl
>            - enum:
>                - mediatek,mt2701-disp-ovl
> +      - items:
> +          - enum:
> +              - mediatek,mt8195-disp-ovl
> +          - enum:
> +              - mediatek,mt8183-disp-ovl
>
>    reg:
>      maxItems: 1
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> index a3c5f4c9fbcd..8ef821641672 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
> @@ -29,6 +29,8 @@ properties:
>            - const: mediatek,mt8173-disp-rdma
>        - items:
>            - const: mediatek,mt8183-disp-rdma
> +      - items:
> +          - const: mediatek,mt8195-disp-rdma
>        - items:
>            - enum:
>                - mediatek,mt7623-disp-rdma
> --
> 2.18.0
>

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
  2022-01-26  7:19 ` jason-jh.lin
@ 2022-02-14 10:13   ` Jason-JH Lin
  -1 siblings, 0 replies; 65+ messages in thread
From: Jason-JH Lin @ 2022-02-14 10:13 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	linux-kernel, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
	moudy.ho, linux-mediatek, Daniel Vetter, hsinyi,
	Enric Balletbo i Serra, nancy.lin, linux-stm32, linux-arm-kernel

Hello Matthias,

The DRM parts are all reviewed by Chun-Kuang.
Can you spare some time to give us some suggestion for mmsys parts?

Or do you think we should separate the driver of mmsys related patches
to another series and resend again?
Would it be better to combine mmsys related patches from vdosys0 [1]
and vdosys1 [2] series?

e.g.
[v1,0/7] soc: mediatek: mmsys: add mt8195 mmsys support 
[v1,1/7] dt-bindings: arm: mediatek: mmsys: add power and gce
properties
[v1,2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
[v1,3/7] dt-bindings: reset: mt8195: add vdosys1 reset control bit
[v1,4/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys0
[v1,5/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys1
[v1,6/7] soc: mediatek: mmsys: add mtk-mmsys config API for mt8195
vdosys1
[v1,7/7] soc: mediatek: mmsys: modify reset controller for MT8195
vdosys1

---
[1] Add Mediatek Soc DRM (vdosys0) support for mt8195
- 
https://patchwork.kernel.org/project/linux-mediatek/list/?series=608548
[2] Add MediaTek SoC DRM (vdosys1) support for mt8195
- 
https://patchwork.kernel.org/project/linux-mediatek/list/?series=604065
---

Regards,
Jason-JH.Lin


On Wed, 2022-01-26 at 15:19 +0800, jason-jh.lin wrote:
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
>   to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
> 
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
>   
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=602528
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>   
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=602834
> 
[snip]
...
> 
> jason-jh.lin (12):
>   dt-bindings: arm: mediatek: mmsys: add power and gce properties
>   dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
>   dt-bindings: display: mediatek: disp: split each block to
> individual
>     yaml
>   dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC
> binding
>   dt-bindings: display: mediatek: merge: add additional prop for
> mt8195
>   dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
>   dt-bindings: arm: mediatek: move out common module from display
> folder
>   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
>   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
>   drm/mediatek: add DSC support for mediatek-drm
>   drm/mediatek: add MERGE support for mediatek-drm
>   drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> 
>  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
>  .../display/mediatek/mediatek,disp.txt        | 219 ----------------
>  .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
>  .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
>  .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
>  .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
>  .../display/mediatek/mediatek,od.yaml         |  53 ++++
>  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
>  .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
>  .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
>  .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
>  .../display/mediatek/mediatek,split.yaml      |  58 +++++
>  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
>  .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
>  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
>  .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
>  .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
>  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
>  drivers/gpu/drm/mediatek/Makefile             |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246
> ++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
>  drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
>  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
>  drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
>  include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
>  30 files changed, 1832 insertions(+), 233 deletions(-)
>  delete mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya
> ml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yam
> l
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yam
> l
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-
> 2l.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.
> yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,split.yam
> l
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-02-14 10:13   ` Jason-JH Lin
  0 siblings, 0 replies; 65+ messages in thread
From: Jason-JH Lin @ 2022-02-14 10:13 UTC (permalink / raw)
  To: Matthias Brugger, Rob Herring, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	linux-kernel, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, CK Hu,
	moudy.ho, linux-mediatek, Daniel Vetter, hsinyi,
	Enric Balletbo i Serra, nancy.lin, linux-stm32, linux-arm-kernel

Hello Matthias,

The DRM parts are all reviewed by Chun-Kuang.
Can you spare some time to give us some suggestion for mmsys parts?

Or do you think we should separate the driver of mmsys related patches
to another series and resend again?
Would it be better to combine mmsys related patches from vdosys0 [1]
and vdosys1 [2] series?

e.g.
[v1,0/7] soc: mediatek: mmsys: add mt8195 mmsys support 
[v1,1/7] dt-bindings: arm: mediatek: mmsys: add power and gce
properties
[v1,2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
[v1,3/7] dt-bindings: reset: mt8195: add vdosys1 reset control bit
[v1,4/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys0
[v1,5/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys1
[v1,6/7] soc: mediatek: mmsys: add mtk-mmsys config API for mt8195
vdosys1
[v1,7/7] soc: mediatek: mmsys: modify reset controller for MT8195
vdosys1

---
[1] Add Mediatek Soc DRM (vdosys0) support for mt8195
- 
https://patchwork.kernel.org/project/linux-mediatek/list/?series=608548
[2] Add MediaTek SoC DRM (vdosys1) support for mt8195
- 
https://patchwork.kernel.org/project/linux-mediatek/list/?series=604065
---

Regards,
Jason-JH.Lin


On Wed, 2022-01-26 at 15:19 +0800, jason-jh.lin wrote:
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
>   to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
> 
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
>   
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=602528
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>   
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=602834
> 
[snip]
...
> 
> jason-jh.lin (12):
>   dt-bindings: arm: mediatek: mmsys: add power and gce properties
>   dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
>   dt-bindings: display: mediatek: disp: split each block to
> individual
>     yaml
>   dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC
> binding
>   dt-bindings: display: mediatek: merge: add additional prop for
> mt8195
>   dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
>   dt-bindings: arm: mediatek: move out common module from display
> folder
>   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
>   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
>   drm/mediatek: add DSC support for mediatek-drm
>   drm/mediatek: add MERGE support for mediatek-drm
>   drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> 
>  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
>  .../display/mediatek/mediatek,disp.txt        | 219 ----------------
>  .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
>  .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
>  .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
>  .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
>  .../display/mediatek/mediatek,od.yaml         |  53 ++++
>  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
>  .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
>  .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
>  .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
>  .../display/mediatek/mediatek,split.yaml      |  58 +++++
>  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
>  .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
>  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
>  .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
>  .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
>  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
>  drivers/gpu/drm/mediatek/Makefile             |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246
> ++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
>  drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
>  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
>  drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
>  include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
>  30 files changed, 1832 insertions(+), 233 deletions(-)
>  delete mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya
> ml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yam
> l
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yam
> l
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-
> 2l.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.
> yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,split.yam
> l
>  create mode 100644
> Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
  2022-02-14 10:13   ` Jason-JH Lin
  (?)
@ 2022-03-02 13:26     ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-02 13:26 UTC (permalink / raw)
  To: Jason-JH Lin, Matthias Brugger, Rob Herring, Chun-Kuang Hu,
	Philipp Zabel
  Cc: Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, CK Hu, Fabien Parent,
	Jitao shi, nancy.lin, singo.chang, devicetree, linux-stm32,
	linux-arm-kernel, linux-mediatek, linux-kernel,
	Project_Global_Chrome_Upstream_Group

Il 14/02/22 11:13, Jason-JH Lin ha scritto:
> Hello Matthias,
> 
> The DRM parts are all reviewed by Chun-Kuang.
> Can you spare some time to give us some suggestion for mmsys parts?
> 
> Or do you think we should separate the driver of mmsys related patches
> to another series and resend again?
> Would it be better to combine mmsys related patches from vdosys0 [1]
> and vdosys1 [2] series?
> 
> e.g.
> [v1,0/7] soc: mediatek: mmsys: add mt8195 mmsys support
> [v1,1/7] dt-bindings: arm: mediatek: mmsys: add power and gce
> properties
> [v1,2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> [v1,3/7] dt-bindings: reset: mt8195: add vdosys1 reset control bit
> [v1,4/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys0
> [v1,5/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys1
> [v1,6/7] soc: mediatek: mmsys: add mtk-mmsys config API for mt8195
> vdosys1
> [v1,7/7] soc: mediatek: mmsys: modify reset controller for MT8195
> vdosys1
> 
> ---
> [1] Add Mediatek Soc DRM (vdosys0) support for mt8195
> -
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=608548
> [2] Add MediaTek SoC DRM (vdosys1) support for mt8195
> -
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=604065
> ---
> 
> Regards,
> Jason-JH.Lin
> 

Hello everyone,

I think that all the drm/mediatek and soc/mediatek patches in this series
are safe and ready (and also tested for regressions on older SoCs).

Feel free to pick them in your trees.

Cheers,
Angelo



^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-02 13:26     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-02 13:26 UTC (permalink / raw)
  To: Jason-JH Lin, Matthias Brugger, Rob Herring, Chun-Kuang Hu,
	Philipp Zabel
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	linux-kernel, singo.chang, Alexandre Torgue, roy-cw.yeh,
	Project_Global_Chrome_Upstream_Group, Fabien Parent, moudy.ho,
	linux-mediatek, Daniel Vetter, hsinyi, CK Hu, nancy.lin,
	linux-stm32, linux-arm-kernel

Il 14/02/22 11:13, Jason-JH Lin ha scritto:
> Hello Matthias,
> 
> The DRM parts are all reviewed by Chun-Kuang.
> Can you spare some time to give us some suggestion for mmsys parts?
> 
> Or do you think we should separate the driver of mmsys related patches
> to another series and resend again?
> Would it be better to combine mmsys related patches from vdosys0 [1]
> and vdosys1 [2] series?
> 
> e.g.
> [v1,0/7] soc: mediatek: mmsys: add mt8195 mmsys support
> [v1,1/7] dt-bindings: arm: mediatek: mmsys: add power and gce
> properties
> [v1,2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> [v1,3/7] dt-bindings: reset: mt8195: add vdosys1 reset control bit
> [v1,4/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys0
> [v1,5/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys1
> [v1,6/7] soc: mediatek: mmsys: add mtk-mmsys config API for mt8195
> vdosys1
> [v1,7/7] soc: mediatek: mmsys: modify reset controller for MT8195
> vdosys1
> 
> ---
> [1] Add Mediatek Soc DRM (vdosys0) support for mt8195
> -
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=608548
> [2] Add MediaTek SoC DRM (vdosys1) support for mt8195
> -
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=604065
> ---
> 
> Regards,
> Jason-JH.Lin
> 

Hello everyone,

I think that all the drm/mediatek and soc/mediatek patches in this series
are safe and ready (and also tested for regressions on older SoCs).

Feel free to pick them in your trees.

Cheers,
Angelo



_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-02 13:26     ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-02 13:26 UTC (permalink / raw)
  To: Jason-JH Lin, Matthias Brugger, Rob Herring, Chun-Kuang Hu,
	Philipp Zabel
  Cc: devicetree, Jitao shi, Maxime Coquelin, David Airlie,
	linux-kernel, singo.chang, Alexandre Torgue, roy-cw.yeh,
	Project_Global_Chrome_Upstream_Group, Fabien Parent, moudy.ho,
	linux-mediatek, Daniel Vetter, hsinyi, CK Hu, nancy.lin,
	linux-stm32, linux-arm-kernel

Il 14/02/22 11:13, Jason-JH Lin ha scritto:
> Hello Matthias,
> 
> The DRM parts are all reviewed by Chun-Kuang.
> Can you spare some time to give us some suggestion for mmsys parts?
> 
> Or do you think we should separate the driver of mmsys related patches
> to another series and resend again?
> Would it be better to combine mmsys related patches from vdosys0 [1]
> and vdosys1 [2] series?
> 
> e.g.
> [v1,0/7] soc: mediatek: mmsys: add mt8195 mmsys support
> [v1,1/7] dt-bindings: arm: mediatek: mmsys: add power and gce
> properties
> [v1,2/7] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> [v1,3/7] dt-bindings: reset: mt8195: add vdosys1 reset control bit
> [v1,4/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys0
> [v1,5/7] soc: mediatek: mmsys: add mtk-mmsys support for mt8195 vdosys1
> [v1,6/7] soc: mediatek: mmsys: add mtk-mmsys config API for mt8195
> vdosys1
> [v1,7/7] soc: mediatek: mmsys: modify reset controller for MT8195
> vdosys1
> 
> ---
> [1] Add Mediatek Soc DRM (vdosys0) support for mt8195
> -
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=608548
> [2] Add MediaTek SoC DRM (vdosys1) support for mt8195
> -
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=604065
> ---
> 
> Regards,
> Jason-JH.Lin
> 

Hello everyone,

I think that all the drm/mediatek and soc/mediatek patches in this series
are safe and ready (and also tested for regressions on older SoCs).

Feel free to pick them in your trees.

Cheers,
Angelo



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
  2022-01-26  7:19 ` jason-jh.lin
  (?)
@ 2022-03-02 23:50   ` Rob Herring
  -1 siblings, 0 replies; 65+ messages in thread
From: Rob Herring @ 2022-03-02 23:50 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: Matthias Brugger, Chun-Kuang Hu, Philipp Zabel,
	AngeloGioacchino Del Regno, Enric Balletbo i Serra,
	Maxime Coquelin, David Airlie, Daniel Vetter, Alexandre Torgue,
	Hsin-Yi Wang, Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu,
	Fabien Parent, Jitao shi, nancy.lin, singo.chang, devicetree,
	moderated list:ARM/STM32 ARCHITECTURE, linux-arm-kernel,
	moderated list:ARM/Mediatek SoC support, linux-kernel

On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
>   to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
>
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=602528
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=602834
>
> Change in v13:
> - remove dts patch
> - rebase on kernel-5.16-rc1
> - rebase on mediatek-drm-next
>
> Change in v12:
> - add clock-names property to merge yaml
> - using BIT(nr) macro to define the settings of mmsys routing table
> - fix clk_get and clk_prepare_enable error handling issue
>
> Change in v11:
> - rebase on kernel-5.15-rc1
> - change mbox label to gce0 for dts node of vdosys0
> - change ovl compatibale to mt8192 to set smi_id_en=true in driver data
> - move common module from display folder to common folder,
>   such as AAL, COCLOR, CCORR and MUTEX
>
> Change in v10:
> - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
> - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857
> - fix some typo and "mediatek" start with capital in every dt-bindings
> - move mutex yaml from dfisplay folder to soc folder
> - separate merge additional propoerties to an individual dt-bindings patch
>
> Change in v9:
> - separate power and gce properties of mmsys into another dt-binding patch
> - rebase on "Separate aal module" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
> - keep mtk_ddp_clk_enable/disable in the same place
> - change mtk_dsc_start config register to mtk_drm_ddp_write_mask
> - remove the 0 setting of merge fifo config function
> - add CCORR driver data for mt8195
>
> Change in v8:
> - add DP_INTF0 mux into mmsys routing table
> - add DP_INTF0 mutex mod and enum into add/remove comp function
> - remove bypass DSC enum in mtk_ddp_comp_init
>
> Change in v7:
> - add dt=binding of mmsys and disp path into this series
> - separate th modidfication of alphabetic order, remove unused define and
>   rename the define of register offset to individual patch
> - add comment for MERGE ultra and preultra setting
>
> Change in v6:
> - adjust alphabetic order for mediatek-drm
> - move the patch that add mt8195 support for mediatek-drm as
>   the lastest patch
> - add MERGE define for const varriable
>
> Change in v5:
> - add power-domain property into vdosys0 and vdosys1 dts node.
> - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
>
> Change in v4:
> - extract dt-binding patches to another patch series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
> - squash DSC module into mtk_drm_ddp_comp.c
> - add coment and simplify MERGE config function
>
> Change in v3:
> - change mmsys and display dt-bindings document from txt to yaml
> - add MERGE additional description in display dt-bindings document
> - fix mboxes-cells number of vdosys0 node in dts
> - drop mutex eof convert define
> - remove pm_runtime apis in DSC and MERGE
> - change DSC and MERGE enum to alphabetic order
>
> Change in v2:
> - add DSC yaml file
> - add mt8195 drm driver porting parts in to one patch
> - remove useless define, variable, structure member and function
> - simplify DSC and MERGE file and switch threre order
>
> jason-jh.lin (12):
>   dt-bindings: arm: mediatek: mmsys: add power and gce properties
>   dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
>   dt-bindings: display: mediatek: disp: split each block to individual
>     yaml
>   dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
>   dt-bindings: display: mediatek: merge: add additional prop for mt8195
>   dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
>   dt-bindings: arm: mediatek: move out common module from display folder
>   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
>   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
>   drm/mediatek: add DSC support for mediatek-drm
>   drm/mediatek: add MERGE support for mediatek-drm
>   drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
>
>  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
>  .../display/mediatek/mediatek,disp.txt        | 219 ----------------
>  .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
>  .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
>  .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
>  .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
>  .../display/mediatek/mediatek,od.yaml         |  53 ++++
>  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
>  .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
>  .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
>  .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
>  .../display/mediatek/mediatek,split.yaml      |  58 +++++
>  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
>  .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
>  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
>  .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
>  .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
>  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
>  drivers/gpu/drm/mediatek/Makefile             |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246 ++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
>  drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
>  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
>  drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
>  include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
>  30 files changed, 1832 insertions(+), 233 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

Looks like this is in linux-next and now:

Error: Documentation/devicetree/bindings/display/mediatek/mediatek,aal.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,dither.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,od.example.dts:24.30-31
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,od.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,color.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,color.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dts:35.50-51
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,split.example.dts:24.35-36
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,split.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,merge.example.dts:27.35-36
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.example.dt.yaml]
Error 1

Please fix 'make dt_binding_check'.

Rob

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-02 23:50   ` Rob Herring
  0 siblings, 0 replies; 65+ messages in thread
From: Rob Herring @ 2022-03-02 23:50 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	devicetree, moderated list:ARM/STM32 ARCHITECTURE, roy-cw.yeh,
	CK Hu, Chun-Kuang Hu, Jitao shi, Maxime Coquelin, nancy.lin,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, linux-arm-kernel,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Philipp Zabel, Enric Balletbo i Serra

On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
>   to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
>
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=602528
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=602834
>
> Change in v13:
> - remove dts patch
> - rebase on kernel-5.16-rc1
> - rebase on mediatek-drm-next
>
> Change in v12:
> - add clock-names property to merge yaml
> - using BIT(nr) macro to define the settings of mmsys routing table
> - fix clk_get and clk_prepare_enable error handling issue
>
> Change in v11:
> - rebase on kernel-5.15-rc1
> - change mbox label to gce0 for dts node of vdosys0
> - change ovl compatibale to mt8192 to set smi_id_en=true in driver data
> - move common module from display folder to common folder,
>   such as AAL, COCLOR, CCORR and MUTEX
>
> Change in v10:
> - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
> - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857
> - fix some typo and "mediatek" start with capital in every dt-bindings
> - move mutex yaml from dfisplay folder to soc folder
> - separate merge additional propoerties to an individual dt-bindings patch
>
> Change in v9:
> - separate power and gce properties of mmsys into another dt-binding patch
> - rebase on "Separate aal module" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
> - keep mtk_ddp_clk_enable/disable in the same place
> - change mtk_dsc_start config register to mtk_drm_ddp_write_mask
> - remove the 0 setting of merge fifo config function
> - add CCORR driver data for mt8195
>
> Change in v8:
> - add DP_INTF0 mux into mmsys routing table
> - add DP_INTF0 mutex mod and enum into add/remove comp function
> - remove bypass DSC enum in mtk_ddp_comp_init
>
> Change in v7:
> - add dt=binding of mmsys and disp path into this series
> - separate th modidfication of alphabetic order, remove unused define and
>   rename the define of register offset to individual patch
> - add comment for MERGE ultra and preultra setting
>
> Change in v6:
> - adjust alphabetic order for mediatek-drm
> - move the patch that add mt8195 support for mediatek-drm as
>   the lastest patch
> - add MERGE define for const varriable
>
> Change in v5:
> - add power-domain property into vdosys0 and vdosys1 dts node.
> - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
>
> Change in v4:
> - extract dt-binding patches to another patch series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
> - squash DSC module into mtk_drm_ddp_comp.c
> - add coment and simplify MERGE config function
>
> Change in v3:
> - change mmsys and display dt-bindings document from txt to yaml
> - add MERGE additional description in display dt-bindings document
> - fix mboxes-cells number of vdosys0 node in dts
> - drop mutex eof convert define
> - remove pm_runtime apis in DSC and MERGE
> - change DSC and MERGE enum to alphabetic order
>
> Change in v2:
> - add DSC yaml file
> - add mt8195 drm driver porting parts in to one patch
> - remove useless define, variable, structure member and function
> - simplify DSC and MERGE file and switch threre order
>
> jason-jh.lin (12):
>   dt-bindings: arm: mediatek: mmsys: add power and gce properties
>   dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
>   dt-bindings: display: mediatek: disp: split each block to individual
>     yaml
>   dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
>   dt-bindings: display: mediatek: merge: add additional prop for mt8195
>   dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
>   dt-bindings: arm: mediatek: move out common module from display folder
>   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
>   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
>   drm/mediatek: add DSC support for mediatek-drm
>   drm/mediatek: add MERGE support for mediatek-drm
>   drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
>
>  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
>  .../display/mediatek/mediatek,disp.txt        | 219 ----------------
>  .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
>  .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
>  .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
>  .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
>  .../display/mediatek/mediatek,od.yaml         |  53 ++++
>  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
>  .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
>  .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
>  .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
>  .../display/mediatek/mediatek,split.yaml      |  58 +++++
>  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
>  .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
>  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
>  .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
>  .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
>  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
>  drivers/gpu/drm/mediatek/Makefile             |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246 ++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
>  drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
>  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
>  drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
>  include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
>  30 files changed, 1832 insertions(+), 233 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

Looks like this is in linux-next and now:

Error: Documentation/devicetree/bindings/display/mediatek/mediatek,aal.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,dither.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,od.example.dts:24.30-31
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,od.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,color.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,color.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dts:35.50-51
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,split.example.dts:24.35-36
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,split.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,merge.example.dts:27.35-36
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.example.dt.yaml]
Error 1

Please fix 'make dt_binding_check'.

Rob

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-02 23:50   ` Rob Herring
  0 siblings, 0 replies; 65+ messages in thread
From: Rob Herring @ 2022-03-02 23:50 UTC (permalink / raw)
  To: jason-jh.lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	devicetree, moderated list:ARM/STM32 ARCHITECTURE, roy-cw.yeh,
	CK Hu, Chun-Kuang Hu, Jitao shi, Maxime Coquelin, nancy.lin,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, linux-arm-kernel,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Philipp Zabel, Enric Balletbo i Serra

On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> Change in v15:
> - remove mt8195-mmsys.h comment for mux settings
> - define the mask macro to replace using value as mask
>   to fix zero mask problem
> - add EOF setting comment for MUTEX sof register
>
> Change in v14:
> - rebase on mediatek-drm-next-5.17
> - rebase on "Add mmsys and mutex support for MDP" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=602528
> - rebase on "media: mediatek: support mdp3 on mt8183 platform" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=602834
>
> Change in v13:
> - remove dts patch
> - rebase on kernel-5.16-rc1
> - rebase on mediatek-drm-next
>
> Change in v12:
> - add clock-names property to merge yaml
> - using BIT(nr) macro to define the settings of mmsys routing table
> - fix clk_get and clk_prepare_enable error handling issue
>
> Change in v11:
> - rebase on kernel-5.15-rc1
> - change mbox label to gce0 for dts node of vdosys0
> - change ovl compatibale to mt8192 to set smi_id_en=true in driver data
> - move common module from display folder to common folder,
>   such as AAL, COCLOR, CCORR and MUTEX
>
> Change in v10:
> - rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489
> - rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=524857
> - fix some typo and "mediatek" start with capital in every dt-bindings
> - move mutex yaml from dfisplay folder to soc folder
> - separate merge additional propoerties to an individual dt-bindings patch
>
> Change in v9:
> - separate power and gce properties of mmsys into another dt-binding patch
> - rebase on "Separate aal module" series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=516463
> - keep mtk_ddp_clk_enable/disable in the same place
> - change mtk_dsc_start config register to mtk_drm_ddp_write_mask
> - remove the 0 setting of merge fifo config function
> - add CCORR driver data for mt8195
>
> Change in v8:
> - add DP_INTF0 mux into mmsys routing table
> - add DP_INTF0 mutex mod and enum into add/remove comp function
> - remove bypass DSC enum in mtk_ddp_comp_init
>
> Change in v7:
> - add dt=binding of mmsys and disp path into this series
> - separate th modidfication of alphabetic order, remove unused define and
>   rename the define of register offset to individual patch
> - add comment for MERGE ultra and preultra setting
>
> Change in v6:
> - adjust alphabetic order for mediatek-drm
> - move the patch that add mt8195 support for mediatek-drm as
>   the lastest patch
> - add MERGE define for const varriable
>
> Change in v5:
> - add power-domain property into vdosys0 and vdosys1 dts node.
> - add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h
>
> Change in v4:
> - extract dt-binding patches to another patch series
>   https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597
> - squash DSC module into mtk_drm_ddp_comp.c
> - add coment and simplify MERGE config function
>
> Change in v3:
> - change mmsys and display dt-bindings document from txt to yaml
> - add MERGE additional description in display dt-bindings document
> - fix mboxes-cells number of vdosys0 node in dts
> - drop mutex eof convert define
> - remove pm_runtime apis in DSC and MERGE
> - change DSC and MERGE enum to alphabetic order
>
> Change in v2:
> - add DSC yaml file
> - add mt8195 drm driver porting parts in to one patch
> - remove useless define, variable, structure member and function
> - simplify DSC and MERGE file and switch threre order
>
> jason-jh.lin (12):
>   dt-bindings: arm: mediatek: mmsys: add power and gce properties
>   dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
>   dt-bindings: display: mediatek: disp: split each block to individual
>     yaml
>   dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding
>   dt-bindings: display: mediatek: merge: add additional prop for mt8195
>   dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0
>   dt-bindings: arm: mediatek: move out common module from display folder
>   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
>   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
>   drm/mediatek: add DSC support for mediatek-drm
>   drm/mediatek: add MERGE support for mediatek-drm
>   drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
>
>  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
>  .../display/mediatek/mediatek,disp.txt        | 219 ----------------
>  .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
>  .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
>  .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
>  .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
>  .../display/mediatek/mediatek,od.yaml         |  53 ++++
>  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
>  .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
>  .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
>  .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
>  .../display/mediatek/mediatek,split.yaml      |  58 +++++
>  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
>  .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
>  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
>  .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
>  .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
>  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
>  drivers/gpu/drm/mediatek/Makefile             |   1 +
>  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
>  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246 ++++++++++++++++++
>  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
>  drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
>  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
>  drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
>  include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
>  30 files changed, 1832 insertions(+), 233 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

Looks like this is in linux-next and now:

Error: Documentation/devicetree/bindings/display/mediatek/mediatek,aal.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,aal.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,dither.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,dither.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,od.example.dts:24.30-31
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,od.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,color.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,color.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dts:35.50-51
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,split.example.dts:24.35-36
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,split.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,merge.example.dts:27.35-36
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,merge.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.example.dt.yaml]
Error 1
Error: Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.example.dts:27.27-28
syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:386:
Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.example.dt.yaml]
Error 1

Please fix 'make dt_binding_check'.

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
  2022-02-07 23:07       ` Chun-Kuang Hu
  (?)
@ 2022-03-03  0:00         ` Rob Herring
  -1 siblings, 0 replies; 65+ messages in thread
From: Rob Herring @ 2022-03-03  0:00 UTC (permalink / raw)
  To: Chun-Kuang Hu, jason-jh . lin
  Cc: Matthias Brugger, Philipp Zabel, AngeloGioacchino Del Regno,
	Enric Balletbo i Serra, Maxime Coquelin, David Airlie,
	Daniel Vetter, Alexandre Torgue, Hsin-Yi Wang, Fei Shao,
	Moudy Ho, roy-cw.yeh, CK Hu, Fabien Parent, Jitao shi, Nancy Lin,
	singo.chang, DTML, moderated list:ARM/STM32 ARCHITECTURE,
	Linux ARM, moderated list:ARM/Mediatek SoC support, linux-kernel

On Mon, Feb 7, 2022 at 5:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> OK, it seems no one has comment on this patch, so

No comment because the patch was not in PW. That's most likely due to this:

Subject: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split
each block to individual yaml
Date: Wed, 26 Jan 2022 15:19:23 +0800 [thread overview]
Message-ID: <20220126071932.32615-4-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20220126071932.32615-1-jason-jh.lin@mediatek.com>

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="y", Size: 50916 bytes --]

"y" is not a valid charset. This is caused when git-send-email asks
for the encoding and you answer 'y' rather than <enter>.

Rob

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
@ 2022-03-03  0:00         ` Rob Herring
  0 siblings, 0 replies; 65+ messages in thread
From: Rob Herring @ 2022-03-03  0:00 UTC (permalink / raw)
  To: Chun-Kuang Hu, jason-jh . lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	moderated list:ARM/STM32 ARCHITECTURE, roy-cw.yeh, CK Hu, DTML,
	Jitao shi, Maxime Coquelin, Nancy Lin,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Philipp Zabel, Enric Balletbo i Serra

On Mon, Feb 7, 2022 at 5:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> OK, it seems no one has comment on this patch, so

No comment because the patch was not in PW. That's most likely due to this:

Subject: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split
each block to individual yaml
Date: Wed, 26 Jan 2022 15:19:23 +0800 [thread overview]
Message-ID: <20220126071932.32615-4-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20220126071932.32615-1-jason-jh.lin@mediatek.com>

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="y", Size: 50916 bytes --]

"y" is not a valid charset. This is caused when git-send-email asks
for the encoding and you answer 'y' rather than <enter>.

Rob

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
@ 2022-03-03  0:00         ` Rob Herring
  0 siblings, 0 replies; 65+ messages in thread
From: Rob Herring @ 2022-03-03  0:00 UTC (permalink / raw)
  To: Chun-Kuang Hu, jason-jh . lin
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	moderated list:ARM/STM32 ARCHITECTURE, roy-cw.yeh, CK Hu, DTML,
	Jitao shi, Maxime Coquelin, Nancy Lin,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Philipp Zabel, Enric Balletbo i Serra

On Mon, Feb 7, 2022 at 5:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> OK, it seems no one has comment on this patch, so

No comment because the patch was not in PW. That's most likely due to this:

Subject: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split
each block to individual yaml
Date: Wed, 26 Jan 2022 15:19:23 +0800 [thread overview]
Message-ID: <20220126071932.32615-4-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20220126071932.32615-1-jason-jh.lin@mediatek.com>

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="y", Size: 50916 bytes --]

"y" is not a valid charset. This is caused when git-send-email asks
for the encoding and you answer 'y' rather than <enter>.

Rob

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
  2022-03-02 23:50   ` Rob Herring
@ 2022-03-03  4:25     ` Jason-JH Lin
  -1 siblings, 0 replies; 65+ messages in thread
From: Jason-JH Lin @ 2022-03-03  4:25 UTC (permalink / raw)
  To: Rob Herring
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	devicetree, moderated list:ARM/STM32 ARCHITECTURE, roy-cw.yeh,
	CK Hu, Chun-Kuang Hu, Jitao shi, Maxime Coquelin, nancy.lin,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, linux-arm-kernel,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Philipp Zabel, Enric Balletbo i Serra

Hi Rob,

Thanks for the reviews.

On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
> On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
> jason-jh.lin@mediatek.com> wrote:
> > 

[snip]

> > jason-jh.lin (12):
> >   dt-bindings: arm: mediatek: mmsys: add power and gce properties
> >   dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> >   dt-bindings: display: mediatek: disp: split each block to
> > individual
> >     yaml
> >   dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC
> > binding
> >   dt-bindings: display: mediatek: merge: add additional prop for
> > mt8195
> >   dt-bindings: display: mediatek: add mt8195 SoC binding for
> > vdosys0
> >   dt-bindings: arm: mediatek: move out common module from display
> > folder
> >   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> >   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> >   drm/mediatek: add DSC support for mediatek-drm
> >   drm/mediatek: add MERGE support for mediatek-drm
> >   drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> > 
> >  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
> >  .../display/mediatek/mediatek,disp.txt        | 219 --------------
> > --
> >  .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
> >  .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
> >  .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
> >  .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
> >  .../display/mediatek/mediatek,od.yaml         |  53 ++++
> >  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
> >  .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
> >  .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
> >  .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
> >  .../display/mediatek/mediatek,split.yaml      |  58 +++++
> >  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
> >  .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
> >  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
> >  .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
> >  .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
> >  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
> >  drivers/gpu/drm/mediatek/Makefile             |   1 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246
> > ++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
> >  drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
> >  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
> >  drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
> >  include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
> >  30 files changed, 1832 insertions(+), 233 deletions(-)
> >  delete mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.tx
> > t
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dither.
> > yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yam
> > l
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y
> > aml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> > aml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-
> > 2l.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yam
> > l
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,postmas
> > k.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.ya
> > ml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,split.y
> > aml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.ya
> > ml
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
> Looks like this is in linux-next and now:
> 
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,aal.examp
> le.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,aal.examp
> le.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.exam
> ple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.exam
> ple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.exa
> mple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ex
> ample.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ex
> ample.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.
> example.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.
> example.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.exam
> ple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.exam
> ple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.exa
> mple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.exam
> ple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.exam
> ple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,od.exampl
> e.dts:24.30-31
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,od.exampl
> e.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,color.exa
> mple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,color.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.exa
> mple.dts:35.50-51
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,split.exa
> mple.dts:24.35-36
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,split.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,merge.exa
> mple.dts:27.35-36
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,merge.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.exa
> mple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.examp
> le.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.examp
> le.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-
> 2l.example.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-
> 2l.example.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.examp
> le.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.examp
> le.dt.yaml]
> Error 1
> 
> Please fix 'make dt_binding_check'.
> 
> Rob
-- 

I'll fix it at the next version.

Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-03  4:25     ` Jason-JH Lin
  0 siblings, 0 replies; 65+ messages in thread
From: Jason-JH Lin @ 2022-03-03  4:25 UTC (permalink / raw)
  To: Rob Herring
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	devicetree, moderated list:ARM/STM32 ARCHITECTURE, roy-cw.yeh,
	CK Hu, Chun-Kuang Hu, Jitao shi, Maxime Coquelin, nancy.lin,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, linux-arm-kernel,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Philipp Zabel, Enric Balletbo i Serra

Hi Rob,

Thanks for the reviews.

On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
> On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
> jason-jh.lin@mediatek.com> wrote:
> > 

[snip]

> > jason-jh.lin (12):
> >   dt-bindings: arm: mediatek: mmsys: add power and gce properties
> >   dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
> >   dt-bindings: display: mediatek: disp: split each block to
> > individual
> >     yaml
> >   dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC
> > binding
> >   dt-bindings: display: mediatek: merge: add additional prop for
> > mt8195
> >   dt-bindings: display: mediatek: add mt8195 SoC binding for
> > vdosys0
> >   dt-bindings: arm: mediatek: move out common module from display
> > folder
> >   soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
> >   soc: mediatek: add mtk-mutex support for mt8195 vdosys0
> >   drm/mediatek: add DSC support for mediatek-drm
> >   drm/mediatek: add MERGE support for mediatek-drm
> >   drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
> > 
> >  .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++-
> >  .../display/mediatek/mediatek,disp.txt        | 219 --------------
> > --
> >  .../display/mediatek/mediatek,dither.yaml     |  76 ++++++
> >  .../display/mediatek/mediatek,dsc.yaml        |  71 +++++
> >  .../display/mediatek/mediatek,gamma.yaml      |  77 ++++++
> >  .../display/mediatek/mediatek,merge.yaml      | 106 ++++++++
> >  .../display/mediatek/mediatek,od.yaml         |  53 ++++
> >  .../display/mediatek/mediatek,ovl-2l.yaml     |  88 +++++++
> >  .../display/mediatek/mediatek,ovl.yaml        | 103 ++++++++
> >  .../display/mediatek/mediatek,postmask.yaml   |  69 +++++
> >  .../display/mediatek/mediatek,rdma.yaml       | 117 +++++++++
> >  .../display/mediatek/mediatek,split.yaml      |  58 +++++
> >  .../display/mediatek/mediatek,ufoe.yaml       |  61 +++++
> >  .../bindings/soc/mediatek/mediatek,aal.yaml   |  72 +++++
> >  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  46 +++-
> >  .../bindings/soc/mediatek/mediatek,color.yaml |  81 ++++++
> >  .../bindings/soc/mediatek/mediatek,mutex.yaml |  77 ++++++
> >  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  47 +++-
> >  drivers/gpu/drm/mediatek/Makefile             |   1 +
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
> >  drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246
> > ++++++++++++++++++
> >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  63 +++++
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  32 ++-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   1 +
> >  drivers/soc/mediatek/mt8195-mmsys.h           | 130 +++++++++
> >  drivers/soc/mediatek/mtk-mmsys.c              |  11 +
> >  drivers/soc/mediatek/mtk-mutex.c              | 103 +++++++-
> >  include/linux/soc/mediatek/mtk-mmsys.h        |   9 +
> >  30 files changed, 1832 insertions(+), 233 deletions(-)
> >  delete mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.tx
> > t
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dither.
> > yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yam
> > l
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.y
> > aml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,merge.y
> > aml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-
> > 2l.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yam
> > l
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,postmas
> > k.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.ya
> > ml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,split.y
> > aml
> >  create mode 100644
> > Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.ya
> > ml
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,aal.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,color.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml
> >  create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> >  create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
> 
> Looks like this is in linux-next and now:
> 
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,aal.examp
> le.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,aal.examp
> le.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.exam
> ple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.exam
> ple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.exa
> mple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ex
> ample.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ex
> ample.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.
> example.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.
> example.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.exam
> ple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.exam
> ple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.exa
> mple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.exam
> ple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.exam
> ple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,od.exampl
> e.dts:24.30-31
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,od.exampl
> e.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,color.exa
> mple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,color.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.exa
> mple.dts:35.50-51
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,split.exa
> mple.dts:24.35-36
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,split.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,merge.exa
> mple.dts:27.35-36
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,merge.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.exa
> mple.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,mutex.exa
> mple.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.examp
> le.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.examp
> le.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-
> 2l.example.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-
> 2l.example.dt.yaml]
> Error 1
> Error:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.examp
> le.dts:27.27-28
> syntax error
> FATAL ERROR: Unable to parse input tree
> make[1]: *** [scripts/Makefile.lib:386:
> Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.examp
> le.dt.yaml]
> Error 1
> 
> Please fix 'make dt_binding_check'.
> 
> Rob
-- 

I'll fix it at the next version.

Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
  2022-03-03  0:00         ` Rob Herring
@ 2022-03-03  4:31           ` Jason-JH Lin
  -1 siblings, 0 replies; 65+ messages in thread
From: Jason-JH Lin @ 2022-03-03  4:31 UTC (permalink / raw)
  To: Rob Herring, Chun-Kuang Hu
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	moderated list:ARM/STM32 ARCHITECTURE, roy-cw.yeh, CK Hu, DTML,
	Jitao shi, Maxime Coquelin, Nancy Lin,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Philipp Zabel, Enric Balletbo i Serra

Hi Rob,

Thanks for the reviews.

On Wed, 2022-03-02 at 18:00 -0600, Rob Herring wrote:
> On Mon, Feb 7, 2022 at 5:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org
> > wrote:
> > 
> > OK, it seems no one has comment on this patch, so
> 
> No comment because the patch was not in PW. That's most likely due to
> this:
> 
> Subject: [PATCH v15 03/12] dt-bindings: display: mediatek: disp:
> split
> each block to individual yaml
> Date: Wed, 26 Jan 2022 15:19:23 +0800 [thread overview]
> Message-ID: <20220126071932.32615-4-jason-jh.lin@mediatek.com> (raw)
> In-Reply-To: <20220126071932.32615-1-jason-jh.lin@mediatek.com>
> 
> [-- Warning: decoded text below may be mangled, UTF-8 assumed --]
> [-- Attachment #1: Type: text/plain; charset="y", Size: 50916 bytes
> --]
> 
> "y" is not a valid charset. This is caused when git-send-email asks
> for the encoding and you answer 'y' rather than <enter>.
> 
> Rob
-- 

Thanks for making me realize the problem.
I'll always use <enter> in the future.

Regards,
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml
@ 2022-03-03  4:31           ` Jason-JH Lin
  0 siblings, 0 replies; 65+ messages in thread
From: Jason-JH Lin @ 2022-03-03  4:31 UTC (permalink / raw)
  To: Rob Herring, Chun-Kuang Hu
  Cc: David Airlie, singo.chang, Alexandre Torgue, Fabien Parent,
	moderated list:ARM/STM32 ARCHITECTURE, roy-cw.yeh, CK Hu, DTML,
	Jitao shi, Maxime Coquelin, Nancy Lin,
	moderated list:ARM/Mediatek SoC support, Hsin-Yi Wang,
	Matthias Brugger, Daniel Vetter, Linux ARM,
	AngeloGioacchino Del Regno, linux-kernel, Moudy Ho,
	Philipp Zabel, Enric Balletbo i Serra

Hi Rob,

Thanks for the reviews.

On Wed, 2022-03-02 at 18:00 -0600, Rob Herring wrote:
> On Mon, Feb 7, 2022 at 5:07 PM Chun-Kuang Hu <chunkuang.hu@kernel.org
> > wrote:
> > 
> > OK, it seems no one has comment on this patch, so
> 
> No comment because the patch was not in PW. That's most likely due to
> this:
> 
> Subject: [PATCH v15 03/12] dt-bindings: display: mediatek: disp:
> split
> each block to individual yaml
> Date: Wed, 26 Jan 2022 15:19:23 +0800 [thread overview]
> Message-ID: <20220126071932.32615-4-jason-jh.lin@mediatek.com> (raw)
> In-Reply-To: <20220126071932.32615-1-jason-jh.lin@mediatek.com>
> 
> [-- Warning: decoded text below may be mangled, UTF-8 assumed --]
> [-- Attachment #1: Type: text/plain; charset="y", Size: 50916 bytes
> --]
> 
> "y" is not a valid charset. This is caused when git-send-email asks
> for the encoding and you answer 'y' rather than <enter>.
> 
> Rob
-- 

Thanks for making me realize the problem.
I'll always use <enter> in the future.

Regards,
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
  2022-03-03  4:25     ` Jason-JH Lin
  (?)
@ 2022-03-03  9:31       ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-03  9:31 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring
  Cc: Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, Maxime Coquelin,
	David Airlie, Daniel Vetter, Alexandre Torgue, Hsin-Yi Wang,
	Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu, Fabien Parent, Jitao shi,
	nancy.lin, singo.chang, devicetree,
	moderated list:ARM/STM32 ARCHITECTURE, linux-arm-kernel,
	moderated list:ARM/Mediatek SoC support, linux-kernel

Il 03/03/22 05:25, Jason-JH Lin ha scritto:
> Hi Rob,
> 
> Thanks for the reviews.
> 
> On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
>> On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
>> jason-jh.lin@mediatek.com> wrote:
>>>
> 
> [snip]
> 

Hello Rob, Jason-JH,

I have just crafted a patch that fixes everything mentioned here,
if it's easier like this, I can either send it for the maintainer(s)
to apply on top, or squash in Jason-JH's original patch.

If you'd like to get my patch, though, I have one question:
this is touching literally all of the YAML files that Jason-JH is
introducing, so, should I send this as one patch per file (which would be
something around 16 patches) or is just one fixing them all fine?

Cheers,
Angelo

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-03  9:31       ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-03  9:31 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring
  Cc: Chun-Kuang Hu, Jitao shi, Maxime Coquelin, David Airlie,
	linux-kernel, singo.chang, Fabien Parent, Alexandre Torgue,
	roy-cw.yeh, CK Hu, devicetree, Moudy Ho,
	moderated list:ARM/Mediatek SoC support, Daniel Vetter,
	Hsin-Yi Wang, Matthias Brugger, Philipp Zabel, nancy.lin,
	moderated list:ARM/STM32 ARCHITECTURE, linux-arm-kernel

Il 03/03/22 05:25, Jason-JH Lin ha scritto:
> Hi Rob,
> 
> Thanks for the reviews.
> 
> On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
>> On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
>> jason-jh.lin@mediatek.com> wrote:
>>>
> 
> [snip]
> 

Hello Rob, Jason-JH,

I have just crafted a patch that fixes everything mentioned here,
if it's easier like this, I can either send it for the maintainer(s)
to apply on top, or squash in Jason-JH's original patch.

If you'd like to get my patch, though, I have one question:
this is touching literally all of the YAML files that Jason-JH is
introducing, so, should I send this as one patch per file (which would be
something around 16 patches) or is just one fixing them all fine?

Cheers,
Angelo

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-03  9:31       ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-03  9:31 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring
  Cc: Matthias Brugger, Chun-Kuang Hu, Philipp Zabel, Maxime Coquelin,
	David Airlie, Daniel Vetter, Alexandre Torgue, Hsin-Yi Wang,
	Fei Shao, Moudy Ho, roy-cw.yeh, CK Hu, Fabien Parent, Jitao shi,
	nancy.lin, singo.chang, devicetree,
	moderated list:ARM/STM32 ARCHITECTURE, linux-arm-kernel,
	moderated list:ARM/Mediatek SoC support, linux-kernel

Il 03/03/22 05:25, Jason-JH Lin ha scritto:
> Hi Rob,
> 
> Thanks for the reviews.
> 
> On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
>> On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
>> jason-jh.lin@mediatek.com> wrote:
>>>
> 
> [snip]
> 

Hello Rob, Jason-JH,

I have just crafted a patch that fixes everything mentioned here,
if it's easier like this, I can either send it for the maintainer(s)
to apply on top, or squash in Jason-JH's original patch.

If you'd like to get my patch, though, I have one question:
this is touching literally all of the YAML files that Jason-JH is
introducing, so, should I send this as one patch per file (which would be
something around 16 patches) or is just one fixing them all fine?

Cheers,
Angelo

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
  2022-03-03  9:31       ` AngeloGioacchino Del Regno
@ 2022-03-04  5:26         ` Jason-JH Lin
  -1 siblings, 0 replies; 65+ messages in thread
From: Jason-JH Lin @ 2022-03-04  5:26 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Rob Herring
  Cc: Chun-Kuang Hu, Maxime Coquelin, David Airlie, linux-kernel,
	singo.chang, Fabien Parent, Alexandre Torgue, roy-cw.yeh, CK Hu,
	devicetree, Moudy Ho, moderated list:ARM/Mediatek SoC support,
	Daniel Vetter, Hsin-Yi Wang, Matthias Brugger, Philipp Zabel,
	nancy.lin, moderated list:ARM/STM32 ARCHITECTURE,
	linux-arm-kernel

Hi Angelo,

Because linux-next has applied these patches:

[v15,04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195
SoC binding
[v15,05/12] dt-bindings: display: mediatek: merge: add additional prop
for mt8195
[v15,06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for
vdosys0
[v15,03/12] dt-bindings: display: mediatek: disp: split each block to
individual yaml


I'll rebase on the latest linux-next, and then send 1 path + 1 series:
[1] a fix up patch for all dt-schema error in each display dt-bindings
(If Rob wants me to split this patch into separate patches for each
file, then I'll resend it.)
[2] a series of remaining patches of this series


I would appreciate it if you would take the time to send [1] for me.
If you can help me to send [1], please let me know.
Thank you very much ;-) 


Regards,
Jason-JH.Lin

On Thu, 2022-03-03 at 10:31 +0100, AngeloGioacchino Del Regno wrote:
> Il 03/03/22 05:25, Jason-JH Lin ha scritto:
> > Hi Rob,
> > 
> > Thanks for the reviews.
> > 
> > On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
> > > On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
> > > jason-jh.lin@mediatek.com> wrote:
> > > > 
> > 
> > [snip]
> > 
> 
> Hello Rob, Jason-JH,
> 
> I have just crafted a patch that fixes everything mentioned here,
> if it's easier like this, I can either send it for the maintainer(s)
> to apply on top, or squash in Jason-JH's original patch.
> 
> If you'd like to get my patch, though, I have one question:
> this is touching literally all of the YAML files that Jason-JH is
> introducing, so, should I send this as one patch per file (which
> would be
> something around 16 patches) or is just one fixing them all fine?
> 
> Cheers,
> Angelo
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> 
https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!3tXE3T-t6I2GMILAOHpkTXhrLHwFAQtmhGqTBtKSY2SLWM2qBBMULlM17TtG6VwNR5yn$
>  
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-04  5:26         ` Jason-JH Lin
  0 siblings, 0 replies; 65+ messages in thread
From: Jason-JH Lin @ 2022-03-04  5:26 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Rob Herring
  Cc: Chun-Kuang Hu, Maxime Coquelin, David Airlie, linux-kernel,
	singo.chang, Fabien Parent, Alexandre Torgue, roy-cw.yeh, CK Hu,
	devicetree, Moudy Ho, moderated list:ARM/Mediatek SoC support,
	Daniel Vetter, Hsin-Yi Wang, Matthias Brugger, Philipp Zabel,
	nancy.lin, moderated list:ARM/STM32 ARCHITECTURE,
	linux-arm-kernel

Hi Angelo,

Because linux-next has applied these patches:

[v15,04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195
SoC binding
[v15,05/12] dt-bindings: display: mediatek: merge: add additional prop
for mt8195
[v15,06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for
vdosys0
[v15,03/12] dt-bindings: display: mediatek: disp: split each block to
individual yaml


I'll rebase on the latest linux-next, and then send 1 path + 1 series:
[1] a fix up patch for all dt-schema error in each display dt-bindings
(If Rob wants me to split this patch into separate patches for each
file, then I'll resend it.)
[2] a series of remaining patches of this series


I would appreciate it if you would take the time to send [1] for me.
If you can help me to send [1], please let me know.
Thank you very much ;-) 


Regards,
Jason-JH.Lin

On Thu, 2022-03-03 at 10:31 +0100, AngeloGioacchino Del Regno wrote:
> Il 03/03/22 05:25, Jason-JH Lin ha scritto:
> > Hi Rob,
> > 
> > Thanks for the reviews.
> > 
> > On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
> > > On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
> > > jason-jh.lin@mediatek.com> wrote:
> > > > 
> > 
> > [snip]
> > 
> 
> Hello Rob, Jason-JH,
> 
> I have just crafted a patch that fixes everything mentioned here,
> if it's easier like this, I can either send it for the maintainer(s)
> to apply on top, or squash in Jason-JH's original patch.
> 
> If you'd like to get my patch, though, I have one question:
> this is touching literally all of the YAML files that Jason-JH is
> introducing, so, should I send this as one patch per file (which
> would be
> something around 16 patches) or is just one fixing them all fine?
> 
> Cheers,
> Angelo
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> 
https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!3tXE3T-t6I2GMILAOHpkTXhrLHwFAQtmhGqTBtKSY2SLWM2qBBMULlM17TtG6VwNR5yn$
>  
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
  2022-03-04  5:26         ` Jason-JH Lin
  (?)
@ 2022-03-04  9:09           ` AngeloGioacchino Del Regno
  -1 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-04  9:09 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring
  Cc: Chun-Kuang Hu, Maxime Coquelin, David Airlie, linux-kernel,
	singo.chang, Fabien Parent, Alexandre Torgue, roy-cw.yeh, CK Hu,
	devicetree, Moudy Ho, moderated list:ARM/Mediatek SoC support,
	Daniel Vetter, Hsin-Yi Wang, Matthias Brugger, Philipp Zabel,
	nancy.lin, moderated list:ARM/STM32 ARCHITECTURE,
	linux-arm-kernel

Il 04/03/22 06:26, Jason-JH Lin ha scritto:
> Hi Angelo,
> 
> Because linux-next has applied these patches:
> 
> [v15,04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195
> SoC binding
> [v15,05/12] dt-bindings: display: mediatek: merge: add additional prop
> for mt8195
> [v15,06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for
> vdosys0
> [v15,03/12] dt-bindings: display: mediatek: disp: split each block to
> individual yaml
> 
> 
> I'll rebase on the latest linux-next, and then send 1 path + 1 series:
> [1] a fix up patch for all dt-schema error in each display dt-bindings
> (If Rob wants me to split this patch into separate patches for each
> file, then I'll resend it.)
> [2] a series of remaining patches of this series
> 
> 
> I would appreciate it if you would take the time to send [1] for me.
> If you can help me to send [1], please let me know.
> Thank you very much ;-)
> 
> 

I will send fixes for [1] later today.

Cheers,
Angelo

> Regards,
> Jason-JH.Lin
> 
> On Thu, 2022-03-03 at 10:31 +0100, AngeloGioacchino Del Regno wrote:
>> Il 03/03/22 05:25, Jason-JH Lin ha scritto:
>>> Hi Rob,
>>>
>>> Thanks for the reviews.
>>>
>>> On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
>>>> On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
>>>> jason-jh.lin@mediatek.com> wrote:
>>>>>
>>>
>>> [snip]
>>>
>>
>> Hello Rob, Jason-JH,
>>
>> I have just crafted a patch that fixes everything mentioned here,
>> if it's easier like this, I can either send it for the maintainer(s)
>> to apply on top, or squash in Jason-JH's original patch.
>>
>> If you'd like to get my patch, though, I have one question:
>> this is touching literally all of the YAML files that Jason-JH is
>> introducing, so, should I send this as one patch per file (which
>> would be
>> something around 16 patches) or is just one fixing them all fine?
>>
>> Cheers,
>> Angelo
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>>
> https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!3tXE3T-t6I2GMILAOHpkTXhrLHwFAQtmhGqTBtKSY2SLWM2qBBMULlM17TtG6VwNR5yn$
>>   




^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-04  9:09           ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-04  9:09 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring
  Cc: Chun-Kuang Hu, Maxime Coquelin, David Airlie, linux-kernel,
	singo.chang, Fabien Parent, Alexandre Torgue, roy-cw.yeh, CK Hu,
	devicetree, Moudy Ho, moderated list:ARM/Mediatek SoC support,
	Daniel Vetter, Hsin-Yi Wang, Matthias Brugger, Philipp Zabel,
	nancy.lin, moderated list:ARM/STM32 ARCHITECTURE,
	linux-arm-kernel

Il 04/03/22 06:26, Jason-JH Lin ha scritto:
> Hi Angelo,
> 
> Because linux-next has applied these patches:
> 
> [v15,04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195
> SoC binding
> [v15,05/12] dt-bindings: display: mediatek: merge: add additional prop
> for mt8195
> [v15,06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for
> vdosys0
> [v15,03/12] dt-bindings: display: mediatek: disp: split each block to
> individual yaml
> 
> 
> I'll rebase on the latest linux-next, and then send 1 path + 1 series:
> [1] a fix up patch for all dt-schema error in each display dt-bindings
> (If Rob wants me to split this patch into separate patches for each
> file, then I'll resend it.)
> [2] a series of remaining patches of this series
> 
> 
> I would appreciate it if you would take the time to send [1] for me.
> If you can help me to send [1], please let me know.
> Thank you very much ;-)
> 
> 

I will send fixes for [1] later today.

Cheers,
Angelo

> Regards,
> Jason-JH.Lin
> 
> On Thu, 2022-03-03 at 10:31 +0100, AngeloGioacchino Del Regno wrote:
>> Il 03/03/22 05:25, Jason-JH Lin ha scritto:
>>> Hi Rob,
>>>
>>> Thanks for the reviews.
>>>
>>> On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
>>>> On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
>>>> jason-jh.lin@mediatek.com> wrote:
>>>>>
>>>
>>> [snip]
>>>
>>
>> Hello Rob, Jason-JH,
>>
>> I have just crafted a patch that fixes everything mentioned here,
>> if it's easier like this, I can either send it for the maintainer(s)
>> to apply on top, or squash in Jason-JH's original patch.
>>
>> If you'd like to get my patch, though, I have one question:
>> this is touching literally all of the YAML files that Jason-JH is
>> introducing, so, should I send this as one patch per file (which
>> would be
>> something around 16 patches) or is just one fixing them all fine?
>>
>> Cheers,
>> Angelo
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>>
> https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!3tXE3T-t6I2GMILAOHpkTXhrLHwFAQtmhGqTBtKSY2SLWM2qBBMULlM17TtG6VwNR5yn$
>>   




_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 65+ messages in thread
* Re: [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-03-04  9:09           ` AngeloGioacchino Del Regno
  0 siblings, 0 replies; 65+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-04  9:09 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring
  Cc: Chun-Kuang Hu, Maxime Coquelin, David Airlie, linux-kernel,
	singo.chang, Fabien Parent, Alexandre Torgue, roy-cw.yeh, CK Hu,
	devicetree, Moudy Ho, moderated list:ARM/Mediatek SoC support,
	Daniel Vetter, Hsin-Yi Wang, Matthias Brugger, Philipp Zabel,
	nancy.lin, moderated list:ARM/STM32 ARCHITECTURE,
	linux-arm-kernel

Il 04/03/22 06:26, Jason-JH Lin ha scritto:
> Hi Angelo,
> 
> Because linux-next has applied these patches:
> 
> [v15,04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195
> SoC binding
> [v15,05/12] dt-bindings: display: mediatek: merge: add additional prop
> for mt8195
> [v15,06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for
> vdosys0
> [v15,03/12] dt-bindings: display: mediatek: disp: split each block to
> individual yaml
> 
> 
> I'll rebase on the latest linux-next, and then send 1 path + 1 series:
> [1] a fix up patch for all dt-schema error in each display dt-bindings
> (If Rob wants me to split this patch into separate patches for each
> file, then I'll resend it.)
> [2] a series of remaining patches of this series
> 
> 
> I would appreciate it if you would take the time to send [1] for me.
> If you can help me to send [1], please let me know.
> Thank you very much ;-)
> 
> 

I will send fixes for [1] later today.

Cheers,
Angelo

> Regards,
> Jason-JH.Lin
> 
> On Thu, 2022-03-03 at 10:31 +0100, AngeloGioacchino Del Regno wrote:
>> Il 03/03/22 05:25, Jason-JH Lin ha scritto:
>>> Hi Rob,
>>>
>>> Thanks for the reviews.
>>>
>>> On Wed, 2022-03-02 at 17:50 -0600, Rob Herring wrote:
>>>> On Wed, Jan 26, 2022 at 1:19 AM jason-jh.lin <
>>>> jason-jh.lin@mediatek.com> wrote:
>>>>>
>>>
>>> [snip]
>>>
>>
>> Hello Rob, Jason-JH,
>>
>> I have just crafted a patch that fixes everything mentioned here,
>> if it's easier like this, I can either send it for the maintainer(s)
>> to apply on top, or squash in Jason-JH's original patch.
>>
>> If you'd like to get my patch, though, I have one question:
>> this is touching literally all of the YAML files that Jason-JH is
>> introducing, so, should I send this as one patch per file (which
>> would be
>> something around 16 patches) or is just one fixing them all fine?
>>
>> Cheers,
>> Angelo
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>>
> https://urldefense.com/v3/__http://lists.infradead.org/mailman/listinfo/linux-mediatek__;!!CTRNKA9wMg0ARbw!3tXE3T-t6I2GMILAOHpkTXhrLHwFAQtmhGqTBtKSY2SLWM2qBBMULlM17TtG6VwNR5yn$
>>   




_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 65+ messages in thread
end of thread, other threads:[~2022-03-04  9:37 UTC | newest]

Thread overview: 65+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-26  7:19 [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2022-01-26  7:19 ` jason-jh.lin
2022-01-26  7:19 ` [PATCH v15 01/12] dt-bindings: arm: mediatek: mmsys: add power and gce properties jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-01-26  7:19 ` [PATCH v15 02/12] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-01-26  7:19 ` [PATCH v15 03/12] dt-bindings: display: mediatek: disp: split each block to individual yaml jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-01-27 15:46   ` Chun-Kuang Hu
2022-01-27 15:46     ` Chun-Kuang Hu
2022-02-07 23:07     ` Chun-Kuang Hu
2022-02-07 23:07       ` Chun-Kuang Hu
2022-03-03  0:00       ` Rob Herring
2022-03-03  0:00         ` Rob Herring
2022-03-03  0:00         ` Rob Herring
2022-03-03  4:31         ` Jason-JH Lin
2022-03-03  4:31           ` Jason-JH Lin
2022-01-26  7:19 ` [PATCH v15 04/12] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-02-07 23:09   ` Chun-Kuang Hu
2022-02-07 23:09     ` Chun-Kuang Hu
2022-02-07 23:09     ` Chun-Kuang Hu
2022-01-26  7:19 ` [PATCH v15 05/12] dt-bindings: display: mediatek: merge: add additional prop for mt8195 jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-02-07 23:09   ` Chun-Kuang Hu
2022-02-07 23:09     ` Chun-Kuang Hu
2022-02-07 23:09     ` Chun-Kuang Hu
2022-01-26  7:19 ` [PATCH v15 06/12] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0 jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-02-07 23:10   ` Chun-Kuang Hu
2022-02-07 23:10     ` Chun-Kuang Hu
2022-02-07 23:10     ` Chun-Kuang Hu
2022-01-26  7:19 ` [PATCH v15 07/12] dt-bindings: arm: mediatek: move out common module from display folder jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-01-26  7:19 ` [PATCH v15 08/12] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-01-26  7:19 ` [PATCH v15 09/12] soc: mediatek: add mtk-mutex " jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-01-26  7:19 ` [PATCH v15 10/12] drm/mediatek: add DSC support for mediatek-drm jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-01-27 10:27   ` AngeloGioacchino Del Regno
2022-01-27 10:27     ` AngeloGioacchino Del Regno
2022-01-27 10:27     ` AngeloGioacchino Del Regno
2022-01-26  7:19 ` [PATCH v15 11/12] drm/mediatek: add MERGE " jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-01-26  7:19 ` [PATCH v15 12/12] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
2022-01-26  7:19   ` jason-jh.lin
2022-02-14 10:13 ` [PATCH v15 00/12] Add Mediatek Soc DRM (vdosys0) " Jason-JH Lin
2022-02-14 10:13   ` Jason-JH Lin
2022-03-02 13:26   ` AngeloGioacchino Del Regno
2022-03-02 13:26     ` AngeloGioacchino Del Regno
2022-03-02 13:26     ` AngeloGioacchino Del Regno
2022-03-02 23:50 ` Rob Herring
2022-03-02 23:50   ` Rob Herring
2022-03-02 23:50   ` Rob Herring
2022-03-03  4:25   ` Jason-JH Lin
2022-03-03  4:25     ` Jason-JH Lin
2022-03-03  9:31     ` AngeloGioacchino Del Regno
2022-03-03  9:31       ` AngeloGioacchino Del Regno
2022-03-03  9:31       ` AngeloGioacchino Del Regno
2022-03-04  5:26       ` Jason-JH Lin
2022-03-04  5:26         ` Jason-JH Lin
2022-03-04  9:09         ` AngeloGioacchino Del Regno
2022-03-04  9:09           ` AngeloGioacchino Del Regno
2022-03-04  9:09           ` AngeloGioacchino Del Regno

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