[RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

[RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

[Alex Bennée]

QEMU doesn't model micro-architectural details which includes most
chip errata. The ARM_ERRATA_798181 work around in the Linux
kernel (see erratum_a15_798181_init) currently detects QEMU's
cortex-a15 as broken and triggers additional expensive TLB flushes as
a result.

Change the MIDR to report what the latest silicon would (r4p0) as well
as setting the IMPDEF revidr bit to indicate these flushes are not
needed. This cuts about 5s from my Debian kernel boot with the latest
6.0rc1 kernel (29s->24s).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Arnd Bergmann <arnd@linaro.org>
Cc: Anders Roxell <anders.roxell@linaro.org>
---
 target/arm/cpu_tcg.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 3099b38e32..59d5278868 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -588,7 +588,9 @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_EL3);
     set_feature(&cpu->env, ARM_FEATURE_PMU);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
-    cpu->midr = 0x412fc0f1;
+    /* r4p0 cpu, not requiring expensive tlb flush errata */
+    cpu->midr = 0x414fc0f0;
+    cpu->revidr = 0x200;
     cpu->reset_fpsid = 0x410430f0;
     cpu->isar.mvfr0 = 0x10110222;
     cpu->isar.mvfr1 = 0x11111111;
-- 
2.34.1

Re: [RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

[Philippe Mathieu-Daudé via]

On Tue, Sep 6, 2022 at 7:23 PM Alex Bennée <alex.bennee@linaro.org> wrote:
>
> QEMU doesn't model micro-architectural details which includes most
> chip errata. The ARM_ERRATA_798181 work around in the Linux
> kernel (see erratum_a15_798181_init) currently detects QEMU's
> cortex-a15 as broken and triggers additional expensive TLB flushes as
> a result.
>
> Change the MIDR to report what the latest silicon would (r4p0) as well
> as setting the IMPDEF revidr bit to indicate these flushes are not
> needed. This cuts about 5s from my Debian kernel boot with the latest
> 6.0rc1 kernel (29s->24s).
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Cc: Arnd Bergmann <arnd@linaro.org>
> Cc: Anders Roxell <anders.roxell@linaro.org>
> ---
>  target/arm/cpu_tcg.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Re: [RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

[Anders Roxell]

On Tue, 6 Sept 2022 at 19:23, Alex Bennée <alex.bennee@linaro.org> wrote:
>
> QEMU doesn't model micro-architectural details which includes most
> chip errata. The ARM_ERRATA_798181 work around in the Linux
> kernel (see erratum_a15_798181_init) currently detects QEMU's
> cortex-a15 as broken and triggers additional expensive TLB flushes as
> a result.
>
> Change the MIDR to report what the latest silicon would (r4p0) as well
> as setting the IMPDEF revidr bit to indicate these flushes are not
> needed. This cuts about 5s from my Debian kernel boot with the latest
> 6.0rc1 kernel (29s->24s).
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> Cc: Arnd Bergmann <arnd@linaro.org>
> Cc: Anders Roxell <anders.roxell@linaro.org>

Tested-by: Anders Roxell <anders.roxell@linaro.org>

> ---
>  target/arm/cpu_tcg.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index 3099b38e32..59d5278868 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -588,7 +588,9 @@ static void cortex_a15_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_EL3);
>      set_feature(&cpu->env, ARM_FEATURE_PMU);
>      cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
> -    cpu->midr = 0x412fc0f1;
> +    /* r4p0 cpu, not requiring expensive tlb flush errata */
> +    cpu->midr = 0x414fc0f0;
> +    cpu->revidr = 0x200;
>      cpu->reset_fpsid = 0x410430f0;
>      cpu->isar.mvfr0 = 0x10110222;
>      cpu->isar.mvfr1 = 0x11111111;
> --
> 2.34.1
>

Re: [RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev

[Arnd Bergmann]

On Tue, Sep 6, 2022, at 7:22 PM, Alex Bennée wrote:
>
> index 3099b38e32..59d5278868 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -588,7 +588,9 @@ static void cortex_a15_initfn(Object *obj)
>      set_feature(&cpu->env, ARM_FEATURE_EL3);
>      set_feature(&cpu->env, ARM_FEATURE_PMU);
>      cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
> -    cpu->midr = 0x412fc0f1;
> +    /* r4p0 cpu, not requiring expensive tlb flush errata */
> +    cpu->midr = 0x414fc0f0;
> +    cpu->revidr = 0x200;
>      cpu->reset_fpsid = 0x410430f0;
>      cpu->isar.mvfr0 = 0x10110222;
>      cpu->isar.mvfr1 = 0x11111111;

This will work correctly with Linux, but after I checked the
Cortex-A15 MPCore r2/r3/r4 Software Developers Errata Notice again,
I think that setting revidr here is not fully correct:

With an r3p3 CPU, bit 9 of revidr (0x200) indicates that no
workaround is necessary, but with r4p0 and higher, this bit
is marked as reserved and both the Documentation and the
Linux source code assume the hardware works correctly.

So I think this should either be 0x413fc0f3/0x200
or 0x414fc0f0/0.

     Arnd