* [PATCH v7 0/6] rockchip_sfc: add support for Rockchip SFC
@ 2021-08-05 8:26 Jon Lin
2021-08-05 8:26 ` [PATCH v7 1/6] spi: " Jon Lin
` (4 more replies)
0 siblings, 5 replies; 23+ messages in thread
From: Jon Lin @ 2021-08-05 8:26 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan, Jon Lin
Changes in v7:
- Make sfc-use-dma configurable
- Remove SPI_NOR_HAS_TB and SPI_NOR_HAS_LOCK
- Make px30 SFC clock configurable
Changes in v6:
- Fix dma transfer logic
- Fix the error of the way to wait for dma transfer finished status
Changes in v5:
- Support dma transfer
- Add CONFIG_IS_ENABLED(CLK) limitation
- Support spinand devices
- Support SFC ver4 ver5
- Using "rockchip, sfc" as compatible id
- Get clock from the index to compatible with those case which's
clock-names is not parsed
- px30 use "rockchip, sfc" as compatible id
Changes in v4:
- None
Changes in v3:
- Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
driver to fix potential issue on hardware. Note I never noticed
this issue while testing, so I cannot test if it fixed any specific
issue for me.
- Updated of-compatible string back to "rockchip,sfc" to match what
is currently proposed for upstream driver. The hardware itself
has multiple versions but a register is present in the hardware that
is read by the driver to set version specific functionality.
- Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that
sfc nodes match what is in upstream.
Changes in v2:
- Resending due to glitch with patch file truncating final two lines
on patch 1/5 and incorrect patch version number on patch 5/5.
Changes in v1:
- Reworked code to utilize spi-mem framework, and based it closely
off of work in progress code for mainline Linux.
- Removed DMA, as it didn't offer much performance benefit for
booting (in my test cases), added complexity to the code, and
interfered with A-TF.
- Updated the names of the bindings to match the work in progress
Linux code.
- Moved alias to u-boot specific device-tree for Odroid Go Advance.
Alias is updated with the spi0 node pointing to the SFC to
help the sf command as well as facilitate booting from the SFC.
- Note 2 below no longer applies, as rebasing this off of upstream
code should allow the device to work for NAND, and by utilizing
the spi-mem framework it no longer has to extract the parameters
Chris Morgan (5):
spi: rockchip_sfc: add support for Rockchip SFC
rockchip: px30: Add support for using SFC
rockchip: px30: add the serial flash controller
mtd: spi-nor-ids: Add XTX XT25F128B
rockchip: px30: add support for SFC for Odroid Go Advance
Jon Lin (1):
rockchip: px30: Support configure SFC
arch/arm/dts/px30.dtsi | 38 ++
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 +
arch/arm/dts/rk3326-odroid-go2.dts | 16 +
arch/arm/mach-rockchip/px30/px30.c | 64 ++
drivers/clk/rockchip/clk_px30.c | 32 +
drivers/mtd/spi/Kconfig | 6 +
drivers/mtd/spi/spi-nor-ids.c | 4 +
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/rockchip_sfc.c | 646 +++++++++++++++++++++
10 files changed, 832 insertions(+)
create mode 100644 drivers/spi/rockchip_sfc.c
--
2.17.1
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v7 1/6] spi: rockchip_sfc: add support for Rockchip SFC
2021-08-05 8:26 [PATCH v7 0/6] rockchip_sfc: add support for Rockchip SFC Jon Lin
@ 2021-08-05 8:26 ` Jon Lin
2021-08-05 11:26 ` Jagan Teki
` (2 more replies)
2021-08-05 8:26 ` [PATCH v7 2/6] rockchip: px30: Add support for using SFC Jon Lin
` (3 subsequent siblings)
4 siblings, 3 replies; 23+ messages in thread
From: Jon Lin @ 2021-08-05 8:26 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan, Jon Lin
From: Chris Morgan <macromorgan@hotmail.com>
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main difference between this and earlier versions
of the driver is that this one does not support DMA. In testing
the performance difference (performing a dual mode read on a 128Mb
chip) is negligible. DMA, if used, must also be disabled in SPL
mode when using A-TF anyway.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v7:
- Make sfc-use-dma configurable
Changes in v6:
- Fix dma transfer logic
- Fix the error of the way to wait for dma transfer finished status
Changes in v5:
- Support dma transfer
- Add CONFIG_IS_ENABLED(CLK) limitation
- Support spinand devices
- Support SFC ver4 ver5
- Using "rockchip, sfc" as compatible id
- Get clock from the index to compatible with those case which's
clock-names is not parsed
Changes in v4:
- None
Changes in v3:
- Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
driver to fix potential issue on hardware. Note I never noticed
this issue while testing, so I cannot test if it fixed any specific
issue for me.
- Updated of-compatible string back to "rockchip,sfc" to match what
is currently proposed for upstream driver. The hardware itself
has multiple versions but a register is present in the hardware that
is read by the driver to set version specific functionality.
- Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that
sfc nodes match what is in upstream.
Changes in v2:
- Resending due to glitch with patch file truncating final two lines
on patch 1/5 and incorrect patch version number on patch 5/5.
Changes in v1:
- Reworked code to utilize spi-mem framework, and based it closely
off of work in progress code for mainline Linux.
- Removed DMA, as it didn't offer much performance benefit for
booting (in my test cases), added complexity to the code, and
interfered with A-TF.
- Updated the names of the bindings to match the work in progress
Linux code.
- Moved alias to u-boot specific device-tree for Odroid Go Advance.
Alias is updated with the spi0 node pointing to the SFC to
help the sf command as well as facilitate booting from the SFC.
- Note 2 below no longer applies, as rebasing this off of upstream
code should allow the device to work for NAND, and by utilizing
the spi-mem framework it no longer has to extract the parameters
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/rockchip_sfc.c | 646 +++++++++++++++++++++++++++++++++++++
3 files changed, 655 insertions(+)
create mode 100644 drivers/spi/rockchip_sfc.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5c2a60a214..e12699bec7 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -319,6 +319,14 @@ config RENESAS_RPC_SPI
on Renesas RCar Gen3 SoCs. This uses driver model and requires a
device tree binding to operate.
+config ROCKCHIP_SFC
+ bool "Rockchip SFC Driver"
+ help
+ Enable the Rockchip SFC Driver for SPI NOR flash. This device is
+ a limited purpose SPI controller for driving NOR flash on certain
+ Rockchip SoCs. This uses driver model and requires a device tree
+ binding to operate.
+
config ROCKCHIP_SPI
bool "Rockchip SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 216e72c60f..d2f24bccef 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
obj-$(CONFIG_SPI_QUP) += spi-qup.o
obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
+obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o
obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
new file mode 100644
index 0000000000..4e2b861f22
--- /dev/null
+++ b/drivers/spi/rockchip_sfc.c
@@ -0,0 +1,646 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Rockchip Serial Flash Controller Driver
+ *
+ * Copyright (c) 2017-2021, Rockchip Inc.
+ * Author: Shawn Lin <shawn.lin@rock-chips.com>
+ * Chris Morgan <macromorgan@hotmail.com>
+ * Jon Lin <Jon.lin@rock-chips.com>
+ */
+
+#include <asm/io.h>
+#include <bouncebuf.h>
+#include <clk.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <spi.h>
+#include <spi-mem.h>
+
+/* System control */
+#define SFC_CTRL 0x0
+#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
+#define SFC_CTRL_CMD_BITS_SHIFT 8
+#define SFC_CTRL_ADDR_BITS_SHIFT 10
+#define SFC_CTRL_DATA_BITS_SHIFT 12
+
+/* Interrupt mask */
+#define SFC_IMR 0x4
+#define SFC_IMR_RX_FULL BIT(0)
+#define SFC_IMR_RX_UFLOW BIT(1)
+#define SFC_IMR_TX_OFLOW BIT(2)
+#define SFC_IMR_TX_EMPTY BIT(3)
+#define SFC_IMR_TRAN_FINISH BIT(4)
+#define SFC_IMR_BUS_ERR BIT(5)
+#define SFC_IMR_NSPI_ERR BIT(6)
+#define SFC_IMR_DMA BIT(7)
+
+/* Interrupt clear */
+#define SFC_ICLR 0x8
+#define SFC_ICLR_RX_FULL BIT(0)
+#define SFC_ICLR_RX_UFLOW BIT(1)
+#define SFC_ICLR_TX_OFLOW BIT(2)
+#define SFC_ICLR_TX_EMPTY BIT(3)
+#define SFC_ICLR_TRAN_FINISH BIT(4)
+#define SFC_ICLR_BUS_ERR BIT(5)
+#define SFC_ICLR_NSPI_ERR BIT(6)
+#define SFC_ICLR_DMA BIT(7)
+
+/* FIFO threshold level */
+#define SFC_FTLR 0xc
+#define SFC_FTLR_TX_SHIFT 0
+#define SFC_FTLR_TX_MASK 0x1f
+#define SFC_FTLR_RX_SHIFT 8
+#define SFC_FTLR_RX_MASK 0x1f
+
+/* Reset FSM and FIFO */
+#define SFC_RCVR 0x10
+#define SFC_RCVR_RESET BIT(0)
+
+/* Enhanced mode */
+#define SFC_AX 0x14
+
+/* Address Bit number */
+#define SFC_ABIT 0x18
+
+/* Interrupt status */
+#define SFC_ISR 0x1c
+#define SFC_ISR_RX_FULL_SHIFT BIT(0)
+#define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
+#define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
+#define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
+#define SFC_ISR_TX_FINISH_SHIFT BIT(4)
+#define SFC_ISR_BUS_ERR_SHIFT BIT(5)
+#define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
+#define SFC_ISR_DMA_SHIFT BIT(7)
+
+/* FIFO status */
+#define SFC_FSR 0x20
+#define SFC_FSR_TX_IS_FULL BIT(0)
+#define SFC_FSR_TX_IS_EMPTY BIT(1)
+#define SFC_FSR_RX_IS_EMPTY BIT(2)
+#define SFC_FSR_RX_IS_FULL BIT(3)
+#define SFC_FSR_TXLV_MASK GENMASK(12, 8)
+#define SFC_FSR_TXLV_SHIFT 8
+#define SFC_FSR_RXLV_MASK GENMASK(20, 16)
+#define SFC_FSR_RXLV_SHIFT 16
+
+/* FSM status */
+#define SFC_SR 0x24
+#define SFC_SR_IS_IDLE 0x0
+#define SFC_SR_IS_BUSY 0x1
+
+/* Raw interrupt status */
+#define SFC_RISR 0x28
+#define SFC_RISR_RX_FULL BIT(0)
+#define SFC_RISR_RX_UNDERFLOW BIT(1)
+#define SFC_RISR_TX_OVERFLOW BIT(2)
+#define SFC_RISR_TX_EMPTY BIT(3)
+#define SFC_RISR_TRAN_FINISH BIT(4)
+#define SFC_RISR_BUS_ERR BIT(5)
+#define SFC_RISR_NSPI_ERR BIT(6)
+#define SFC_RISR_DMA BIT(7)
+
+/* Version */
+#define SFC_VER 0x2C
+#define SFC_VER_3 0x3
+#define SFC_VER_4 0x4
+#define SFC_VER_5 0x5
+
+/* Delay line controller resiter */
+#define SFC_DLL_CTRL0 0x3C
+#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
+#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU
+#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU
+
+/* Master trigger */
+#define SFC_DMA_TRIGGER 0x80
+
+/* Src or Dst addr for master */
+#define SFC_DMA_ADDR 0x84
+
+/* Length control register extension 32GB */
+#define SFC_LEN_CTRL 0x88
+#define SFC_LEN_CTRL_TRB_SEL 1
+#define SFC_LEN_EXT 0x8C
+
+/* Command */
+#define SFC_CMD 0x100
+#define SFC_CMD_IDX_SHIFT 0
+#define SFC_CMD_DUMMY_SHIFT 8
+#define SFC_CMD_DIR_SHIFT 12
+#define SFC_CMD_DIR_RD 0
+#define SFC_CMD_DIR_WR 1
+#define SFC_CMD_ADDR_SHIFT 14
+#define SFC_CMD_ADDR_0BITS 0
+#define SFC_CMD_ADDR_24BITS 1
+#define SFC_CMD_ADDR_32BITS 2
+#define SFC_CMD_ADDR_XBITS 3
+#define SFC_CMD_TRAN_BYTES_SHIFT 16
+#define SFC_CMD_CS_SHIFT 30
+
+/* Address */
+#define SFC_ADDR 0x104
+
+/* Data */
+#define SFC_DATA 0x108
+
+/* The controller and documentation reports that it supports up to 4 CS
+ * devices (0-3), however I have only been able to test a single CS (CS 0)
+ * due to the configuration of my device.
+ */
+#define SFC_MAX_CHIPSELECT_NUM 4
+
+/* The SFC can transfer max 16KB - 1 at one time
+ * we set it to 15.5KB here for alignment.
+ */
+#define SFC_MAX_IOSIZE_VER3 (512 * 31)
+
+#define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
+
+/* DMA is only enabled for large data transmission */
+#define SFC_DMA_TRANS_THRETHOLD (0x40)
+
+/* Maximum clock values from datasheet suggest keeping clock value under
+ * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
+ * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
+ */
+#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
+#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
+#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
+
+struct rockchip_sfc {
+ void __iomem *regbase;
+ struct clk hclk;
+ struct clk clk;
+ u32 max_freq;
+ u32 speed;
+ bool use_dma;
+ u32 max_iosize;
+ u16 version;
+};
+
+static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
+{
+ int err;
+ u32 status;
+
+ writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
+
+ err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
+ !(status & SFC_RCVR_RESET),
+ 1000000);
+ if (err)
+ printf("SFC reset never finished\n");
+
+ /* Still need to clear the masked interrupt from RISR */
+ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
+
+ debug("reset\n");
+
+ return err;
+}
+
+static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
+{
+ return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
+}
+
+static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
+{
+ if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
+ return SFC_MAX_IOSIZE_VER4;
+
+ return SFC_MAX_IOSIZE_VER3;
+}
+
+static int rockchip_sfc_init(struct rockchip_sfc *sfc)
+{
+ writel(0, sfc->regbase + SFC_CTRL);
+ if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
+ writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
+
+ return 0;
+}
+
+static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
+{
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
+
+ sfc->regbase = dev_read_addr_ptr(bus);
+ if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
+ sfc->use_dma = false;
+ else
+ sfc->use_dma = true;
+
+#if CONFIG_IS_ENABLED(CLK)
+ int ret;
+
+ ret = clk_get_by_index(bus, 0, &sfc->clk);
+ if (ret < 0) {
+ printf("Could not get clock for %s: %d\n", bus->name, ret);
+ return ret;
+ }
+
+ ret = clk_get_by_index(bus, 1, &sfc->hclk);
+ if (ret < 0) {
+ printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
+
+static int rockchip_sfc_probe(struct udevice *bus)
+{
+ struct rockchip_sfc *sfc = dev_get_plat(bus);
+ int ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_enable(&sfc->hclk);
+ if (ret)
+ debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
+
+ ret = clk_enable(&sfc->clk);
+ if (ret)
+ debug("Enable clock fail for %s: %d\n", bus->name, ret);
+
+ ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ);
+ if (ret)
+ debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
+#endif
+
+ ret = rockchip_sfc_init(sfc);
+ if (ret)
+ goto err_init;
+
+ sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
+ sfc->version = rockchip_sfc_get_version(sfc);
+ sfc->speed = SFC_DEFAULT_SPEED_HZ;
+
+ return 0;
+
+err_init:
+#if CONFIG_IS_ENABLED(CLK)
+ clk_disable(&sfc->clk);
+ clk_disable(&sfc->hclk);
+#endif
+
+ return ret;
+}
+
+static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr)
+{
+ u32 fsr = readl(sfc->regbase + SFC_FSR);
+ int level;
+
+ if (wr)
+ level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
+ else
+ level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
+
+ return level;
+}
+
+static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout)
+{
+ unsigned long tbase = get_timer(0);
+ int level;
+
+ while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) {
+ if (get_timer(tbase) > timeout) {
+ debug("%s fifo timeout\n", wr ? "write" : "read");
+ return -ETIMEDOUT;
+ }
+ udelay(1);
+ }
+
+ return level;
+}
+
+static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
+{
+ if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
+ /*
+ * SFC not support output DUMMY cycles right after CMD cycles, so
+ * treat it as ADDR cycles.
+ */
+ op->addr.nbytes = op->dummy.nbytes;
+ op->addr.buswidth = op->dummy.buswidth;
+ op->addr.val = 0xFFFFFFFFF;
+
+ op->dummy.nbytes = 0;
+ }
+}
+
+static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout)
+{
+ unsigned long tbase;
+
+ /* Wait for the DMA interrupt status */
+ tbase = get_timer(0);
+ while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) {
+ if (get_timer(tbase) > timeout) {
+ printf("dma timeout\n");
+ rockchip_sfc_reset(sfc);
+
+ return -ETIMEDOUT;
+ }
+
+ udelay(1);
+ }
+
+ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
+
+ return 0;
+}
+
+static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
+ struct spi_slave *mem,
+ const struct spi_mem_op *op,
+ u32 len)
+{
+ struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
+ u32 ctrl = 0, cmd = 0;
+
+ /* set CMD */
+ cmd = op->cmd.opcode;
+ ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
+
+ /* set ADDR */
+ if (op->addr.nbytes) {
+ if (op->addr.nbytes == 4) {
+ cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
+ } else if (op->addr.nbytes == 3) {
+ cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
+ } else {
+ cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
+ writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
+ }
+
+ ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
+ }
+
+ /* set DUMMY */
+ if (op->dummy.nbytes) {
+ if (op->dummy.buswidth == 4)
+ cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
+ else if (op->dummy.buswidth == 2)
+ cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
+ else
+ cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
+ }
+
+ /* set DATA */
+ if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
+ writel(len, sfc->regbase + SFC_LEN_EXT);
+ else
+ cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
+ if (len) {
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
+
+ ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
+ }
+ if (!len && op->addr.nbytes)
+ cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
+
+ /* set the Controller */
+ ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
+ cmd |= plat->cs << SFC_CMD_CS_SHIFT;
+
+ debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
+ op->addr.nbytes, op->addr.buswidth,
+ op->dummy.nbytes, op->dummy.buswidth);
+ debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
+ ctrl, cmd, op->addr.val, len);
+
+ writel(ctrl, sfc->regbase + SFC_CTRL);
+ writel(cmd, sfc->regbase + SFC_CMD);
+ if (op->addr.nbytes)
+ writel(op->addr.val, sfc->regbase + SFC_ADDR);
+
+ return 0;
+}
+
+static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
+{
+ u8 bytes = len & 0x3;
+ u32 dwords;
+ int tx_level;
+ u32 write_words;
+ u32 tmp = 0;
+
+ dwords = len >> 2;
+ while (dwords) {
+ tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
+ if (tx_level < 0)
+ return tx_level;
+ write_words = min_t(u32, tx_level, dwords);
+ writesl(sfc->regbase + SFC_DATA, buf, write_words);
+ buf += write_words << 2;
+ dwords -= write_words;
+ }
+
+ /* write the rest non word aligned bytes */
+ if (bytes) {
+ tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
+ if (tx_level < 0)
+ return tx_level;
+ memcpy(&tmp, buf, bytes);
+ writel(tmp, sfc->regbase + SFC_DATA);
+ }
+
+ return len;
+}
+
+static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
+{
+ u8 bytes = len & 0x3;
+ u32 dwords;
+ u8 read_words;
+ int rx_level;
+ int tmp;
+
+ /* word aligned access only */
+ dwords = len >> 2;
+ while (dwords) {
+ rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
+ if (rx_level < 0)
+ return rx_level;
+ read_words = min_t(u32, rx_level, dwords);
+ readsl(sfc->regbase + SFC_DATA, buf, read_words);
+ buf += read_words << 2;
+ dwords -= read_words;
+ }
+
+ /* read the rest non word aligned bytes */
+ if (bytes) {
+ rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
+ if (rx_level < 0)
+ return rx_level;
+ tmp = readl(sfc->regbase + SFC_DATA);
+ memcpy(buf, &tmp, bytes);
+ }
+
+ return len;
+}
+
+static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
+{
+ writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
+ writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
+ writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
+
+ return len;
+}
+
+static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
+ const struct spi_mem_op *op, u32 len)
+{
+ debug("xfer_poll len=%x\n", len);
+
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
+ else
+ return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
+}
+
+static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
+ const struct spi_mem_op *op, u32 len)
+{
+ struct bounce_buffer bb;
+ unsigned int bb_flags;
+ void *dma_buf;
+ int ret;
+
+ debug("xfer_dma len=%x\n", len);
+
+ if (op->data.dir == SPI_MEM_DATA_OUT) {
+ dma_buf = (void *)op->data.buf.out;
+ bb_flags = GEN_BB_READ;
+ } else {
+ dma_buf = (void *)op->data.buf.in;
+ bb_flags = GEN_BB_WRITE;
+ }
+
+ ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags);
+ if (ret)
+ return ret;
+
+ ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len);
+ rockchip_sfc_wait_for_dma_finished(sfc, len * 10);
+ bounce_buffer_stop(&bb);
+
+ return ret;
+}
+
+static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
+{
+ unsigned long tbase = get_timer(0);
+ int ret = 0;
+ u32 timeout = timeout_us;
+
+ while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) {
+ if (get_timer(tbase) > timeout) {
+ printf("wait sfc idle timeout\n");
+ rockchip_sfc_reset(sfc);
+
+ return -ETIMEDOUT;
+ }
+
+ udelay(1);
+ }
+
+ return ret;
+}
+
+static int rockchip_sfc_exec_op(struct spi_slave *mem,
+ const struct spi_mem_op *op)
+{
+ struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
+ u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
+ int ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+ if (unlikely(mem->max_hz != sfc->speed)) {
+ ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
+ (uint)SFC_MAX_SPEED_HZ));
+ if (ret < 0) {
+ printf("set_freq=%dHz fail, check if it's the cru support level\n",
+ mem->max_hz);
+ return ret;
+ }
+
+ sfc->max_freq = mem->max_hz;
+ sfc->speed = mem->max_hz;
+ debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed);
+ }
+#endif
+
+ rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
+
+ rockchip_sfc_xfer_setup(sfc, mem, op, len);
+ if (len) {
+ if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD)
+ ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
+ else
+ ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
+
+ if (ret != len) {
+ printf("xfer data failed ret %d dir %d\n", ret, op->data.dir);
+
+ return -EIO;
+ }
+ }
+
+ return rockchip_sfc_xfer_done(sfc, 100000);
+}
+
+static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op)
+{
+ struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
+
+ op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
+ return 0;
+}
+
+static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
+{
+ /* We set up speed later for each transmission.
+ */
+ return 0;
+}
+
+static int rockchip_sfc_set_mode(struct udevice *bus, uint mode)
+{
+ return 0;
+}
+
+static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
+ .adjust_op_size = rockchip_sfc_adjust_op_size,
+ .exec_op = rockchip_sfc_exec_op,
+};
+
+static const struct dm_spi_ops rockchip_sfc_ops = {
+ .mem_ops = &rockchip_sfc_mem_ops,
+ .set_speed = rockchip_sfc_set_speed,
+ .set_mode = rockchip_sfc_set_mode,
+};
+
+static const struct udevice_id rockchip_sfc_ids[] = {
+ { .compatible = "rockchip,sfc"},
+ {},
+};
+
+U_BOOT_DRIVER(rockchip_sfc_driver) = {
+ .name = "rockchip_sfc",
+ .id = UCLASS_SPI,
+ .of_match = rockchip_sfc_ids,
+ .ops = &rockchip_sfc_ops,
+ .of_to_plat = rockchip_sfc_ofdata_to_platdata,
+ .plat_auto = sizeof(struct rockchip_sfc),
+ .probe = rockchip_sfc_probe,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v7 2/6] rockchip: px30: Add support for using SFC
2021-08-05 8:26 [PATCH v7 0/6] rockchip_sfc: add support for Rockchip SFC Jon Lin
2021-08-05 8:26 ` [PATCH v7 1/6] spi: " Jon Lin
@ 2021-08-05 8:26 ` Jon Lin
2021-08-11 10:19 ` Kever Yang
2021-08-05 8:26 ` [PATCH v7 3/6] rockchip: px30: add the serial flash controller Jon Lin
` (2 subsequent siblings)
4 siblings, 1 reply; 23+ messages in thread
From: Jon Lin @ 2021-08-05 8:26 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan, Jon Lin
From: Chris Morgan <macromorgan@hotmail.com>
This patch adds support for setting the correct pin configuration
for the Rockchip Serial Flash Controller found on the PX30.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
(no changes since v1)
arch/arm/mach-rockchip/px30/px30.c | 64 ++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
index 6fcef63c1b..be70d30cc8 100644
--- a/arch/arm/mach-rockchip/px30/px30.c
+++ b/arch/arm/mach-rockchip/px30/px30.c
@@ -51,6 +51,57 @@ struct mm_region *mem_map = px30_mem_map;
#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
+/* GRF_GPIO1AL_IOMUX */
+enum {
+ GPIO1A3_SHIFT = 12,
+ GPIO1A3_MASK = 0xf << GPIO1A3_SHIFT,
+ GPIO1A3_GPIO = 0,
+ GPIO1A3_FLASH_D3,
+ GPIO1A3_EMMC_D3,
+ GPIO1A3_SFC_SIO3,
+
+ GPIO1A2_SHIFT = 8,
+ GPIO1A2_MASK = 0xf << GPIO1A2_SHIFT,
+ GPIO1A2_GPIO = 0,
+ GPIO1A2_FLASH_D2,
+ GPIO1A2_EMMC_D2,
+ GPIO1A2_SFC_SIO2,
+
+ GPIO1A1_SHIFT = 4,
+ GPIO1A1_MASK = 0xf << GPIO1A1_SHIFT,
+ GPIO1A1_GPIO = 0,
+ GPIO1A1_FLASH_D1,
+ GPIO1A1_EMMC_D1,
+ GPIO1A1_SFC_SIO1,
+
+ GPIO1A0_SHIFT = 0,
+ GPIO1A0_MASK = 0xf << GPIO1A0_SHIFT,
+ GPIO1A0_GPIO = 0,
+ GPIO1A0_FLASH_D0,
+ GPIO1A0_EMMC_D0,
+ GPIO1A0_SFC_SIO0,
+};
+
+/* GRF_GPIO1AH_IOMUX */
+enum {
+ GPIO1A4_SHIFT = 0,
+ GPIO1A4_MASK = 0xf << GPIO1A4_SHIFT,
+ GPIO1A4_GPIO = 0,
+ GPIO1A4_FLASH_D4,
+ GPIO1A4_EMMC_D4,
+ GPIO1A4_SFC_CSN0,
+};
+
+/* GRF_GPIO1BL_IOMUX */
+enum {
+ GPIO1B1_SHIFT = 4,
+ GPIO1B1_MASK = 0xf << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_FLASH_RDY,
+ GPIO1B1_EMMC_CLKOUT,
+ GPIO1B1_SFC_CLK,
+};
+
/* GRF_GPIO1BH_IOMUX */
enum {
GPIO1B7_SHIFT = 12,
@@ -193,6 +244,19 @@ int arch_cpu_init(void)
GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
#endif
+#ifdef CONFIG_ROCKCHIP_SFC
+ rk_clrsetreg(&grf->gpio1al_iomux,
+ GPIO1A3_MASK | GPIO1A2_MASK | GPIO1A1_MASK | GPIO1A0_MASK,
+ GPIO1A3_SFC_SIO3 << GPIO1A3_SHIFT |
+ GPIO1A2_SFC_SIO2 << GPIO1A2_SHIFT |
+ GPIO1A1_SFC_SIO1 << GPIO1A1_SHIFT |
+ GPIO1A0_SFC_SIO0 << GPIO1A0_SHIFT);
+ rk_clrsetreg(&grf->gpio1ah_iomux, GPIO1A4_MASK,
+ GPIO1A4_SFC_CSN0 << GPIO1A4_SHIFT);
+ rk_clrsetreg(&grf->gpio1bl_iomux, GPIO1B1_MASK,
+ GPIO1B1_SFC_CLK << GPIO1B1_SHIFT);
+#endif
+
#endif
/* Enable PD_VO (default disable at reset) */
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v7 3/6] rockchip: px30: add the serial flash controller
2021-08-05 8:26 [PATCH v7 0/6] rockchip_sfc: add support for Rockchip SFC Jon Lin
2021-08-05 8:26 ` [PATCH v7 1/6] spi: " Jon Lin
2021-08-05 8:26 ` [PATCH v7 2/6] rockchip: px30: Add support for using SFC Jon Lin
@ 2021-08-05 8:26 ` Jon Lin
2021-08-05 11:30 ` Jagan Teki
2021-08-11 10:19 ` Kever Yang
2021-08-05 8:26 ` [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B Jon Lin
2021-08-05 8:27 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Jon Lin
4 siblings, 2 replies; 23+ messages in thread
From: Jon Lin @ 2021-08-05 8:26 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan, Jon Lin
From: Chris Morgan <macromorgan@hotmail.com>
Add the serial flash controller to the devicetree for the PX30.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
(no changes since v5)
Changes in v5:
- px30 use "rockchip, sfc" as compatible id
arch/arm/dts/px30.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index b6c79e7ed3..aaa8ae2235 100644
--- a/arch/arm/dts/px30.dtsi
+++ b/arch/arm/dts/px30.dtsi
@@ -960,6 +960,18 @@
status = "disabled";
};
+ sfc: sfc@ff3a0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff3a0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
gpu: gpu@ff400000 {
compatible = "rockchip,px30-mali", "arm,mali-bifrost";
reg = <0x0 0xff400000 0x0 0x4000>;
@@ -1926,6 +1938,32 @@
};
};
+ serial_flash {
+ sfc_bus4: sfc-bus4 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ sfc_bus2: sfc-bus2 {
+ rockchip,pins =
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ sfc_cs: sfc-cs {
+ rockchip,pins =
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ sfc_clk: sfc-clk {
+ rockchip,pins =
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+ };
+
lcdc {
lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
rockchip,pins =
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B
2021-08-05 8:26 [PATCH v7 0/6] rockchip_sfc: add support for Rockchip SFC Jon Lin
` (2 preceding siblings ...)
2021-08-05 8:26 ` [PATCH v7 3/6] rockchip: px30: add the serial flash controller Jon Lin
@ 2021-08-05 8:26 ` Jon Lin
2021-08-05 11:34 ` Jagan Teki
` (2 more replies)
2021-08-05 8:27 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Jon Lin
4 siblings, 3 replies; 23+ messages in thread
From: Jon Lin @ 2021-08-05 8:26 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan, Jon Lin
From: Chris Morgan <macromorgan@hotmail.com>
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
this chip uses a continuation code which I cannot seem to parse, so
there are possibly going to be collisions with chips that use the same
manufacturer/ID.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v7:
- Remove SPI_NOR_HAS_TB and SPI_NOR_HAS_LOCK
drivers/mtd/spi/Kconfig | 6 ++++++
drivers/mtd/spi/spi-nor-ids.c | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 1b2ef37e92..b2291f7290 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -204,6 +204,12 @@ config SPI_FLASH_XMC
Add support for various XMC (Wuhan Xinxin Semiconductor
Manufacturing Corp.) SPI flash chips (XM25xxx)
+config SPI_FLASH_XTX
+ bool "XTX SPI flash support"
+ help
+ Add support for various XTX (XTX Technology Limited)
+ SPI flash chips (XT25xxx).
+
endif
config SPI_FLASH_USE_4K_SECTORS
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index cb3a08872d..4aef1ddd6e 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -361,6 +361,10 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+#endif
+#ifdef CONFIG_SPI_FLASH_XTX
+ /* XTX Technology (Shenzhen) Limited */
+ { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
{ },
};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance
2021-08-05 8:26 [PATCH v7 0/6] rockchip_sfc: add support for Rockchip SFC Jon Lin
` (3 preceding siblings ...)
2021-08-05 8:26 ` [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B Jon Lin
@ 2021-08-05 8:27 ` Jon Lin
2021-08-05 8:27 ` [PATCH v7 6/6] rockchip: px30: Support configure SFC Jon Lin
` (2 more replies)
4 siblings, 3 replies; 23+ messages in thread
From: Jon Lin @ 2021-08-05 8:27 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan, Jon Lin
From: Chris Morgan <macromorgan@hotmail.com>
The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Changing the pinctrl to bus2 and setting tx
and rx lines to 2 for this reason.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
(no changes since v1)
arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 +++++++++++++++++
arch/arm/dts/rk3326-odroid-go2.dts | 16 ++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
index 00767d2abd..741e8dd935 100644
--- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
+++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
@@ -7,6 +7,15 @@
chosen {
u-boot,spl-boot-order = &sdmmc;
};
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdmmc;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ spi0 = &sfc;
+ };
};
&cru {
@@ -57,6 +66,14 @@
u-boot,spl-fifo-mode;
};
+&sfc {
+ u-boot,dm-pre-reloc;
+};
+
+&spi_flash {
+ u-boot,dm-pre-reloc;
+};
+
&uart1 {
clock-frequency = <24000000>;
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
index 8cd4688c49..6f91f5040b 100644
--- a/arch/arm/dts/rk3326-odroid-go2.dts
+++ b/arch/arm/dts/rk3326-odroid-go2.dts
@@ -617,6 +617,22 @@
status = "okay";
};
+&sfc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
+ status = "okay";
+
+ spi_flash: xt25f128b@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <2>;
+ spi-tx-bus-width = <2>;
+ };
+};
+
&tsadc {
status = "okay";
};
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v7 6/6] rockchip: px30: Support configure SFC
2021-08-05 8:27 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Jon Lin
@ 2021-08-05 8:27 ` Jon Lin
2021-08-05 11:36 ` Jagan Teki
` (2 more replies)
2021-08-05 17:32 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Chris Morgan
2021-08-11 10:20 ` Kever Yang
2 siblings, 3 replies; 23+ messages in thread
From: Jon Lin @ 2021-08-05 8:27 UTC (permalink / raw)
To: u-boot
Cc: heiko.stuebner, vigneshr, jagan, kever.yang, philipp.tomsich,
sjg, macromorgan, Jon Lin
Make px30 SFC clock configurable
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
---
Changes in v7:
- Make px30 SFC clock configurable
drivers/clk/rockchip/clk_px30.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 6b746f4c65..a49b6f19f4 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -581,6 +581,32 @@ static ulong px30_mmc_set_clk(struct px30_clk_priv *priv,
return px30_mmc_get_clk(priv, clk_id);
}
+static ulong px30_sfc_get_clk(struct px30_clk_priv *priv, uint clk_id)
+{
+ struct px30_cru *cru = priv->cru;
+ u32 div, con;
+
+ con = readl(&cru->clksel_con[22]);
+ div = (con & SFC_DIV_CON_MASK) >> SFC_DIV_CON_SHIFT;
+
+ return DIV_TO_RATE(priv->gpll_hz, div);
+}
+
+static ulong px30_sfc_set_clk(struct px30_clk_priv *priv,
+ ulong clk_id, ulong set_rate)
+{
+ struct px30_cru *cru = priv->cru;
+ int src_clk_div;
+
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate);
+ rk_clrsetreg(&cru->clksel_con[22],
+ SFC_PLL_SEL_MASK | SFC_DIV_CON_MASK,
+ 0 << SFC_PLL_SEL_SHIFT |
+ (src_clk_div - 1) << SFC_DIV_CON_SHIFT);
+
+ return px30_sfc_get_clk(priv, clk_id);
+}
+
static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id)
{
struct px30_cru *cru = priv->cru;
@@ -1192,6 +1218,9 @@ static ulong px30_clk_get_rate(struct clk *clk)
case SCLK_EMMC_SAMPLE:
rate = px30_mmc_get_clk(priv, clk->id);
break;
+ case SCLK_SFC:
+ rate = px30_sfc_get_clk(priv, clk->id);
+ break;
case SCLK_I2C0:
case SCLK_I2C1:
case SCLK_I2C2:
@@ -1271,6 +1300,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_EMMC:
ret = px30_mmc_set_clk(priv, clk->id, rate);
break;
+ case SCLK_SFC:
+ ret = px30_sfc_set_clk(priv, clk->id, rate);
+ break;
case SCLK_I2C0:
case SCLK_I2C1:
case SCLK_I2C2:
--
2.17.1
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v7 1/6] spi: rockchip_sfc: add support for Rockchip SFC
2021-08-05 8:26 ` [PATCH v7 1/6] spi: " Jon Lin
@ 2021-08-05 11:26 ` Jagan Teki
2021-08-05 16:17 ` Chris Morgan
2021-08-11 10:19 ` Kever Yang
2021-08-11 10:26 ` Philipp Tomsich
2 siblings, 1 reply; 23+ messages in thread
From: Jagan Teki @ 2021-08-05 11:26 UTC (permalink / raw)
To: Jon Lin
Cc: U-Boot-Denx, Heiko Stuebner, Vignesh R, Kever Yang,
philipp.tomsich, Simon Glass, macromorgan
On Thu, Aug 5, 2021 at 1:57 PM Jon Lin <jon.lin@rock-chips.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> This patch adds support for the Rockchip serial flash controller
> found on the PX30 SoC. It should work for versions 3-5 of the SFC
> IP, however I am only able to test it on v3.
>
> This is adapted from the WIP SPI-MEM driver for the SFC on mainline
> Linux. Note that the main difference between this and earlier versions
> of the driver is that this one does not support DMA. In testing
> the performance difference (performing a dual mode read on a 128Mb
> chip) is negligible. DMA, if used, must also be disabled in SPL
> mode when using A-TF anyway.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
>
> Changes in v7:
> - Make sfc-use-dma configurable
>
> Changes in v6:
> - Fix dma transfer logic
> - Fix the error of the way to wait for dma transfer finished status
>
> Changes in v5:
> - Support dma transfer
> - Add CONFIG_IS_ENABLED(CLK) limitation
> - Support spinand devices
> - Support SFC ver4 ver5
> - Using "rockchip, sfc" as compatible id
> - Get clock from the index to compatible with those case which's
> clock-names is not parsed
>
> Changes in v4:
> - None
>
> Changes in v3:
> - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
> driver to fix potential issue on hardware. Note I never noticed
> this issue while testing, so I cannot test if it fixed any specific
> issue for me.
> - Updated of-compatible string back to "rockchip,sfc" to match what
> is currently proposed for upstream driver. The hardware itself
> has multiple versions but a register is present in the hardware that
> is read by the driver to set version specific functionality.
> - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that
> sfc nodes match what is in upstream.
>
> Changes in v2:
> - Resending due to glitch with patch file truncating final two lines
> on patch 1/5 and incorrect patch version number on patch 5/5.
>
> Changes in v1:
> - Reworked code to utilize spi-mem framework, and based it closely
> off of work in progress code for mainline Linux.
> - Removed DMA, as it didn't offer much performance benefit for
> booting (in my test cases), added complexity to the code, and
> interfered with A-TF.
> - Updated the names of the bindings to match the work in progress
> Linux code.
> - Moved alias to u-boot specific device-tree for Odroid Go Advance.
> Alias is updated with the spi0 node pointing to the SFC to
> help the sf command as well as facilitate booting from the SFC.
> - Note 2 below no longer applies, as rebasing this off of upstream
> code should allow the device to work for NAND, and by utilizing
> the spi-mem framework it no longer has to extract the parameters
>
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/rockchip_sfc.c | 646 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 655 insertions(+)
> create mode 100644 drivers/spi/rockchip_sfc.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 5c2a60a214..e12699bec7 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -319,6 +319,14 @@ config RENESAS_RPC_SPI
> on Renesas RCar Gen3 SoCs. This uses driver model and requires a
> device tree binding to operate.
>
> +config ROCKCHIP_SFC
> + bool "Rockchip SFC Driver"
> + help
> + Enable the Rockchip SFC Driver for SPI NOR flash. This device is
> + a limited purpose SPI controller for driving NOR flash on certain
> + Rockchip SoCs. This uses driver model and requires a device tree
> + binding to operate.
> +
> config ROCKCHIP_SPI
> bool "Rockchip SPI driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 216e72c60f..d2f24bccef 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -54,6 +54,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
> obj-$(CONFIG_SPI_QUP) += spi-qup.o
> obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
> obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
> +obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o
> obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
> obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
> obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
> diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
> new file mode 100644
> index 0000000000..4e2b861f22
> --- /dev/null
> +++ b/drivers/spi/rockchip_sfc.c
> @@ -0,0 +1,646 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Rockchip Serial Flash Controller Driver
> + *
> + * Copyright (c) 2017-2021, Rockchip Inc.
> + * Author: Shawn Lin <shawn.lin@rock-chips.com>
> + * Chris Morgan <macromorgan@hotmail.com>
> + * Jon Lin <Jon.lin@rock-chips.com>
> + */
> +
> +#include <asm/io.h>
> +#include <bouncebuf.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/iopoll.h>
> +#include <spi.h>
> +#include <spi-mem.h>
> +
> +/* System control */
> +#define SFC_CTRL 0x0
> +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
> +#define SFC_CTRL_CMD_BITS_SHIFT 8
> +#define SFC_CTRL_ADDR_BITS_SHIFT 10
> +#define SFC_CTRL_DATA_BITS_SHIFT 12
> +
> +/* Interrupt mask */
> +#define SFC_IMR 0x4
> +#define SFC_IMR_RX_FULL BIT(0)
> +#define SFC_IMR_RX_UFLOW BIT(1)
> +#define SFC_IMR_TX_OFLOW BIT(2)
> +#define SFC_IMR_TX_EMPTY BIT(3)
> +#define SFC_IMR_TRAN_FINISH BIT(4)
> +#define SFC_IMR_BUS_ERR BIT(5)
> +#define SFC_IMR_NSPI_ERR BIT(6)
> +#define SFC_IMR_DMA BIT(7)
> +
> +/* Interrupt clear */
> +#define SFC_ICLR 0x8
> +#define SFC_ICLR_RX_FULL BIT(0)
> +#define SFC_ICLR_RX_UFLOW BIT(1)
> +#define SFC_ICLR_TX_OFLOW BIT(2)
> +#define SFC_ICLR_TX_EMPTY BIT(3)
> +#define SFC_ICLR_TRAN_FINISH BIT(4)
> +#define SFC_ICLR_BUS_ERR BIT(5)
> +#define SFC_ICLR_NSPI_ERR BIT(6)
> +#define SFC_ICLR_DMA BIT(7)
> +
> +/* FIFO threshold level */
> +#define SFC_FTLR 0xc
> +#define SFC_FTLR_TX_SHIFT 0
> +#define SFC_FTLR_TX_MASK 0x1f
> +#define SFC_FTLR_RX_SHIFT 8
> +#define SFC_FTLR_RX_MASK 0x1f
> +
> +/* Reset FSM and FIFO */
> +#define SFC_RCVR 0x10
> +#define SFC_RCVR_RESET BIT(0)
> +
> +/* Enhanced mode */
> +#define SFC_AX 0x14
> +
> +/* Address Bit number */
> +#define SFC_ABIT 0x18
> +
> +/* Interrupt status */
> +#define SFC_ISR 0x1c
> +#define SFC_ISR_RX_FULL_SHIFT BIT(0)
> +#define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
> +#define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
> +#define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
> +#define SFC_ISR_TX_FINISH_SHIFT BIT(4)
> +#define SFC_ISR_BUS_ERR_SHIFT BIT(5)
> +#define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
> +#define SFC_ISR_DMA_SHIFT BIT(7)
> +
> +/* FIFO status */
> +#define SFC_FSR 0x20
> +#define SFC_FSR_TX_IS_FULL BIT(0)
> +#define SFC_FSR_TX_IS_EMPTY BIT(1)
> +#define SFC_FSR_RX_IS_EMPTY BIT(2)
> +#define SFC_FSR_RX_IS_FULL BIT(3)
> +#define SFC_FSR_TXLV_MASK GENMASK(12, 8)
> +#define SFC_FSR_TXLV_SHIFT 8
> +#define SFC_FSR_RXLV_MASK GENMASK(20, 16)
> +#define SFC_FSR_RXLV_SHIFT 16
> +
> +/* FSM status */
> +#define SFC_SR 0x24
> +#define SFC_SR_IS_IDLE 0x0
> +#define SFC_SR_IS_BUSY 0x1
> +
> +/* Raw interrupt status */
> +#define SFC_RISR 0x28
> +#define SFC_RISR_RX_FULL BIT(0)
> +#define SFC_RISR_RX_UNDERFLOW BIT(1)
> +#define SFC_RISR_TX_OVERFLOW BIT(2)
> +#define SFC_RISR_TX_EMPTY BIT(3)
> +#define SFC_RISR_TRAN_FINISH BIT(4)
> +#define SFC_RISR_BUS_ERR BIT(5)
> +#define SFC_RISR_NSPI_ERR BIT(6)
> +#define SFC_RISR_DMA BIT(7)
> +
> +/* Version */
> +#define SFC_VER 0x2C
> +#define SFC_VER_3 0x3
> +#define SFC_VER_4 0x4
> +#define SFC_VER_5 0x5
> +
> +/* Delay line controller resiter */
> +#define SFC_DLL_CTRL0 0x3C
> +#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
> +#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU
> +#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU
> +
> +/* Master trigger */
> +#define SFC_DMA_TRIGGER 0x80
> +
> +/* Src or Dst addr for master */
> +#define SFC_DMA_ADDR 0x84
> +
> +/* Length control register extension 32GB */
> +#define SFC_LEN_CTRL 0x88
> +#define SFC_LEN_CTRL_TRB_SEL 1
> +#define SFC_LEN_EXT 0x8C
> +
> +/* Command */
> +#define SFC_CMD 0x100
> +#define SFC_CMD_IDX_SHIFT 0
> +#define SFC_CMD_DUMMY_SHIFT 8
> +#define SFC_CMD_DIR_SHIFT 12
> +#define SFC_CMD_DIR_RD 0
> +#define SFC_CMD_DIR_WR 1
> +#define SFC_CMD_ADDR_SHIFT 14
> +#define SFC_CMD_ADDR_0BITS 0
> +#define SFC_CMD_ADDR_24BITS 1
> +#define SFC_CMD_ADDR_32BITS 2
> +#define SFC_CMD_ADDR_XBITS 3
> +#define SFC_CMD_TRAN_BYTES_SHIFT 16
> +#define SFC_CMD_CS_SHIFT 30
> +
> +/* Address */
> +#define SFC_ADDR 0x104
> +
> +/* Data */
> +#define SFC_DATA 0x108
> +
> +/* The controller and documentation reports that it supports up to 4 CS
> + * devices (0-3), however I have only been able to test a single CS (CS 0)
> + * due to the configuration of my device.
> + */
> +#define SFC_MAX_CHIPSELECT_NUM 4
> +
> +/* The SFC can transfer max 16KB - 1 at one time
> + * we set it to 15.5KB here for alignment.
> + */
> +#define SFC_MAX_IOSIZE_VER3 (512 * 31)
> +
> +#define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
> +
> +/* DMA is only enabled for large data transmission */
> +#define SFC_DMA_TRANS_THRETHOLD (0x40)
> +
> +/* Maximum clock values from datasheet suggest keeping clock value under
> + * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
> + * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
> + */
> +#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
> +#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
> +#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
> +
> +struct rockchip_sfc {
> + void __iomem *regbase;
> + struct clk hclk;
> + struct clk clk;
> + u32 max_freq;
> + u32 speed;
> + bool use_dma;
> + u32 max_iosize;
> + u16 version;
> +};
> +
> +static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
> +{
> + int err;
> + u32 status;
> +
> + writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
> +
> + err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
> + !(status & SFC_RCVR_RESET),
> + 1000000);
> + if (err)
> + printf("SFC reset never finished\n");
> +
> + /* Still need to clear the masked interrupt from RISR */
> + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> +
> + debug("reset\n");
Unneeded debug.
> +
> + return err;
> +}
> +
> +static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
> +{
> + return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
> +}
> +
> +static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
> +{
> + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
> + return SFC_MAX_IOSIZE_VER4;
> +
> + return SFC_MAX_IOSIZE_VER3;
> +}
> +
> +static int rockchip_sfc_init(struct rockchip_sfc *sfc)
> +{
> + writel(0, sfc->regbase + SFC_CTRL);
> + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
> + writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
> +
> + return 0;
> +}
> +
> +static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
> +{
> + struct rockchip_sfc *sfc = dev_get_plat(bus);
> +
> + sfc->regbase = dev_read_addr_ptr(bus);
> + if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
> + sfc->use_dma = false;
> + else
> + sfc->use_dma = true;
> +
> +#if CONFIG_IS_ENABLED(CLK)
Better drop this as rockchip by default support DM_CLK.
> + int ret;
> +
> + ret = clk_get_by_index(bus, 0, &sfc->clk);
> + if (ret < 0) {
> + printf("Could not get clock for %s: %d\n", bus->name, ret);
> + return ret;
> + }
> +
> + ret = clk_get_by_index(bus, 1, &sfc->hclk);
> + if (ret < 0) {
> + printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
> + return ret;
> + }
> +#endif
> +
> + return 0;
> +}
> +
> +static int rockchip_sfc_probe(struct udevice *bus)
> +{
> + struct rockchip_sfc *sfc = dev_get_plat(bus);
> + int ret;
> +
> +#if CONFIG_IS_ENABLED(CLK)
> + ret = clk_enable(&sfc->hclk);
> + if (ret)
> + debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
> +
> + ret = clk_enable(&sfc->clk);
> + if (ret)
> + debug("Enable clock fail for %s: %d\n", bus->name, ret);
> +
> + ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ);
> + if (ret)
> + debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
> +#endif
> +
> + ret = rockchip_sfc_init(sfc);
> + if (ret)
> + goto err_init;
> +
> + sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
> + sfc->version = rockchip_sfc_get_version(sfc);
> + sfc->speed = SFC_DEFAULT_SPEED_HZ;
Why this default speed? better get it from set_speed and use.
> +
> + return 0;
> +
> +err_init:
> +#if CONFIG_IS_ENABLED(CLK)
> + clk_disable(&sfc->clk);
> + clk_disable(&sfc->hclk);
> +#endif
> +
> + return ret;
> +}
> +
> +static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr)
> +{
> + u32 fsr = readl(sfc->regbase + SFC_FSR);
> + int level;
> +
> + if (wr)
> + level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
> + else
> + level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
> +
> + return level;
Please simplify by using set/clr bit API's
> +}
> +
> +static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout)
> +{
> + unsigned long tbase = get_timer(0);
> + int level;
> +
> + while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) {
> + if (get_timer(tbase) > timeout) {
> + debug("%s fifo timeout\n", wr ? "write" : "read");
> + return -ETIMEDOUT;
> + }
> + udelay(1);
> + }
Use readpoll.
> +
> + return level;
> +}
> +
> +static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
> +{
> + if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
> + /*
> + * SFC not support output DUMMY cycles right after CMD cycles, so
> + * treat it as ADDR cycles.
> + */
> + op->addr.nbytes = op->dummy.nbytes;
> + op->addr.buswidth = op->dummy.buswidth;
> + op->addr.val = 0xFFFFFFFFF;
> +
> + op->dummy.nbytes = 0;
> + }
> +}
> +
> +static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout)
> +{
> + unsigned long tbase;
> +
> + /* Wait for the DMA interrupt status */
> + tbase = get_timer(0);
> + while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) {
> + if (get_timer(tbase) > timeout) {
> + printf("dma timeout\n");
> + rockchip_sfc_reset(sfc);
> +
> + return -ETIMEDOUT;
> + }
> +
Use readpoll.
> + udelay(1);
> + }
> +
> + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> +
> + return 0;
> +}
> +
> +static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
> + struct spi_slave *mem,
> + const struct spi_mem_op *op,
> + u32 len)
> +{
> + struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
> + u32 ctrl = 0, cmd = 0;
> +
> + /* set CMD */
> + cmd = op->cmd.opcode;
> + ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
> +
> + /* set ADDR */
> + if (op->addr.nbytes) {
> + if (op->addr.nbytes == 4) {
> + cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
> + } else if (op->addr.nbytes == 3) {
> + cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
> + } else {
> + cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
> + writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
> + }
> +
> + ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
> + }
> +
> + /* set DUMMY */
> + if (op->dummy.nbytes) {
> + if (op->dummy.buswidth == 4)
> + cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
> + else if (op->dummy.buswidth == 2)
> + cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
> + else
> + cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
> + }
> +
> + /* set DATA */
> + if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
> + writel(len, sfc->regbase + SFC_LEN_EXT);
> + else
> + cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
> + if (len) {
> + if (op->data.dir == SPI_MEM_DATA_OUT)
> + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
> +
> + ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
> + }
> + if (!len && op->addr.nbytes)
> + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
> +
> + /* set the Controller */
> + ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
> + cmd |= plat->cs << SFC_CMD_CS_SHIFT;
> +
> + debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
> + op->addr.nbytes, op->addr.buswidth,
> + op->dummy.nbytes, op->dummy.buswidth);
> + debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
> + ctrl, cmd, op->addr.val, len);
Not sure these debugs, we have in spi-mem driver.
> +
> + writel(ctrl, sfc->regbase + SFC_CTRL);
> + writel(cmd, sfc->regbase + SFC_CMD);
> + if (op->addr.nbytes)
> + writel(op->addr.val, sfc->regbase + SFC_ADDR);
> +
> + return 0;
> +}
> +
> +static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
> +{
> + u8 bytes = len & 0x3;
> + u32 dwords;
> + int tx_level;
> + u32 write_words;
> + u32 tmp = 0;
> +
> + dwords = len >> 2;
> + while (dwords) {
> + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
> + if (tx_level < 0)
> + return tx_level;
> + write_words = min_t(u32, tx_level, dwords);
> + writesl(sfc->regbase + SFC_DATA, buf, write_words);
> + buf += write_words << 2;
> + dwords -= write_words;
> + }
> +
> + /* write the rest non word aligned bytes */
> + if (bytes) {
> + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
> + if (tx_level < 0)
> + return tx_level;
> + memcpy(&tmp, buf, bytes);
> + writel(tmp, sfc->regbase + SFC_DATA);
> + }
> +
> + return len;
> +}
> +
> +static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
> +{
> + u8 bytes = len & 0x3;
> + u32 dwords;
> + u8 read_words;
> + int rx_level;
> + int tmp;
> +
> + /* word aligned access only */
> + dwords = len >> 2;
> + while (dwords) {
> + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
> + if (rx_level < 0)
> + return rx_level;
> + read_words = min_t(u32, rx_level, dwords);
> + readsl(sfc->regbase + SFC_DATA, buf, read_words);
> + buf += read_words << 2;
> + dwords -= read_words;
> + }
> +
> + /* read the rest non word aligned bytes */
> + if (bytes) {
> + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
> + if (rx_level < 0)
> + return rx_level;
> + tmp = readl(sfc->regbase + SFC_DATA);
> + memcpy(buf, &tmp, bytes);
> + }
> +
> + return len;
> +}
> +
> +static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
> +{
> + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> + writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
> + writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
Please use associated BIT names instead of magic numbers.
> +
> + return len;
> +}
> +
> +static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
> + const struct spi_mem_op *op, u32 len)
> +{
> + debug("xfer_poll len=%x\n", len);
> +
> + if (op->data.dir == SPI_MEM_DATA_OUT)
> + return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
> + else
> + return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
> +}
> +
> +static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
> + const struct spi_mem_op *op, u32 len)
> +{
> + struct bounce_buffer bb;
> + unsigned int bb_flags;
> + void *dma_buf;
> + int ret;
> +
> + debug("xfer_dma len=%x\n", len);
> +
> + if (op->data.dir == SPI_MEM_DATA_OUT) {
> + dma_buf = (void *)op->data.buf.out;
> + bb_flags = GEN_BB_READ;
> + } else {
> + dma_buf = (void *)op->data.buf.in;
> + bb_flags = GEN_BB_WRITE;
> + }
> +
> + ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags);
> + if (ret)
> + return ret;
> +
> + ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len);
> + rockchip_sfc_wait_for_dma_finished(sfc, len * 10);
> + bounce_buffer_stop(&bb);
> +
> + return ret;
> +}
> +
> +static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
> +{
> + unsigned long tbase = get_timer(0);
> + int ret = 0;
> + u32 timeout = timeout_us;
> +
> + while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) {
> + if (get_timer(tbase) > timeout) {
> + printf("wait sfc idle timeout\n");
> + rockchip_sfc_reset(sfc);
> +
> + return -ETIMEDOUT;
> + }
> +
> + udelay(1);
> + }
> +
> + return ret;
> +}
> +
> +static int rockchip_sfc_exec_op(struct spi_slave *mem,
> + const struct spi_mem_op *op)
> +{
> + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
> + u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
> + int ret;
> +
> +#if CONFIG_IS_ENABLED(CLK)
> + if (unlikely(mem->max_hz != sfc->speed)) {
> + ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
> + (uint)SFC_MAX_SPEED_HZ));
> + if (ret < 0) {
> + printf("set_freq=%dHz fail, check if it's the cru support level\n",
> + mem->max_hz);
> + return ret;
> + }
> +
> + sfc->max_freq = mem->max_hz;
> + sfc->speed = mem->max_hz;
> + debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed);
> + }
> +#endif
> +
> + rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
> +
> + rockchip_sfc_xfer_setup(sfc, mem, op, len);
> + if (len) {
> + if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD)
This seems confusing, please simply if possible.
> + ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
> + else
> + ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
> +
> + if (ret != len) {
> + printf("xfer data failed ret %d dir %d\n", ret, op->data.dir);
> +
> + return -EIO;
> + }
> + }
> +
> + return rockchip_sfc_xfer_done(sfc, 100000);
> +}
> +
> +static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op)
> +{
> + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
> +
> + op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
> + return 0;
> +}
> +
> +static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
> +{
> + /* We set up speed later for each transmission.
> + */
> + return 0;
This is the best place to alter speed instead of probe or other.
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 3/6] rockchip: px30: add the serial flash controller
2021-08-05 8:26 ` [PATCH v7 3/6] rockchip: px30: add the serial flash controller Jon Lin
@ 2021-08-05 11:30 ` Jagan Teki
2021-08-05 15:27 ` Chris Morgan
2021-08-11 10:19 ` Kever Yang
1 sibling, 1 reply; 23+ messages in thread
From: Jagan Teki @ 2021-08-05 11:30 UTC (permalink / raw)
To: Jon Lin
Cc: U-Boot-Denx, Heiko Stuebner, Vignesh R, Kever Yang,
philipp.tomsich, Simon Glass, macromorgan
On Thu, Aug 5, 2021 at 1:57 PM Jon Lin <jon.lin@rock-chips.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add the serial flash controller to the devicetree for the PX30.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
>
> (no changes since v5)
>
> Changes in v5:
> - px30 use "rockchip, sfc" as compatible id
>
> arch/arm/dts/px30.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
> index b6c79e7ed3..aaa8ae2235 100644
> --- a/arch/arm/dts/px30.dtsi
> +++ b/arch/arm/dts/px30.dtsi
> @@ -960,6 +960,18 @@
> status = "disabled";
> };
>
> + sfc: sfc@ff3a0000 {
> + compatible = "rockchip,sfc";
> + reg = <0x0 0xff3a0000 0x0 0x4000>;
> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
> + clock-names = "clk_sfc", "hclk_sfc";
> + pinctrl-names = "default";
> + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
> + power-domains = <&power PX30_PD_MMC_NAND>;
> + status = "disabled";
> + };
> +
> gpu: gpu@ff400000 {
> compatible = "rockchip,px30-mali", "arm,mali-bifrost";
> reg = <0x0 0xff400000 0x0 0x4000>;
> @@ -1926,6 +1938,32 @@
> };
> };
>
> + serial_flash {
> + sfc_bus4: sfc-bus4 {
> + rockchip,pins =
> + <1 RK_PA0 3 &pcfg_pull_none>,
> + <1 RK_PA1 3 &pcfg_pull_none>,
> + <1 RK_PA2 3 &pcfg_pull_none>,
> + <1 RK_PA3 3 &pcfg_pull_none>;
> + };
> +
> + sfc_bus2: sfc-bus2 {
> + rockchip,pins =
> + <1 RK_PA0 3 &pcfg_pull_none>,
> + <1 RK_PA1 3 &pcfg_pull_none>;
> + };
> +
> + sfc_cs: sfc-cs {
> + rockchip,pins =
> + <1 RK_PA4 3 &pcfg_pull_none>;
> + };
> +
> + sfc_clk: sfc-clk {
> + rockchip,pins =
> + <1 RK_PB1 3 &pcfg_pull_none>;
> + };
> + };
> +
Better to sync the Linux, instead of intermediate add-ons. Add it in
-u-boot.dtsi so-that it can remove while syncing rc tags, may be Kever
can comment. Whole idea is to keep px30.dtsi as same as Linux.
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B
2021-08-05 8:26 ` [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B Jon Lin
@ 2021-08-05 11:34 ` Jagan Teki
2021-08-11 10:19 ` Kever Yang
2021-08-11 10:27 ` Philipp Tomsich
2 siblings, 0 replies; 23+ messages in thread
From: Jagan Teki @ 2021-08-05 11:34 UTC (permalink / raw)
To: Jon Lin
Cc: U-Boot-Denx, Heiko Stuebner, Vignesh R, Kever Yang,
philipp.tomsich, Simon Glass, macromorgan
On Thu, Aug 5, 2021 at 1:56 PM Jon Lin <jon.lin@rock-chips.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
> this chip uses a continuation code which I cannot seem to parse, so
> there are possibly going to be collisions with chips that use the same
> manufacturer/ID.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
Applied to u-boot-spi/master
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 6/6] rockchip: px30: Support configure SFC
2021-08-05 8:27 ` [PATCH v7 6/6] rockchip: px30: Support configure SFC Jon Lin
@ 2021-08-05 11:36 ` Jagan Teki
2021-08-11 10:20 ` Kever Yang
2021-08-11 10:28 ` Philipp Tomsich
2 siblings, 0 replies; 23+ messages in thread
From: Jagan Teki @ 2021-08-05 11:36 UTC (permalink / raw)
To: Jon Lin
Cc: U-Boot-Denx, Heiko Stuebner, Vignesh R, Kever Yang,
philipp.tomsich, Simon Glass, macromorgan
On Thu, Aug 5, 2021 at 1:58 PM Jon Lin <jon.lin@rock-chips.com> wrote:
>
> Make px30 SFC clock configurable
>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 3/6] rockchip: px30: add the serial flash controller
2021-08-05 11:30 ` Jagan Teki
@ 2021-08-05 15:27 ` Chris Morgan
0 siblings, 0 replies; 23+ messages in thread
From: Chris Morgan @ 2021-08-05 15:27 UTC (permalink / raw)
To: Jagan Teki
Cc: Jon Lin, U-Boot-Denx, Heiko Stuebner, Vignesh R, Kever Yang,
philipp.tomsich, Simon Glass
On Thu, Aug 05, 2021 at 05:00:44PM +0530, Jagan Teki wrote:
> On Thu, Aug 5, 2021 at 1:57 PM Jon Lin <jon.lin@rock-chips.com> wrote:
> >
> > From: Chris Morgan <macromorgan@hotmail.com>
> >
> > Add the serial flash controller to the devicetree for the PX30.
> >
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> > ---
> >
> > (no changes since v5)
> >
> > Changes in v5:
> > - px30 use "rockchip, sfc" as compatible id
> >
> > arch/arm/dts/px30.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> >
> > diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
> > index b6c79e7ed3..aaa8ae2235 100644
> > --- a/arch/arm/dts/px30.dtsi
> > +++ b/arch/arm/dts/px30.dtsi
> > @@ -960,6 +960,18 @@
> > status = "disabled";
> > };
> >
> > + sfc: sfc@ff3a0000 {
> > + compatible = "rockchip,sfc";
> > + reg = <0x0 0xff3a0000 0x0 0x4000>;
> > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
> > + clock-names = "clk_sfc", "hclk_sfc";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
> > + power-domains = <&power PX30_PD_MMC_NAND>;
> > + status = "disabled";
> > + };
> > +
> > gpu: gpu@ff400000 {
> > compatible = "rockchip,px30-mali", "arm,mali-bifrost";
> > reg = <0x0 0xff400000 0x0 0x4000>;
> > @@ -1926,6 +1938,32 @@
> > };
> > };
> >
> > + serial_flash {
> > + sfc_bus4: sfc-bus4 {
> > + rockchip,pins =
> > + <1 RK_PA0 3 &pcfg_pull_none>,
> > + <1 RK_PA1 3 &pcfg_pull_none>,
> > + <1 RK_PA2 3 &pcfg_pull_none>,
> > + <1 RK_PA3 3 &pcfg_pull_none>;
> > + };
> > +
> > + sfc_bus2: sfc-bus2 {
> > + rockchip,pins =
> > + <1 RK_PA0 3 &pcfg_pull_none>,
> > + <1 RK_PA1 3 &pcfg_pull_none>;
> > + };
> > +
> > + sfc_cs: sfc-cs {
> > + rockchip,pins =
> > + <1 RK_PA4 3 &pcfg_pull_none>;
> > + };
> > +
> > + sfc_clk: sfc-clk {
> > + rockchip,pins =
> > + <1 RK_PB1 3 &pcfg_pull_none>;
> > + };
> > + };
> > +
>
> Better to sync the Linux, instead of intermediate add-ons. Add it in
> -u-boot.dtsi so-that it can remove while syncing rc tags, may be Kever
> can comment. Whole idea is to keep px30.dtsi as same as Linux.
>
> Thanks,
> Jagan.
The Linux driver itself is getting updated in exactly the same way. The
expectation is that once it's accepted this will be exactly how it's
done in the upstream Linux px30.dtsi file.
Thank you.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 1/6] spi: rockchip_sfc: add support for Rockchip SFC
2021-08-05 11:26 ` Jagan Teki
@ 2021-08-05 16:17 ` Chris Morgan
0 siblings, 0 replies; 23+ messages in thread
From: Chris Morgan @ 2021-08-05 16:17 UTC (permalink / raw)
To: Jagan Teki
Cc: Jon Lin, U-Boot-Denx, Heiko Stuebner, Vignesh R, Kever Yang,
philipp.tomsich, Simon Glass
On Thu, Aug 05, 2021 at 04:56:31PM +0530, Jagan Teki wrote:
> On Thu, Aug 5, 2021 at 1:57 PM Jon Lin <jon.lin@rock-chips.com> wrote:
> >
> > From: Chris Morgan <macromorgan@hotmail.com>
> >
> > This patch adds support for the Rockchip serial flash controller
> > found on the PX30 SoC. It should work for versions 3-5 of the SFC
> > IP, however I am only able to test it on v3.
> >
> > This is adapted from the WIP SPI-MEM driver for the SFC on mainline
> > Linux. Note that the main difference between this and earlier versions
> > of the driver is that this one does not support DMA. In testing
> > the performance difference (performing a dual mode read on a 128Mb
> > chip) is negligible. DMA, if used, must also be disabled in SPL
> > mode when using A-TF anyway.
> >
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> > Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> > ---
> >
> > Changes in v7:
> > - Make sfc-use-dma configurable
> >
> > Changes in v6:
> > - Fix dma transfer logic
> > - Fix the error of the way to wait for dma transfer finished status
> >
> > Changes in v5:
> > - Support dma transfer
> > - Add CONFIG_IS_ENABLED(CLK) limitation
> > - Support spinand devices
> > - Support SFC ver4 ver5
> > - Using "rockchip, sfc" as compatible id
> > - Get clock from the index to compatible with those case which's
> > clock-names is not parsed
> >
> > Changes in v4:
> > - None
> >
> > Changes in v3:
> > - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
> > driver to fix potential issue on hardware. Note I never noticed
> > this issue while testing, so I cannot test if it fixed any specific
> > issue for me.
> > - Updated of-compatible string back to "rockchip,sfc" to match what
> > is currently proposed for upstream driver. The hardware itself
> > has multiple versions but a register is present in the hardware that
> > is read by the driver to set version specific functionality.
> > - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that
> > sfc nodes match what is in upstream.
> >
> > Changes in v2:
> > - Resending due to glitch with patch file truncating final two lines
> > on patch 1/5 and incorrect patch version number on patch 5/5.
> >
> > Changes in v1:
> > - Reworked code to utilize spi-mem framework, and based it closely
> > off of work in progress code for mainline Linux.
> > - Removed DMA, as it didn't offer much performance benefit for
> > booting (in my test cases), added complexity to the code, and
> > interfered with A-TF.
> > - Updated the names of the bindings to match the work in progress
> > Linux code.
> > - Moved alias to u-boot specific device-tree for Odroid Go Advance.
> > Alias is updated with the spi0 node pointing to the SFC to
> > help the sf command as well as facilitate booting from the SFC.
> > - Note 2 below no longer applies, as rebasing this off of upstream
> > code should allow the device to work for NAND, and by utilizing
> > the spi-mem framework it no longer has to extract the parameters
> >
> > drivers/spi/Kconfig | 8 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/rockchip_sfc.c | 646 +++++++++++++++++++++++++++++++++++++
> > 3 files changed, 655 insertions(+)
> > create mode 100644 drivers/spi/rockchip_sfc.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index 5c2a60a214..e12699bec7 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -319,6 +319,14 @@ config RENESAS_RPC_SPI
> > on Renesas RCar Gen3 SoCs. This uses driver model and requires a
> > device tree binding to operate.
> >
> > +config ROCKCHIP_SFC
> > + bool "Rockchip SFC Driver"
> > + help
> > + Enable the Rockchip SFC Driver for SPI NOR flash. This device is
> > + a limited purpose SPI controller for driving NOR flash on certain
> > + Rockchip SoCs. This uses driver model and requires a device tree
> > + binding to operate.
> > +
> > config ROCKCHIP_SPI
> > bool "Rockchip SPI driver"
> > help
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > index 216e72c60f..d2f24bccef 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -54,6 +54,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
> > obj-$(CONFIG_SPI_QUP) += spi-qup.o
> > obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
> > obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
> > +obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o
> > obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
> > obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
> > obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
> > diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
> > new file mode 100644
> > index 0000000000..4e2b861f22
> > --- /dev/null
> > +++ b/drivers/spi/rockchip_sfc.c
> > @@ -0,0 +1,646 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Rockchip Serial Flash Controller Driver
> > + *
> > + * Copyright (c) 2017-2021, Rockchip Inc.
> > + * Author: Shawn Lin <shawn.lin@rock-chips.com>
> > + * Chris Morgan <macromorgan@hotmail.com>
> > + * Jon Lin <Jon.lin@rock-chips.com>
> > + */
> > +
> > +#include <asm/io.h>
> > +#include <bouncebuf.h>
> > +#include <clk.h>
> > +#include <dm.h>
> > +#include <linux/bitops.h>
> > +#include <linux/delay.h>
> > +#include <linux/iopoll.h>
> > +#include <spi.h>
> > +#include <spi-mem.h>
> > +
> > +/* System control */
> > +#define SFC_CTRL 0x0
> > +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
> > +#define SFC_CTRL_CMD_BITS_SHIFT 8
> > +#define SFC_CTRL_ADDR_BITS_SHIFT 10
> > +#define SFC_CTRL_DATA_BITS_SHIFT 12
> > +
> > +/* Interrupt mask */
> > +#define SFC_IMR 0x4
> > +#define SFC_IMR_RX_FULL BIT(0)
> > +#define SFC_IMR_RX_UFLOW BIT(1)
> > +#define SFC_IMR_TX_OFLOW BIT(2)
> > +#define SFC_IMR_TX_EMPTY BIT(3)
> > +#define SFC_IMR_TRAN_FINISH BIT(4)
> > +#define SFC_IMR_BUS_ERR BIT(5)
> > +#define SFC_IMR_NSPI_ERR BIT(6)
> > +#define SFC_IMR_DMA BIT(7)
> > +
> > +/* Interrupt clear */
> > +#define SFC_ICLR 0x8
> > +#define SFC_ICLR_RX_FULL BIT(0)
> > +#define SFC_ICLR_RX_UFLOW BIT(1)
> > +#define SFC_ICLR_TX_OFLOW BIT(2)
> > +#define SFC_ICLR_TX_EMPTY BIT(3)
> > +#define SFC_ICLR_TRAN_FINISH BIT(4)
> > +#define SFC_ICLR_BUS_ERR BIT(5)
> > +#define SFC_ICLR_NSPI_ERR BIT(6)
> > +#define SFC_ICLR_DMA BIT(7)
> > +
> > +/* FIFO threshold level */
> > +#define SFC_FTLR 0xc
> > +#define SFC_FTLR_TX_SHIFT 0
> > +#define SFC_FTLR_TX_MASK 0x1f
> > +#define SFC_FTLR_RX_SHIFT 8
> > +#define SFC_FTLR_RX_MASK 0x1f
> > +
> > +/* Reset FSM and FIFO */
> > +#define SFC_RCVR 0x10
> > +#define SFC_RCVR_RESET BIT(0)
> > +
> > +/* Enhanced mode */
> > +#define SFC_AX 0x14
> > +
> > +/* Address Bit number */
> > +#define SFC_ABIT 0x18
> > +
> > +/* Interrupt status */
> > +#define SFC_ISR 0x1c
> > +#define SFC_ISR_RX_FULL_SHIFT BIT(0)
> > +#define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
> > +#define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
> > +#define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
> > +#define SFC_ISR_TX_FINISH_SHIFT BIT(4)
> > +#define SFC_ISR_BUS_ERR_SHIFT BIT(5)
> > +#define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
> > +#define SFC_ISR_DMA_SHIFT BIT(7)
> > +
> > +/* FIFO status */
> > +#define SFC_FSR 0x20
> > +#define SFC_FSR_TX_IS_FULL BIT(0)
> > +#define SFC_FSR_TX_IS_EMPTY BIT(1)
> > +#define SFC_FSR_RX_IS_EMPTY BIT(2)
> > +#define SFC_FSR_RX_IS_FULL BIT(3)
> > +#define SFC_FSR_TXLV_MASK GENMASK(12, 8)
> > +#define SFC_FSR_TXLV_SHIFT 8
> > +#define SFC_FSR_RXLV_MASK GENMASK(20, 16)
> > +#define SFC_FSR_RXLV_SHIFT 16
> > +
> > +/* FSM status */
> > +#define SFC_SR 0x24
> > +#define SFC_SR_IS_IDLE 0x0
> > +#define SFC_SR_IS_BUSY 0x1
> > +
> > +/* Raw interrupt status */
> > +#define SFC_RISR 0x28
> > +#define SFC_RISR_RX_FULL BIT(0)
> > +#define SFC_RISR_RX_UNDERFLOW BIT(1)
> > +#define SFC_RISR_TX_OVERFLOW BIT(2)
> > +#define SFC_RISR_TX_EMPTY BIT(3)
> > +#define SFC_RISR_TRAN_FINISH BIT(4)
> > +#define SFC_RISR_BUS_ERR BIT(5)
> > +#define SFC_RISR_NSPI_ERR BIT(6)
> > +#define SFC_RISR_DMA BIT(7)
> > +
> > +/* Version */
> > +#define SFC_VER 0x2C
> > +#define SFC_VER_3 0x3
> > +#define SFC_VER_4 0x4
> > +#define SFC_VER_5 0x5
> > +
> > +/* Delay line controller resiter */
> > +#define SFC_DLL_CTRL0 0x3C
> > +#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
> > +#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU
> > +#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU
> > +
> > +/* Master trigger */
> > +#define SFC_DMA_TRIGGER 0x80
> > +
> > +/* Src or Dst addr for master */
> > +#define SFC_DMA_ADDR 0x84
> > +
> > +/* Length control register extension 32GB */
> > +#define SFC_LEN_CTRL 0x88
> > +#define SFC_LEN_CTRL_TRB_SEL 1
> > +#define SFC_LEN_EXT 0x8C
> > +
> > +/* Command */
> > +#define SFC_CMD 0x100
> > +#define SFC_CMD_IDX_SHIFT 0
> > +#define SFC_CMD_DUMMY_SHIFT 8
> > +#define SFC_CMD_DIR_SHIFT 12
> > +#define SFC_CMD_DIR_RD 0
> > +#define SFC_CMD_DIR_WR 1
> > +#define SFC_CMD_ADDR_SHIFT 14
> > +#define SFC_CMD_ADDR_0BITS 0
> > +#define SFC_CMD_ADDR_24BITS 1
> > +#define SFC_CMD_ADDR_32BITS 2
> > +#define SFC_CMD_ADDR_XBITS 3
> > +#define SFC_CMD_TRAN_BYTES_SHIFT 16
> > +#define SFC_CMD_CS_SHIFT 30
> > +
> > +/* Address */
> > +#define SFC_ADDR 0x104
> > +
> > +/* Data */
> > +#define SFC_DATA 0x108
> > +
> > +/* The controller and documentation reports that it supports up to 4 CS
> > + * devices (0-3), however I have only been able to test a single CS (CS 0)
> > + * due to the configuration of my device.
> > + */
> > +#define SFC_MAX_CHIPSELECT_NUM 4
> > +
> > +/* The SFC can transfer max 16KB - 1 at one time
> > + * we set it to 15.5KB here for alignment.
> > + */
> > +#define SFC_MAX_IOSIZE_VER3 (512 * 31)
> > +
> > +#define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
> > +
> > +/* DMA is only enabled for large data transmission */
> > +#define SFC_DMA_TRANS_THRETHOLD (0x40)
> > +
> > +/* Maximum clock values from datasheet suggest keeping clock value under
> > + * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
> > + * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
> > + */
> > +#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
> > +#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
> > +#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
> > +
> > +struct rockchip_sfc {
> > + void __iomem *regbase;
> > + struct clk hclk;
> > + struct clk clk;
> > + u32 max_freq;
> > + u32 speed;
> > + bool use_dma;
> > + u32 max_iosize;
> > + u16 version;
> > +};
> > +
> > +static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
> > +{
> > + int err;
> > + u32 status;
> > +
> > + writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
> > +
> > + err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
> > + !(status & SFC_RCVR_RESET),
> > + 1000000);
> > + if (err)
> > + printf("SFC reset never finished\n");
> > +
> > + /* Still need to clear the masked interrupt from RISR */
> > + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> > +
> > + debug("reset\n");
>
> Unneeded debug.
>
> > +
> > + return err;
> > +}
> > +
> > +static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
> > +{
> > + return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
> > +}
> > +
> > +static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
> > +{
> > + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
> > + return SFC_MAX_IOSIZE_VER4;
> > +
> > + return SFC_MAX_IOSIZE_VER3;
> > +}
> > +
> > +static int rockchip_sfc_init(struct rockchip_sfc *sfc)
> > +{
> > + writel(0, sfc->regbase + SFC_CTRL);
> > + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
> > + writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
> > +
> > + return 0;
> > +}
> > +
> > +static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
> > +{
> > + struct rockchip_sfc *sfc = dev_get_plat(bus);
> > +
> > + sfc->regbase = dev_read_addr_ptr(bus);
> > + if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
> > + sfc->use_dma = false;
> > + else
> > + sfc->use_dma = true;
> > +
> > +#if CONFIG_IS_ENABLED(CLK)
>
> Better drop this as rockchip by default support DM_CLK.
>
> > + int ret;
> > +
> > + ret = clk_get_by_index(bus, 0, &sfc->clk);
> > + if (ret < 0) {
> > + printf("Could not get clock for %s: %d\n", bus->name, ret);
> > + return ret;
> > + }
> > +
> > + ret = clk_get_by_index(bus, 1, &sfc->hclk);
> > + if (ret < 0) {
> > + printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
> > + return ret;
> > + }
> > +#endif
> > +
> > + return 0;
> > +}
> > +
> > +static int rockchip_sfc_probe(struct udevice *bus)
> > +{
> > + struct rockchip_sfc *sfc = dev_get_plat(bus);
> > + int ret;
> > +
> > +#if CONFIG_IS_ENABLED(CLK)
> > + ret = clk_enable(&sfc->hclk);
> > + if (ret)
> > + debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
> > +
> > + ret = clk_enable(&sfc->clk);
> > + if (ret)
> > + debug("Enable clock fail for %s: %d\n", bus->name, ret);
> > +
> > + ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ);
> > + if (ret)
> > + debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
> > +#endif
> > +
> > + ret = rockchip_sfc_init(sfc);
> > + if (ret)
> > + goto err_init;
> > +
> > + sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
> > + sfc->version = rockchip_sfc_get_version(sfc);
> > + sfc->speed = SFC_DEFAULT_SPEED_HZ;
>
> Why this default speed? better get it from set_speed and use.
Honestly because that's how it was set up in the BSP U-Boot
implementation.
>
> > +
> > + return 0;
> > +
> > +err_init:
> > +#if CONFIG_IS_ENABLED(CLK)
> > + clk_disable(&sfc->clk);
> > + clk_disable(&sfc->hclk);
> > +#endif
> > +
> > + return ret;
> > +}
> > +
> > +static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr)
> > +{
> > + u32 fsr = readl(sfc->regbase + SFC_FSR);
> > + int level;
> > +
> > + if (wr)
> > + level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
> > + else
> > + level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
> > +
> > + return level;
>
> Please simplify by using set/clr bit API's
>
> > +}
> > +
> > +static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout)
> > +{
> > + unsigned long tbase = get_timer(0);
> > + int level;
> > +
> > + while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) {
> > + if (get_timer(tbase) > timeout) {
> > + debug("%s fifo timeout\n", wr ? "write" : "read");
> > + return -ETIMEDOUT;
> > + }
> > + udelay(1);
> > + }
>
> Use readpoll.
>
> > +
> > + return level;
> > +}
> > +
> > +static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
> > +{
> > + if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
> > + /*
> > + * SFC not support output DUMMY cycles right after CMD cycles, so
> > + * treat it as ADDR cycles.
> > + */
> > + op->addr.nbytes = op->dummy.nbytes;
> > + op->addr.buswidth = op->dummy.buswidth;
> > + op->addr.val = 0xFFFFFFFFF;
> > +
> > + op->dummy.nbytes = 0;
> > + }
> > +}
> > +
> > +static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout)
> > +{
> > + unsigned long tbase;
> > +
> > + /* Wait for the DMA interrupt status */
> > + tbase = get_timer(0);
> > + while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) {
> > + if (get_timer(tbase) > timeout) {
> > + printf("dma timeout\n");
> > + rockchip_sfc_reset(sfc);
> > +
> > + return -ETIMEDOUT;
> > + }
> > +
>
> Use readpoll.
>
> > + udelay(1);
> > + }
> > +
> > + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> > +
> > + return 0;
> > +}
> > +
> > +static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
> > + struct spi_slave *mem,
> > + const struct spi_mem_op *op,
> > + u32 len)
> > +{
> > + struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
> > + u32 ctrl = 0, cmd = 0;
> > +
> > + /* set CMD */
> > + cmd = op->cmd.opcode;
> > + ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
> > +
> > + /* set ADDR */
> > + if (op->addr.nbytes) {
> > + if (op->addr.nbytes == 4) {
> > + cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
> > + } else if (op->addr.nbytes == 3) {
> > + cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
> > + } else {
> > + cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
> > + writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
> > + }
> > +
> > + ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
> > + }
> > +
> > + /* set DUMMY */
> > + if (op->dummy.nbytes) {
> > + if (op->dummy.buswidth == 4)
> > + cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
> > + else if (op->dummy.buswidth == 2)
> > + cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
> > + else
> > + cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
> > + }
> > +
> > + /* set DATA */
> > + if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
> > + writel(len, sfc->regbase + SFC_LEN_EXT);
> > + else
> > + cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
> > + if (len) {
> > + if (op->data.dir == SPI_MEM_DATA_OUT)
> > + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
> > +
> > + ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
> > + }
> > + if (!len && op->addr.nbytes)
> > + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
> > +
> > + /* set the Controller */
> > + ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
> > + cmd |= plat->cs << SFC_CMD_CS_SHIFT;
> > +
> > + debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
> > + op->addr.nbytes, op->addr.buswidth,
> > + op->dummy.nbytes, op->dummy.buswidth);
> > + debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
> > + ctrl, cmd, op->addr.val, len);
>
> Not sure these debugs, we have in spi-mem driver.
>
> > +
> > + writel(ctrl, sfc->regbase + SFC_CTRL);
> > + writel(cmd, sfc->regbase + SFC_CMD);
> > + if (op->addr.nbytes)
> > + writel(op->addr.val, sfc->regbase + SFC_ADDR);
> > +
> > + return 0;
> > +}
> > +
> > +static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
> > +{
> > + u8 bytes = len & 0x3;
> > + u32 dwords;
> > + int tx_level;
> > + u32 write_words;
> > + u32 tmp = 0;
> > +
> > + dwords = len >> 2;
> > + while (dwords) {
> > + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
> > + if (tx_level < 0)
> > + return tx_level;
> > + write_words = min_t(u32, tx_level, dwords);
> > + writesl(sfc->regbase + SFC_DATA, buf, write_words);
> > + buf += write_words << 2;
> > + dwords -= write_words;
> > + }
> > +
> > + /* write the rest non word aligned bytes */
> > + if (bytes) {
> > + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
> > + if (tx_level < 0)
> > + return tx_level;
> > + memcpy(&tmp, buf, bytes);
> > + writel(tmp, sfc->regbase + SFC_DATA);
> > + }
> > +
> > + return len;
> > +}
> > +
> > +static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
> > +{
> > + u8 bytes = len & 0x3;
> > + u32 dwords;
> > + u8 read_words;
> > + int rx_level;
> > + int tmp;
> > +
> > + /* word aligned access only */
> > + dwords = len >> 2;
> > + while (dwords) {
> > + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
> > + if (rx_level < 0)
> > + return rx_level;
> > + read_words = min_t(u32, rx_level, dwords);
> > + readsl(sfc->regbase + SFC_DATA, buf, read_words);
> > + buf += read_words << 2;
> > + dwords -= read_words;
> > + }
> > +
> > + /* read the rest non word aligned bytes */
> > + if (bytes) {
> > + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
> > + if (rx_level < 0)
> > + return rx_level;
> > + tmp = readl(sfc->regbase + SFC_DATA);
> > + memcpy(buf, &tmp, bytes);
> > + }
> > +
> > + return len;
> > +}
> > +
> > +static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
> > +{
> > + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> > + writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
> > + writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
>
> Please use associated BIT names instead of magic numbers.
>
> > +
> > + return len;
> > +}
> > +
> > +static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
> > + const struct spi_mem_op *op, u32 len)
> > +{
> > + debug("xfer_poll len=%x\n", len);
> > +
> > + if (op->data.dir == SPI_MEM_DATA_OUT)
> > + return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
> > + else
> > + return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
> > +}
> > +
> > +static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
> > + const struct spi_mem_op *op, u32 len)
> > +{
> > + struct bounce_buffer bb;
> > + unsigned int bb_flags;
> > + void *dma_buf;
> > + int ret;
> > +
> > + debug("xfer_dma len=%x\n", len);
> > +
> > + if (op->data.dir == SPI_MEM_DATA_OUT) {
> > + dma_buf = (void *)op->data.buf.out;
> > + bb_flags = GEN_BB_READ;
> > + } else {
> > + dma_buf = (void *)op->data.buf.in;
> > + bb_flags = GEN_BB_WRITE;
> > + }
> > +
> > + ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags);
> > + if (ret)
> > + return ret;
> > +
> > + ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len);
> > + rockchip_sfc_wait_for_dma_finished(sfc, len * 10);
> > + bounce_buffer_stop(&bb);
> > +
> > + return ret;
> > +}
> > +
> > +static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
> > +{
> > + unsigned long tbase = get_timer(0);
> > + int ret = 0;
> > + u32 timeout = timeout_us;
> > +
> > + while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) {
> > + if (get_timer(tbase) > timeout) {
> > + printf("wait sfc idle timeout\n");
> > + rockchip_sfc_reset(sfc);
> > +
> > + return -ETIMEDOUT;
> > + }
> > +
> > + udelay(1);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static int rockchip_sfc_exec_op(struct spi_slave *mem,
> > + const struct spi_mem_op *op)
> > +{
> > + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
> > + u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
> > + int ret;
> > +
> > +#if CONFIG_IS_ENABLED(CLK)
> > + if (unlikely(mem->max_hz != sfc->speed)) {
> > + ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
> > + (uint)SFC_MAX_SPEED_HZ));
> > + if (ret < 0) {
> > + printf("set_freq=%dHz fail, check if it's the cru support level\n",
> > + mem->max_hz);
> > + return ret;
> > + }
> > +
> > + sfc->max_freq = mem->max_hz;
> > + sfc->speed = mem->max_hz;
> > + debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed);
> > + }
> > +#endif
> > +
> > + rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
> > +
> > + rockchip_sfc_xfer_setup(sfc, mem, op, len);
> > + if (len) {
> > + if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD)
>
> This seems confusing, please simply if possible.
Sorry. Basically this is telling the driver to use DMA mode when 3
conditions are met. DMA is not explicitly disabled, the length is word
aligned, and the size is greater than the DMA threshold. These checks
are in place because this driver needs to disable DMA for SPL mode (or
else A-TF doesn't work properly), it can only do word aligned
transfers in DMA mode, and (Jon will need to correct me if I'm wrong)
the overhead of setting up a DMA transfer is not worth it if the bytes
to be transferred are below a certain threshold.
>
> > + ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
> > + else
> > + ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
> > +
> > + if (ret != len) {
> > + printf("xfer data failed ret %d dir %d\n", ret, op->data.dir);
> > +
> > + return -EIO;
> > + }
> > + }
> > +
> > + return rockchip_sfc_xfer_done(sfc, 100000);
> > +}
> > +
> > +static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op)
> > +{
> > + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
> > +
> > + op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
> > + return 0;
> > +}
> > +
> > +static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
> > +{
> > + /* We set up speed later for each transmission.
> > + */
> > + return 0;
>
> This is the best place to alter speed instead of probe or other.
>
> Thanks,
> Jagan.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance
2021-08-05 8:27 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Jon Lin
2021-08-05 8:27 ` [PATCH v7 6/6] rockchip: px30: Support configure SFC Jon Lin
@ 2021-08-05 17:32 ` Chris Morgan
2021-08-11 10:20 ` Kever Yang
2 siblings, 0 replies; 23+ messages in thread
From: Chris Morgan @ 2021-08-05 17:32 UTC (permalink / raw)
To: Jon Lin
Cc: u-boot, heiko.stuebner, vigneshr, jagan, kever.yang,
philipp.tomsich, sjg
On Thu, Aug 05, 2021 at 04:27:52PM +0800, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
> XT25F128B SPI NOR flash chip. This adds support for both. Note that
> while both the controller and chip support quad mode, only two lines
> are connected to the chip. Changing the pinctrl to bus2 and setting tx
> and rx lines to 2 for this reason.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> ---
>
> (no changes since v1)
>
> arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 +++++++++++++++++
> arch/arm/dts/rk3326-odroid-go2.dts | 16 ++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> index 00767d2abd..741e8dd935 100644
> --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> @@ -7,6 +7,15 @@
> chosen {
> u-boot,spl-boot-order = &sdmmc;
> };
> +
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + mmc0 = &sdmmc;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + spi0 = &sfc;
> + };
> };
>
> &cru {
> @@ -57,6 +66,14 @@
> u-boot,spl-fifo-mode;
> };
>
> +&sfc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&spi_flash {
> + u-boot,dm-pre-reloc;
> +};
See comments below. If we change that devicetree node to match upstream
linux proposed patch, we'll need to change this to the following:
&{/sfc@ff3a0000/flash@0} {
u-boot,dm-pre-reloc;
};
> +
> &uart1 {
> clock-frequency = <24000000>;
> u-boot,dm-pre-reloc;
> diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
> index 8cd4688c49..6f91f5040b 100644
> --- a/arch/arm/dts/rk3326-odroid-go2.dts
> +++ b/arch/arm/dts/rk3326-odroid-go2.dts
> @@ -617,6 +617,22 @@
> status = "okay";
> };
>
> +&sfc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
> + status = "okay";
> +
> + spi_flash: xt25f128b@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <108000000>;
> + spi-rx-bus-width = <2>;
> + spi-tx-bus-width = <2>;
> + };
Let's add support for this exactly how we have it queued up for the
mainline kernel. I've tested the following devicetree configuration
and it works for me. For anyone else reading, note that in Linux
the chip fails if the spi-tx-bus-width is set to 2 but not 1,
there seems to be something implementation specific for the OGA
that requires this setting. U-Boot is not affected, however,
but setting it here anyway to match upstream Linux is wise. Jon
could not reproduce the issue on his px30 based hardware, but
I could always reproduce the issue on my Odroid Go Advance.
&sfc {
pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <108000000>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <1>;
};
};
> +};
> +
> &tsadc {
> status = "okay";
> };
> --
> 2.17.1
>
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 1/6] spi: rockchip_sfc: add support for Rockchip SFC
2021-08-05 8:26 ` [PATCH v7 1/6] spi: " Jon Lin
2021-08-05 11:26 ` Jagan Teki
@ 2021-08-11 10:19 ` Kever Yang
2021-08-11 10:26 ` Philipp Tomsich
2 siblings, 0 replies; 23+ messages in thread
From: Kever Yang @ 2021-08-11 10:19 UTC (permalink / raw)
To: Jon Lin, u-boot
Cc: heiko.stuebner, vigneshr, jagan, philipp.tomsich, sjg, macromorgan
On 2021/8/5 下午4:26, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> This patch adds support for the Rockchip serial flash controller
> found on the PX30 SoC. It should work for versions 3-5 of the SFC
> IP, however I am only able to test it on v3.
>
> This is adapted from the WIP SPI-MEM driver for the SFC on mainline
> Linux. Note that the main difference between this and earlier versions
> of the driver is that this one does not support DMA. In testing
> the performance difference (performing a dual mode read on a 128Mb
> chip) is negligible. DMA, if used, must also be disabled in SPL
> mode when using A-TF anyway.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
>
> Changes in v7:
> - Make sfc-use-dma configurable
>
> Changes in v6:
> - Fix dma transfer logic
> - Fix the error of the way to wait for dma transfer finished status
>
> Changes in v5:
> - Support dma transfer
> - Add CONFIG_IS_ENABLED(CLK) limitation
> - Support spinand devices
> - Support SFC ver4 ver5
> - Using "rockchip, sfc" as compatible id
> - Get clock from the index to compatible with those case which's
> clock-names is not parsed
>
> Changes in v4:
> - None
>
> Changes in v3:
> - Added "rockchip_sfc_adjust_op_work()" function from proposed Linux
> driver to fix potential issue on hardware. Note I never noticed
> this issue while testing, so I cannot test if it fixed any specific
> issue for me.
> - Updated of-compatible string back to "rockchip,sfc" to match what
> is currently proposed for upstream driver. The hardware itself
> has multiple versions but a register is present in the hardware that
> is read by the driver to set version specific functionality.
> - Updated px30.dtsi and rk3266-odroid-go2.dts device-trees so that
> sfc nodes match what is in upstream.
>
> Changes in v2:
> - Resending due to glitch with patch file truncating final two lines
> on patch 1/5 and incorrect patch version number on patch 5/5.
>
> Changes in v1:
> - Reworked code to utilize spi-mem framework, and based it closely
> off of work in progress code for mainline Linux.
> - Removed DMA, as it didn't offer much performance benefit for
> booting (in my test cases), added complexity to the code, and
> interfered with A-TF.
> - Updated the names of the bindings to match the work in progress
> Linux code.
> - Moved alias to u-boot specific device-tree for Odroid Go Advance.
> Alias is updated with the spi0 node pointing to the SFC to
> help the sf command as well as facilitate booting from the SFC.
> - Note 2 below no longer applies, as rebasing this off of upstream
> code should allow the device to work for NAND, and by utilizing
> the spi-mem framework it no longer has to extract the parameters
>
> drivers/spi/Kconfig | 8 +
> drivers/spi/Makefile | 1 +
> drivers/spi/rockchip_sfc.c | 646 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 655 insertions(+)
> create mode 100644 drivers/spi/rockchip_sfc.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 5c2a60a214..e12699bec7 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -319,6 +319,14 @@ config RENESAS_RPC_SPI
> on Renesas RCar Gen3 SoCs. This uses driver model and requires a
> device tree binding to operate.
>
> +config ROCKCHIP_SFC
> + bool "Rockchip SFC Driver"
> + help
> + Enable the Rockchip SFC Driver for SPI NOR flash. This device is
> + a limited purpose SPI controller for driving NOR flash on certain
> + Rockchip SoCs. This uses driver model and requires a device tree
> + binding to operate.
> +
> config ROCKCHIP_SPI
> bool "Rockchip SPI driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 216e72c60f..d2f24bccef 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -54,6 +54,7 @@ obj-$(CONFIG_PL022_SPI) += pl022_spi.o
> obj-$(CONFIG_SPI_QUP) += spi-qup.o
> obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
> obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
> +obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o
> obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
> obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
> obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
> diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
> new file mode 100644
> index 0000000000..4e2b861f22
> --- /dev/null
> +++ b/drivers/spi/rockchip_sfc.c
> @@ -0,0 +1,646 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Rockchip Serial Flash Controller Driver
> + *
> + * Copyright (c) 2017-2021, Rockchip Inc.
> + * Author: Shawn Lin <shawn.lin@rock-chips.com>
> + * Chris Morgan <macromorgan@hotmail.com>
> + * Jon Lin <Jon.lin@rock-chips.com>
> + */
> +
> +#include <asm/io.h>
> +#include <bouncebuf.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/iopoll.h>
> +#include <spi.h>
> +#include <spi-mem.h>
> +
> +/* System control */
> +#define SFC_CTRL 0x0
> +#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
> +#define SFC_CTRL_CMD_BITS_SHIFT 8
> +#define SFC_CTRL_ADDR_BITS_SHIFT 10
> +#define SFC_CTRL_DATA_BITS_SHIFT 12
> +
> +/* Interrupt mask */
> +#define SFC_IMR 0x4
> +#define SFC_IMR_RX_FULL BIT(0)
> +#define SFC_IMR_RX_UFLOW BIT(1)
> +#define SFC_IMR_TX_OFLOW BIT(2)
> +#define SFC_IMR_TX_EMPTY BIT(3)
> +#define SFC_IMR_TRAN_FINISH BIT(4)
> +#define SFC_IMR_BUS_ERR BIT(5)
> +#define SFC_IMR_NSPI_ERR BIT(6)
> +#define SFC_IMR_DMA BIT(7)
> +
> +/* Interrupt clear */
> +#define SFC_ICLR 0x8
> +#define SFC_ICLR_RX_FULL BIT(0)
> +#define SFC_ICLR_RX_UFLOW BIT(1)
> +#define SFC_ICLR_TX_OFLOW BIT(2)
> +#define SFC_ICLR_TX_EMPTY BIT(3)
> +#define SFC_ICLR_TRAN_FINISH BIT(4)
> +#define SFC_ICLR_BUS_ERR BIT(5)
> +#define SFC_ICLR_NSPI_ERR BIT(6)
> +#define SFC_ICLR_DMA BIT(7)
> +
> +/* FIFO threshold level */
> +#define SFC_FTLR 0xc
> +#define SFC_FTLR_TX_SHIFT 0
> +#define SFC_FTLR_TX_MASK 0x1f
> +#define SFC_FTLR_RX_SHIFT 8
> +#define SFC_FTLR_RX_MASK 0x1f
> +
> +/* Reset FSM and FIFO */
> +#define SFC_RCVR 0x10
> +#define SFC_RCVR_RESET BIT(0)
> +
> +/* Enhanced mode */
> +#define SFC_AX 0x14
> +
> +/* Address Bit number */
> +#define SFC_ABIT 0x18
> +
> +/* Interrupt status */
> +#define SFC_ISR 0x1c
> +#define SFC_ISR_RX_FULL_SHIFT BIT(0)
> +#define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
> +#define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
> +#define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
> +#define SFC_ISR_TX_FINISH_SHIFT BIT(4)
> +#define SFC_ISR_BUS_ERR_SHIFT BIT(5)
> +#define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
> +#define SFC_ISR_DMA_SHIFT BIT(7)
> +
> +/* FIFO status */
> +#define SFC_FSR 0x20
> +#define SFC_FSR_TX_IS_FULL BIT(0)
> +#define SFC_FSR_TX_IS_EMPTY BIT(1)
> +#define SFC_FSR_RX_IS_EMPTY BIT(2)
> +#define SFC_FSR_RX_IS_FULL BIT(3)
> +#define SFC_FSR_TXLV_MASK GENMASK(12, 8)
> +#define SFC_FSR_TXLV_SHIFT 8
> +#define SFC_FSR_RXLV_MASK GENMASK(20, 16)
> +#define SFC_FSR_RXLV_SHIFT 16
> +
> +/* FSM status */
> +#define SFC_SR 0x24
> +#define SFC_SR_IS_IDLE 0x0
> +#define SFC_SR_IS_BUSY 0x1
> +
> +/* Raw interrupt status */
> +#define SFC_RISR 0x28
> +#define SFC_RISR_RX_FULL BIT(0)
> +#define SFC_RISR_RX_UNDERFLOW BIT(1)
> +#define SFC_RISR_TX_OVERFLOW BIT(2)
> +#define SFC_RISR_TX_EMPTY BIT(3)
> +#define SFC_RISR_TRAN_FINISH BIT(4)
> +#define SFC_RISR_BUS_ERR BIT(5)
> +#define SFC_RISR_NSPI_ERR BIT(6)
> +#define SFC_RISR_DMA BIT(7)
> +
> +/* Version */
> +#define SFC_VER 0x2C
> +#define SFC_VER_3 0x3
> +#define SFC_VER_4 0x4
> +#define SFC_VER_5 0x5
> +
> +/* Delay line controller resiter */
> +#define SFC_DLL_CTRL0 0x3C
> +#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
> +#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU
> +#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU
> +
> +/* Master trigger */
> +#define SFC_DMA_TRIGGER 0x80
> +
> +/* Src or Dst addr for master */
> +#define SFC_DMA_ADDR 0x84
> +
> +/* Length control register extension 32GB */
> +#define SFC_LEN_CTRL 0x88
> +#define SFC_LEN_CTRL_TRB_SEL 1
> +#define SFC_LEN_EXT 0x8C
> +
> +/* Command */
> +#define SFC_CMD 0x100
> +#define SFC_CMD_IDX_SHIFT 0
> +#define SFC_CMD_DUMMY_SHIFT 8
> +#define SFC_CMD_DIR_SHIFT 12
> +#define SFC_CMD_DIR_RD 0
> +#define SFC_CMD_DIR_WR 1
> +#define SFC_CMD_ADDR_SHIFT 14
> +#define SFC_CMD_ADDR_0BITS 0
> +#define SFC_CMD_ADDR_24BITS 1
> +#define SFC_CMD_ADDR_32BITS 2
> +#define SFC_CMD_ADDR_XBITS 3
> +#define SFC_CMD_TRAN_BYTES_SHIFT 16
> +#define SFC_CMD_CS_SHIFT 30
> +
> +/* Address */
> +#define SFC_ADDR 0x104
> +
> +/* Data */
> +#define SFC_DATA 0x108
> +
> +/* The controller and documentation reports that it supports up to 4 CS
> + * devices (0-3), however I have only been able to test a single CS (CS 0)
> + * due to the configuration of my device.
> + */
> +#define SFC_MAX_CHIPSELECT_NUM 4
> +
> +/* The SFC can transfer max 16KB - 1 at one time
> + * we set it to 15.5KB here for alignment.
> + */
> +#define SFC_MAX_IOSIZE_VER3 (512 * 31)
> +
> +#define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
> +
> +/* DMA is only enabled for large data transmission */
> +#define SFC_DMA_TRANS_THRETHOLD (0x40)
> +
> +/* Maximum clock values from datasheet suggest keeping clock value under
> + * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
> + * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
> + */
> +#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
> +#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
> +#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
> +
> +struct rockchip_sfc {
> + void __iomem *regbase;
> + struct clk hclk;
> + struct clk clk;
> + u32 max_freq;
> + u32 speed;
> + bool use_dma;
> + u32 max_iosize;
> + u16 version;
> +};
> +
> +static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
> +{
> + int err;
> + u32 status;
> +
> + writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
> +
> + err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
> + !(status & SFC_RCVR_RESET),
> + 1000000);
> + if (err)
> + printf("SFC reset never finished\n");
> +
> + /* Still need to clear the masked interrupt from RISR */
> + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> +
> + debug("reset\n");
> +
> + return err;
> +}
> +
> +static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
> +{
> + return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
> +}
> +
> +static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
> +{
> + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
> + return SFC_MAX_IOSIZE_VER4;
> +
> + return SFC_MAX_IOSIZE_VER3;
> +}
> +
> +static int rockchip_sfc_init(struct rockchip_sfc *sfc)
> +{
> + writel(0, sfc->regbase + SFC_CTRL);
> + if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
> + writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
> +
> + return 0;
> +}
> +
> +static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
> +{
> + struct rockchip_sfc *sfc = dev_get_plat(bus);
> +
> + sfc->regbase = dev_read_addr_ptr(bus);
> + if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
> + sfc->use_dma = false;
> + else
> + sfc->use_dma = true;
> +
> +#if CONFIG_IS_ENABLED(CLK)
> + int ret;
> +
> + ret = clk_get_by_index(bus, 0, &sfc->clk);
> + if (ret < 0) {
> + printf("Could not get clock for %s: %d\n", bus->name, ret);
> + return ret;
> + }
> +
> + ret = clk_get_by_index(bus, 1, &sfc->hclk);
> + if (ret < 0) {
> + printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
> + return ret;
> + }
> +#endif
> +
> + return 0;
> +}
> +
> +static int rockchip_sfc_probe(struct udevice *bus)
> +{
> + struct rockchip_sfc *sfc = dev_get_plat(bus);
> + int ret;
> +
> +#if CONFIG_IS_ENABLED(CLK)
> + ret = clk_enable(&sfc->hclk);
> + if (ret)
> + debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
> +
> + ret = clk_enable(&sfc->clk);
> + if (ret)
> + debug("Enable clock fail for %s: %d\n", bus->name, ret);
> +
> + ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ);
> + if (ret)
> + debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
> +#endif
> +
> + ret = rockchip_sfc_init(sfc);
> + if (ret)
> + goto err_init;
> +
> + sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
> + sfc->version = rockchip_sfc_get_version(sfc);
> + sfc->speed = SFC_DEFAULT_SPEED_HZ;
> +
> + return 0;
> +
> +err_init:
> +#if CONFIG_IS_ENABLED(CLK)
> + clk_disable(&sfc->clk);
> + clk_disable(&sfc->hclk);
> +#endif
> +
> + return ret;
> +}
> +
> +static inline int rockchip_sfc_get_fifo_level(struct rockchip_sfc *sfc, int wr)
> +{
> + u32 fsr = readl(sfc->regbase + SFC_FSR);
> + int level;
> +
> + if (wr)
> + level = (fsr & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
> + else
> + level = (fsr & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
> +
> + return level;
> +}
> +
> +static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int wr, u32 timeout)
> +{
> + unsigned long tbase = get_timer(0);
> + int level;
> +
> + while (!(level = rockchip_sfc_get_fifo_level(sfc, wr))) {
> + if (get_timer(tbase) > timeout) {
> + debug("%s fifo timeout\n", wr ? "write" : "read");
> + return -ETIMEDOUT;
> + }
> + udelay(1);
> + }
> +
> + return level;
> +}
> +
> +static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
> +{
> + if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
> + /*
> + * SFC not support output DUMMY cycles right after CMD cycles, so
> + * treat it as ADDR cycles.
> + */
> + op->addr.nbytes = op->dummy.nbytes;
> + op->addr.buswidth = op->dummy.buswidth;
> + op->addr.val = 0xFFFFFFFFF;
> +
> + op->dummy.nbytes = 0;
> + }
> +}
> +
> +static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout)
> +{
> + unsigned long tbase;
> +
> + /* Wait for the DMA interrupt status */
> + tbase = get_timer(0);
> + while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) {
> + if (get_timer(tbase) > timeout) {
> + printf("dma timeout\n");
> + rockchip_sfc_reset(sfc);
> +
> + return -ETIMEDOUT;
> + }
> +
> + udelay(1);
> + }
> +
> + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> +
> + return 0;
> +}
> +
> +static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
> + struct spi_slave *mem,
> + const struct spi_mem_op *op,
> + u32 len)
> +{
> + struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
> + u32 ctrl = 0, cmd = 0;
> +
> + /* set CMD */
> + cmd = op->cmd.opcode;
> + ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
> +
> + /* set ADDR */
> + if (op->addr.nbytes) {
> + if (op->addr.nbytes == 4) {
> + cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
> + } else if (op->addr.nbytes == 3) {
> + cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
> + } else {
> + cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
> + writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
> + }
> +
> + ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
> + }
> +
> + /* set DUMMY */
> + if (op->dummy.nbytes) {
> + if (op->dummy.buswidth == 4)
> + cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
> + else if (op->dummy.buswidth == 2)
> + cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
> + else
> + cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
> + }
> +
> + /* set DATA */
> + if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
> + writel(len, sfc->regbase + SFC_LEN_EXT);
> + else
> + cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
> + if (len) {
> + if (op->data.dir == SPI_MEM_DATA_OUT)
> + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
> +
> + ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
> + }
> + if (!len && op->addr.nbytes)
> + cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
> +
> + /* set the Controller */
> + ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
> + cmd |= plat->cs << SFC_CMD_CS_SHIFT;
> +
> + debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
> + op->addr.nbytes, op->addr.buswidth,
> + op->dummy.nbytes, op->dummy.buswidth);
> + debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
> + ctrl, cmd, op->addr.val, len);
> +
> + writel(ctrl, sfc->regbase + SFC_CTRL);
> + writel(cmd, sfc->regbase + SFC_CMD);
> + if (op->addr.nbytes)
> + writel(op->addr.val, sfc->regbase + SFC_ADDR);
> +
> + return 0;
> +}
> +
> +static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
> +{
> + u8 bytes = len & 0x3;
> + u32 dwords;
> + int tx_level;
> + u32 write_words;
> + u32 tmp = 0;
> +
> + dwords = len >> 2;
> + while (dwords) {
> + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
> + if (tx_level < 0)
> + return tx_level;
> + write_words = min_t(u32, tx_level, dwords);
> + writesl(sfc->regbase + SFC_DATA, buf, write_words);
> + buf += write_words << 2;
> + dwords -= write_words;
> + }
> +
> + /* write the rest non word aligned bytes */
> + if (bytes) {
> + tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_WR, 1000);
> + if (tx_level < 0)
> + return tx_level;
> + memcpy(&tmp, buf, bytes);
> + writel(tmp, sfc->regbase + SFC_DATA);
> + }
> +
> + return len;
> +}
> +
> +static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
> +{
> + u8 bytes = len & 0x3;
> + u32 dwords;
> + u8 read_words;
> + int rx_level;
> + int tmp;
> +
> + /* word aligned access only */
> + dwords = len >> 2;
> + while (dwords) {
> + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
> + if (rx_level < 0)
> + return rx_level;
> + read_words = min_t(u32, rx_level, dwords);
> + readsl(sfc->regbase + SFC_DATA, buf, read_words);
> + buf += read_words << 2;
> + dwords -= read_words;
> + }
> +
> + /* read the rest non word aligned bytes */
> + if (bytes) {
> + rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_CMD_DIR_RD, 1000);
> + if (rx_level < 0)
> + return rx_level;
> + tmp = readl(sfc->regbase + SFC_DATA);
> + memcpy(buf, &tmp, bytes);
> + }
> +
> + return len;
> +}
> +
> +static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
> +{
> + writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
> + writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
> + writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
> +
> + return len;
> +}
> +
> +static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
> + const struct spi_mem_op *op, u32 len)
> +{
> + debug("xfer_poll len=%x\n", len);
> +
> + if (op->data.dir == SPI_MEM_DATA_OUT)
> + return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
> + else
> + return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
> +}
> +
> +static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
> + const struct spi_mem_op *op, u32 len)
> +{
> + struct bounce_buffer bb;
> + unsigned int bb_flags;
> + void *dma_buf;
> + int ret;
> +
> + debug("xfer_dma len=%x\n", len);
> +
> + if (op->data.dir == SPI_MEM_DATA_OUT) {
> + dma_buf = (void *)op->data.buf.out;
> + bb_flags = GEN_BB_READ;
> + } else {
> + dma_buf = (void *)op->data.buf.in;
> + bb_flags = GEN_BB_WRITE;
> + }
> +
> + ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags);
> + if (ret)
> + return ret;
> +
> + ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len);
> + rockchip_sfc_wait_for_dma_finished(sfc, len * 10);
> + bounce_buffer_stop(&bb);
> +
> + return ret;
> +}
> +
> +static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
> +{
> + unsigned long tbase = get_timer(0);
> + int ret = 0;
> + u32 timeout = timeout_us;
> +
> + while (readl(sfc->regbase + SFC_SR) & SFC_SR_IS_BUSY) {
> + if (get_timer(tbase) > timeout) {
> + printf("wait sfc idle timeout\n");
> + rockchip_sfc_reset(sfc);
> +
> + return -ETIMEDOUT;
> + }
> +
> + udelay(1);
> + }
> +
> + return ret;
> +}
> +
> +static int rockchip_sfc_exec_op(struct spi_slave *mem,
> + const struct spi_mem_op *op)
> +{
> + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
> + u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
> + int ret;
> +
> +#if CONFIG_IS_ENABLED(CLK)
> + if (unlikely(mem->max_hz != sfc->speed)) {
> + ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
> + (uint)SFC_MAX_SPEED_HZ));
> + if (ret < 0) {
> + printf("set_freq=%dHz fail, check if it's the cru support level\n",
> + mem->max_hz);
> + return ret;
> + }
> +
> + sfc->max_freq = mem->max_hz;
> + sfc->speed = mem->max_hz;
> + debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed);
> + }
> +#endif
> +
> + rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
> +
> + rockchip_sfc_xfer_setup(sfc, mem, op, len);
> + if (len) {
> + if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD)
> + ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
> + else
> + ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
> +
> + if (ret != len) {
> + printf("xfer data failed ret %d dir %d\n", ret, op->data.dir);
> +
> + return -EIO;
> + }
> + }
> +
> + return rockchip_sfc_xfer_done(sfc, 100000);
> +}
> +
> +static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op)
> +{
> + struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
> +
> + op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
> + return 0;
> +}
> +
> +static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
> +{
> + /* We set up speed later for each transmission.
> + */
> + return 0;
> +}
> +
> +static int rockchip_sfc_set_mode(struct udevice *bus, uint mode)
> +{
> + return 0;
> +}
> +
> +static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
> + .adjust_op_size = rockchip_sfc_adjust_op_size,
> + .exec_op = rockchip_sfc_exec_op,
> +};
> +
> +static const struct dm_spi_ops rockchip_sfc_ops = {
> + .mem_ops = &rockchip_sfc_mem_ops,
> + .set_speed = rockchip_sfc_set_speed,
> + .set_mode = rockchip_sfc_set_mode,
> +};
> +
> +static const struct udevice_id rockchip_sfc_ids[] = {
> + { .compatible = "rockchip,sfc"},
> + {},
> +};
> +
> +U_BOOT_DRIVER(rockchip_sfc_driver) = {
> + .name = "rockchip_sfc",
> + .id = UCLASS_SPI,
> + .of_match = rockchip_sfc_ids,
> + .ops = &rockchip_sfc_ops,
> + .of_to_plat = rockchip_sfc_ofdata_to_platdata,
> + .plat_auto = sizeof(struct rockchip_sfc),
> + .probe = rockchip_sfc_probe,
> +};
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 2/6] rockchip: px30: Add support for using SFC
2021-08-05 8:26 ` [PATCH v7 2/6] rockchip: px30: Add support for using SFC Jon Lin
@ 2021-08-11 10:19 ` Kever Yang
0 siblings, 0 replies; 23+ messages in thread
From: Kever Yang @ 2021-08-11 10:19 UTC (permalink / raw)
To: Jon Lin, u-boot
Cc: heiko.stuebner, vigneshr, jagan, philipp.tomsich, sjg, macromorgan
On 2021/8/5 下午4:26, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> This patch adds support for setting the correct pin configuration
> for the Rockchip Serial Flash Controller found on the PX30.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
>
> (no changes since v1)
>
> arch/arm/mach-rockchip/px30/px30.c | 64 ++++++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c
> index 6fcef63c1b..be70d30cc8 100644
> --- a/arch/arm/mach-rockchip/px30/px30.c
> +++ b/arch/arm/mach-rockchip/px30/px30.c
> @@ -51,6 +51,57 @@ struct mm_region *mem_map = px30_mem_map;
>
> #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
>
> +/* GRF_GPIO1AL_IOMUX */
> +enum {
> + GPIO1A3_SHIFT = 12,
> + GPIO1A3_MASK = 0xf << GPIO1A3_SHIFT,
> + GPIO1A3_GPIO = 0,
> + GPIO1A3_FLASH_D3,
> + GPIO1A3_EMMC_D3,
> + GPIO1A3_SFC_SIO3,
> +
> + GPIO1A2_SHIFT = 8,
> + GPIO1A2_MASK = 0xf << GPIO1A2_SHIFT,
> + GPIO1A2_GPIO = 0,
> + GPIO1A2_FLASH_D2,
> + GPIO1A2_EMMC_D2,
> + GPIO1A2_SFC_SIO2,
> +
> + GPIO1A1_SHIFT = 4,
> + GPIO1A1_MASK = 0xf << GPIO1A1_SHIFT,
> + GPIO1A1_GPIO = 0,
> + GPIO1A1_FLASH_D1,
> + GPIO1A1_EMMC_D1,
> + GPIO1A1_SFC_SIO1,
> +
> + GPIO1A0_SHIFT = 0,
> + GPIO1A0_MASK = 0xf << GPIO1A0_SHIFT,
> + GPIO1A0_GPIO = 0,
> + GPIO1A0_FLASH_D0,
> + GPIO1A0_EMMC_D0,
> + GPIO1A0_SFC_SIO0,
> +};
> +
> +/* GRF_GPIO1AH_IOMUX */
> +enum {
> + GPIO1A4_SHIFT = 0,
> + GPIO1A4_MASK = 0xf << GPIO1A4_SHIFT,
> + GPIO1A4_GPIO = 0,
> + GPIO1A4_FLASH_D4,
> + GPIO1A4_EMMC_D4,
> + GPIO1A4_SFC_CSN0,
> +};
> +
> +/* GRF_GPIO1BL_IOMUX */
> +enum {
> + GPIO1B1_SHIFT = 4,
> + GPIO1B1_MASK = 0xf << GPIO1B1_SHIFT,
> + GPIO1B1_GPIO = 0,
> + GPIO1B1_FLASH_RDY,
> + GPIO1B1_EMMC_CLKOUT,
> + GPIO1B1_SFC_CLK,
> +};
> +
> /* GRF_GPIO1BH_IOMUX */
> enum {
> GPIO1B7_SHIFT = 12,
> @@ -193,6 +244,19 @@ int arch_cpu_init(void)
> GPIO1D4_SDMMC_D2 << GPIO1D4_SHIFT);
> #endif
>
> +#ifdef CONFIG_ROCKCHIP_SFC
> + rk_clrsetreg(&grf->gpio1al_iomux,
> + GPIO1A3_MASK | GPIO1A2_MASK | GPIO1A1_MASK | GPIO1A0_MASK,
> + GPIO1A3_SFC_SIO3 << GPIO1A3_SHIFT |
> + GPIO1A2_SFC_SIO2 << GPIO1A2_SHIFT |
> + GPIO1A1_SFC_SIO1 << GPIO1A1_SHIFT |
> + GPIO1A0_SFC_SIO0 << GPIO1A0_SHIFT);
> + rk_clrsetreg(&grf->gpio1ah_iomux, GPIO1A4_MASK,
> + GPIO1A4_SFC_CSN0 << GPIO1A4_SHIFT);
> + rk_clrsetreg(&grf->gpio1bl_iomux, GPIO1B1_MASK,
> + GPIO1B1_SFC_CLK << GPIO1B1_SHIFT);
> +#endif
> +
> #endif
>
> /* Enable PD_VO (default disable at reset) */
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 3/6] rockchip: px30: add the serial flash controller
2021-08-05 8:26 ` [PATCH v7 3/6] rockchip: px30: add the serial flash controller Jon Lin
2021-08-05 11:30 ` Jagan Teki
@ 2021-08-11 10:19 ` Kever Yang
1 sibling, 0 replies; 23+ messages in thread
From: Kever Yang @ 2021-08-11 10:19 UTC (permalink / raw)
To: Jon Lin, u-boot
Cc: heiko.stuebner, vigneshr, jagan, philipp.tomsich, sjg, macromorgan
On 2021/8/5 下午4:26, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Add the serial flash controller to the devicetree for the PX30.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
>
> (no changes since v5)
>
> Changes in v5:
> - px30 use "rockchip, sfc" as compatible id
>
> arch/arm/dts/px30.dtsi | 38 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
> index b6c79e7ed3..aaa8ae2235 100644
> --- a/arch/arm/dts/px30.dtsi
> +++ b/arch/arm/dts/px30.dtsi
> @@ -960,6 +960,18 @@
> status = "disabled";
> };
>
> + sfc: sfc@ff3a0000 {
> + compatible = "rockchip,sfc";
> + reg = <0x0 0xff3a0000 0x0 0x4000>;
> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
> + clock-names = "clk_sfc", "hclk_sfc";
> + pinctrl-names = "default";
> + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus4>;
> + power-domains = <&power PX30_PD_MMC_NAND>;
> + status = "disabled";
> + };
> +
> gpu: gpu@ff400000 {
> compatible = "rockchip,px30-mali", "arm,mali-bifrost";
> reg = <0x0 0xff400000 0x0 0x4000>;
> @@ -1926,6 +1938,32 @@
> };
> };
>
> + serial_flash {
> + sfc_bus4: sfc-bus4 {
> + rockchip,pins =
> + <1 RK_PA0 3 &pcfg_pull_none>,
> + <1 RK_PA1 3 &pcfg_pull_none>,
> + <1 RK_PA2 3 &pcfg_pull_none>,
> + <1 RK_PA3 3 &pcfg_pull_none>;
> + };
> +
> + sfc_bus2: sfc-bus2 {
> + rockchip,pins =
> + <1 RK_PA0 3 &pcfg_pull_none>,
> + <1 RK_PA1 3 &pcfg_pull_none>;
> + };
> +
> + sfc_cs: sfc-cs {
> + rockchip,pins =
> + <1 RK_PA4 3 &pcfg_pull_none>;
> + };
> +
> + sfc_clk: sfc-clk {
> + rockchip,pins =
> + <1 RK_PB1 3 &pcfg_pull_none>;
> + };
> + };
> +
> lcdc {
> lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
> rockchip,pins =
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B
2021-08-05 8:26 ` [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B Jon Lin
2021-08-05 11:34 ` Jagan Teki
@ 2021-08-11 10:19 ` Kever Yang
2021-08-11 10:27 ` Philipp Tomsich
2 siblings, 0 replies; 23+ messages in thread
From: Kever Yang @ 2021-08-11 10:19 UTC (permalink / raw)
To: Jon Lin, u-boot
Cc: heiko.stuebner, vigneshr, jagan, philipp.tomsich, sjg, macromorgan
On 2021/8/5 下午4:26, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
> this chip uses a continuation code which I cannot seem to parse, so
> there are possibly going to be collisions with chips that use the same
> manufacturer/ID.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
>
> Changes in v7:
> - Remove SPI_NOR_HAS_TB and SPI_NOR_HAS_LOCK
>
> drivers/mtd/spi/Kconfig | 6 ++++++
> drivers/mtd/spi/spi-nor-ids.c | 4 ++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
> index 1b2ef37e92..b2291f7290 100644
> --- a/drivers/mtd/spi/Kconfig
> +++ b/drivers/mtd/spi/Kconfig
> @@ -204,6 +204,12 @@ config SPI_FLASH_XMC
> Add support for various XMC (Wuhan Xinxin Semiconductor
> Manufacturing Corp.) SPI flash chips (XM25xxx)
>
> +config SPI_FLASH_XTX
> + bool "XTX SPI flash support"
> + help
> + Add support for various XTX (XTX Technology Limited)
> + SPI flash chips (XT25xxx).
> +
> endif
>
> config SPI_FLASH_USE_4K_SECTORS
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index cb3a08872d..4aef1ddd6e 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -361,6 +361,10 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> +#endif
> +#ifdef CONFIG_SPI_FLASH_XTX
> + /* XTX Technology (Shenzhen) Limited */
> + { INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> #endif
> { },
> };
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance
2021-08-05 8:27 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Jon Lin
2021-08-05 8:27 ` [PATCH v7 6/6] rockchip: px30: Support configure SFC Jon Lin
2021-08-05 17:32 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Chris Morgan
@ 2021-08-11 10:20 ` Kever Yang
2 siblings, 0 replies; 23+ messages in thread
From: Kever Yang @ 2021-08-11 10:20 UTC (permalink / raw)
To: Jon Lin, u-boot
Cc: heiko.stuebner, vigneshr, jagan, philipp.tomsich, sjg, macromorgan
On 2021/8/5 下午4:27, Jon Lin wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
> XT25F128B SPI NOR flash chip. This adds support for both. Note that
> while both the controller and chip support quad mode, only two lines
> are connected to the chip. Changing the pinctrl to bus2 and setting tx
> and rx lines to 2 for this reason.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
>
> (no changes since v1)
>
> arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi | 17 +++++++++++++++++
> arch/arm/dts/rk3326-odroid-go2.dts | 16 ++++++++++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> index 00767d2abd..741e8dd935 100644
> --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi
> @@ -7,6 +7,15 @@
> chosen {
> u-boot,spl-boot-order = &sdmmc;
> };
> +
> + aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + mmc0 = &sdmmc;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + spi0 = &sfc;
> + };
> };
>
> &cru {
> @@ -57,6 +66,14 @@
> u-boot,spl-fifo-mode;
> };
>
> +&sfc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&spi_flash {
> + u-boot,dm-pre-reloc;
> +};
> +
> &uart1 {
> clock-frequency = <24000000>;
> u-boot,dm-pre-reloc;
> diff --git a/arch/arm/dts/rk3326-odroid-go2.dts b/arch/arm/dts/rk3326-odroid-go2.dts
> index 8cd4688c49..6f91f5040b 100644
> --- a/arch/arm/dts/rk3326-odroid-go2.dts
> +++ b/arch/arm/dts/rk3326-odroid-go2.dts
> @@ -617,6 +617,22 @@
> status = "okay";
> };
>
> +&sfc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
> + status = "okay";
> +
> + spi_flash: xt25f128b@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <108000000>;
> + spi-rx-bus-width = <2>;
> + spi-tx-bus-width = <2>;
> + };
> +};
> +
> &tsadc {
> status = "okay";
> };
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 6/6] rockchip: px30: Support configure SFC
2021-08-05 8:27 ` [PATCH v7 6/6] rockchip: px30: Support configure SFC Jon Lin
2021-08-05 11:36 ` Jagan Teki
@ 2021-08-11 10:20 ` Kever Yang
2021-08-11 10:28 ` Philipp Tomsich
2 siblings, 0 replies; 23+ messages in thread
From: Kever Yang @ 2021-08-11 10:20 UTC (permalink / raw)
To: Jon Lin, u-boot
Cc: heiko.stuebner, vigneshr, jagan, philipp.tomsich, sjg, macromorgan
On 2021/8/5 下午4:27, Jon Lin wrote:
> Make px30 SFC clock configurable
>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
>
> Changes in v7:
> - Make px30 SFC clock configurable
>
> drivers/clk/rockchip/clk_px30.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
> index 6b746f4c65..a49b6f19f4 100644
> --- a/drivers/clk/rockchip/clk_px30.c
> +++ b/drivers/clk/rockchip/clk_px30.c
> @@ -581,6 +581,32 @@ static ulong px30_mmc_set_clk(struct px30_clk_priv *priv,
> return px30_mmc_get_clk(priv, clk_id);
> }
>
> +static ulong px30_sfc_get_clk(struct px30_clk_priv *priv, uint clk_id)
> +{
> + struct px30_cru *cru = priv->cru;
> + u32 div, con;
> +
> + con = readl(&cru->clksel_con[22]);
> + div = (con & SFC_DIV_CON_MASK) >> SFC_DIV_CON_SHIFT;
> +
> + return DIV_TO_RATE(priv->gpll_hz, div);
> +}
> +
> +static ulong px30_sfc_set_clk(struct px30_clk_priv *priv,
> + ulong clk_id, ulong set_rate)
> +{
> + struct px30_cru *cru = priv->cru;
> + int src_clk_div;
> +
> + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, set_rate);
> + rk_clrsetreg(&cru->clksel_con[22],
> + SFC_PLL_SEL_MASK | SFC_DIV_CON_MASK,
> + 0 << SFC_PLL_SEL_SHIFT |
> + (src_clk_div - 1) << SFC_DIV_CON_SHIFT);
> +
> + return px30_sfc_get_clk(priv, clk_id);
> +}
> +
> static ulong px30_pwm_get_clk(struct px30_clk_priv *priv, ulong clk_id)
> {
> struct px30_cru *cru = priv->cru;
> @@ -1192,6 +1218,9 @@ static ulong px30_clk_get_rate(struct clk *clk)
> case SCLK_EMMC_SAMPLE:
> rate = px30_mmc_get_clk(priv, clk->id);
> break;
> + case SCLK_SFC:
> + rate = px30_sfc_get_clk(priv, clk->id);
> + break;
> case SCLK_I2C0:
> case SCLK_I2C1:
> case SCLK_I2C2:
> @@ -1271,6 +1300,9 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate)
> case SCLK_EMMC:
> ret = px30_mmc_set_clk(priv, clk->id, rate);
> break;
> + case SCLK_SFC:
> + ret = px30_sfc_set_clk(priv, clk->id, rate);
> + break;
> case SCLK_I2C0:
> case SCLK_I2C1:
> case SCLK_I2C2:
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 1/6] spi: rockchip_sfc: add support for Rockchip SFC
2021-08-05 8:26 ` [PATCH v7 1/6] spi: " Jon Lin
2021-08-05 11:26 ` Jagan Teki
2021-08-11 10:19 ` Kever Yang
@ 2021-08-11 10:26 ` Philipp Tomsich
2 siblings, 0 replies; 23+ messages in thread
From: Philipp Tomsich @ 2021-08-11 10:26 UTC (permalink / raw)
To: Jon Lin
Cc: U-Boot Mailing List, heiko.stuebner, vigneshr, Jagan Teki,
Kever Yang, Simon Glass, macromorgan
On Thu, 5 Aug 2021 at 10:26, Jon Lin <jon.lin@rock-chips.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> This patch adds support for the Rockchip serial flash controller
> found on the PX30 SoC. It should work for versions 3-5 of the SFC
> IP, however I am only able to test it on v3.
>
> This is adapted from the WIP SPI-MEM driver for the SFC on mainline
> Linux. Note that the main difference between this and earlier versions
> of the driver is that this one does not support DMA. In testing
> the performance difference (performing a dual mode read on a 128Mb
> chip) is negligible. DMA, if used, must also be disabled in SPL
> mode when using A-TF anyway.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B
2021-08-05 8:26 ` [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B Jon Lin
2021-08-05 11:34 ` Jagan Teki
2021-08-11 10:19 ` Kever Yang
@ 2021-08-11 10:27 ` Philipp Tomsich
2 siblings, 0 replies; 23+ messages in thread
From: Philipp Tomsich @ 2021-08-11 10:27 UTC (permalink / raw)
To: Jon Lin
Cc: U-Boot Mailing List, heiko.stuebner, vigneshr, Jagan Teki,
Kever Yang, Simon Glass, macromorgan
On Thu, 5 Aug 2021 at 10:27, Jon Lin <jon.lin@rock-chips.com> wrote:
>
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
> this chip uses a continuation code which I cannot seem to parse, so
> there are possibly going to be collisions with chips that use the same
> manufacturer/ID.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v7 6/6] rockchip: px30: Support configure SFC
2021-08-05 8:27 ` [PATCH v7 6/6] rockchip: px30: Support configure SFC Jon Lin
2021-08-05 11:36 ` Jagan Teki
2021-08-11 10:20 ` Kever Yang
@ 2021-08-11 10:28 ` Philipp Tomsich
2 siblings, 0 replies; 23+ messages in thread
From: Philipp Tomsich @ 2021-08-11 10:28 UTC (permalink / raw)
To: Jon Lin
Cc: U-Boot Mailing List, heiko.stuebner, vigneshr, Jagan Teki,
Kever Yang, Simon Glass, macromorgan
On Thu, 5 Aug 2021 at 10:28, Jon Lin <jon.lin@rock-chips.com> wrote:
>
> Make px30 SFC clock configurable
>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2021-08-11 10:29 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-05 8:26 [PATCH v7 0/6] rockchip_sfc: add support for Rockchip SFC Jon Lin
2021-08-05 8:26 ` [PATCH v7 1/6] spi: " Jon Lin
2021-08-05 11:26 ` Jagan Teki
2021-08-05 16:17 ` Chris Morgan
2021-08-11 10:19 ` Kever Yang
2021-08-11 10:26 ` Philipp Tomsich
2021-08-05 8:26 ` [PATCH v7 2/6] rockchip: px30: Add support for using SFC Jon Lin
2021-08-11 10:19 ` Kever Yang
2021-08-05 8:26 ` [PATCH v7 3/6] rockchip: px30: add the serial flash controller Jon Lin
2021-08-05 11:30 ` Jagan Teki
2021-08-05 15:27 ` Chris Morgan
2021-08-11 10:19 ` Kever Yang
2021-08-05 8:26 ` [PATCH v7 4/6] mtd: spi-nor-ids: Add XTX XT25F128B Jon Lin
2021-08-05 11:34 ` Jagan Teki
2021-08-11 10:19 ` Kever Yang
2021-08-11 10:27 ` Philipp Tomsich
2021-08-05 8:27 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Jon Lin
2021-08-05 8:27 ` [PATCH v7 6/6] rockchip: px30: Support configure SFC Jon Lin
2021-08-05 11:36 ` Jagan Teki
2021-08-11 10:20 ` Kever Yang
2021-08-11 10:28 ` Philipp Tomsich
2021-08-05 17:32 ` [PATCH v7 5/6] rockchip: px30: add support for SFC for Odroid Go Advance Chris Morgan
2021-08-11 10:20 ` Kever Yang
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