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From: Reiji Watanabe <reijiw@google.com>
To: Andrew Jones <drjones@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Will Deacon <will@kernel.org>,
	Peng Liang <liangpeng10@huawei.com>,
	Peter Shier <pshier@google.com>,
	Ricardo Koller <ricarkol@google.com>,
	Oliver Upton <oupton@google.com>,
	Jing Zhang <jingzhangos@google.com>,
	Raghavendra Rao Anata <rananta@google.com>
Subject: Re: [RFC PATCH 04/25] KVM: arm64: Introduce struct id_reg_info
Date: Sat, 16 Oct 2021 21:43:52 -0700	[thread overview]
Message-ID: <CAAeT=Fw-ECM0n1C1HvtiiNEm-xhcK2-R0fWbA7hd38BJge+2RQ@mail.gmail.com> (raw)
In-Reply-To: <20211015134741.b7jahdmypu6tqkt2@gator>

> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -263,6 +263,76 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu,
> >               return read_zero(vcpu, p);
> >  }
> >
> > +struct id_reg_info {
> > +     u32     sys_reg;        /* Register ID */
> > +     u64     sys_val;        /* Sanitized system value */
> > +
> > +     /*
> > +      * Limit value of the register for a vcpu. The value is sys_val
> > +      * with bits cleared for unsupported features for the guest.
> > +      */
> > +     u64     vcpu_limit_val;
>
> Maybe I'll see a need for both later, but at the moment I'd think we only
> need sys_val with the bits cleared for disabled features.

Uh, yes, sys_val is used in patch-15 and I should have introduced
the field in the patch.  I will fix it in v2.


> > -static int __set_id_reg(const struct kvm_vcpu *vcpu,
> > +static int __set_id_reg(struct kvm_vcpu *vcpu,
> >                       const struct sys_reg_desc *rd, void __user *uaddr,
> >                       bool raz)
> >  {
> >       const u64 id = sys_reg_to_index(rd);
> > +     u32 encoding = reg_to_encoding(rd);
> >       int err;
> >       u64 val;
> >
> > @@ -1252,10 +1327,18 @@ static int __set_id_reg(const struct kvm_vcpu *vcpu,
> >       if (err)
> >               return err;
> >
> > -     /* This is what we mean by invariant: you can't change it. */
> > -     if (val != read_id_reg(vcpu, rd, raz))
> > +     /* Don't allow to change the reg unless the reg has id_reg_info */
> > +     if (val != read_id_reg(vcpu, rd, raz) && !GET_ID_REG_INFO(encoding))
> >               return -EINVAL;
> >
> > +     if (raz)
> > +             return (val == 0) ? 0 : -EINVAL;
>
> This is already covered by the val != read_id_reg(vcpu, rd, raz) check.

Yes, it can simply return 0 for raz case in this patch.
I will fix this in v2.


> > +     err = validate_id_reg(vcpu, rd, val);
> > +     if (err)
> > +             return err;
> > +
> > +     __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(encoding)) = val;
> >       return 0;
> >  }
> >
> > @@ -2818,6 +2901,23 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
> >       return write_demux_regids(uindices);
> >  }
> >
> > +static void id_reg_info_init_all(void)
> > +{
> > +     int i;
> > +     struct id_reg_info *id_reg;
> > +
> > +     for (i = 0; i < ARRAY_SIZE(id_reg_info_table); i++) {
> > +             id_reg = (struct id_reg_info *)id_reg_info_table[i];
> > +             if (!id_reg)
> > +                     continue;
> > +
> > +             if (id_reg->init)
> > +                     id_reg->init(id_reg);
> > +             else
> > +                     id_reg_info_init(id_reg);
>
> Maybe call id_reg->init(id_reg) from within id_reg_info_init() in case we
> wanted to apply some common id register initialization at some point?

Thank you for the nice suggestion.
That sounds like a better idea. I'll look into fixing it in v2.

Thanks,
Reiji

WARNING: multiple messages have this Message-ID (diff)
From: Reiji Watanabe <reijiw@google.com>
To: Andrew Jones <drjones@redhat.com>
Cc: kvm@vger.kernel.org, Marc Zyngier <maz@kernel.org>,
	Peter Shier <pshier@google.com>, Will Deacon <will@kernel.org>,
	Paolo Bonzini <pbonzini@redhat.com>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH 04/25] KVM: arm64: Introduce struct id_reg_info
Date: Sat, 16 Oct 2021 21:43:52 -0700	[thread overview]
Message-ID: <CAAeT=Fw-ECM0n1C1HvtiiNEm-xhcK2-R0fWbA7hd38BJge+2RQ@mail.gmail.com> (raw)
In-Reply-To: <20211015134741.b7jahdmypu6tqkt2@gator>

> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -263,6 +263,76 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu,
> >               return read_zero(vcpu, p);
> >  }
> >
> > +struct id_reg_info {
> > +     u32     sys_reg;        /* Register ID */
> > +     u64     sys_val;        /* Sanitized system value */
> > +
> > +     /*
> > +      * Limit value of the register for a vcpu. The value is sys_val
> > +      * with bits cleared for unsupported features for the guest.
> > +      */
> > +     u64     vcpu_limit_val;
>
> Maybe I'll see a need for both later, but at the moment I'd think we only
> need sys_val with the bits cleared for disabled features.

Uh, yes, sys_val is used in patch-15 and I should have introduced
the field in the patch.  I will fix it in v2.


> > -static int __set_id_reg(const struct kvm_vcpu *vcpu,
> > +static int __set_id_reg(struct kvm_vcpu *vcpu,
> >                       const struct sys_reg_desc *rd, void __user *uaddr,
> >                       bool raz)
> >  {
> >       const u64 id = sys_reg_to_index(rd);
> > +     u32 encoding = reg_to_encoding(rd);
> >       int err;
> >       u64 val;
> >
> > @@ -1252,10 +1327,18 @@ static int __set_id_reg(const struct kvm_vcpu *vcpu,
> >       if (err)
> >               return err;
> >
> > -     /* This is what we mean by invariant: you can't change it. */
> > -     if (val != read_id_reg(vcpu, rd, raz))
> > +     /* Don't allow to change the reg unless the reg has id_reg_info */
> > +     if (val != read_id_reg(vcpu, rd, raz) && !GET_ID_REG_INFO(encoding))
> >               return -EINVAL;
> >
> > +     if (raz)
> > +             return (val == 0) ? 0 : -EINVAL;
>
> This is already covered by the val != read_id_reg(vcpu, rd, raz) check.

Yes, it can simply return 0 for raz case in this patch.
I will fix this in v2.


> > +     err = validate_id_reg(vcpu, rd, val);
> > +     if (err)
> > +             return err;
> > +
> > +     __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(encoding)) = val;
> >       return 0;
> >  }
> >
> > @@ -2818,6 +2901,23 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
> >       return write_demux_regids(uindices);
> >  }
> >
> > +static void id_reg_info_init_all(void)
> > +{
> > +     int i;
> > +     struct id_reg_info *id_reg;
> > +
> > +     for (i = 0; i < ARRAY_SIZE(id_reg_info_table); i++) {
> > +             id_reg = (struct id_reg_info *)id_reg_info_table[i];
> > +             if (!id_reg)
> > +                     continue;
> > +
> > +             if (id_reg->init)
> > +                     id_reg->init(id_reg);
> > +             else
> > +                     id_reg_info_init(id_reg);
>
> Maybe call id_reg->init(id_reg) from within id_reg_info_init() in case we
> wanted to apply some common id register initialization at some point?

Thank you for the nice suggestion.
That sounds like a better idea. I'll look into fixing it in v2.

Thanks,
Reiji
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Reiji Watanabe <reijiw@google.com>
To: Andrew Jones <drjones@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
	 linux-arm-kernel@lists.infradead.org,
	James Morse <james.morse@arm.com>,
	 Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	 Paolo Bonzini <pbonzini@redhat.com>,
	Will Deacon <will@kernel.org>,
	 Peng Liang <liangpeng10@huawei.com>,
	Peter Shier <pshier@google.com>,
	 Ricardo Koller <ricarkol@google.com>,
	Oliver Upton <oupton@google.com>,
	 Jing Zhang <jingzhangos@google.com>,
	Raghavendra Rao Anata <rananta@google.com>
Subject: Re: [RFC PATCH 04/25] KVM: arm64: Introduce struct id_reg_info
Date: Sat, 16 Oct 2021 21:43:52 -0700	[thread overview]
Message-ID: <CAAeT=Fw-ECM0n1C1HvtiiNEm-xhcK2-R0fWbA7hd38BJge+2RQ@mail.gmail.com> (raw)
In-Reply-To: <20211015134741.b7jahdmypu6tqkt2@gator>

> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -263,6 +263,76 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu,
> >               return read_zero(vcpu, p);
> >  }
> >
> > +struct id_reg_info {
> > +     u32     sys_reg;        /* Register ID */
> > +     u64     sys_val;        /* Sanitized system value */
> > +
> > +     /*
> > +      * Limit value of the register for a vcpu. The value is sys_val
> > +      * with bits cleared for unsupported features for the guest.
> > +      */
> > +     u64     vcpu_limit_val;
>
> Maybe I'll see a need for both later, but at the moment I'd think we only
> need sys_val with the bits cleared for disabled features.

Uh, yes, sys_val is used in patch-15 and I should have introduced
the field in the patch.  I will fix it in v2.


> > -static int __set_id_reg(const struct kvm_vcpu *vcpu,
> > +static int __set_id_reg(struct kvm_vcpu *vcpu,
> >                       const struct sys_reg_desc *rd, void __user *uaddr,
> >                       bool raz)
> >  {
> >       const u64 id = sys_reg_to_index(rd);
> > +     u32 encoding = reg_to_encoding(rd);
> >       int err;
> >       u64 val;
> >
> > @@ -1252,10 +1327,18 @@ static int __set_id_reg(const struct kvm_vcpu *vcpu,
> >       if (err)
> >               return err;
> >
> > -     /* This is what we mean by invariant: you can't change it. */
> > -     if (val != read_id_reg(vcpu, rd, raz))
> > +     /* Don't allow to change the reg unless the reg has id_reg_info */
> > +     if (val != read_id_reg(vcpu, rd, raz) && !GET_ID_REG_INFO(encoding))
> >               return -EINVAL;
> >
> > +     if (raz)
> > +             return (val == 0) ? 0 : -EINVAL;
>
> This is already covered by the val != read_id_reg(vcpu, rd, raz) check.

Yes, it can simply return 0 for raz case in this patch.
I will fix this in v2.


> > +     err = validate_id_reg(vcpu, rd, val);
> > +     if (err)
> > +             return err;
> > +
> > +     __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(encoding)) = val;
> >       return 0;
> >  }
> >
> > @@ -2818,6 +2901,23 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
> >       return write_demux_regids(uindices);
> >  }
> >
> > +static void id_reg_info_init_all(void)
> > +{
> > +     int i;
> > +     struct id_reg_info *id_reg;
> > +
> > +     for (i = 0; i < ARRAY_SIZE(id_reg_info_table); i++) {
> > +             id_reg = (struct id_reg_info *)id_reg_info_table[i];
> > +             if (!id_reg)
> > +                     continue;
> > +
> > +             if (id_reg->init)
> > +                     id_reg->init(id_reg);
> > +             else
> > +                     id_reg_info_init(id_reg);
>
> Maybe call id_reg->init(id_reg) from within id_reg_info_init() in case we
> wanted to apply some common id register initialization at some point?

Thank you for the nice suggestion.
That sounds like a better idea. I'll look into fixing it in v2.

Thanks,
Reiji

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-10-17  4:44 UTC|newest]

Thread overview: 108+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-12  4:35 [RFC PATCH 00/25] KVM: arm64: Make CPU ID registers writable by userspace Reiji Watanabe
2021-10-12  4:35 ` Reiji Watanabe
2021-10-12  4:35 ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 01/25] KVM: arm64: Add has_reset_once flag for vcpu Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-15 10:12   ` Andrew Jones
2021-10-15 10:12     ` Andrew Jones
2021-10-15 10:12     ` Andrew Jones
2021-10-16 19:54     ` Reiji Watanabe
2021-10-16 19:54       ` Reiji Watanabe
2021-10-16 19:54       ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 02/25] KVM: arm64: Save ID registers' sanitized value per vCPU Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-15 13:09   ` Andrew Jones
2021-10-15 13:09     ` Andrew Jones
2021-10-15 13:09     ` Andrew Jones
2021-10-17  0:42     ` Reiji Watanabe
2021-10-17  0:42       ` Reiji Watanabe
2021-10-17  0:42       ` Reiji Watanabe
2021-10-18 14:30       ` Andrew Jones
2021-10-18 14:30         ` Andrew Jones
2021-10-18 14:30         ` Andrew Jones
2021-10-18 23:54         ` Reiji Watanabe
2021-10-18 23:54           ` Reiji Watanabe
2021-10-18 23:54           ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 03/25] KVM: arm64: Introduce a validation function for an ID register Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-15 13:30   ` Andrew Jones
2021-10-15 13:30     ` Andrew Jones
2021-10-15 13:30     ` Andrew Jones
     [not found]     ` <CAAeT=Fy-enk=X_PaRSDEKQ01yQzdyU=bcpq8cuCZhtpzC=JvnQ@mail.gmail.com>
     [not found]       ` <20211018144215.fvz7lrqiqlwhadms@gator.home>
     [not found]         ` <CAAeT=FyvRg7cD9-N81BM4gz0FaZHcaoWWQptniB5zDKdL=OkXg@mail.gmail.com>
     [not found]           ` <20211019062516.smjbbil5ugbipwno@gator.home>
2021-10-19  7:26             ` Reiji Watanabe
2021-10-19  7:26               ` Reiji Watanabe
2021-10-19  7:26               ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 04/25] KVM: arm64: Introduce struct id_reg_info Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-15 13:47   ` Andrew Jones
2021-10-15 13:47     ` Andrew Jones
2021-10-15 13:47     ` Andrew Jones
2021-10-17  4:43     ` Reiji Watanabe [this message]
2021-10-17  4:43       ` Reiji Watanabe
2021-10-17  4:43       ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 05/25] KVM: arm64: Keep consistency of ID registers between vCPUs Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 06/25] KVM: arm64: Make ID_AA64PFR0_EL1 writable Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 07/25] KVM: arm64: Make ID_AA64PFR1_EL1 writable Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 08/25] KVM: arm64: Make ID_AA64ISAR0_EL1 writable Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 09/25] KVM: arm64: Make ID_AA64ISAR1_EL1 writable Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 10/25] KVM: arm64: Make ID_AA64DFR0_EL1 writable Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 11/25] KVM: arm64: Make ID_DFR0_EL1 writable Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 12/25] KVM: arm64: Make MVFR1_EL1 writable Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 13/25] KVM: arm64: Make ID registers without id_reg_info writable Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 14/25] KVM: arm64: Add consistency checking for frac fields of ID registers Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 15/25] KVM: arm64: Introduce KVM_CAP_ARM_ID_REG_WRITABLE capability Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 16/25] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 17/25] KVM: arm64: Use vcpu->arch.mdcr_el2 to track value of mdcr_el2 Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 18/25] KVM: arm64: Introduce framework to trap disabled features Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 19/25] KVM: arm64: Trap disabled features of ID_AA64PFR0_EL1 Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 20/25] KVM: arm64: Trap disabled features of ID_AA64PFR1_EL1 Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 21/25] KVM: arm64: Trap disabled features of ID_AA64DFR0_EL1 Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 22/25] KVM: arm64: Trap disabled features of ID_AA64MMFR1_EL1 Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 23/25] KVM: arm64: Trap disabled features of ID_AA64ISAR1_EL1 Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 24/25] KVM: arm64: Activate trapping of disabled CPU features for the guest Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 25/25] KVM: arm64: selftests: Introduce id_reg_test Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe
2021-10-12  4:35   ` Reiji Watanabe

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