[OpenRISC] Tomasulo's Core

[OpenRISC] Tomasulo's Core

[Robert Finch]

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Hi, I have been perusing the OpenRISC site and studying the OpenRISC
design. I read a comment about the lack of out-of-order cores and thought
people may be interested in the one I am working on. It is not really ready
for prime-time yet. It is located in Github at
https://github.com/robfinch/Thor/tree/main/Thor2022

It is another core using a version of Tomasulo’s Algorithm.

I was glad to see the OpenRISC design make branch delay slots optional. Is
there a way to set a true/ false value in a register using a set
instruction? OpenRISC looks like an excellent design. I am interested in
64/128 bit though. 128-bit decimal floating-point.


Robert Finch
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[OpenRISC] Tomasulo's Core

[Stafford Horne]

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Hi Robert,

This looks like a neat project you are working on.

On Wed, Apr 13, 2022 at 9:16 PM Robert Finch <robfi680@gmail.com> wrote:
>
> Hi, I have been perusing the OpenRISC site and studying the OpenRISC design. I read a comment about the lack of out-of-order cores and thought people may be interested in the one I am working on. It is not really ready for prime-time yet. It is located in Github at https://github.com/robfinch/Thor/tree/main/Thor2022
>
> It is another core using a version of Tomasulo’s Algorithm.

There is a  Tomasulo's algorithm implementation of openrisc here:
https://github.com/openrisc/or1k_marocchino

Does your fetch stage fetch multiple instructions in parallel?  The
marocchino currently only fetches one instruction at a time.  It then
executes in parallel.

We have found a neat tool for measuring parallelization:
  https://github.com/shioyadan/Konata

> I was glad to see the OpenRISC design make branch delay slots optional. Is there a way to set a true/ false value in a register using a set instruction? OpenRISC looks like an excellent design. I am interested in 64/128 bit though. 128-bit decimal floating-point.

Having delay slots on and off in the CPU core is hard coded and cannot
be changed during runtime.   The OpenRISC cores are all 32-bit now,
the Marocchino implements 64-bit floating point.

-Stafford