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From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] arm: socfpga: gen5: don't zero bss in board_init_f()
Date: Fri, 12 Jul 2019 12:30:32 +0200	[thread overview]
Message-ID: <CAAh8qsxMtMJzNLrT0jKUwHxGwWSxsZs0nY6MkGMUf7XJS6PO+A@mail.gmail.com> (raw)
In-Reply-To: <ed4238fe-9abf-1dc5-3821-7af2a67669c8@denx.de>

On Fri, Jul 12, 2019 at 12:29 PM Marek Vasut <marex@denx.de> wrote:
>
> On 7/12/19 7:29 AM, Simon Goldschmidt wrote:
> > On Fri, Jul 12, 2019 at 7:15 AM Marek Vasut <marex@denx.de> wrote:
> >>
> >> On 7/11/19 9:18 PM, Simon Goldschmidt wrote:
> >>> The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the
> >>> DDR driver does not use bss any more, bss is not used before board_init_r()
> >>> and we can remove this hack.
> >>>
> >>> Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> >>> ---
> >>>
> >>>  arch/arm/mach-socfpga/spl_gen5.c | 2 --
> >>>  1 file changed, 2 deletions(-)
> >>>
> >>> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> >>> index 87b76b47de..47e63709ad 100644
> >>> --- a/arch/arm/mach-socfpga/spl_gen5.c
> >>> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> >>> @@ -79,8 +79,6 @@ void board_init_f(ulong dummy)
> >>>               writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
> >>>                      &sysmgr_regs->eccgrp_ocram);
> >>>
> >>> -     memset(__bss_start, 0, __bss_end - __bss_start);
> >>> -
> >>>       socfpga_sdram_remap_zero();
> >>>       socfpga_pl310_clear();
> >>
> >> So who will zero out the BSS ?
> >
> > BSS is zeroed by crt0.S, but after board_init_f(), before board_init_r().
> > Socfpga just had this double-zeroing because it invalidly used BSS in
> > board_init_f().
>
> Can you add that to the commit message and resend just this patch ? I
> applied the other one.

Sure.

>
> > Some weeks ago on this list, we've had a discussion whether it would be good to
> > generally allow such early usage of BSS, possibly via a config option (socfpga
> > is not the only platform affected). The outcome was negative and so I've started
> > this patch.

      reply	other threads:[~2019-07-12 10:30 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-11 19:18 [U-Boot] [PATCH 0/2] arm: socfpga: gen5 SPL bss cleanup Simon Goldschmidt
2019-07-11 19:18 ` [U-Boot] [PATCH 1/2] dm: ddr: socfpga: fix gen5 ddr driver to not use bss Simon Goldschmidt
2019-07-12  4:07   ` Marek Vasut
2019-07-11 19:18 ` [U-Boot] [PATCH 2/2] arm: socfpga: gen5: don't zero bss in board_init_f() Simon Goldschmidt
2019-07-12  4:07   ` Marek Vasut
2019-07-12  5:29     ` Simon Goldschmidt
2019-07-12 10:00       ` Marek Vasut
2019-07-12 10:30         ` Simon Goldschmidt [this message]

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