* [PATCH v2 0/3] arm: socfpga: arria10: Update device tree
@ 2020-04-07 7:43 Ley Foon Tan
2020-04-07 7:43 ` [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi Ley Foon Tan
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Ley Foon Tan @ 2020-04-07 7:43 UTC (permalink / raw)
To: u-boot
This patchset mainly to update Arria 10 dts/dtsi from Linux v5.6.2.
All uboot specific properties are moved to *u-boot.dtsi.
The 3rd patch is to fix missing u-boot,dm-pre-reloc for L2 cache node
and enable cache driver in SPL.
v2:
- Add Linux commit ID in commit description.
- Enable CONFIG_SPL_CACHE in Kconfig instead of defconfig.
History:
v1: https://patchwork.ozlabs.org/cover/1266732/
Thanks.
Regards
Ley Foon
Ley Foon Tan (3):
arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
arm: dts: arria10: Update dtsi/dts from Linux
arm: socfpga: arria10: Enable cache driver in SPL
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 142 ++++++++++++++++++
arch/arm/dts/socfpga_arria10.dtsi | 118 ++++++++-------
.../arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 17 +++
arch/arm/dts/socfpga_arria10_socdk.dtsi | 66 ++++----
.../socfpga_arria10_socdk_sdmmc-u-boot.dtsi | 46 ++++++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 53 +------
arch/arm/mach-socfpga/Kconfig | 1 +
7 files changed, 297 insertions(+), 146 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
--
2.19.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
2020-04-07 7:43 [PATCH v2 0/3] arm: socfpga: arria10: Update device tree Ley Foon Tan
@ 2020-04-07 7:43 ` Ley Foon Tan
2020-04-08 5:56 ` Simon Goldschmidt
2020-04-07 7:43 ` [PATCH v2 2/3] arm: dts: arria10: Update dtsi/dts from Linux Ley Foon Tan
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Ley Foon Tan @ 2020-04-07 7:43 UTC (permalink / raw)
To: u-boot
Move Uboot specific properties to *u-boot.dtsi files.
Preparation to sync Arria 10 device tree from Linux.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 123 ++++++++++++++++++
arch/arm/dts/socfpga_arria10.dtsi | 28 ----
.../arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 17 +++
arch/arm/dts/socfpga_arria10_socdk.dtsi | 27 ----
.../socfpga_arria10_socdk_sdmmc-u-boot.dtsi | 46 +++++++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 37 ------
6 files changed, 186 insertions(+), 92 deletions(-)
create mode 100644 arch/arm/dts/socfpga_arria10-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
new file mode 100644
index 000000000000..c637b100738a
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014, 2020, Intel Corporation
+ */
+
+/ {
+ chosen {
+ tick-timer = &timer2;
+ u-boot,dm-pre-reloc;
+ };
+
+ memory at 0 {
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&clkmgr {
+ u-boot,dm-pre-reloc;
+
+ clocks {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cb_intosc_hs_div2_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&cb_intosc_ls_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&f2s_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&i2c0 {
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ reset-names = "i2c";
+};
+
+&i2c4 {
+ reset-names = "i2c";
+};
+
+&l4_mp_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&l4_sp_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&l4_sys_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&main_periph_ref_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&main_pll {
+ u-boot,dm-pre-reloc;
+};
+
+&main_noc_base_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&noc_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&osc1 {
+ u-boot,dm-pre-reloc;
+};
+
+&peri_noc_base_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&periph_pll {
+ u-boot,dm-pre-reloc;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&portc {
+ bank-name = "portc";
+};
+
+&rst {
+ u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&timer2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index cc529bcd1156..c8cd5a84b8a8 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -21,11 +21,6 @@
#address-cells = <1>;
#size-cells = <1>;
- chosen {
- tick-timer = &timer2;
- u-boot,dm-pre-reloc;
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -60,7 +55,6 @@
device_type = "soc";
interrupt-parent = <&intc>;
ranges;
- u-boot,dm-pre-reloc;
amba {
compatible = "simple-bus";
@@ -99,35 +93,29 @@
clkmgr: clkmgr at ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
- u-boot,dm-pre-reloc;
clocks {
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- u-boot,dm-pre-reloc;
};
cb_intosc_ls_clk: cb_intosc_ls_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- u-boot,dm-pre-reloc;
};
f2s_free_clk: f2s_free_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- u-boot,dm-pre-reloc;
};
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
- u-boot,dm-pre-reloc;
};
main_pll: main_pll at 40 {
@@ -138,7 +126,6 @@
clocks = <&osc1>, <&cb_intosc_ls_clk>,
<&f2s_free_clk>;
reg = <0x40>;
- u-boot,dm-pre-reloc;
main_mpu_base_clk: main_mpu_base_clk {
#clock-cells = <0>;
@@ -152,7 +139,6 @@
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
div-reg = <0x144 0 11>;
- u-boot,dm-pre-reloc;
};
main_emaca_clk: main_emaca_clk at 68 {
@@ -228,7 +214,6 @@
clocks = <&osc1>, <&cb_intosc_ls_clk>,
<&f2s_free_clk>, <&main_periph_ref_clk>;
reg = <0xC0>;
- u-boot,dm-pre-reloc;
peri_mpu_base_clk: peri_mpu_base_clk {
#clock-cells = <0>;
@@ -242,7 +227,6 @@
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
div-reg = <0x144 16 11>;
- u-boot,dm-pre-reloc;
};
peri_emaca_clk: peri_emaca_clk at e8 {
@@ -318,7 +302,6 @@
<&osc1>, <&cb_intosc_hs_div2_clk>,
<&f2s_free_clk>;
reg = <0x64>;
- u-boot,dm-pre-reloc;
};
s2f_user1_free_clk: s2f_user1_free_clk at 104 {
@@ -345,7 +328,6 @@
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&noc_free_clk>;
fixed-divider = <4>;
- u-boot,dm-pre-reloc;
};
l4_main_clk: l4_main_clk {
@@ -500,7 +482,6 @@
porta: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "porta";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -520,7 +501,6 @@
portb: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "portb";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <29>;
@@ -540,7 +520,6 @@
portc: gpio-controller at 0 {
compatible = "snps,dw-apb-gpio-port";
- bank-name = "portc";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <27>;
@@ -568,7 +547,6 @@
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C0_RESET>;
- reset-names = "i2c";
status = "disabled";
};
@@ -580,7 +558,6 @@
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C1_RESET>;
- reset-names = "i2c";
status = "disabled";
};
@@ -592,7 +569,6 @@
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C2_RESET>;
- reset-names = "i2c";
status = "disabled";
};
@@ -604,7 +580,6 @@
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C3_RESET>;
- reset-names = "i2c";
status = "disabled";
};
@@ -616,7 +591,6 @@
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sp_clk>;
resets = <&rst I2C4_RESET>;
- reset-names = "i2c";
status = "disabled";
};
@@ -767,7 +741,6 @@
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x100>;
altr,modrst-offset = <0x20>;
- u-boot,dm-pre-reloc;
};
scu: snoop-control-unit at ffffc000 {
@@ -811,7 +784,6 @@
reg = <0xffd00000 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
- u-boot,dm-pre-reloc;
};
timer3: timer3 at ffd00100 {
diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
new file mode 100644
index 000000000000..58cd49782165
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015, 2020 Intel. All rights reserved.
+ */
+
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+ aliases {
+ bootargs = "console=ttyS0,115200";
+ i2c0 = &i2c1;
+ };
+};
+
+&uart1 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index ef10708ee867..e704243c14c1 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -24,7 +24,6 @@
aliases {
ethernet0 = &gmac0;
serial0 = &uart1;
- i2c0 = &i2c1;
};
chosen {
@@ -36,7 +35,6 @@
name = "memory";
device_type = "memory";
reg = <0x0 0x40000000>; /* 1GB */
- u-boot,dm-pre-reloc;
};
a10leds {
@@ -63,9 +61,6 @@
};
};
- soc {
- u-boot,dm-pre-reloc;
- };
};
&gmac0 {
@@ -155,7 +150,6 @@
};
&uart1 {
- u-boot,dm-pre-reloc;
status = "okay";
};
@@ -167,24 +161,3 @@
&watchdog1 {
status = "okay";
};
-
-/* Clock available early */
-&main_periph_ref_clk {
- u-boot,dm-pre-reloc;
-};
-
-&l4_mp_clk {
- u-boot,dm-pre-reloc;
-};
-
-&l4_sp_clk {
- u-boot,dm-pre-reloc;
-};
-
-&clkmgr {
- u-boot,dm-pre-reloc;
-};
-
-&sysmgr {
- u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
new file mode 100644
index 000000000000..c229e82de962
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2015, 2020 Intel. All rights reserved.
+ */
+
+#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_socdk-u-boot.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = <&fs_loader0>;
+ };
+
+ fs_loader0: fs-loader {
+ u-boot,dm-pre-reloc;
+ compatible = "u-boot,fs-loader";
+ phandlepart = <&mmc 1>;
+ };
+};
+
+&fpga_mgr {
+ u-boot,dm-pre-reloc;
+ altr,bitstream = "fit_spl_fpga.itb";
+};
+
+&mmc {
+ u-boot,dm-pre-reloc;
+};
+
+/* Clock available early */
+&main_sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index d6b6c2ddc091..040a164ba148 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -17,28 +17,8 @@
/dts-v1/;
#include "socfpga_arria10_socdk.dtsi"
-#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
-#include "socfpga_arria10_handoff_u-boot.dtsi"
-
-/ {
- chosen {
- firmware-loader = <&fs_loader0>;
- };
-
- fs_loader0: fs-loader {
- u-boot,dm-pre-reloc;
- compatible = "u-boot,fs-loader";
- phandlepart = <&mmc 1>;
- };
-};
-
-&fpga_mgr {
- u-boot,dm-pre-reloc;
- altr,bitstream = "fit_spl_fpga.itb";
-};
&mmc {
- u-boot,dm-pre-reloc;
status = "okay";
num-slots = <1>;
cap-sd-highspeed;
@@ -57,20 +37,3 @@
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
-
-/* Clock available early */
-&main_sdmmc_clk {
- u-boot,dm-pre-reloc;
-};
-
-&peri_sdmmc_clk {
- u-boot,dm-pre-reloc;
-};
-
-&sdmmc_free_clk {
- u-boot,dm-pre-reloc;
-};
-
-&sdmmc_clk {
- u-boot,dm-pre-reloc;
-};
--
2.19.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] arm: dts: arria10: Update dtsi/dts from Linux
2020-04-07 7:43 [PATCH v2 0/3] arm: socfpga: arria10: Update device tree Ley Foon Tan
2020-04-07 7:43 ` [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi Ley Foon Tan
@ 2020-04-07 7:43 ` Ley Foon Tan
2020-04-08 5:56 ` Simon Goldschmidt
2020-04-07 7:43 ` [PATCH v2 3/3] arm: socfpga: arria10: Enable cache driver in SPL Ley Foon Tan
2020-04-08 13:25 ` [PATCH v2 0/3] arm: socfpga: arria10: Update device tree Marek Vasut
3 siblings, 1 reply; 8+ messages in thread
From: Ley Foon Tan @ 2020-04-07 7:43 UTC (permalink / raw)
To: u-boot
Update these 3 files from Linux:.
- socfpga_arria10.dtsi (Commit ID c1459a9d7e92)
- socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b)
- socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f)
Change in socfpga_arria10.dtsi:
- Add clkmgr label, so that can reference to it in u-boot.dtsi.
Change in socfpga_arria10-u-boot.dtsi:
- Add compatible and altr,sysmgr-syscon for uboot.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
v2: Update commit ID in description.
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 15 ++++
arch/arm/dts/socfpga_arria10.dtsi | 90 ++++++++++++++------
arch/arm/dts/socfpga_arria10_socdk.dtsi | 43 +++++++---
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 16 +---
4 files changed, 108 insertions(+), 56 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
index c637b100738a..0db358cf1f2b 100644
--- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -38,6 +38,21 @@
u-boot,dm-pre-reloc;
};
+&gmac0 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+};
+
+&gmac1 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+};
+
+&gmac2 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
+};
+
&i2c0 {
reset-names = "i2c";
};
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index c8cd5a84b8a8..a598c7554266 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright Altera Corporation (C) 2014. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -79,6 +68,8 @@
#dma-requests = <32>;
clocks = <&l4_main_clk>;
clock-names = "apb_pclk";
+ resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
+ reset-names = "dma", "dma-ocp";
};
};
@@ -377,13 +368,28 @@
clk-gate = <0xC8 11>;
};
- nand_clk: nand_clk {
+ nand_x_clk: nand_x_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_mp_clk>;
clk-gate = <0xC8 10>;
};
+ nand_ecc_clk: nand_ecc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&nand_x_clk>;
+ clk-gate = <0xC8 10>;
+ };
+
+ nand_clk: nand_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-a10-gate-clk";
+ clocks = <&nand_x_clk>;
+ fixed-divider = <4>;
+ clk-gate = <0xC8 10>;
+ };
+
spi_m_clk: spi_m_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
@@ -414,7 +420,7 @@
};
gmac0: ethernet at ff800000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
+ compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
reg = <0xff800000 0x2000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -434,8 +440,8 @@
};
gmac1: ethernet at ff802000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x48 8>;
reg = <0xff802000 0x2000>;
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -454,8 +460,8 @@
};
gmac2: ethernet at ff804000 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
- altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
+ compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
reg = <0xff804000 0x2000>;
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -478,6 +484,7 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02900 0x100>;
+ resets = <&rst GPIO0_RESET>;
status = "disabled";
porta: gpio-controller at 0 {
@@ -497,6 +504,7 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02a00 0x100>;
+ resets = <&rst GPIO1_RESET>;
status = "disabled";
portb: gpio-controller at 0 {
@@ -516,6 +524,7 @@
#size-cells = <0>;
compatible = "snps,dw-apb-gpio";
reg = <0xffc02b00 0x100>;
+ resets = <&rst GPIO2_RESET>;
status = "disabled";
portc: gpio-controller at 0 {
@@ -594,22 +603,35 @@
status = "disabled";
};
+ spi0: spi at ffda4000 {
+ compatible = "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xffda4000 0x100>;
+ interrupts = <0 101 4>;
+ num-cs = <4>;
+ /*32bit_access;*/
+ clocks = <&spi_m_clk>;
+ resets = <&rst SPIM0_RESET>;
+ status = "disabled";
+ };
+
spi1: spi at ffda5000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xffda5000 0x100>;
interrupts = <0 102 4>;
- num-chipselect = <4>;
- bus-num = <0>;
+ num-cs = <4>;
/*32bit_access;*/
tx-dma-channel = <&pdma 16>;
rx-dma-channel = <&pdma 17>;
clocks = <&spi_m_clk>;
+ resets = <&rst SPIM1_RESET>;
status = "disabled";
};
- sdr: sdr at ffc25000 {
+ sdr: sdr at ffcfb100 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffcfb100 0x80>;
};
@@ -640,14 +662,14 @@
nand: nand at ffb90000 {
#address-cells = <1>;
- #size-cells = <1>;
- compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
- reg = <0xffb90000 0x20>,
- <0xffb80000 0x1000>;
+ #size-cells = <0>;
+ compatible = "altr,socfpga-denali-nand";
+ reg = <0xffb90000 0x72000>,
+ <0xffb80000 0x10000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 99 4>;
- dma-mask = <0xffffffff>;
- clocks = <&nand_clk>;
+ clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+ clock-names = "nand", "nand_x", "ecc";
resets = <&rst NAND_RESET>;
status = "disabled";
};
@@ -733,6 +755,8 @@
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
clocks = <&qspi_clk>;
+ resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
+ reset-names = "qspi", "qspi-ocp";
status = "disabled";
};
@@ -758,7 +782,7 @@
timer at ffffc600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xffffc600 0x100>;
- interrupts = <1 13 0xf04>;
+ interrupts = <1 13 0xf01>;
clocks = <&mpu_periph_clk>;
};
@@ -768,6 +792,8 @@
reg = <0xffc02700 0x100>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER0_RESET>;
+ reset-names = "timer";
};
timer1: timer1 at ffc02800 {
@@ -776,6 +802,8 @@
reg = <0xffc02800 0x100>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER1_RESET>;
+ reset-names = "timer";
};
timer2: timer2 at ffd00000 {
@@ -784,6 +812,8 @@
reg = <0xffd00000 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
+ resets = <&rst L4SYSTIMER0_RESET>;
+ reset-names = "timer";
};
timer3: timer3 at ffd00100 {
@@ -792,6 +822,8 @@
reg = <0xffd01000 0x100>;
clocks = <&l4_sys_free_clk>;
clock-names = "timer";
+ resets = <&rst L4SYSTIMER1_RESET>;
+ reset-names = "timer";
};
uart0: serial0 at ffc02000 {
@@ -853,6 +885,7 @@
reg = <0xffd00200 0x100>;
interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sys_free_clk>;
+ resets = <&rst L4WD0_RESET>;
status = "disabled";
};
@@ -861,6 +894,7 @@
reg = <0xffd00300 0x100>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l4_sys_free_clk>;
+ resets = <&rst L4WD1_RESET>;
status = "disabled";
};
};
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index e704243c14c1..0efbeccc5cd2 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -1,20 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-
#include "socfpga_arria10.dtsi"
/ {
@@ -61,6 +48,22 @@
};
};
+ ref_033v: 033-v-ref {
+ compatible = "regulator-fixed";
+ regulator-name = "0.33V";
+ regulator-min-microvolt = <330000>;
+ regulator-max-microvolt = <330000>;
+ };
+
+ soc {
+ clkmgr at ffd04000 {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+ };
};
&gmac0 {
@@ -132,6 +135,18 @@
i2c-sda-falling-time-ns = <6000>;
i2c-scl-falling-time-ns = <6000>;
+ adc at 14 {
+ compatible = "lltc,ltc2497";
+ reg = <0x14>;
+ vref-supply = <&ref_033v>;
+ };
+
+ adc at 16 {
+ compatible = "lltc,ltc2497";
+ reg = <0x16>;
+ vref-supply = <&ref_033v>;
+ };
+
eeprom at 51 {
compatible = "atmel,24c32";
reg = <0x51>;
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index 040a164ba148..64dc0799f3d7 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/dts-v1/;
@@ -20,8 +8,8 @@
&mmc {
status = "okay";
- num-slots = <1>;
cap-sd-highspeed;
+ cap-mmc-highspeed;
broken-cd;
bus-width = <4>;
};
--
2.19.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] arm: socfpga: arria10: Enable cache driver in SPL
2020-04-07 7:43 [PATCH v2 0/3] arm: socfpga: arria10: Update device tree Ley Foon Tan
2020-04-07 7:43 ` [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi Ley Foon Tan
2020-04-07 7:43 ` [PATCH v2 2/3] arm: dts: arria10: Update dtsi/dts from Linux Ley Foon Tan
@ 2020-04-07 7:43 ` Ley Foon Tan
2020-04-08 5:56 ` Simon Goldschmidt
2020-04-08 13:25 ` [PATCH v2 0/3] arm: socfpga: arria10: Update device tree Marek Vasut
3 siblings, 1 reply; 8+ messages in thread
From: Ley Foon Tan @ 2020-04-07 7:43 UTC (permalink / raw)
To: u-boot
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.
This fixed error below in SPL:
cache controller driver NOT found!
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
v2: Enable SPL_CACHE in Kconfig instead of defconfig.
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 4 ++++
arch/arm/mach-socfpga/Kconfig | 1 +
2 files changed, 5 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
index 0db358cf1f2b..6ff1ea6e5eb7 100644
--- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
@@ -73,6 +73,10 @@
reset-names = "i2c";
};
+&L2 {
+ u-boot,dm-pre-reloc;
+};
+
&l4_mp_clk {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 38d6c1b2ba32..a3699e82a19e 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -46,6 +46,7 @@ config TARGET_SOCFPGA_ARRIA10
bool
select SPL_ALTERA_SDRAM
select SPL_BOARD_INIT if SPL
+ select SPL_CACHE if SPL
select CLK
select SPL_CLK if SPL
select DM_I2C
--
2.19.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi
2020-04-07 7:43 ` [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi Ley Foon Tan
@ 2020-04-08 5:56 ` Simon Goldschmidt
0 siblings, 0 replies; 8+ messages in thread
From: Simon Goldschmidt @ 2020-04-08 5:56 UTC (permalink / raw)
To: u-boot
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> Move Uboot specific properties to *u-boot.dtsi files.
> Preparation to sync Arria 10 device tree from Linux.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 123 ++++++++++++++++++
> arch/arm/dts/socfpga_arria10.dtsi | 28 ----
> .../arm/dts/socfpga_arria10_socdk-u-boot.dtsi | 17 +++
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 27 ----
> .../socfpga_arria10_socdk_sdmmc-u-boot.dtsi | 46 +++++++
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 37 ------
> 6 files changed, 186 insertions(+), 92 deletions(-)
> create mode 100644 arch/arm/dts/socfpga_arria10-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
> create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> new file mode 100644
> index 000000000000..c637b100738a
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2014, 2020, Intel Corporation
> + */
> +
> +/ {
> + chosen {
> + tick-timer = &timer2;
> + u-boot,dm-pre-reloc;
> + };
> +
> + memory at 0 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + soc {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&clkmgr {
> + u-boot,dm-pre-reloc;
> +
> + clocks {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&cb_intosc_hs_div2_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&cb_intosc_ls_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&f2s_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&i2c0 {
> + reset-names = "i2c";
> +};
> +
> +&i2c1 {
> + reset-names = "i2c";
> +};
> +
> +&i2c2 {
> + reset-names = "i2c";
> +};
> +
> +&i2c3 {
> + reset-names = "i2c";
> +};
> +
> +&i2c4 {
> + reset-names = "i2c";
> +};
> +
> +&l4_mp_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&l4_sp_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&l4_sys_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&main_periph_ref_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&main_pll {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&main_noc_base_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&noc_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&osc1 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&peri_noc_base_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&periph_pll {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&porta {
> + bank-name = "porta";
> +};
> +
> +&portb {
> + bank-name = "portb";
> +};
> +
> +&portc {
> + bank-name = "portc";
> +};
> +
> +&rst {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sysmgr {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&timer2 {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
> index cc529bcd1156..c8cd5a84b8a8 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -21,11 +21,6 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> - chosen {
> - tick-timer = &timer2;
> - u-boot,dm-pre-reloc;
> - };
> -
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -60,7 +55,6 @@
> device_type = "soc";
> interrupt-parent = <&intc>;
> ranges;
> - u-boot,dm-pre-reloc;
>
> amba {
> compatible = "simple-bus";
> @@ -99,35 +93,29 @@
> clkmgr: clkmgr at ffd04000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd04000 0x1000>;
> - u-boot,dm-pre-reloc;
>
> clocks {
> #address-cells = <1>;
> #size-cells = <0>;
> - u-boot,dm-pre-reloc;
>
> cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - u-boot,dm-pre-reloc;
> };
>
> cb_intosc_ls_clk: cb_intosc_ls_clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - u-boot,dm-pre-reloc;
> };
>
> f2s_free_clk: f2s_free_clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - u-boot,dm-pre-reloc;
> };
>
> osc1: osc1 {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - u-boot,dm-pre-reloc;
> };
>
> main_pll: main_pll at 40 {
> @@ -138,7 +126,6 @@
> clocks = <&osc1>, <&cb_intosc_ls_clk>,
> <&f2s_free_clk>;
> reg = <0x40>;
> - u-boot,dm-pre-reloc;
>
> main_mpu_base_clk: main_mpu_base_clk {
> #clock-cells = <0>;
> @@ -152,7 +139,6 @@
> compatible = "altr,socfpga-a10-perip-clk";
> clocks = <&main_pll>;
> div-reg = <0x144 0 11>;
> - u-boot,dm-pre-reloc;
> };
>
> main_emaca_clk: main_emaca_clk at 68 {
> @@ -228,7 +214,6 @@
> clocks = <&osc1>, <&cb_intosc_ls_clk>,
> <&f2s_free_clk>, <&main_periph_ref_clk>;
> reg = <0xC0>;
> - u-boot,dm-pre-reloc;
>
> peri_mpu_base_clk: peri_mpu_base_clk {
> #clock-cells = <0>;
> @@ -242,7 +227,6 @@
> compatible = "altr,socfpga-a10-perip-clk";
> clocks = <&periph_pll>;
> div-reg = <0x144 16 11>;
> - u-boot,dm-pre-reloc;
> };
>
> peri_emaca_clk: peri_emaca_clk at e8 {
> @@ -318,7 +302,6 @@
> <&osc1>, <&cb_intosc_hs_div2_clk>,
> <&f2s_free_clk>;
> reg = <0x64>;
> - u-boot,dm-pre-reloc;
> };
>
> s2f_user1_free_clk: s2f_user1_free_clk at 104 {
> @@ -345,7 +328,6 @@
> compatible = "altr,socfpga-a10-perip-clk";
> clocks = <&noc_free_clk>;
> fixed-divider = <4>;
> - u-boot,dm-pre-reloc;
> };
>
> l4_main_clk: l4_main_clk {
> @@ -500,7 +482,6 @@
>
> porta: gpio-controller at 0 {
> compatible = "snps,dw-apb-gpio-port";
> - bank-name = "porta";
> gpio-controller;
> #gpio-cells = <2>;
> snps,nr-gpios = <29>;
> @@ -520,7 +501,6 @@
>
> portb: gpio-controller at 0 {
> compatible = "snps,dw-apb-gpio-port";
> - bank-name = "portb";
> gpio-controller;
> #gpio-cells = <2>;
> snps,nr-gpios = <29>;
> @@ -540,7 +520,6 @@
>
> portc: gpio-controller at 0 {
> compatible = "snps,dw-apb-gpio-port";
> - bank-name = "portc";
> gpio-controller;
> #gpio-cells = <2>;
> snps,nr-gpios = <27>;
> @@ -568,7 +547,6 @@
> interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sp_clk>;
> resets = <&rst I2C0_RESET>;
> - reset-names = "i2c";
> status = "disabled";
> };
>
> @@ -580,7 +558,6 @@
> interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sp_clk>;
> resets = <&rst I2C1_RESET>;
> - reset-names = "i2c";
> status = "disabled";
> };
>
> @@ -592,7 +569,6 @@
> interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sp_clk>;
> resets = <&rst I2C2_RESET>;
> - reset-names = "i2c";
> status = "disabled";
> };
>
> @@ -604,7 +580,6 @@
> interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sp_clk>;
> resets = <&rst I2C3_RESET>;
> - reset-names = "i2c";
> status = "disabled";
> };
>
> @@ -616,7 +591,6 @@
> interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sp_clk>;
> resets = <&rst I2C4_RESET>;
> - reset-names = "i2c";
> status = "disabled";
> };
>
> @@ -767,7 +741,6 @@
> compatible = "altr,rst-mgr";
> reg = <0xffd05000 0x100>;
> altr,modrst-offset = <0x20>;
> - u-boot,dm-pre-reloc;
> };
>
> scu: snoop-control-unit at ffffc000 {
> @@ -811,7 +784,6 @@
> reg = <0xffd00000 0x100>;
> clocks = <&l4_sys_free_clk>;
> clock-names = "timer";
> - u-boot,dm-pre-reloc;
> };
>
> timer3: timer3 at ffd00100 {
> diff --git a/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
> new file mode 100644
> index 000000000000..58cd49782165
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10_socdk-u-boot.dtsi
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2015, 2020 Intel. All rights reserved.
> + */
> +
> +#include "socfpga_arria10-u-boot.dtsi"
> +
> +/ {
> + aliases {
> + bootargs = "console=ttyS0,115200";
> + i2c0 = &i2c1;
> + };
> +};
> +
> +&uart1 {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> index ef10708ee867..e704243c14c1 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> @@ -24,7 +24,6 @@
> aliases {
> ethernet0 = &gmac0;
> serial0 = &uart1;
> - i2c0 = &i2c1;
> };
>
> chosen {
> @@ -36,7 +35,6 @@
> name = "memory";
> device_type = "memory";
> reg = <0x0 0x40000000>; /* 1GB */
> - u-boot,dm-pre-reloc;
> };
>
> a10leds {
> @@ -63,9 +61,6 @@
> };
> };
>
> - soc {
> - u-boot,dm-pre-reloc;
> - };
> };
>
> &gmac0 {
> @@ -155,7 +150,6 @@
> };
>
> &uart1 {
> - u-boot,dm-pre-reloc;
> status = "okay";
> };
>
> @@ -167,24 +161,3 @@
> &watchdog1 {
> status = "okay";
> };
> -
> -/* Clock available early */
> -&main_periph_ref_clk {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&l4_mp_clk {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&l4_sp_clk {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&clkmgr {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&sysmgr {
> - u-boot,dm-pre-reloc;
> -};
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
> new file mode 100644
> index 000000000000..c229e82de962
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
> @@ -0,0 +1,46 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2014-2015, 2020 Intel. All rights reserved.
> + */
> +
> +#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
> +#include "socfpga_arria10_handoff_u-boot.dtsi"
> +#include "socfpga_arria10_socdk-u-boot.dtsi"
> +
> +/ {
> + chosen {
> + firmware-loader = <&fs_loader0>;
> + };
> +
> + fs_loader0: fs-loader {
> + u-boot,dm-pre-reloc;
> + compatible = "u-boot,fs-loader";
> + phandlepart = <&mmc 1>;
> + };
> +};
> +
> +&fpga_mgr {
> + u-boot,dm-pre-reloc;
> + altr,bitstream = "fit_spl_fpga.itb";
> +};
> +
> +&mmc {
> + u-boot,dm-pre-reloc;
> +};
> +
> +/* Clock available early */
> +&main_sdmmc_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&peri_sdmmc_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc_free_clk {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sdmmc_clk {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index d6b6c2ddc091..040a164ba148 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> @@ -17,28 +17,8 @@
>
> /dts-v1/;
> #include "socfpga_arria10_socdk.dtsi"
> -#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
> -#include "socfpga_arria10_handoff_u-boot.dtsi"
> -
> -/ {
> - chosen {
> - firmware-loader = <&fs_loader0>;
> - };
> -
> - fs_loader0: fs-loader {
> - u-boot,dm-pre-reloc;
> - compatible = "u-boot,fs-loader";
> - phandlepart = <&mmc 1>;
> - };
> -};
> -
> -&fpga_mgr {
> - u-boot,dm-pre-reloc;
> - altr,bitstream = "fit_spl_fpga.itb";
> -};
>
> &mmc {
> - u-boot,dm-pre-reloc;
> status = "okay";
> num-slots = <1>;
> cap-sd-highspeed;
> @@ -57,20 +37,3 @@
> <48 IRQ_TYPE_LEVEL_HIGH>;
> };
> };
> -
> -/* Clock available early */
> -&main_sdmmc_clk {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&peri_sdmmc_clk {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&sdmmc_free_clk {
> - u-boot,dm-pre-reloc;
> -};
> -
> -&sdmmc_clk {
> - u-boot,dm-pre-reloc;
> -};
> --
> 2.19.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 2/3] arm: dts: arria10: Update dtsi/dts from Linux
2020-04-07 7:43 ` [PATCH v2 2/3] arm: dts: arria10: Update dtsi/dts from Linux Ley Foon Tan
@ 2020-04-08 5:56 ` Simon Goldschmidt
0 siblings, 0 replies; 8+ messages in thread
From: Simon Goldschmidt @ 2020-04-08 5:56 UTC (permalink / raw)
To: u-boot
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> Update these 3 files from Linux:.
> - socfpga_arria10.dtsi (Commit ID c1459a9d7e92)
> - socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b)
> - socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f)
>
> Change in socfpga_arria10.dtsi:
> - Add clkmgr label, so that can reference to it in u-boot.dtsi.
>
> Change in socfpga_arria10-u-boot.dtsi:
> - Add compatible and altr,sysmgr-syscon for uboot.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>
> ---
> v2: Update commit ID in description.
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 15 ++++
> arch/arm/dts/socfpga_arria10.dtsi | 90 ++++++++++++++------
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 43 +++++++---
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 16 +---
> 4 files changed, 108 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> index c637b100738a..0db358cf1f2b 100644
> --- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -38,6 +38,21 @@
> u-boot,dm-pre-reloc;
> };
>
> +&gmac0 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> +};
> +
> +&gmac1 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> +};
> +
> +&gmac2 {
> + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
> +};
> +
> &i2c0 {
> reset-names = "i2c";
> };
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
> index c8cd5a84b8a8..a598c7554266 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -1,17 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0
> /*
> * Copyright Altera Corporation (C) 2014. All rights reserved.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms and conditions of the GNU General Public License,
> - * version 2, as published by the Free Software Foundation.
> - *
> - * This program is distributed in the hope it will be useful, but WITHOUT
> - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> - * more details.
> - *
> - * You should have received a copy of the GNU General Public License along with
> - * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -79,6 +68,8 @@
> #dma-requests = <32>;
> clocks = <&l4_main_clk>;
> clock-names = "apb_pclk";
> + resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
> + reset-names = "dma", "dma-ocp";
> };
> };
>
> @@ -377,13 +368,28 @@
> clk-gate = <0xC8 11>;
> };
>
> - nand_clk: nand_clk {
> + nand_x_clk: nand_x_clk {
> #clock-cells = <0>;
> compatible = "altr,socfpga-a10-gate-clk";
> clocks = <&l4_mp_clk>;
> clk-gate = <0xC8 10>;
> };
>
> + nand_ecc_clk: nand_ecc_clk {
> + #clock-cells = <0>;
> + compatible = "altr,socfpga-a10-gate-clk";
> + clocks = <&nand_x_clk>;
> + clk-gate = <0xC8 10>;
> + };
> +
> + nand_clk: nand_clk {
> + #clock-cells = <0>;
> + compatible = "altr,socfpga-a10-gate-clk";
> + clocks = <&nand_x_clk>;
> + fixed-divider = <4>;
> + clk-gate = <0xC8 10>;
> + };
> +
> spi_m_clk: spi_m_clk {
> #clock-cells = <0>;
> compatible = "altr,socfpga-a10-gate-clk";
> @@ -414,7 +420,7 @@
> };
>
> gmac0: ethernet at ff800000 {
> - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
> altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> reg = <0xff800000 0x2000>;
> interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
> @@ -434,8 +440,8 @@
> };
>
> gmac1: ethernet at ff802000 {
> - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> - altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x48 8>;
> reg = <0xff802000 0x2000>;
> interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "macirq";
> @@ -454,8 +460,8 @@
> };
>
> gmac2: ethernet at ff804000 {
> - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
> - altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
> + compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
> + altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
> reg = <0xff804000 0x2000>;
> interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "macirq";
> @@ -478,6 +484,7 @@
> #size-cells = <0>;
> compatible = "snps,dw-apb-gpio";
> reg = <0xffc02900 0x100>;
> + resets = <&rst GPIO0_RESET>;
> status = "disabled";
>
> porta: gpio-controller at 0 {
> @@ -497,6 +504,7 @@
> #size-cells = <0>;
> compatible = "snps,dw-apb-gpio";
> reg = <0xffc02a00 0x100>;
> + resets = <&rst GPIO1_RESET>;
> status = "disabled";
>
> portb: gpio-controller at 0 {
> @@ -516,6 +524,7 @@
> #size-cells = <0>;
> compatible = "snps,dw-apb-gpio";
> reg = <0xffc02b00 0x100>;
> + resets = <&rst GPIO2_RESET>;
> status = "disabled";
>
> portc: gpio-controller at 0 {
> @@ -594,22 +603,35 @@
> status = "disabled";
> };
>
> + spi0: spi at ffda4000 {
> + compatible = "snps,dw-apb-ssi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0xffda4000 0x100>;
> + interrupts = <0 101 4>;
> + num-cs = <4>;
> + /*32bit_access;*/
> + clocks = <&spi_m_clk>;
> + resets = <&rst SPIM0_RESET>;
> + status = "disabled";
> + };
> +
> spi1: spi at ffda5000 {
> compatible = "snps,dw-apb-ssi";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0xffda5000 0x100>;
> interrupts = <0 102 4>;
> - num-chipselect = <4>;
> - bus-num = <0>;
> + num-cs = <4>;
> /*32bit_access;*/
> tx-dma-channel = <&pdma 16>;
> rx-dma-channel = <&pdma 17>;
> clocks = <&spi_m_clk>;
> + resets = <&rst SPIM1_RESET>;
> status = "disabled";
> };
>
> - sdr: sdr at ffc25000 {
> + sdr: sdr at ffcfb100 {
> compatible = "altr,sdr-ctl", "syscon";
> reg = <0xffcfb100 0x80>;
> };
> @@ -640,14 +662,14 @@
>
> nand: nand at ffb90000 {
> #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
> - reg = <0xffb90000 0x20>,
> - <0xffb80000 0x1000>;
> + #size-cells = <0>;
> + compatible = "altr,socfpga-denali-nand";
> + reg = <0xffb90000 0x72000>,
> + <0xffb80000 0x10000>;
> reg-names = "nand_data", "denali_reg";
> interrupts = <0 99 4>;
> - dma-mask = <0xffffffff>;
> - clocks = <&nand_clk>;
> + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
> + clock-names = "nand", "nand_x", "ecc";
> resets = <&rst NAND_RESET>;
> status = "disabled";
> };
> @@ -733,6 +755,8 @@
> cdns,fifo-width = <4>;
> cdns,trigger-address = <0x00000000>;
> clocks = <&qspi_clk>;
> + resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
> + reset-names = "qspi", "qspi-ocp";
> status = "disabled";
> };
>
> @@ -758,7 +782,7 @@
> timer at ffffc600 {
> compatible = "arm,cortex-a9-twd-timer";
> reg = <0xffffc600 0x100>;
> - interrupts = <1 13 0xf04>;
> + interrupts = <1 13 0xf01>;
> clocks = <&mpu_periph_clk>;
> };
>
> @@ -768,6 +792,8 @@
> reg = <0xffc02700 0x100>;
> clocks = <&l4_sp_clk>;
> clock-names = "timer";
> + resets = <&rst SPTIMER0_RESET>;
> + reset-names = "timer";
> };
>
> timer1: timer1 at ffc02800 {
> @@ -776,6 +802,8 @@
> reg = <0xffc02800 0x100>;
> clocks = <&l4_sp_clk>;
> clock-names = "timer";
> + resets = <&rst SPTIMER1_RESET>;
> + reset-names = "timer";
> };
>
> timer2: timer2 at ffd00000 {
> @@ -784,6 +812,8 @@
> reg = <0xffd00000 0x100>;
> clocks = <&l4_sys_free_clk>;
> clock-names = "timer";
> + resets = <&rst L4SYSTIMER0_RESET>;
> + reset-names = "timer";
> };
>
> timer3: timer3 at ffd00100 {
> @@ -792,6 +822,8 @@
> reg = <0xffd01000 0x100>;
> clocks = <&l4_sys_free_clk>;
> clock-names = "timer";
> + resets = <&rst L4SYSTIMER1_RESET>;
> + reset-names = "timer";
> };
>
> uart0: serial0 at ffc02000 {
> @@ -853,6 +885,7 @@
> reg = <0xffd00200 0x100>;
> interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sys_free_clk>;
> + resets = <&rst L4WD0_RESET>;
> status = "disabled";
> };
>
> @@ -861,6 +894,7 @@
> reg = <0xffd00300 0x100>;
> interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&l4_sys_free_clk>;
> + resets = <&rst L4WD1_RESET>;
> status = "disabled";
> };
> };
> diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> index e704243c14c1..0efbeccc5cd2 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> @@ -1,20 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2015 Altera Corporation <www.altera.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
> -
> #include "socfpga_arria10.dtsi"
>
> / {
> @@ -61,6 +48,22 @@
> };
> };
>
> + ref_033v: 033-v-ref {
> + compatible = "regulator-fixed";
> + regulator-name = "0.33V";
> + regulator-min-microvolt = <330000>;
> + regulator-max-microvolt = <330000>;
> + };
> +
> + soc {
> + clkmgr at ffd04000 {
> + clocks {
> + osc1 {
> + clock-frequency = <25000000>;
> + };
> + };
> + };
> + };
> };
>
> &gmac0 {
> @@ -132,6 +135,18 @@
> i2c-sda-falling-time-ns = <6000>;
> i2c-scl-falling-time-ns = <6000>;
>
> + adc at 14 {
> + compatible = "lltc,ltc2497";
> + reg = <0x14>;
> + vref-supply = <&ref_033v>;
> + };
> +
> + adc at 16 {
> + compatible = "lltc,ltc2497";
> + reg = <0x16>;
> + vref-supply = <&ref_033v>;
> + };
> +
> eeprom at 51 {
> compatible = "atmel,24c32";
> reg = <0x51>;
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index 040a164ba148..64dc0799f3d7 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> @@ -1,18 +1,6 @@
> +// SPDX-License-Identifier: GPL-2.0+
> /*
> * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> /dts-v1/;
> @@ -20,8 +8,8 @@
>
> &mmc {
> status = "okay";
> - num-slots = <1>;
> cap-sd-highspeed;
> + cap-mmc-highspeed;
> broken-cd;
> bus-width = <4>;
> };
> --
> 2.19.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] arm: socfpga: arria10: Enable cache driver in SPL
2020-04-07 7:43 ` [PATCH v2 3/3] arm: socfpga: arria10: Enable cache driver in SPL Ley Foon Tan
@ 2020-04-08 5:56 ` Simon Goldschmidt
0 siblings, 0 replies; 8+ messages in thread
From: Simon Goldschmidt @ 2020-04-08 5:56 UTC (permalink / raw)
To: u-boot
On Tue, Apr 7, 2020 at 9:43 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
> to enable cache driver in SPL.
>
> This fixed error below in SPL:
> cache controller driver NOT found!
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
>
> ---
> v2: Enable SPL_CACHE in Kconfig instead of defconfig.
> ---
> arch/arm/dts/socfpga_arria10-u-boot.dtsi | 4 ++++
> arch/arm/mach-socfpga/Kconfig | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> index 0db358cf1f2b..6ff1ea6e5eb7 100644
> --- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi
> @@ -73,6 +73,10 @@
> reset-names = "i2c";
> };
>
> +&L2 {
> + u-boot,dm-pre-reloc;
> +};
> +
> &l4_mp_clk {
> u-boot,dm-pre-reloc;
> };
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 38d6c1b2ba32..a3699e82a19e 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -46,6 +46,7 @@ config TARGET_SOCFPGA_ARRIA10
> bool
> select SPL_ALTERA_SDRAM
> select SPL_BOARD_INIT if SPL
> + select SPL_CACHE if SPL
> select CLK
> select SPL_CLK if SPL
> select DM_I2C
> --
> 2.19.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 0/3] arm: socfpga: arria10: Update device tree
2020-04-07 7:43 [PATCH v2 0/3] arm: socfpga: arria10: Update device tree Ley Foon Tan
` (2 preceding siblings ...)
2020-04-07 7:43 ` [PATCH v2 3/3] arm: socfpga: arria10: Enable cache driver in SPL Ley Foon Tan
@ 2020-04-08 13:25 ` Marek Vasut
3 siblings, 0 replies; 8+ messages in thread
From: Marek Vasut @ 2020-04-08 13:25 UTC (permalink / raw)
To: u-boot
On 4/7/20 9:43 AM, Ley Foon Tan wrote:
> This patchset mainly to update Arria 10 dts/dtsi from Linux v5.6.2.
> All uboot specific properties are moved to *u-boot.dtsi.
>
> The 3rd patch is to fix missing u-boot,dm-pre-reloc for L2 cache node
> and enable cache driver in SPL.
Applied all to socfpga/next, thanks.
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-04-08 13:25 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-07 7:43 [PATCH v2 0/3] arm: socfpga: arria10: Update device tree Ley Foon Tan
2020-04-07 7:43 ` [PATCH v2 1/3] arm: dts: arria10: Move uboot specific properties to u-boot.dtsi Ley Foon Tan
2020-04-08 5:56 ` Simon Goldschmidt
2020-04-07 7:43 ` [PATCH v2 2/3] arm: dts: arria10: Update dtsi/dts from Linux Ley Foon Tan
2020-04-08 5:56 ` Simon Goldschmidt
2020-04-07 7:43 ` [PATCH v2 3/3] arm: socfpga: arria10: Enable cache driver in SPL Ley Foon Tan
2020-04-08 5:56 ` Simon Goldschmidt
2020-04-08 13:25 ` [PATCH v2 0/3] arm: socfpga: arria10: Update device tree Marek Vasut
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