From: Anup Patel <anup@brainfault.org> To: Christoph Hellwig <hch@infradead.org> Cc: Anup Patel <Anup.Patel@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Atish Patra <Atish.Patra@wdc.com>, Paul Walmsley <paul.walmsley@sifive.com>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org> Subject: Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h Date: Wed, 24 Apr 2019 12:15:45 +0530 [thread overview] Message-ID: <CAAhSdy1Xc9AjPKY0RzLL_qsBs6wax23fi2BTVtMhuS0mAoKZmQ@mail.gmail.com> (raw) In-Reply-To: <20190424062947.GB10400@infradead.org> On Wed, Apr 24, 2019 at 11:59 AM Christoph Hellwig <hch@infradead.org> wrote: > > On Mon, Apr 15, 2019 at 09:37:23AM +0000, Anup Patel wrote: > > This patch adds SCAUSE interrupt flag and SCAUSE interrupt related > > defines to asm/csr.h. We also use these defines in kernel/irq.c and > > express SIE/SIP flags in-terms of SCAUSE interrupt causes. > > I'm not a fan of this. For one this pollutes csr.h with bits not really > needed by most users, and it makes adding the M-mode nommu port which has > to use the M-mode causes much harder: It's not polluting asm/csr.h because when we get interrupt numer in lower bits of SCAUSE CSR. These defines certainly belong to asm/csr.h because they represent possible exception causes when we get interrupt. We need these defines for programming HIDELEG CSR in KVM kernel module so it will be used at multiple places. > > http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba You can certainly use these defines in your nommu commit by using "#ifdef CONFIG_M_MODE" in switch case of do_IRQ(). Regards, Anup
WARNING: multiple messages have this Message-ID (diff)
From: Anup Patel <anup@brainfault.org> To: Christoph Hellwig <hch@infradead.org> Cc: Palmer Dabbelt <palmer@sifive.com>, Anup Patel <Anup.Patel@wdc.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Atish Patra <Atish.Patra@wdc.com>, Albert Ou <aou@eecs.berkeley.edu>, Paul Walmsley <paul.walmsley@sifive.com>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org> Subject: Re: [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines in asm/csr.h Date: Wed, 24 Apr 2019 12:15:45 +0530 [thread overview] Message-ID: <CAAhSdy1Xc9AjPKY0RzLL_qsBs6wax23fi2BTVtMhuS0mAoKZmQ@mail.gmail.com> (raw) In-Reply-To: <20190424062947.GB10400@infradead.org> On Wed, Apr 24, 2019 at 11:59 AM Christoph Hellwig <hch@infradead.org> wrote: > > On Mon, Apr 15, 2019 at 09:37:23AM +0000, Anup Patel wrote: > > This patch adds SCAUSE interrupt flag and SCAUSE interrupt related > > defines to asm/csr.h. We also use these defines in kernel/irq.c and > > express SIE/SIP flags in-terms of SCAUSE interrupt causes. > > I'm not a fan of this. For one this pollutes csr.h with bits not really > needed by most users, and it makes adding the M-mode nommu port which has > to use the M-mode causes much harder: It's not polluting asm/csr.h because when we get interrupt numer in lower bits of SCAUSE CSR. These defines certainly belong to asm/csr.h because they represent possible exception causes when we get interrupt. We need these defines for programming HIDELEG CSR in KVM kernel module so it will be used at multiple places. > > http://git.infradead.org/users/hch/misc.git/commitdiff/1221f5c32345ebe7ea2c1cd6e8a01ad4b422aaba You can certainly use these defines in your nommu commit by using "#ifdef CONFIG_M_MODE" in switch case of do_IRQ(). Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-04-24 6:46 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-04-15 9:37 [PATCH v3 0/3] Allow accessing CSR using CSR number Anup Patel 2019-04-15 9:37 ` Anup Patel 2019-04-15 9:37 ` [PATCH v3 1/3] RISC-V: Use tabs to align macro values in asm/csr.h Anup Patel 2019-04-15 9:37 ` Anup Patel 2019-04-24 6:27 ` Christoph Hellwig 2019-04-24 6:27 ` Christoph Hellwig 2019-04-15 9:37 ` [PATCH v3 2/3] RISC-V: Add interrupt related SCAUSE defines " Anup Patel 2019-04-15 9:37 ` Anup Patel 2019-04-24 6:29 ` Christoph Hellwig 2019-04-24 6:29 ` Christoph Hellwig 2019-04-24 6:45 ` Anup Patel [this message] 2019-04-24 6:45 ` Anup Patel 2019-04-24 15:01 ` Christoph Hellwig 2019-04-24 15:01 ` Christoph Hellwig 2019-04-25 5:04 ` Anup Patel 2019-04-25 5:04 ` Anup Patel 2019-04-15 9:37 ` [PATCH v3 3/3] RISC-V: Access CSRs using CSR numbers Anup Patel 2019-04-15 9:37 ` Anup Patel 2019-04-24 6:30 ` Christoph Hellwig 2019-04-24 6:30 ` Christoph Hellwig
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