* [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support
@ 2020-05-29 3:43 Jiaxun Yang
2020-05-29 3:43 ` [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards Jiaxun Yang
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw)
To: maz
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
linux-mips, devicetree, linux-kernel
With this series, LS7A and Loongson-3A4000 is finally supported
note that this series should depend on irqchip support[1], which
is likely to get merged soon.
Thanks.
[1]: https://lkml.org/lkml/2020/5/16/72
Jiaxun Yang (3):
dt-bindings: mips: Document two Loongson generic boards
MIPS: Loongson64: DeviceTree for LS7A PCH
MIPS: Loongson64:Load LS7A dtbs
.../bindings/mips/loongson/devices.yaml | 8 +
arch/mips/boot/dts/loongson/Makefile | 5 +-
.../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++
.../dts/loongson/loongson3_4core_ls7a.dts | 25 +++
.../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 +
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++
.../asm/mach-loongson64/builtin_dtbs.h | 2 +
arch/mips/loongson64/env.c | 56 +++---
8 files changed, 342 insertions(+), 23 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi
--
2.27.0.rc0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards 2020-05-29 3:43 [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Jiaxun Yang @ 2020-05-29 3:43 ` Jiaxun Yang 2020-05-29 8:37 ` WANG Xuerui 2020-05-29 21:04 ` Rob Herring 2020-05-29 3:43 ` [PATCH 2/3] MIPS: Loongson64: DeviceTree for LS7A PCH Jiaxun Yang ` (2 subsequent siblings) 3 siblings, 2 replies; 9+ messages in thread From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw) To: maz Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen, linux-mips, devicetree, linux-kernel Document loongson3-8core-ls7a and loongson3-r4-ls7a, with two boards LS7A PCH. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- .../devicetree/bindings/mips/loongson/devices.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml index 74ed4e397a78..6164b0fcb493 100644 --- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml @@ -24,4 +24,12 @@ properties: - description: Generic Loongson3 Octa Core + RS780E items: - const: loongson,loongson3-8core-rs780e + + - description: Generic Loongson3 Quad Core + LS7A + items: + - const: loongson,loongson3-8core-ls7a + + - description: Generic Loongson3 Release 4 + LS7A + items: + - const: loongson,loongson3-r4-ls7a ... -- 2.27.0.rc0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards 2020-05-29 3:43 ` [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards Jiaxun Yang @ 2020-05-29 8:37 ` WANG Xuerui 2020-05-29 21:04 ` Rob Herring 1 sibling, 0 replies; 9+ messages in thread From: WANG Xuerui @ 2020-05-29 8:37 UTC (permalink / raw) To: Jiaxun Yang, maz Cc: Thomas Bogendoerfer, Rob Herring, Huacai Chen, linux-mips, devicetree, linux-kernel Hi Jiaxun, On 2020/5/29 11:43, Jiaxun Yang wrote: > Document loongson3-8core-ls7a and loongson3-r4-ls7a, with > two boards LS7A PCH. "with two boards LS7A PCH" -- maybe you mean "two boards with LS7A PCH"? > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > .../devicetree/bindings/mips/loongson/devices.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml > index 74ed4e397a78..6164b0fcb493 100644 > --- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml > +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml > @@ -24,4 +24,12 @@ properties: > - description: Generic Loongson3 Octa Core + RS780E > items: > - const: loongson,loongson3-8core-rs780e > + > + - description: Generic Loongson3 Quad Core + LS7A > + items: > + - const: loongson,loongson3-8core-ls7a > + > + - description: Generic Loongson3 Release 4 + LS7A "R4" instead of "Release 4", as in /proc/cpuinfo output? > + items: > + - const: loongson,loongson3-r4-ls7a > ... ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards 2020-05-29 3:43 ` [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards Jiaxun Yang 2020-05-29 8:37 ` WANG Xuerui @ 2020-05-29 21:04 ` Rob Herring 1 sibling, 0 replies; 9+ messages in thread From: Rob Herring @ 2020-05-29 21:04 UTC (permalink / raw) To: Jiaxun Yang Cc: maz, Thomas Bogendoerfer, Huacai Chen, linux-mips, devicetree, linux-kernel On Fri, May 29, 2020 at 11:43:18AM +0800, Jiaxun Yang wrote: > Document loongson3-8core-ls7a and loongson3-r4-ls7a, with > two boards LS7A PCH. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > .../devicetree/bindings/mips/loongson/devices.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml > index 74ed4e397a78..6164b0fcb493 100644 > --- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml > +++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml > @@ -24,4 +24,12 @@ properties: > - description: Generic Loongson3 Octa Core + RS780E > items: > - const: loongson,loongson3-8core-rs780e > + > + - description: Generic Loongson3 Quad Core + LS7A Quad or.. > + items: > + - const: loongson,loongson3-8core-ls7a 8 core? > + > + - description: Generic Loongson3 Release 4 + LS7A > + items: > + - const: loongson,loongson3-r4-ls7a > ... > -- > 2.27.0.rc0 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] MIPS: Loongson64: DeviceTree for LS7A PCH 2020-05-29 3:43 [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Jiaxun Yang 2020-05-29 3:43 ` [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards Jiaxun Yang @ 2020-05-29 3:43 ` Jiaxun Yang 2020-05-29 3:43 ` [PATCH 3/3] MIPS: Loongson64:Load LS7A dtbs Jiaxun Yang 2020-05-29 4:13 ` [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Huacai Chen 3 siblings, 0 replies; 9+ messages in thread From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw) To: maz Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen, linux-mips, devicetree, linux-kernel DeviceTree for Loongson-3 Quad core + LS7A boards and Loongson-3 Release 4 + LS7A boards. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/boot/dts/loongson/Makefile | 5 +- .../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++ .../dts/loongson/loongson3_4core_ls7a.dts | 25 +++ .../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 + arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++ .../asm/mach-loongson64/builtin_dtbs.h | 2 + 6 files changed, 300 insertions(+), 1 deletion(-) create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile index 56d379471262..8f94fcb5d32e 100644 --- a/arch/mips/boot/dts/loongson/Makefile +++ b/arch/mips/boot/dts/loongson/Makefile @@ -1,4 +1,7 @@ # SPDX_License_Identifier: GPL_2.0 -dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_8core_rs780e.dtb +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_ls7a.dtb +dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_r4_ls7a.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi new file mode 100644 index 000000000000..e3d33f31e2b6 --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + package0: bus@1fe00000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x1fe00000 0 0x1fe00000 0x100000 + 0 0x3ff00000 0 0x3ff00000 0x100000 + 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>; + + liointc: interrupt-controller@3ff01400 { + compatible = "loongson,liointc-1.0"; + reg = <0 0x3ff01400 0x64>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>; + interrupt-names = "int0", "int1"; + + loongson,parent_int_map = <0xf0ffffff>, /* int0 */ + <0x0f000000>, /* int1 */ + <0x00000000>, /* int2 */ + <0x00000000>; /* int3 */ + + }; + + cpu_uart0: serial@1fe001e0 { + compatible = "ns16550a"; + reg = <0 0x1fe00100 0x10>; + clock-frequency = <100000000>; + interrupt-parent = <&liointc>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + no-loopback-test; + }; + + cpu_uart1: serial@1fe001e8 { + status = "disabled"; + compatible = "ns16550a"; + reg = <0 0x1fe00110 0x10>; + clock-frequency = <100000000>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&liointc>; + no-loopback-test; + }; + + htvec: interrupt-controller@efdfb000080 { + compatible = "loongson,htvec-1.0"; + reg = <0xefd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts new file mode 100644 index 000000000000..4eadcf99423d --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson3-package.dtsi" +#include "ls7a-pch.dtsi" + +/ { + compatible = "loongson,loongson3-4core-ls7a"; +}; + +&package0 { + htvec: interrupt-controller@efdfb000080 { + compatible = "loongson,htvec-1.0"; + reg = <0xefd 0xfb000080 0x40>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&liointc>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <25 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>; + }; +}; diff --git a/arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts b/arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts new file mode 100644 index 000000000000..d171f3a1a0ef --- /dev/null +++ b/arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "loongson3-r4-package.dtsi" +#include "ls7a-pch.dtsi" + +/ { + compatible = "loongson,loongson3-r4-ls7a"; +}; diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi new file mode 100644 index 000000000000..9c124601fe4c --- /dev/null +++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + bus@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x00000000 0 0x00000000 0 0x00040000 /* PIO */ + 0 0x10000000 0 0x10000000 0 0xf000000 /* CONF & APB */ + 0 0x20000000 0 0x20000000 0 0x10000000 + 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */ + 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>; + + pic: interrupt-controller@10000000 { + compatible = "loongson,pch-pic-1.0"; + reg = <0 0x10000000 0 0x400>; + interrupt-controller; + interrupt-parent = <&htvec>; + loongson,pic-base-vec = <64>; + #interrupt-cells = <2>; + }; + + pci@1a000000 { + compatible = "loongson,ls7a-pci"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <2>; + msi-parent = <&msi>; + + reg = <0 0x1a000000 0 0x02000000>, + <0xefe 0x00000000 0 0x20000000>; + + ranges = <0x01000000 0x0 0x00020000 0x0 0x00020000 0x0 0x00020000>, + <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; + + ohci@4,0 { + compatible = "pci0014,7a24.0", + "pci0014,7a24", + "pciclass0c0310", + "pciclass0c03"; + + reg = <0x2000 0x0 0x0 0x0 0x0>; + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + }; + + ehci@4,1 { + compatible = "pci0014,7a14.0", + "pci0014,7a14", + "pciclass0c0320", + "pciclass0c03"; + + reg = <0x2100 0x0 0x0 0x0 0x0>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + }; + + ohci@5,0 { + compatible = "pci0014,7a24.0", + "pci0014,7a24", + "pciclass0c0310", + "pciclass0c03"; + + reg = <0x2800 0x0 0x0 0x0 0x0>; + interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + }; + + ehci@5,1 { + compatible = "pci0014,7a14.0", + "pci0014,7a14", + "pciclass0c0320", + "pciclass0c03"; + + reg = <0x2900 0x0 0x0 0x0 0x0>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + }; + + sata@8,0 { + compatible = "pci0014,7a08.0", + "pci0014,7a08", + "pciclass010601", + "pciclass0106"; + + reg = <0x4000 0x0 0x0 0x0 0x0>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + }; + + sata@8,1 { + compatible = "pci0014,7a08.0", + "pci0014,7a08", + "pciclass010601", + "pciclass0106"; + + reg = <0x4100 0x0 0x0 0x0 0x0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + }; + + sata@8,2 { + compatible = "pci0014,7a08.0", + "pci0014,7a08", + "pciclass010601", + "pciclass0106"; + + reg = <0x4200 0x0 0x0 0x0 0x0>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + }; + + pci_bridge@9,0 { + compatible = "pci0014,7a19.0", + "pci0014,7a19", + "pciclass060400", + "pciclass0604"; + + reg = <0x4800 0x0 0x0 0x0 0x0>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci_bridge@b,0 { + compatible = "pci0014,7a09.0", + "pci0014,7a09", + "pciclass060400", + "pciclass0604"; + + reg = <0x5800 0x0 0x0 0x0 0x0>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci_bridge@d,0 { + compatible = "pci0014,7a19.0", + "pci0014,7a19", + "pciclass060400", + "pciclass0604"; + + reg = <0x6800 0x0 0x0 0x0 0x0>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci_bridge@11,0 { + compatible = "pci0014,7a29.0", + "pci0014,7a29", + "pciclass060400", + "pciclass0604"; + + reg = <0x8800 0x0 0x0 0x0 0x0>; + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pic>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + msi: msi-controller@2ff00000 { + compatible = "loongson,pch-msi-1.0"; + reg = <0 0x2ff00000 0 0x8>; + interrupt-controller; + msi-controller; + loongson,msi-base-vec = <0>; + loongson,msi-num-vecs = <64>; + interrupt-parent = <&htvec>; + }; + }; +}; diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h index 853c6d80887b..cf563fafc0ea 100644 --- a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h +++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h @@ -10,4 +10,6 @@ extern u32 __dtb_loongson3_4core_rs780e_begin[]; extern u32 __dtb_loongson3_8core_rs780e_begin[]; +extern u32 __dtb_loongson3_4core_ls7a_begin[]; +extern u32 __dtb_loongson3_r4_ls7a_begin[]; #endif -- 2.27.0.rc0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] MIPS: Loongson64:Load LS7A dtbs 2020-05-29 3:43 [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Jiaxun Yang 2020-05-29 3:43 ` [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards Jiaxun Yang 2020-05-29 3:43 ` [PATCH 2/3] MIPS: Loongson64: DeviceTree for LS7A PCH Jiaxun Yang @ 2020-05-29 3:43 ` Jiaxun Yang 2020-05-29 4:13 ` [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Huacai Chen 3 siblings, 0 replies; 9+ messages in thread From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw) To: maz Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen, linux-mips, devicetree, linux-kernel Load correct devicetree according to PRID and PCH type. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/loongson64/env.c | 56 +++++++++++++++++++++++--------------- 1 file changed, 34 insertions(+), 22 deletions(-) diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c index d11bc346bbca..9b56f4a80b62 100644 --- a/arch/mips/loongson64/env.c +++ b/arch/mips/loongson64/env.c @@ -126,28 +126,6 @@ void __init prom_init_env(void) loongson_sysconf.cores_per_node - 1) / loongson_sysconf.cores_per_node; - if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) { - switch (read_c0_prid() & PRID_REV_MASK) { - case PRID_REV_LOONGSON3A_R1: - case PRID_REV_LOONGSON3A_R2_0: - case PRID_REV_LOONGSON3A_R2_1: - case PRID_REV_LOONGSON3A_R3_0: - case PRID_REV_LOONGSON3A_R3_1: - loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin; - break; - case PRID_REV_LOONGSON3B_R1: - case PRID_REV_LOONGSON3B_R2: - loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin; - break; - default: - break; - } - } - - - if (!loongson_fdt_blob) - pr_err("Failed to determine built-in Loongson64 dtb\n"); - loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr; loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr; loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr; @@ -198,4 +176,38 @@ void __init prom_init_env(void) loongson_sysconf.bridgetype = RS780E; loongson_sysconf.early_config = rs780e_early_config; } + + if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) { + switch (read_c0_prid() & PRID_REV_MASK) { + case PRID_REV_LOONGSON3A_R1: + case PRID_REV_LOONGSON3A_R2_0: + case PRID_REV_LOONGSON3A_R2_1: + case PRID_REV_LOONGSON3A_R3_0: + case PRID_REV_LOONGSON3A_R3_1: + switch (loongson_sysconf.bridgetype) { + case RS780E: + loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin; + break; + case LS7A: + loongson_fdt_blob = __dtb_loongson3_4core_ls7a_begin; + break; + default: + break; + } + break; + case PRID_REV_LOONGSON3B_R1: + case PRID_REV_LOONGSON3B_R2: + if (loongson_sysconf.bridgetype == RS780E) + loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin; + break; + default: + break; + } + } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) { + if (loongson_sysconf.bridgetype == LS7A) + loongson_fdt_blob = __dtb_loongson3_r4_ls7a_begin; + } + + if (!loongson_fdt_blob) + pr_err("Failed to determine built-in Loongson64 dtb\n"); } -- 2.27.0.rc0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support 2020-05-29 3:43 [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Jiaxun Yang ` (2 preceding siblings ...) 2020-05-29 3:43 ` [PATCH 3/3] MIPS: Loongson64:Load LS7A dtbs Jiaxun Yang @ 2020-05-29 4:13 ` Huacai Chen 2020-05-29 4:36 ` Jiaxun Yang 3 siblings, 1 reply; 9+ messages in thread From: Huacai Chen @ 2020-05-29 4:13 UTC (permalink / raw) To: Jiaxun Yang Cc: Marc Zyngier, Thomas Bogendoerfer, Rob Herring, open list:MIPS, devicetree, LKML Hi, Jiaxun, On Fri, May 29, 2020 at 11:45 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > > With this series, LS7A and Loongson-3A4000 is finally supported > note that this series should depend on irqchip support[1], which > is likely to get merged soon. > > Thanks. > > [1]: https://lkml.org/lkml/2020/5/16/72 > > Jiaxun Yang (3): > dt-bindings: mips: Document two Loongson generic boards > MIPS: Loongson64: DeviceTree for LS7A PCH > MIPS: Loongson64:Load LS7A dtbs > > .../bindings/mips/loongson/devices.yaml | 8 + > arch/mips/boot/dts/loongson/Makefile | 5 +- > .../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++ > .../dts/loongson/loongson3_4core_ls7a.dts | 25 +++ > .../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 + > arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++ > .../asm/mach-loongson64/builtin_dtbs.h | 2 + > arch/mips/loongson64/env.c | 56 +++--- > 8 files changed, 342 insertions(+), 23 deletions(-) > create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi > create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts > create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts > create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi I think the naming can be like this: Old processor (Loongson 3A R1~R3) use loongson64c_ prefix instead of loongson3, new processor (Loongson 3A R4) use loongson64g_ prefix instead of loongson3_r4, and Loongson-2K use loongson64r_ prefix, this makes them consistent with their PRID definitions. > > -- > 2.27.0.rc0 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support 2020-05-29 4:13 ` [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Huacai Chen @ 2020-05-29 4:36 ` Jiaxun Yang 2020-05-29 9:47 ` Huacai Chen 0 siblings, 1 reply; 9+ messages in thread From: Jiaxun Yang @ 2020-05-29 4:36 UTC (permalink / raw) To: Huacai Chen Cc: Marc Zyngier, Thomas Bogendoerfer, Rob Herring, open list:MIPS, devicetree, LKML 于 2020年5月29日 GMT+08:00 下午12:13:36, Huacai Chen <chenhc@lemote.com> 写到: >Hi, Jiaxun, > >On Fri, May 29, 2020 at 11:45 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: >> >> With this series, LS7A and Loongson-3A4000 is finally supported >> note that this series should depend on irqchip support[1], which >> is likely to get merged soon. >> >> Thanks. >> >> [1]: https://lkml.org/lkml/2020/5/16/72 >> >> Jiaxun Yang (3): >> dt-bindings: mips: Document two Loongson generic boards >> MIPS: Loongson64: DeviceTree for LS7A PCH >> MIPS: Loongson64:Load LS7A dtbs >> >> .../bindings/mips/loongson/devices.yaml | 8 + >> arch/mips/boot/dts/loongson/Makefile | 5 +- >> .../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++ >> .../dts/loongson/loongson3_4core_ls7a.dts | 25 +++ >> .../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 + >> arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++ >> .../asm/mach-loongson64/builtin_dtbs.h | 2 + >> arch/mips/loongson64/env.c | 56 +++--- >> 8 files changed, 342 insertions(+), 23 deletions(-) >> create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi >> create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts >> create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts >> create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi >I think the naming can be like this: Old processor (Loongson 3A R1~R3) >use loongson64c_ prefix instead of loongson3, new processor (Loongson >3A R4) use loongson64g_ prefix instead of loongson3_r4, and >Loongson-2K use loongson64r_ prefix, this makes them consistent with >their PRID definitions. DeviceTree bindings have stable ABI. Although they're currently only used internally in Kernel. I don't think it's a good idea to rename existing bindings. Also, Loongson64C/64G/64R never came to a part of Loongson's official naming. I doubt if end users will recognize these names. I'd prefer keep naming as is. It's really not a big deal. Thanks. > >> >> -- >> 2.27.0.rc0 >> -- Jiaxun Yang ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support 2020-05-29 4:36 ` Jiaxun Yang @ 2020-05-29 9:47 ` Huacai Chen 0 siblings, 0 replies; 9+ messages in thread From: Huacai Chen @ 2020-05-29 9:47 UTC (permalink / raw) To: Jiaxun Yang Cc: Marc Zyngier, Thomas Bogendoerfer, Rob Herring, open list:MIPS, devicetree, LKML Hi, Jiaxun, On Fri, May 29, 2020 at 12:37 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > > > > 于 2020年5月29日 GMT+08:00 下午12:13:36, Huacai Chen <chenhc@lemote.com> 写到: > >Hi, Jiaxun, > > > >On Fri, May 29, 2020 at 11:45 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > >> > >> With this series, LS7A and Loongson-3A4000 is finally supported > >> note that this series should depend on irqchip support[1], which > >> is likely to get merged soon. > >> > >> Thanks. > >> > >> [1]: https://lkml.org/lkml/2020/5/16/72 > >> > >> Jiaxun Yang (3): > >> dt-bindings: mips: Document two Loongson generic boards > >> MIPS: Loongson64: DeviceTree for LS7A PCH > >> MIPS: Loongson64:Load LS7A dtbs > >> > >> .../bindings/mips/loongson/devices.yaml | 8 + > >> arch/mips/boot/dts/loongson/Makefile | 5 +- > >> .../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++ > >> .../dts/loongson/loongson3_4core_ls7a.dts | 25 +++ > >> .../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 + > >> arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++ > >> .../asm/mach-loongson64/builtin_dtbs.h | 2 + > >> arch/mips/loongson64/env.c | 56 +++--- > >> 8 files changed, 342 insertions(+), 23 deletions(-) > >> create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi > >> create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts > >> create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts > >> create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi > >I think the naming can be like this: Old processor (Loongson 3A R1~R3) > >use loongson64c_ prefix instead of loongson3, new processor (Loongson > >3A R4) use loongson64g_ prefix instead of loongson3_r4, and > >Loongson-2K use loongson64r_ prefix, this makes them consistent with > >their PRID definitions. > > > DeviceTree bindings have stable ABI. Although they're currently > only used internally in Kernel. I don't think it's a good idea > to rename existing bindings. I think consistency is important, and this renaming doesn't break anything. > > Also, Loongson64C/64G/64R never came to a part of Loongson's > official naming. I doubt if end users will recognize these names. > > I'd prefer keep naming as is. It's really not a big deal. > > Thanks. > > > > > >> > >> -- > >> 2.27.0.rc0 > >> > > -- > Jiaxun Yang ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-05-29 21:04 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-29 3:43 [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Jiaxun Yang 2020-05-29 3:43 ` [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards Jiaxun Yang 2020-05-29 8:37 ` WANG Xuerui 2020-05-29 21:04 ` Rob Herring 2020-05-29 3:43 ` [PATCH 2/3] MIPS: Loongson64: DeviceTree for LS7A PCH Jiaxun Yang 2020-05-29 3:43 ` [PATCH 3/3] MIPS: Loongson64:Load LS7A dtbs Jiaxun Yang 2020-05-29 4:13 ` [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support Huacai Chen 2020-05-29 4:36 ` Jiaxun Yang 2020-05-29 9:47 ` Huacai Chen
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