* [Qemu-devel] [PATCH] arm: add Cortex A7 CPU parameters
@ 2016-08-29 22:36 Andrey Yurovsky
2016-08-29 22:41 ` Peter Maydell
0 siblings, 1 reply; 5+ messages in thread
From: Andrey Yurovsky @ 2016-08-29 22:36 UTC (permalink / raw)
To: qemu-devel; +Cc: Andrey Yurovsky, peter.maydell
From: Andrey Yurovsky <yurovsky@gmail.com>
Add the "cortex-a7" CPU with features and registers matching the Cortex-A7
MPCore Technical Reference Manual and the Cortex-A7 Floating-Point Unit
Technical Reference Manual. The A7 is very similar to the A15.
Tested via the "virt" machine.
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
---
target-arm/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index ce8b8f4..c2352da 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1129,6 +1129,51 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static void cortex_a7_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a7";
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
+ cpu->midr = 0x410fc075;
+ cpu->reset_fpsid = 0x41023075;
+ cpu->mvfr0 = 0x10110221;
+ cpu->mvfr1 = 0x11000011;
+ cpu->ctr = 0x84448003;
+ cpu->reset_sctlr = 0x00c50078;
+ cpu->id_pfr0 = 0x00001131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x02010555;
+ cpu->pmceid0 = 0x3fff0f3f;
+ cpu->pmceid1 = 0x00000000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10101105;
+ cpu->id_mmfr1 = 0x40000000;
+ cpu->id_mmfr2 = 0x01240000;
+ cpu->id_mmfr3 = 0x02102211;
+ cpu->id_isar0 = 0x01101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232041;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x10011142;
+ cpu->dbgdidr = 0x3515f005;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+ define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
+}
+
static void cortex_a15_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1385,6 +1430,7 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
+ { .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [Qemu-devel] [PATCH] arm: add Cortex A7 CPU parameters
2016-08-29 22:36 [Qemu-devel] [PATCH] arm: add Cortex A7 CPU parameters Andrey Yurovsky
@ 2016-08-29 22:41 ` Peter Maydell
2016-08-29 22:53 ` Andrey Yurovsky
0 siblings, 1 reply; 5+ messages in thread
From: Peter Maydell @ 2016-08-29 22:41 UTC (permalink / raw)
To: Andrey Yurovsky; +Cc: QEMU Developers
On 29 August 2016 at 18:36, Andrey Yurovsky <yurovsky@gmail.com> wrote:
> From: Andrey Yurovsky <yurovsky@gmail.com>
>
> Add the "cortex-a7" CPU with features and registers matching the Cortex-A7
> MPCore Technical Reference Manual and the Cortex-A7 Floating-Point Unit
> Technical Reference Manual. The A7 is very similar to the A15.
>
> Tested via the "virt" machine.
>
> Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
No particular objection, but what's your use case for this
where just using cortex-a15 wouldn't do?
(Will review more carefully later.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH] arm: add Cortex A7 CPU parameters
2016-08-29 22:41 ` Peter Maydell
@ 2016-08-29 22:53 ` Andrey Yurovsky
0 siblings, 0 replies; 5+ messages in thread
From: Andrey Yurovsky @ 2016-08-29 22:53 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Developers
On Mon, Aug 29, 2016 at 3:41 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 29 August 2016 at 18:36, Andrey Yurovsky <yurovsky@gmail.com> wrote:
>> From: Andrey Yurovsky <yurovsky@gmail.com>
>>
>> Add the "cortex-a7" CPU with features and registers matching the Cortex-A7
>> MPCore Technical Reference Manual and the Cortex-A7 Floating-Point Unit
>> Technical Reference Manual. The A7 is very similar to the A15.
>>
>> Tested via the "virt" machine.
>>
>> Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
>
> No particular objection, but what's your use case for this
> where just using cortex-a15 wouldn't do?
I'm working on i.MX7 emulation and wanted to add the A7 as a known CPU
before introducing a machine that would have an A7 on it, otherwise
it's very similar to the A15 though the registers in this patch will
reflect some feature differences.
> (Will review more carefully later.)
Thank you.
^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <CAFEAcA8fD-njRzu3rY9LS1LucHExGG2f0q0FFBLu0jUxaWJU-g@mail.gmail.com>]
* [Qemu-devel] [PATCH] arm: add Cortex A7 CPU parameters
[not found] <CAFEAcA8fD-njRzu3rY9LS1LucHExGG2f0q0FFBLu0jUxaWJU-g@mail.gmail.com>
@ 2016-09-06 18:07 ` Andrey Yurovsky
2016-09-19 12:47 ` Peter Maydell
0 siblings, 1 reply; 5+ messages in thread
From: Andrey Yurovsky @ 2016-09-06 18:07 UTC (permalink / raw)
To: qemu-devel; +Cc: Andrey Yurovsky, peter.maydell
Add the "cortex-a7" CPU with features and registers matching the Cortex-A7
MPCore Technical Reference Manual and the Cortex-A7 Floating-Point Unit
Technical Reference Manual. The A7 is very similar to the A15.
Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index ce8b8f4..1b9540e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1129,6 +1129,51 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static void cortex_a7_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a7";
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
+ cpu->midr = 0x410fc075;
+ cpu->reset_fpsid = 0x41023075;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x11111111;
+ cpu->ctr = 0x84448003;
+ cpu->reset_sctlr = 0x00c50078;
+ cpu->id_pfr0 = 0x00001131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x02010555;
+ cpu->pmceid0 = 0x00000000;
+ cpu->pmceid1 = 0x00000000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10101105;
+ cpu->id_mmfr1 = 0x40000000;
+ cpu->id_mmfr2 = 0x01240000;
+ cpu->id_mmfr3 = 0x02102211;
+ cpu->id_isar0 = 0x01101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232041;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x10011142;
+ cpu->dbgdidr = 0x3515f005;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+ define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
+}
+
static void cortex_a15_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1385,6 +1430,7 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
+ { .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [Qemu-devel] [PATCH] arm: add Cortex A7 CPU parameters
2016-09-06 18:07 ` Andrey Yurovsky
@ 2016-09-19 12:47 ` Peter Maydell
0 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2016-09-19 12:47 UTC (permalink / raw)
To: Andrey Yurovsky; +Cc: QEMU Developers
On 6 September 2016 at 19:07, Andrey Yurovsky <yurovsky@gmail.com> wrote:
> Add the "cortex-a7" CPU with features and registers matching the Cortex-A7
> MPCore Technical Reference Manual and the Cortex-A7 Floating-Point Unit
> Technical Reference Manual. The A7 is very similar to the A15.
>
> Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-09-19 12:47 UTC | newest]
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2016-08-29 22:36 [Qemu-devel] [PATCH] arm: add Cortex A7 CPU parameters Andrey Yurovsky
2016-08-29 22:41 ` Peter Maydell
2016-08-29 22:53 ` Andrey Yurovsky
[not found] <CAFEAcA8fD-njRzu3rY9LS1LucHExGG2f0q0FFBLu0jUxaWJU-g@mail.gmail.com>
2016-09-06 18:07 ` Andrey Yurovsky
2016-09-19 12:47 ` Peter Maydell
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