* [PATCH v4 0/2] Xilinx Slave Serial FPGA Manager @ 2017-02-28 16:40 Anatolij Gustschin 2017-02-28 16:40 ` [PATCH v4 1/2] dt: bindings: fpga: add xilinx slave-serial binding description Anatolij Gustschin 2017-02-28 16:40 ` [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver Anatolij Gustschin 0 siblings, 2 replies; 13+ messages in thread From: Anatolij Gustschin @ 2017-02-28 16:40 UTC (permalink / raw) To: linux-fpga, linux-kernel, devicetree Cc: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland This series adds an FPGA manager driver for Xilinx Spartan6 FPGAs that can configure them using an SPI port and two GPIOs. Anatolij Gustschin (2): dt: bindings: fpga: add xilinx slave-serial binding description fpga manager: Add Xilinx slave serial SPI driver Changes in v4: - add Acked-by tags for DT bindings - increase program latency up to 7.5ms for other Xilinx FPGAs - continue to apply CCLK cycles until specified timeout elapses (to cover more possible configuration DONE scenarios) - apply 8 CCLK cycles afer DONE signal - rebased to apply on top of Kconfig/Makefile changes by queued fpga manager patches Changes in v3: - extend example to show the usage in SPI master node, connected to the fpga-region node - use named constant for udelay()/usleep_range() arguments - drop not needed .owner init - correct module licence (GPL v2) - fix build warning with newer gcc (in min() macro) Changes in v2: - corrected gpios properties and node name in example in DT binding document - rebased on v4.10 .../bindings/fpga/xilinx-slave-serial.txt | 44 +++++ drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/xilinx-spi.c | 198 +++++++++++++++++++++ 4 files changed, 250 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt create mode 100644 drivers/fpga/xilinx-spi.c -- 2.7.4 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v4 1/2] dt: bindings: fpga: add xilinx slave-serial binding description 2017-02-28 16:40 [PATCH v4 0/2] Xilinx Slave Serial FPGA Manager Anatolij Gustschin @ 2017-02-28 16:40 ` Anatolij Gustschin 2017-03-16 11:01 ` Michal Simek 2017-02-28 16:40 ` [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver Anatolij Gustschin 1 sibling, 1 reply; 13+ messages in thread From: Anatolij Gustschin @ 2017-02-28 16:40 UTC (permalink / raw) To: linux-fpga, linux-kernel, devicetree Cc: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland Add dt binding documentation details for Xilinx FPGA configuration over slave serial interface. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Moritz Fischer <mdf@kernel.org> Acked-by: Rob Herring <robh@kernel.org> --- Changes in v4: - add Acked-by tags Changes in v3: - extend example to show the usage in SPI master node, connected to the fpga-region node Changes in v2: - correct gpios properties in example to match above description - use fpga-mgr@0 instead of fpga-spi@0 in example .../bindings/fpga/xilinx-slave-serial.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt new file mode 100644 index 0000000..9766f74 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt @@ -0,0 +1,44 @@ +Xilinx Slave Serial SPI FPGA Manager + +Xilinx Spartan-6 FPGAs support a method of loading the bitstream over +what is referred to as "slave serial" interface. +The slave serial link is not technically SPI, and might require extra +circuits in order to play nicely with other SPI slaves on the same bus. + +See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf + +Required properties: +- compatible: should contain "xlnx,fpga-slave-serial" +- reg: spi chip select of the FPGA +- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual) +- done-gpios: config status pin (referred to as DONE in the manual) + +Example for full FPGA configuration: + + fpga-region0 { + compatible = "fpga-region"; + fpga-mgr = <&fpga_mgr_spi>; + #address-cells = <0x1>; + #size-cells = <0x1>; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "okay"; + + fpga_mgr_spi: fpga-mgr@0 { + compatible = "xlnx,fpga-slave-serial"; + spi-max-frequency = <60000000>; + spi-cpha; + reg = <0>; + done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; -- 2.7.4 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt: bindings: fpga: add xilinx slave-serial binding description @ 2017-03-16 11:01 ` Michal Simek 0 siblings, 0 replies; 13+ messages in thread From: Michal Simek @ 2017-03-16 11:01 UTC (permalink / raw) To: Anatolij Gustschin, linux-fpga, linux-kernel, devicetree Cc: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland [-- Attachment #1.1: Type: text/plain, Size: 2958 bytes --] On 28.2.2017 17:40, Anatolij Gustschin wrote: > Add dt binding documentation details for Xilinx FPGA configuration > over slave serial interface. > > Signed-off-by: Anatolij Gustschin <agust@denx.de> > Acked-by: Moritz Fischer <mdf@kernel.org> > Acked-by: Rob Herring <robh@kernel.org> > --- > Changes in v4: > > - add Acked-by tags > > Changes in v3: > > - extend example to show the usage in SPI master node, connected > to the fpga-region node > > Changes in v2: > > - correct gpios properties in example to match above description > > - use fpga-mgr@0 instead of fpga-spi@0 in example > > .../bindings/fpga/xilinx-slave-serial.txt | 44 ++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > new file mode 100644 > index 0000000..9766f74 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > @@ -0,0 +1,44 @@ > +Xilinx Slave Serial SPI FPGA Manager > + > +Xilinx Spartan-6 FPGAs support a method of loading the bitstream over > +what is referred to as "slave serial" interface. > +The slave serial link is not technically SPI, and might require extra > +circuits in order to play nicely with other SPI slaves on the same bus. > + > +See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf > + > +Required properties: > +- compatible: should contain "xlnx,fpga-slave-serial" > +- reg: spi chip select of the FPGA > +- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual) > +- done-gpios: config status pin (referred to as DONE in the manual) > + > +Example for full FPGA configuration: > + > + fpga-region0 { > + compatible = "fpga-region"; > + fpga-mgr = <&fpga_mgr_spi>; > + #address-cells = <0x1>; > + #size-cells = <0x1>; > + }; > + > + spi1: spi@10680 { > + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; > + pinctrl-0 = <&spi0_pins>; > + pinctrl-names = "default"; > + #address-cells = <1>; > + #size-cells = <0>; > + cell-index = <1>; > + interrupts = <92>; > + clocks = <&coreclk 0>; > + status = "okay"; > + > + fpga_mgr_spi: fpga-mgr@0 { > + compatible = "xlnx,fpga-slave-serial"; > + spi-max-frequency = <60000000>; > + spi-cpha; > + reg = <0>; > + done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; > + prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; > + }; > + }; > Acked-by: Michal Simek <michal.simek@xilinx.com> Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 198 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt: bindings: fpga: add xilinx slave-serial binding description @ 2017-03-16 11:01 ` Michal Simek 0 siblings, 0 replies; 13+ messages in thread From: Michal Simek @ 2017-03-16 11:01 UTC (permalink / raw) To: Anatolij Gustschin, linux-fpga-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA Cc: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland [-- Attachment #1.1: Type: text/plain, Size: 3066 bytes --] On 28.2.2017 17:40, Anatolij Gustschin wrote: > Add dt binding documentation details for Xilinx FPGA configuration > over slave serial interface. > > Signed-off-by: Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> > Acked-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> > Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> > --- > Changes in v4: > > - add Acked-by tags > > Changes in v3: > > - extend example to show the usage in SPI master node, connected > to the fpga-region node > > Changes in v2: > > - correct gpios properties in example to match above description > > - use fpga-mgr@0 instead of fpga-spi@0 in example > > .../bindings/fpga/xilinx-slave-serial.txt | 44 ++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > new file mode 100644 > index 0000000..9766f74 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt > @@ -0,0 +1,44 @@ > +Xilinx Slave Serial SPI FPGA Manager > + > +Xilinx Spartan-6 FPGAs support a method of loading the bitstream over > +what is referred to as "slave serial" interface. > +The slave serial link is not technically SPI, and might require extra > +circuits in order to play nicely with other SPI slaves on the same bus. > + > +See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf > + > +Required properties: > +- compatible: should contain "xlnx,fpga-slave-serial" > +- reg: spi chip select of the FPGA > +- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual) > +- done-gpios: config status pin (referred to as DONE in the manual) > + > +Example for full FPGA configuration: > + > + fpga-region0 { > + compatible = "fpga-region"; > + fpga-mgr = <&fpga_mgr_spi>; > + #address-cells = <0x1>; > + #size-cells = <0x1>; > + }; > + > + spi1: spi@10680 { > + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; > + pinctrl-0 = <&spi0_pins>; > + pinctrl-names = "default"; > + #address-cells = <1>; > + #size-cells = <0>; > + cell-index = <1>; > + interrupts = <92>; > + clocks = <&coreclk 0>; > + status = "okay"; > + > + fpga_mgr_spi: fpga-mgr@0 { > + compatible = "xlnx,fpga-slave-serial"; > + spi-max-frequency = <60000000>; > + spi-cpha; > + reg = <0>; > + done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; > + prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; > + }; > + }; > Acked-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 198 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt: bindings: fpga: add xilinx slave-serial binding description @ 2017-03-23 23:56 ` Alan Tull 0 siblings, 0 replies; 13+ messages in thread From: Alan Tull @ 2017-03-23 23:56 UTC (permalink / raw) To: Michal Simek Cc: Anatolij Gustschin, linux-fpga, linux-kernel, devicetree, Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland On Thu, Mar 16, 2017 at 6:01 AM, Michal Simek <monstr@monstr.eu> wrote: > On 28.2.2017 17:40, Anatolij Gustschin wrote: >> Add dt binding documentation details for Xilinx FPGA configuration >> over slave serial interface. >> >> Signed-off-by: Anatolij Gustschin <agust@denx.de> >> Acked-by: Moritz Fischer <mdf@kernel.org> >> Acked-by: Rob Herring <robh@kernel.org> >> --- >> Changes in v4: >> >> - add Acked-by tags >> >> Changes in v3: >> >> - extend example to show the usage in SPI master node, connected >> to the fpga-region node >> >> Changes in v2: >> >> - correct gpios properties in example to match above description >> >> - use fpga-mgr@0 instead of fpga-spi@0 in example >> >> .../bindings/fpga/xilinx-slave-serial.txt | 44 ++++++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt >> >> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt >> new file mode 100644 >> index 0000000..9766f74 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt >> @@ -0,0 +1,44 @@ >> +Xilinx Slave Serial SPI FPGA Manager >> + >> +Xilinx Spartan-6 FPGAs support a method of loading the bitstream over >> +what is referred to as "slave serial" interface. >> +The slave serial link is not technically SPI, and might require extra >> +circuits in order to play nicely with other SPI slaves on the same bus. >> + >> +See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf >> + >> +Required properties: >> +- compatible: should contain "xlnx,fpga-slave-serial" >> +- reg: spi chip select of the FPGA >> +- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual) >> +- done-gpios: config status pin (referred to as DONE in the manual) >> + >> +Example for full FPGA configuration: >> + >> + fpga-region0 { >> + compatible = "fpga-region"; >> + fpga-mgr = <&fpga_mgr_spi>; >> + #address-cells = <0x1>; >> + #size-cells = <0x1>; >> + }; >> + >> + spi1: spi@10680 { >> + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; >> + pinctrl-0 = <&spi0_pins>; >> + pinctrl-names = "default"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + cell-index = <1>; >> + interrupts = <92>; >> + clocks = <&coreclk 0>; >> + status = "okay"; >> + >> + fpga_mgr_spi: fpga-mgr@0 { >> + compatible = "xlnx,fpga-slave-serial"; >> + spi-max-frequency = <60000000>; >> + spi-cpha; >> + reg = <0>; >> + done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; >> + prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; >> + }; >> + }; >> > > Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Alan Tull <atull@kernel.org> > > Thanks, > Michal > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Xilinx Microblaze > Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs > U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs > > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 1/2] dt: bindings: fpga: add xilinx slave-serial binding description @ 2017-03-23 23:56 ` Alan Tull 0 siblings, 0 replies; 13+ messages in thread From: Alan Tull @ 2017-03-23 23:56 UTC (permalink / raw) To: Michal Simek Cc: Anatolij Gustschin, linux-fpga-u79uwXL29TY76Z2rM5mHXA, linux-kernel, devicetree-u79uwXL29TY76Z2rM5mHXA, Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland On Thu, Mar 16, 2017 at 6:01 AM, Michal Simek <monstr-pSz03upnqPeHXe+LvDLADg@public.gmane.org> wrote: > On 28.2.2017 17:40, Anatolij Gustschin wrote: >> Add dt binding documentation details for Xilinx FPGA configuration >> over slave serial interface. >> >> Signed-off-by: Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> >> Acked-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> >> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> >> --- >> Changes in v4: >> >> - add Acked-by tags >> >> Changes in v3: >> >> - extend example to show the usage in SPI master node, connected >> to the fpga-region node >> >> Changes in v2: >> >> - correct gpios properties in example to match above description >> >> - use fpga-mgr@0 instead of fpga-spi@0 in example >> >> .../bindings/fpga/xilinx-slave-serial.txt | 44 ++++++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt >> >> diff --git a/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt >> new file mode 100644 >> index 0000000..9766f74 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/fpga/xilinx-slave-serial.txt >> @@ -0,0 +1,44 @@ >> +Xilinx Slave Serial SPI FPGA Manager >> + >> +Xilinx Spartan-6 FPGAs support a method of loading the bitstream over >> +what is referred to as "slave serial" interface. >> +The slave serial link is not technically SPI, and might require extra >> +circuits in order to play nicely with other SPI slaves on the same bus. >> + >> +See https://www.xilinx.com/support/documentation/user_guides/ug380.pdf >> + >> +Required properties: >> +- compatible: should contain "xlnx,fpga-slave-serial" >> +- reg: spi chip select of the FPGA >> +- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual) >> +- done-gpios: config status pin (referred to as DONE in the manual) >> + >> +Example for full FPGA configuration: >> + >> + fpga-region0 { >> + compatible = "fpga-region"; >> + fpga-mgr = <&fpga_mgr_spi>; >> + #address-cells = <0x1>; >> + #size-cells = <0x1>; >> + }; >> + >> + spi1: spi@10680 { >> + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; >> + pinctrl-0 = <&spi0_pins>; >> + pinctrl-names = "default"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + cell-index = <1>; >> + interrupts = <92>; >> + clocks = <&coreclk 0>; >> + status = "okay"; >> + >> + fpga_mgr_spi: fpga-mgr@0 { >> + compatible = "xlnx,fpga-slave-serial"; >> + spi-max-frequency = <60000000>; >> + spi-cpha; >> + reg = <0>; >> + done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; >> + prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; >> + }; >> + }; >> > > Acked-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> Acked-by: Alan Tull <atull-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> > > Thanks, > Michal > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Xilinx Microblaze > Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs > U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs > > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver 2017-02-28 16:40 [PATCH v4 0/2] Xilinx Slave Serial FPGA Manager Anatolij Gustschin 2017-02-28 16:40 ` [PATCH v4 1/2] dt: bindings: fpga: add xilinx slave-serial binding description Anatolij Gustschin @ 2017-02-28 16:40 ` Anatolij Gustschin 2017-03-16 11:01 ` Michal Simek 2017-03-16 14:58 ` Moritz Fischer 1 sibling, 2 replies; 13+ messages in thread From: Anatolij Gustschin @ 2017-02-28 16:40 UTC (permalink / raw) To: linux-fpga, linux-kernel, devicetree Cc: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland The driver loads FPGA firmware over SPI, using the "slave serial" configuration interface on Xilinx FPGAs. Signed-off-by: Anatolij Gustschin <agust@denx.de> --- This patch requires patch https://lkml.org/lkml/2017/2/15/667 for building Changes in v4: - increase program latency up to 7.5ms for other Xilinx FPGAs - continue to apply CCLK cycles until specified timeout elapses (to cover more possible configuration DONE scenarios) - apply 8 CCLK cycles afer DONE signal - rebased to apply on top of Kconfig/Makefile changes by queued fpga manager patches Changes in v3: - use named constant for udelay()/usleep_range() arguments - drop not needed .owner init - correct module licence (GPL v2) - fix build warning with newer gcc (in min() macro) Changes in v2: - rebased on v4.10 drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/xilinx-spi.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 206 insertions(+) create mode 100644 drivers/fpga/xilinx-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index dee470f..c81cb7d 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -46,6 +46,13 @@ config FPGA_MGR_TS73XX FPGA manager driver support for the Altera Cyclone II FPGA present on the TS-73xx SBC boards. +config FPGA_MGR_XILINX_SPI + tristate "Xilinx Configuration over Slave Serial (SPI)" + depends on SPI + help + FPGA manager driver support for Xilinx FPGA configuration + over slave serial interface. + config FPGA_MGR_ZYNQ_FPGA tristate "Xilinx Zynq FPGA" depends on ARCH_ZYNQ || COMPILE_TEST diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index a5ee3ff..c6f5d74 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o +obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o # FPGA Bridge Drivers diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c new file mode 100644 index 0000000..9b62a4c --- /dev/null +++ b/drivers/fpga/xilinx-spi.c @@ -0,0 +1,198 @@ +/* + * Xilinx Spartan6 Slave Serial SPI Driver + * + * Copyright (C) 2017 DENX Software Engineering + * + * Anatolij Gustschin <agust@denx.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * Manage Xilinx FPGA firmware that is loaded over SPI using + * the slave serial configuration interface. + */ + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/of.h> +#include <linux/spi/spi.h> +#include <linux/sizes.h> + +struct xilinx_spi_conf { + struct spi_device *spi; + struct gpio_desc *prog_b; + struct gpio_desc *done; +}; + +static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) +{ + struct xilinx_spi_conf *conf = mgr->priv; + + if (!gpiod_get_value(conf->done)) + return FPGA_MGR_STATE_RESET; + + return FPGA_MGR_STATE_UNKNOWN; +} + +static int xilinx_spi_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct xilinx_spi_conf *conf = mgr->priv; + const size_t prog_latency_7500us = 7500; + const size_t prog_pulse_1us = 1; + + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); + return -EINVAL; + } + + gpiod_set_value(conf->prog_b, 1); + + udelay(prog_pulse_1us); /* min is 500 ns */ + + gpiod_set_value(conf->prog_b, 0); + + if (gpiod_get_value(conf->done)) { + dev_err(&mgr->dev, "Unexpected DONE pin state...\n"); + return -EIO; + } + + /* program latency */ + usleep_range(prog_latency_7500us, prog_latency_7500us + 100); + return 0; +} + +static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct xilinx_spi_conf *conf = mgr->priv; + const char *fw_data = buf; + const char *fw_data_end = fw_data + count; + + while (fw_data < fw_data_end) { + size_t remaining, stride; + int ret; + + remaining = fw_data_end - fw_data; + stride = min_t(size_t, remaining, SZ_4K); + + ret = spi_write(conf->spi, fw_data, stride); + if (ret) { + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", + ret); + return ret; + } + fw_data += stride; + } + + return 0; +} + +static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf) +{ + struct spi_device *spi = conf->spi; + const u8 din_data[1] = { 0xff }; + int ret; + + ret = spi_write(conf->spi, din_data, sizeof(din_data)); + if (ret) + dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret); + + return ret; +} + +static int xilinx_spi_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct xilinx_spi_conf *conf = mgr->priv; + unsigned long timeout; + int ret; + + if (gpiod_get_value(conf->done)) + return xilinx_spi_apply_cclk_cycles(conf); + + timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us); + + while (time_before(jiffies, timeout)) { + + ret = xilinx_spi_apply_cclk_cycles(conf); + if (ret) + return ret; + + if (gpiod_get_value(conf->done)) + return xilinx_spi_apply_cclk_cycles(conf); + } + + dev_err(&mgr->dev, "Timeout after config data transfer.\n"); + return -ETIMEDOUT; +} + +static const struct fpga_manager_ops xilinx_spi_ops = { + .state = xilinx_spi_state, + .write_init = xilinx_spi_write_init, + .write = xilinx_spi_write, + .write_complete = xilinx_spi_write_complete, +}; + +static int xilinx_spi_probe(struct spi_device *spi) +{ + struct xilinx_spi_conf *conf; + + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); + if (!conf) + return -ENOMEM; + + conf->spi = spi; + + /* PROGRAM_B is active low */ + conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW); + if (IS_ERR(conf->prog_b)) { + dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n", + PTR_ERR(conf->prog_b)); + return PTR_ERR(conf->prog_b); + } + + conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN); + if (IS_ERR(conf->done)) { + dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n", + PTR_ERR(conf->done)); + return PTR_ERR(conf->done); + } + + return fpga_mgr_register(&spi->dev, "Xilinx Slave Serial FPGA Manager", + &xilinx_spi_ops, conf); +} + +static int xilinx_spi_remove(struct spi_device *spi) +{ + fpga_mgr_unregister(&spi->dev); + + return 0; +} + +static const struct of_device_id xlnx_spi_of_match[] = { + { .compatible = "xlnx,fpga-slave-serial", }, + {} +}; +MODULE_DEVICE_TABLE(of, xlnx_spi_of_match); + +static struct spi_driver xilinx_slave_spi_driver = { + .driver = { + .name = "xlnx-slave-spi", + .of_match_table = of_match_ptr(xlnx_spi_of_match), + }, + .probe = xilinx_spi_probe, + .remove = xilinx_spi_remove, +}; + +module_spi_driver(xilinx_slave_spi_driver) + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>"); +MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI"); -- 2.7.4 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver @ 2017-03-16 11:01 ` Michal Simek 0 siblings, 0 replies; 13+ messages in thread From: Michal Simek @ 2017-03-16 11:01 UTC (permalink / raw) To: Anatolij Gustschin, linux-fpga, linux-kernel, devicetree Cc: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland [-- Attachment #1.1: Type: text/plain, Size: 8515 bytes --] On 28.2.2017 17:40, Anatolij Gustschin wrote: > The driver loads FPGA firmware over SPI, using the "slave serial" > configuration interface on Xilinx FPGAs. > > Signed-off-by: Anatolij Gustschin <agust@denx.de> > --- > This patch requires patch https://lkml.org/lkml/2017/2/15/667 > for building > > Changes in v4: > > - increase program latency up to 7.5ms for other Xilinx FPGAs > - continue to apply CCLK cycles until specified timeout elapses (to > cover more possible configuration DONE scenarios) > - apply 8 CCLK cycles afer DONE signal > - rebased to apply on top of Kconfig/Makefile changes by queued > fpga manager patches > > Changes in v3: > > - use named constant for udelay()/usleep_range() arguments > - drop not needed .owner init > - correct module licence (GPL v2) > - fix build warning with newer gcc (in min() macro) > > Changes in v2: > > - rebased on v4.10 > > drivers/fpga/Kconfig | 7 ++ > drivers/fpga/Makefile | 1 + > drivers/fpga/xilinx-spi.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 206 insertions(+) > create mode 100644 drivers/fpga/xilinx-spi.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index dee470f..c81cb7d 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -46,6 +46,13 @@ config FPGA_MGR_TS73XX > FPGA manager driver support for the Altera Cyclone II FPGA > present on the TS-73xx SBC boards. > > +config FPGA_MGR_XILINX_SPI > + tristate "Xilinx Configuration over Slave Serial (SPI)" > + depends on SPI > + help > + FPGA manager driver support for Xilinx FPGA configuration > + over slave serial interface. > + > config FPGA_MGR_ZYNQ_FPGA > tristate "Xilinx Zynq FPGA" > depends on ARCH_ZYNQ || COMPILE_TEST > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index a5ee3ff..c6f5d74 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o > obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > +obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > # FPGA Bridge Drivers > diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c > new file mode 100644 > index 0000000..9b62a4c > --- /dev/null > +++ b/drivers/fpga/xilinx-spi.c > @@ -0,0 +1,198 @@ > +/* > + * Xilinx Spartan6 Slave Serial SPI Driver > + * > + * Copyright (C) 2017 DENX Software Engineering > + * > + * Anatolij Gustschin <agust@denx.de> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * Manage Xilinx FPGA firmware that is loaded over SPI using > + * the slave serial configuration interface. > + */ > + > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/gpio/consumer.h> > +#include <linux/module.h> > +#include <linux/mod_devicetable.h> > +#include <linux/of.h> > +#include <linux/spi/spi.h> > +#include <linux/sizes.h> > + > +struct xilinx_spi_conf { > + struct spi_device *spi; > + struct gpio_desc *prog_b; > + struct gpio_desc *done; > +}; > + > +static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + > + if (!gpiod_get_value(conf->done)) > + return FPGA_MGR_STATE_RESET; > + > + return FPGA_MGR_STATE_UNKNOWN; > +} > + > +static int xilinx_spi_write_init(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + const size_t prog_latency_7500us = 7500; > + const size_t prog_pulse_1us = 1; > + > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > + dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); > + return -EINVAL; > + } > + > + gpiod_set_value(conf->prog_b, 1); > + > + udelay(prog_pulse_1us); /* min is 500 ns */ > + > + gpiod_set_value(conf->prog_b, 0); > + > + if (gpiod_get_value(conf->done)) { > + dev_err(&mgr->dev, "Unexpected DONE pin state...\n"); > + return -EIO; > + } > + > + /* program latency */ > + usleep_range(prog_latency_7500us, prog_latency_7500us + 100); > + return 0; > +} > + > +static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf, > + size_t count) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + const char *fw_data = buf; > + const char *fw_data_end = fw_data + count; > + > + while (fw_data < fw_data_end) { > + size_t remaining, stride; > + int ret; > + > + remaining = fw_data_end - fw_data; > + stride = min_t(size_t, remaining, SZ_4K); > + > + ret = spi_write(conf->spi, fw_data, stride); > + if (ret) { > + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", > + ret); > + return ret; > + } > + fw_data += stride; > + } > + > + return 0; > +} > + > +static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf) > +{ > + struct spi_device *spi = conf->spi; > + const u8 din_data[1] = { 0xff }; > + int ret; > + > + ret = spi_write(conf->spi, din_data, sizeof(din_data)); > + if (ret) > + dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret); > + > + return ret; > +} > + > +static int xilinx_spi_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + unsigned long timeout; > + int ret; > + > + if (gpiod_get_value(conf->done)) > + return xilinx_spi_apply_cclk_cycles(conf); > + > + timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us); > + > + while (time_before(jiffies, timeout)) { > + > + ret = xilinx_spi_apply_cclk_cycles(conf); > + if (ret) > + return ret; > + > + if (gpiod_get_value(conf->done)) > + return xilinx_spi_apply_cclk_cycles(conf); > + } > + > + dev_err(&mgr->dev, "Timeout after config data transfer.\n"); > + return -ETIMEDOUT; > +} > + > +static const struct fpga_manager_ops xilinx_spi_ops = { > + .state = xilinx_spi_state, > + .write_init = xilinx_spi_write_init, > + .write = xilinx_spi_write, > + .write_complete = xilinx_spi_write_complete, > +}; > + > +static int xilinx_spi_probe(struct spi_device *spi) > +{ > + struct xilinx_spi_conf *conf; > + > + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); > + if (!conf) > + return -ENOMEM; > + > + conf->spi = spi; > + > + /* PROGRAM_B is active low */ > + conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW); > + if (IS_ERR(conf->prog_b)) { > + dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n", > + PTR_ERR(conf->prog_b)); > + return PTR_ERR(conf->prog_b); > + } > + > + conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN); > + if (IS_ERR(conf->done)) { > + dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n", > + PTR_ERR(conf->done)); > + return PTR_ERR(conf->done); > + } > + > + return fpga_mgr_register(&spi->dev, "Xilinx Slave Serial FPGA Manager", > + &xilinx_spi_ops, conf); > +} > + > +static int xilinx_spi_remove(struct spi_device *spi) > +{ > + fpga_mgr_unregister(&spi->dev); > + > + return 0; > +} > + > +static const struct of_device_id xlnx_spi_of_match[] = { > + { .compatible = "xlnx,fpga-slave-serial", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, xlnx_spi_of_match); > + > +static struct spi_driver xilinx_slave_spi_driver = { > + .driver = { > + .name = "xlnx-slave-spi", > + .of_match_table = of_match_ptr(xlnx_spi_of_match), > + }, > + .probe = xilinx_spi_probe, > + .remove = xilinx_spi_remove, > +}; > + > +module_spi_driver(xilinx_slave_spi_driver) > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>"); > +MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI"); > Acked-by: Michal Simek <michal.simek@xilinx.com> Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 198 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver @ 2017-03-16 11:01 ` Michal Simek 0 siblings, 0 replies; 13+ messages in thread From: Michal Simek @ 2017-03-16 11:01 UTC (permalink / raw) To: Anatolij Gustschin, linux-fpga-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA Cc: Alan Tull, Moritz Fischer, Rob Herring, Mark Rutland [-- Attachment #1.1: Type: text/plain, Size: 8607 bytes --] On 28.2.2017 17:40, Anatolij Gustschin wrote: > The driver loads FPGA firmware over SPI, using the "slave serial" > configuration interface on Xilinx FPGAs. > > Signed-off-by: Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> > --- > This patch requires patch https://lkml.org/lkml/2017/2/15/667 > for building > > Changes in v4: > > - increase program latency up to 7.5ms for other Xilinx FPGAs > - continue to apply CCLK cycles until specified timeout elapses (to > cover more possible configuration DONE scenarios) > - apply 8 CCLK cycles afer DONE signal > - rebased to apply on top of Kconfig/Makefile changes by queued > fpga manager patches > > Changes in v3: > > - use named constant for udelay()/usleep_range() arguments > - drop not needed .owner init > - correct module licence (GPL v2) > - fix build warning with newer gcc (in min() macro) > > Changes in v2: > > - rebased on v4.10 > > drivers/fpga/Kconfig | 7 ++ > drivers/fpga/Makefile | 1 + > drivers/fpga/xilinx-spi.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 206 insertions(+) > create mode 100644 drivers/fpga/xilinx-spi.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index dee470f..c81cb7d 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -46,6 +46,13 @@ config FPGA_MGR_TS73XX > FPGA manager driver support for the Altera Cyclone II FPGA > present on the TS-73xx SBC boards. > > +config FPGA_MGR_XILINX_SPI > + tristate "Xilinx Configuration over Slave Serial (SPI)" > + depends on SPI > + help > + FPGA manager driver support for Xilinx FPGA configuration > + over slave serial interface. > + > config FPGA_MGR_ZYNQ_FPGA > tristate "Xilinx Zynq FPGA" > depends on ARCH_ZYNQ || COMPILE_TEST > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index a5ee3ff..c6f5d74 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o > obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > +obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > # FPGA Bridge Drivers > diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c > new file mode 100644 > index 0000000..9b62a4c > --- /dev/null > +++ b/drivers/fpga/xilinx-spi.c > @@ -0,0 +1,198 @@ > +/* > + * Xilinx Spartan6 Slave Serial SPI Driver > + * > + * Copyright (C) 2017 DENX Software Engineering > + * > + * Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * Manage Xilinx FPGA firmware that is loaded over SPI using > + * the slave serial configuration interface. > + */ > + > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/gpio/consumer.h> > +#include <linux/module.h> > +#include <linux/mod_devicetable.h> > +#include <linux/of.h> > +#include <linux/spi/spi.h> > +#include <linux/sizes.h> > + > +struct xilinx_spi_conf { > + struct spi_device *spi; > + struct gpio_desc *prog_b; > + struct gpio_desc *done; > +}; > + > +static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + > + if (!gpiod_get_value(conf->done)) > + return FPGA_MGR_STATE_RESET; > + > + return FPGA_MGR_STATE_UNKNOWN; > +} > + > +static int xilinx_spi_write_init(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + const size_t prog_latency_7500us = 7500; > + const size_t prog_pulse_1us = 1; > + > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > + dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); > + return -EINVAL; > + } > + > + gpiod_set_value(conf->prog_b, 1); > + > + udelay(prog_pulse_1us); /* min is 500 ns */ > + > + gpiod_set_value(conf->prog_b, 0); > + > + if (gpiod_get_value(conf->done)) { > + dev_err(&mgr->dev, "Unexpected DONE pin state...\n"); > + return -EIO; > + } > + > + /* program latency */ > + usleep_range(prog_latency_7500us, prog_latency_7500us + 100); > + return 0; > +} > + > +static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf, > + size_t count) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + const char *fw_data = buf; > + const char *fw_data_end = fw_data + count; > + > + while (fw_data < fw_data_end) { > + size_t remaining, stride; > + int ret; > + > + remaining = fw_data_end - fw_data; > + stride = min_t(size_t, remaining, SZ_4K); > + > + ret = spi_write(conf->spi, fw_data, stride); > + if (ret) { > + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", > + ret); > + return ret; > + } > + fw_data += stride; > + } > + > + return 0; > +} > + > +static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf) > +{ > + struct spi_device *spi = conf->spi; > + const u8 din_data[1] = { 0xff }; > + int ret; > + > + ret = spi_write(conf->spi, din_data, sizeof(din_data)); > + if (ret) > + dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret); > + > + return ret; > +} > + > +static int xilinx_spi_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + unsigned long timeout; > + int ret; > + > + if (gpiod_get_value(conf->done)) > + return xilinx_spi_apply_cclk_cycles(conf); > + > + timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us); > + > + while (time_before(jiffies, timeout)) { > + > + ret = xilinx_spi_apply_cclk_cycles(conf); > + if (ret) > + return ret; > + > + if (gpiod_get_value(conf->done)) > + return xilinx_spi_apply_cclk_cycles(conf); > + } > + > + dev_err(&mgr->dev, "Timeout after config data transfer.\n"); > + return -ETIMEDOUT; > +} > + > +static const struct fpga_manager_ops xilinx_spi_ops = { > + .state = xilinx_spi_state, > + .write_init = xilinx_spi_write_init, > + .write = xilinx_spi_write, > + .write_complete = xilinx_spi_write_complete, > +}; > + > +static int xilinx_spi_probe(struct spi_device *spi) > +{ > + struct xilinx_spi_conf *conf; > + > + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); > + if (!conf) > + return -ENOMEM; > + > + conf->spi = spi; > + > + /* PROGRAM_B is active low */ > + conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW); > + if (IS_ERR(conf->prog_b)) { > + dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n", > + PTR_ERR(conf->prog_b)); > + return PTR_ERR(conf->prog_b); > + } > + > + conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN); > + if (IS_ERR(conf->done)) { > + dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n", > + PTR_ERR(conf->done)); > + return PTR_ERR(conf->done); > + } > + > + return fpga_mgr_register(&spi->dev, "Xilinx Slave Serial FPGA Manager", > + &xilinx_spi_ops, conf); > +} > + > +static int xilinx_spi_remove(struct spi_device *spi) > +{ > + fpga_mgr_unregister(&spi->dev); > + > + return 0; > +} > + > +static const struct of_device_id xlnx_spi_of_match[] = { > + { .compatible = "xlnx,fpga-slave-serial", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, xlnx_spi_of_match); > + > +static struct spi_driver xilinx_slave_spi_driver = { > + .driver = { > + .name = "xlnx-slave-spi", > + .of_match_table = of_match_ptr(xlnx_spi_of_match), > + }, > + .probe = xilinx_spi_probe, > + .remove = xilinx_spi_remove, > +}; > + > +module_spi_driver(xilinx_slave_spi_driver) > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org>"); > +MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI"); > Acked-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 198 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver @ 2017-03-16 14:58 ` Moritz Fischer 0 siblings, 0 replies; 13+ messages in thread From: Moritz Fischer @ 2017-03-16 14:58 UTC (permalink / raw) To: Anatolij Gustschin Cc: linux-fpga, Linux Kernel Mailing List, Devicetree List, Alan Tull, Rob Herring, Mark Rutland On Tue, Feb 28, 2017 at 8:40 AM, Anatolij Gustschin <agust@denx.de> wrote: > The driver loads FPGA firmware over SPI, using the "slave serial" > configuration interface on Xilinx FPGAs. > > Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Moritz Fischer <mdf@kernel.org> > --- > This patch requires patch https://lkml.org/lkml/2017/2/15/667 > for building > > Changes in v4: > > - increase program latency up to 7.5ms for other Xilinx FPGAs > - continue to apply CCLK cycles until specified timeout elapses (to > cover more possible configuration DONE scenarios) > - apply 8 CCLK cycles afer DONE signal > - rebased to apply on top of Kconfig/Makefile changes by queued > fpga manager patches > > Changes in v3: > > - use named constant for udelay()/usleep_range() arguments > - drop not needed .owner init > - correct module licence (GPL v2) > - fix build warning with newer gcc (in min() macro) > > Changes in v2: > > - rebased on v4.10 > > drivers/fpga/Kconfig | 7 ++ > drivers/fpga/Makefile | 1 + > drivers/fpga/xilinx-spi.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 206 insertions(+) > create mode 100644 drivers/fpga/xilinx-spi.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index dee470f..c81cb7d 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -46,6 +46,13 @@ config FPGA_MGR_TS73XX > FPGA manager driver support for the Altera Cyclone II FPGA > present on the TS-73xx SBC boards. > > +config FPGA_MGR_XILINX_SPI > + tristate "Xilinx Configuration over Slave Serial (SPI)" > + depends on SPI > + help > + FPGA manager driver support for Xilinx FPGA configuration > + over slave serial interface. > + > config FPGA_MGR_ZYNQ_FPGA > tristate "Xilinx Zynq FPGA" > depends on ARCH_ZYNQ || COMPILE_TEST > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index a5ee3ff..c6f5d74 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o > obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > +obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > # FPGA Bridge Drivers > diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c > new file mode 100644 > index 0000000..9b62a4c > --- /dev/null > +++ b/drivers/fpga/xilinx-spi.c > @@ -0,0 +1,198 @@ > +/* > + * Xilinx Spartan6 Slave Serial SPI Driver > + * > + * Copyright (C) 2017 DENX Software Engineering > + * > + * Anatolij Gustschin <agust@denx.de> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * Manage Xilinx FPGA firmware that is loaded over SPI using > + * the slave serial configuration interface. > + */ > + > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/gpio/consumer.h> > +#include <linux/module.h> > +#include <linux/mod_devicetable.h> > +#include <linux/of.h> > +#include <linux/spi/spi.h> > +#include <linux/sizes.h> > + > +struct xilinx_spi_conf { > + struct spi_device *spi; > + struct gpio_desc *prog_b; > + struct gpio_desc *done; > +}; > + > +static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + > + if (!gpiod_get_value(conf->done)) > + return FPGA_MGR_STATE_RESET; > + > + return FPGA_MGR_STATE_UNKNOWN; > +} > + > +static int xilinx_spi_write_init(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + const size_t prog_latency_7500us = 7500; > + const size_t prog_pulse_1us = 1; > + > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > + dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); > + return -EINVAL; > + } > + > + gpiod_set_value(conf->prog_b, 1); > + > + udelay(prog_pulse_1us); /* min is 500 ns */ > + > + gpiod_set_value(conf->prog_b, 0); > + > + if (gpiod_get_value(conf->done)) { > + dev_err(&mgr->dev, "Unexpected DONE pin state...\n"); > + return -EIO; > + } > + > + /* program latency */ > + usleep_range(prog_latency_7500us, prog_latency_7500us + 100); > + return 0; > +} > + > +static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf, > + size_t count) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + const char *fw_data = buf; > + const char *fw_data_end = fw_data + count; > + > + while (fw_data < fw_data_end) { > + size_t remaining, stride; > + int ret; > + > + remaining = fw_data_end - fw_data; > + stride = min_t(size_t, remaining, SZ_4K); > + > + ret = spi_write(conf->spi, fw_data, stride); > + if (ret) { > + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", > + ret); > + return ret; > + } > + fw_data += stride; > + } > + > + return 0; > +} > + > +static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf) > +{ > + struct spi_device *spi = conf->spi; > + const u8 din_data[1] = { 0xff }; > + int ret; > + > + ret = spi_write(conf->spi, din_data, sizeof(din_data)); > + if (ret) > + dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret); > + > + return ret; > +} > + > +static int xilinx_spi_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + unsigned long timeout; > + int ret; > + > + if (gpiod_get_value(conf->done)) > + return xilinx_spi_apply_cclk_cycles(conf); > + > + timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us); > + > + while (time_before(jiffies, timeout)) { > + > + ret = xilinx_spi_apply_cclk_cycles(conf); > + if (ret) > + return ret; > + > + if (gpiod_get_value(conf->done)) > + return xilinx_spi_apply_cclk_cycles(conf); > + } > + > + dev_err(&mgr->dev, "Timeout after config data transfer.\n"); > + return -ETIMEDOUT; > +} > + > +static const struct fpga_manager_ops xilinx_spi_ops = { > + .state = xilinx_spi_state, > + .write_init = xilinx_spi_write_init, > + .write = xilinx_spi_write, > + .write_complete = xilinx_spi_write_complete, > +}; > + > +static int xilinx_spi_probe(struct spi_device *spi) > +{ > + struct xilinx_spi_conf *conf; > + > + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); > + if (!conf) > + return -ENOMEM; > + > + conf->spi = spi; > + > + /* PROGRAM_B is active low */ > + conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW); > + if (IS_ERR(conf->prog_b)) { > + dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n", > + PTR_ERR(conf->prog_b)); > + return PTR_ERR(conf->prog_b); > + } > + > + conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN); > + if (IS_ERR(conf->done)) { > + dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n", > + PTR_ERR(conf->done)); > + return PTR_ERR(conf->done); > + } > + > + return fpga_mgr_register(&spi->dev, "Xilinx Slave Serial FPGA Manager", > + &xilinx_spi_ops, conf); > +} > + > +static int xilinx_spi_remove(struct spi_device *spi) > +{ > + fpga_mgr_unregister(&spi->dev); > + > + return 0; > +} > + > +static const struct of_device_id xlnx_spi_of_match[] = { > + { .compatible = "xlnx,fpga-slave-serial", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, xlnx_spi_of_match); > + > +static struct spi_driver xilinx_slave_spi_driver = { > + .driver = { > + .name = "xlnx-slave-spi", > + .of_match_table = of_match_ptr(xlnx_spi_of_match), > + }, > + .probe = xilinx_spi_probe, > + .remove = xilinx_spi_remove, > +}; > + > +module_spi_driver(xilinx_slave_spi_driver) > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>"); > +MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI"); > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver @ 2017-03-16 14:58 ` Moritz Fischer 0 siblings, 0 replies; 13+ messages in thread From: Moritz Fischer @ 2017-03-16 14:58 UTC (permalink / raw) To: Anatolij Gustschin Cc: linux-fpga-u79uwXL29TY76Z2rM5mHXA, Linux Kernel Mailing List, Devicetree List, Alan Tull, Rob Herring, Mark Rutland On Tue, Feb 28, 2017 at 8:40 AM, Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> wrote: > The driver loads FPGA firmware over SPI, using the "slave serial" > configuration interface on Xilinx FPGAs. > > Signed-off-by: Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> Reviewed-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> > --- > This patch requires patch https://lkml.org/lkml/2017/2/15/667 > for building > > Changes in v4: > > - increase program latency up to 7.5ms for other Xilinx FPGAs > - continue to apply CCLK cycles until specified timeout elapses (to > cover more possible configuration DONE scenarios) > - apply 8 CCLK cycles afer DONE signal > - rebased to apply on top of Kconfig/Makefile changes by queued > fpga manager patches > > Changes in v3: > > - use named constant for udelay()/usleep_range() arguments > - drop not needed .owner init > - correct module licence (GPL v2) > - fix build warning with newer gcc (in min() macro) > > Changes in v2: > > - rebased on v4.10 > > drivers/fpga/Kconfig | 7 ++ > drivers/fpga/Makefile | 1 + > drivers/fpga/xilinx-spi.c | 198 ++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 206 insertions(+) > create mode 100644 drivers/fpga/xilinx-spi.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index dee470f..c81cb7d 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -46,6 +46,13 @@ config FPGA_MGR_TS73XX > FPGA manager driver support for the Altera Cyclone II FPGA > present on the TS-73xx SBC boards. > > +config FPGA_MGR_XILINX_SPI > + tristate "Xilinx Configuration over Slave Serial (SPI)" > + depends on SPI > + help > + FPGA manager driver support for Xilinx FPGA configuration > + over slave serial interface. > + > config FPGA_MGR_ZYNQ_FPGA > tristate "Xilinx Zynq FPGA" > depends on ARCH_ZYNQ || COMPILE_TEST > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index a5ee3ff..c6f5d74 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -10,6 +10,7 @@ obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o > obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o > obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > +obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > # FPGA Bridge Drivers > diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c > new file mode 100644 > index 0000000..9b62a4c > --- /dev/null > +++ b/drivers/fpga/xilinx-spi.c > @@ -0,0 +1,198 @@ > +/* > + * Xilinx Spartan6 Slave Serial SPI Driver > + * > + * Copyright (C) 2017 DENX Software Engineering > + * > + * Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * Manage Xilinx FPGA firmware that is loaded over SPI using > + * the slave serial configuration interface. > + */ > + > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/gpio/consumer.h> > +#include <linux/module.h> > +#include <linux/mod_devicetable.h> > +#include <linux/of.h> > +#include <linux/spi/spi.h> > +#include <linux/sizes.h> > + > +struct xilinx_spi_conf { > + struct spi_device *spi; > + struct gpio_desc *prog_b; > + struct gpio_desc *done; > +}; > + > +static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + > + if (!gpiod_get_value(conf->done)) > + return FPGA_MGR_STATE_RESET; > + > + return FPGA_MGR_STATE_UNKNOWN; > +} > + > +static int xilinx_spi_write_init(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + const size_t prog_latency_7500us = 7500; > + const size_t prog_pulse_1us = 1; > + > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > + dev_err(&mgr->dev, "Partial reconfiguration not supported.\n"); > + return -EINVAL; > + } > + > + gpiod_set_value(conf->prog_b, 1); > + > + udelay(prog_pulse_1us); /* min is 500 ns */ > + > + gpiod_set_value(conf->prog_b, 0); > + > + if (gpiod_get_value(conf->done)) { > + dev_err(&mgr->dev, "Unexpected DONE pin state...\n"); > + return -EIO; > + } > + > + /* program latency */ > + usleep_range(prog_latency_7500us, prog_latency_7500us + 100); > + return 0; > +} > + > +static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf, > + size_t count) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + const char *fw_data = buf; > + const char *fw_data_end = fw_data + count; > + > + while (fw_data < fw_data_end) { > + size_t remaining, stride; > + int ret; > + > + remaining = fw_data_end - fw_data; > + stride = min_t(size_t, remaining, SZ_4K); > + > + ret = spi_write(conf->spi, fw_data, stride); > + if (ret) { > + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", > + ret); > + return ret; > + } > + fw_data += stride; > + } > + > + return 0; > +} > + > +static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf) > +{ > + struct spi_device *spi = conf->spi; > + const u8 din_data[1] = { 0xff }; > + int ret; > + > + ret = spi_write(conf->spi, din_data, sizeof(din_data)); > + if (ret) > + dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret); > + > + return ret; > +} > + > +static int xilinx_spi_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + struct xilinx_spi_conf *conf = mgr->priv; > + unsigned long timeout; > + int ret; > + > + if (gpiod_get_value(conf->done)) > + return xilinx_spi_apply_cclk_cycles(conf); > + > + timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us); > + > + while (time_before(jiffies, timeout)) { > + > + ret = xilinx_spi_apply_cclk_cycles(conf); > + if (ret) > + return ret; > + > + if (gpiod_get_value(conf->done)) > + return xilinx_spi_apply_cclk_cycles(conf); > + } > + > + dev_err(&mgr->dev, "Timeout after config data transfer.\n"); > + return -ETIMEDOUT; > +} > + > +static const struct fpga_manager_ops xilinx_spi_ops = { > + .state = xilinx_spi_state, > + .write_init = xilinx_spi_write_init, > + .write = xilinx_spi_write, > + .write_complete = xilinx_spi_write_complete, > +}; > + > +static int xilinx_spi_probe(struct spi_device *spi) > +{ > + struct xilinx_spi_conf *conf; > + > + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); > + if (!conf) > + return -ENOMEM; > + > + conf->spi = spi; > + > + /* PROGRAM_B is active low */ > + conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW); > + if (IS_ERR(conf->prog_b)) { > + dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n", > + PTR_ERR(conf->prog_b)); > + return PTR_ERR(conf->prog_b); > + } > + > + conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN); > + if (IS_ERR(conf->done)) { > + dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n", > + PTR_ERR(conf->done)); > + return PTR_ERR(conf->done); > + } > + > + return fpga_mgr_register(&spi->dev, "Xilinx Slave Serial FPGA Manager", > + &xilinx_spi_ops, conf); > +} > + > +static int xilinx_spi_remove(struct spi_device *spi) > +{ > + fpga_mgr_unregister(&spi->dev); > + > + return 0; > +} > + > +static const struct of_device_id xlnx_spi_of_match[] = { > + { .compatible = "xlnx,fpga-slave-serial", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, xlnx_spi_of_match); > + > +static struct spi_driver xilinx_slave_spi_driver = { > + .driver = { > + .name = "xlnx-slave-spi", > + .of_match_table = of_match_ptr(xlnx_spi_of_match), > + }, > + .probe = xilinx_spi_probe, > + .remove = xilinx_spi_remove, > +}; > + > +module_spi_driver(xilinx_slave_spi_driver) > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org>"); > +MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI"); > -- > 2.7.4 > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver @ 2017-03-23 23:51 ` Alan Tull 0 siblings, 0 replies; 13+ messages in thread From: Alan Tull @ 2017-03-23 23:51 UTC (permalink / raw) To: Moritz Fischer Cc: Anatolij Gustschin, linux-fpga, Linux Kernel Mailing List, Devicetree List, Alan Tull, Rob Herring, Mark Rutland On Thu, Mar 16, 2017 at 9:58 AM, Moritz Fischer <mdf@kernel.org> wrote: > On Tue, Feb 28, 2017 at 8:40 AM, Anatolij Gustschin <agust@denx.de> wrote: >> The driver loads FPGA firmware over SPI, using the "slave serial" >> configuration interface on Xilinx FPGAs. >> >> Signed-off-by: Anatolij Gustschin <agust@denx.de> > Reviewed-by: Moritz Fischer <mdf@kernel.org> Acked-by: Alan Tull <atull@kernel.org> ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver @ 2017-03-23 23:51 ` Alan Tull 0 siblings, 0 replies; 13+ messages in thread From: Alan Tull @ 2017-03-23 23:51 UTC (permalink / raw) To: Moritz Fischer Cc: Anatolij Gustschin, linux-fpga-u79uwXL29TY76Z2rM5mHXA, Linux Kernel Mailing List, Devicetree List, Alan Tull, Rob Herring, Mark Rutland On Thu, Mar 16, 2017 at 9:58 AM, Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote: > On Tue, Feb 28, 2017 at 8:40 AM, Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> wrote: >> The driver loads FPGA firmware over SPI, using the "slave serial" >> configuration interface on Xilinx FPGAs. >> >> Signed-off-by: Anatolij Gustschin <agust-ynQEQJNshbs@public.gmane.org> > Reviewed-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> Acked-by: Alan Tull <atull-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-03-23 23:57 UTC | newest] Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-02-28 16:40 [PATCH v4 0/2] Xilinx Slave Serial FPGA Manager Anatolij Gustschin 2017-02-28 16:40 ` [PATCH v4 1/2] dt: bindings: fpga: add xilinx slave-serial binding description Anatolij Gustschin 2017-03-16 11:01 ` Michal Simek 2017-03-16 11:01 ` Michal Simek 2017-03-23 23:56 ` Alan Tull 2017-03-23 23:56 ` Alan Tull 2017-02-28 16:40 ` [PATCH v4 2/2] fpga manager: Add Xilinx slave serial SPI driver Anatolij Gustschin 2017-03-16 11:01 ` Michal Simek 2017-03-16 11:01 ` Michal Simek 2017-03-16 14:58 ` Moritz Fischer 2017-03-16 14:58 ` Moritz Fischer 2017-03-23 23:51 ` Alan Tull 2017-03-23 23:51 ` Alan Tull
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