* [PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used
@ 2018-06-15 6:45 Chunming Zhou
[not found] ` <20180615064542.16504-1-david1.zhou-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Chunming Zhou @ 2018-06-15 6:45 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w,
Marek.Olsak-5C7GfCeVMHo, Sean.Ryan-5C7GfCeVMHo, Chunming Zhou
PAGE_SIZE for start_alignment is far much than hw requirement,
And now, update to expereince value from window side.
Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 392dd24e83f5..d041dddaad0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
type = AMD_IP_BLOCK_TYPE_GFX;
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
- ib_size_alignment = 8;
+ ib_start_alignment = 32;
+ ib_size_alignment = 32;
break;
case AMDGPU_HW_IP_COMPUTE:
type = AMD_IP_BLOCK_TYPE_GFX;
for (i = 0; i < adev->gfx.num_compute_rings; i++)
ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
- ib_size_alignment = 8;
+ ib_start_alignment = 32;
+ ib_size_alignment = 32;
break;
case AMDGPU_HW_IP_DMA:
type = AMD_IP_BLOCK_TYPE_SDMA;
for (i = 0; i < adev->sdma.num_instances; i++)
ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
- ib_size_alignment = 1;
+ ib_start_alignment = 256;
+ ib_size_alignment = 4;
break;
case AMDGPU_HW_IP_UVD:
type = AMD_IP_BLOCK_TYPE_UVD;
for (i = 0; i < adev->uvd.num_uvd_inst; i++)
ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i);
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
- ib_size_alignment = 16;
+ ib_start_alignment = 64;
+ ib_size_alignment = 64;
break;
case AMDGPU_HW_IP_VCE:
type = AMD_IP_BLOCK_TYPE_VCE;
for (i = 0; i < adev->vce.num_rings; i++)
ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+ ib_start_alignment = 4;
ib_size_alignment = 1;
break;
case AMDGPU_HW_IP_UVD_ENC:
@@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
ring_mask |=
((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) <<
(j + i * adev->uvd.num_enc_rings));
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
- ib_size_alignment = 1;
+ ib_start_alignment = 64;
+ ib_size_alignment = 64;
break;
case AMDGPU_HW_IP_VCN_DEC:
type = AMD_IP_BLOCK_TYPE_VCN;
ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+ ib_start_alignment = 16;
ib_size_alignment = 16;
break;
case AMDGPU_HW_IP_VCN_ENC:
type = AMD_IP_BLOCK_TYPE_VCN;
for (i = 0; i < adev->vcn.num_enc_rings; i++)
ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i);
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+ ib_start_alignment = 64;
ib_size_alignment = 1;
break;
case AMDGPU_HW_IP_VCN_JPEG:
type = AMD_IP_BLOCK_TYPE_VCN;
ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
+ ib_start_alignment = 16;
ib_size_alignment = 16;
break;
default:
--
2.14.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used
[not found] ` <20180615064542.16504-1-david1.zhou-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-15 7:09 ` Christian König
[not found] ` <dd3006dc-203f-9fb8-b43f-14151f01127a-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Christian König @ 2018-06-15 7:09 UTC (permalink / raw)
To: Chunming Zhou, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Marek.Olsak-5C7GfCeVMHo, Sean.Ryan-5C7GfCeVMHo
Am 15.06.2018 um 08:45 schrieb Chunming Zhou:
> PAGE_SIZE for start_alignment is far much than hw requirement,
> And now, update to expereince value from window side.
>
> Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5
> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 392dd24e83f5..d041dddaad0c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
> type = AMD_IP_BLOCK_TYPE_GFX;
> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> - ib_size_alignment = 8;
> + ib_start_alignment = 32;
> + ib_size_alignment = 32;
> break;
> case AMDGPU_HW_IP_COMPUTE:
> type = AMD_IP_BLOCK_TYPE_GFX;
> for (i = 0; i < adev->gfx.num_compute_rings; i++)
> ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> - ib_size_alignment = 8;
> + ib_start_alignment = 32;
> + ib_size_alignment = 32;
> break;
> case AMDGPU_HW_IP_DMA:
> type = AMD_IP_BLOCK_TYPE_SDMA;
> for (i = 0; i < adev->sdma.num_instances; i++)
> ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> - ib_size_alignment = 1;
> + ib_start_alignment = 256;
> + ib_size_alignment = 4;
> break;
> case AMDGPU_HW_IP_UVD:
> type = AMD_IP_BLOCK_TYPE_UVD;
> for (i = 0; i < adev->uvd.num_uvd_inst; i++)
> ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i);
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> - ib_size_alignment = 16;
> + ib_start_alignment = 64;
> + ib_size_alignment = 64;
> break;
> case AMDGPU_HW_IP_VCE:
> type = AMD_IP_BLOCK_TYPE_VCE;
> for (i = 0; i < adev->vce.num_rings; i++)
> ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> + ib_start_alignment = 4;
> ib_size_alignment = 1;
> break;
> case AMDGPU_HW_IP_UVD_ENC:
> @@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
> ring_mask |=
> ((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) <<
> (j + i * adev->uvd.num_enc_rings));
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> - ib_size_alignment = 1;
> + ib_start_alignment = 64;
> + ib_size_alignment = 64;
> break;
> case AMDGPU_HW_IP_VCN_DEC:
> type = AMD_IP_BLOCK_TYPE_VCN;
> ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> + ib_start_alignment = 16;
> ib_size_alignment = 16;
> break;
> case AMDGPU_HW_IP_VCN_ENC:
> type = AMD_IP_BLOCK_TYPE_VCN;
> for (i = 0; i < adev->vcn.num_enc_rings; i++)
> ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i);
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> + ib_start_alignment = 64;
> ib_size_alignment = 1;
> break;
> case AMDGPU_HW_IP_VCN_JPEG:
> type = AMD_IP_BLOCK_TYPE_VCN;
> ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> + ib_start_alignment = 16;
> ib_size_alignment = 16;
> break;
> default:
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used
[not found] ` <dd3006dc-203f-9fb8-b43f-14151f01127a-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2018-06-15 7:16 ` Zhang, Jerry
[not found] ` <CY4PR12MB141405AC0D97B1A681203BC6FF7C0-rpdhrqHFk04b0eJBKAp/BwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Zhang, Jerry @ 2018-06-15 7:16 UTC (permalink / raw)
To: Koenig, Christian, Zhou, David(ChunMing),
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Olsak, Marek, Ryan, Sean
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of
> Christian K?nig
> Sent: Friday, June 15, 2018 15:09
> To: Zhou, David(ChunMing) <David1.Zhou@amd.com>; amd-
> gfx@lists.freedesktop.org
> Cc: Olsak, Marek <Marek.Olsak@amd.com>; Ryan, Sean <Sean.Ryan@amd.com>
> Subject: Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as
> windows used
>
> Am 15.06.2018 um 08:45 schrieb Chunming Zhou:
> > PAGE_SIZE for start_alignment is far much than hw requirement, And
> > now, update to expereince value from window side.
> >
> > Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5
> > Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
>
> Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Junwei Zhang <Jerry.Zhang@amd.com>
BTW, any issue it fixes?
Jerry
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28 ++++++++++++++---------
> -----
> > 1 file changed, 14 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > index 392dd24e83f5..d041dddaad0c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > @@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
> void *data, struct drm_file
> > type = AMD_IP_BLOCK_TYPE_GFX;
> > for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> > ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0)
> << i);
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > - ib_size_alignment = 8;
> > + ib_start_alignment = 32;
> > + ib_size_alignment = 32;
> > break;
> > case AMDGPU_HW_IP_COMPUTE:
> > type = AMD_IP_BLOCK_TYPE_GFX;
> > for (i = 0; i < adev->gfx.num_compute_rings; i++)
> > ring_mask |= ((adev->gfx.compute_ring[i].ready ?
> 1 : 0) << i);
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > - ib_size_alignment = 8;
> > + ib_start_alignment = 32;
> > + ib_size_alignment = 32;
> > break;
> > case AMDGPU_HW_IP_DMA:
> > type = AMD_IP_BLOCK_TYPE_SDMA;
> > for (i = 0; i < adev->sdma.num_instances; i++)
> > ring_mask |= ((adev-
> >sdma.instance[i].ring.ready ? 1 : 0) << i);
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > - ib_size_alignment = 1;
> > + ib_start_alignment = 256;
> > + ib_size_alignment = 4;
> > break;
> > case AMDGPU_HW_IP_UVD:
> > type = AMD_IP_BLOCK_TYPE_UVD;
> > for (i = 0; i < adev->uvd.num_uvd_inst; i++)
> > ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0)
> << i);
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > - ib_size_alignment = 16;
> > + ib_start_alignment = 64;
> > + ib_size_alignment = 64;
> > break;
> > case AMDGPU_HW_IP_VCE:
> > type = AMD_IP_BLOCK_TYPE_VCE;
> > for (i = 0; i < adev->vce.num_rings; i++)
> > ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) <<
> i);
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > + ib_start_alignment = 4;
> > ib_size_alignment = 1;
> > break;
> > case AMDGPU_HW_IP_UVD_ENC:
> > @@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
> void *data, struct drm_file
> > ring_mask |=
> > ((adev->uvd.inst[i].ring_enc[j].ready ? 1 :
> 0) <<
> > (j + i * adev->uvd.num_enc_rings));
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > - ib_size_alignment = 1;
> > + ib_start_alignment = 64;
> > + ib_size_alignment = 64;
> > break;
> > case AMDGPU_HW_IP_VCN_DEC:
> > type = AMD_IP_BLOCK_TYPE_VCN;
> > ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > + ib_start_alignment = 16;
> > ib_size_alignment = 16;
> > break;
> > case AMDGPU_HW_IP_VCN_ENC:
> > type = AMD_IP_BLOCK_TYPE_VCN;
> > for (i = 0; i < adev->vcn.num_enc_rings; i++)
> > ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0)
> << i);
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > + ib_start_alignment = 64;
> > ib_size_alignment = 1;
> > break;
> > case AMDGPU_HW_IP_VCN_JPEG:
> > type = AMD_IP_BLOCK_TYPE_VCN;
> > ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
> > - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> > + ib_start_alignment = 16;
> > ib_size_alignment = 16;
> > break;
> > default:
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used
[not found] ` <CY4PR12MB141405AC0D97B1A681203BC6FF7C0-rpdhrqHFk04b0eJBKAp/BwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-06-15 7:22 ` zhoucm1
[not found] ` <21a15654-b8f1-da9b-5771-bfd28c8a25ca-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: zhoucm1 @ 2018-06-15 7:22 UTC (permalink / raw)
To: Zhang, Jerry, Koenig, Christian, Zhou, David(ChunMing),
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Olsak, Marek, Ryan, Sean
On 2018年06月15日 15:16, Zhang, Jerry wrote:
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of
>> Christian K?nig
>> Sent: Friday, June 15, 2018 15:09
>> To: Zhou, David(ChunMing) <David1.Zhou@amd.com>; amd-
>> gfx@lists.freedesktop.org
>> Cc: Olsak, Marek <Marek.Olsak@amd.com>; Ryan, Sean <Sean.Ryan@amd.com>
>> Subject: Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as
>> windows used
>>
>> Am 15.06.2018 um 08:45 schrieb Chunming Zhou:
>>> PAGE_SIZE for start_alignment is far much than hw requirement, And
>>> now, update to expereince value from window side.
>>>
>>> Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5
>>> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
>> Acked-by: Christian König <christian.koenig@amd.com>
> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com>
>
> BTW, any issue it fixes?
Yes, as talked in internal brahma list " whether ib_start_alignment is
proper", which fixes some PAL assert checking.
Regards,
David Zhou
>
> Jerry
>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28 ++++++++++++++---------
>> -----
>>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> index 392dd24e83f5..d041dddaad0c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>> @@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>> void *data, struct drm_file
>>> type = AMD_IP_BLOCK_TYPE_GFX;
>>> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>>> ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0)
>> << i);
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> - ib_size_alignment = 8;
>>> + ib_start_alignment = 32;
>>> + ib_size_alignment = 32;
>>> break;
>>> case AMDGPU_HW_IP_COMPUTE:
>>> type = AMD_IP_BLOCK_TYPE_GFX;
>>> for (i = 0; i < adev->gfx.num_compute_rings; i++)
>>> ring_mask |= ((adev->gfx.compute_ring[i].ready ?
>> 1 : 0) << i);
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> - ib_size_alignment = 8;
>>> + ib_start_alignment = 32;
>>> + ib_size_alignment = 32;
>>> break;
>>> case AMDGPU_HW_IP_DMA:
>>> type = AMD_IP_BLOCK_TYPE_SDMA;
>>> for (i = 0; i < adev->sdma.num_instances; i++)
>>> ring_mask |= ((adev-
>>> sdma.instance[i].ring.ready ? 1 : 0) << i);
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> - ib_size_alignment = 1;
>>> + ib_start_alignment = 256;
>>> + ib_size_alignment = 4;
>>> break;
>>> case AMDGPU_HW_IP_UVD:
>>> type = AMD_IP_BLOCK_TYPE_UVD;
>>> for (i = 0; i < adev->uvd.num_uvd_inst; i++)
>>> ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0)
>> << i);
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> - ib_size_alignment = 16;
>>> + ib_start_alignment = 64;
>>> + ib_size_alignment = 64;
>>> break;
>>> case AMDGPU_HW_IP_VCE:
>>> type = AMD_IP_BLOCK_TYPE_VCE;
>>> for (i = 0; i < adev->vce.num_rings; i++)
>>> ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) <<
>> i);
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> + ib_start_alignment = 4;
>>> ib_size_alignment = 1;
>>> break;
>>> case AMDGPU_HW_IP_UVD_ENC:
>>> @@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>> void *data, struct drm_file
>>> ring_mask |=
>>> ((adev->uvd.inst[i].ring_enc[j].ready ? 1 :
>> 0) <<
>>> (j + i * adev->uvd.num_enc_rings));
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> - ib_size_alignment = 1;
>>> + ib_start_alignment = 64;
>>> + ib_size_alignment = 64;
>>> break;
>>> case AMDGPU_HW_IP_VCN_DEC:
>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>> ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> + ib_start_alignment = 16;
>>> ib_size_alignment = 16;
>>> break;
>>> case AMDGPU_HW_IP_VCN_ENC:
>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>> for (i = 0; i < adev->vcn.num_enc_rings; i++)
>>> ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0)
>> << i);
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> + ib_start_alignment = 64;
>>> ib_size_alignment = 1;
>>> break;
>>> case AMDGPU_HW_IP_VCN_JPEG:
>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>> ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>> + ib_start_alignment = 16;
>>> ib_size_alignment = 16;
>>> break;
>>> default:
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used
[not found] ` <21a15654-b8f1-da9b-5771-bfd28c8a25ca-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-15 7:25 ` zhoucm1
[not found] ` <b4dcf392-e29b-ca30-12d8-69434c28e834-5C7GfCeVMHo@public.gmane.org>
2018-06-15 7:29 ` Zhang, Jerry (Junwei)
1 sibling, 1 reply; 7+ messages in thread
From: zhoucm1 @ 2018-06-15 7:25 UTC (permalink / raw)
To: Zhang, Jerry, Koenig, Christian, Zhou, David(ChunMing),
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Olsak, Marek, Ryan, Sean
Marek, Can I get your RB or Acked on this patches? Since these info are
reported to UMD.
Thanks,
David Zhou
On 2018年06月15日 15:22, zhoucm1 wrote:
>
>
> On 2018年06月15日 15:16, Zhang, Jerry wrote:
>>> -----Original Message-----
>>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On
>>> Behalf Of
>>> Christian K?nig
>>> Sent: Friday, June 15, 2018 15:09
>>> To: Zhou, David(ChunMing) <David1.Zhou@amd.com>; amd-
>>> gfx@lists.freedesktop.org
>>> Cc: Olsak, Marek <Marek.Olsak@amd.com>; Ryan, Sean <Sean.Ryan@amd.com>
>>> Subject: Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as
>>> windows used
>>>
>>> Am 15.06.2018 um 08:45 schrieb Chunming Zhou:
>>>> PAGE_SIZE for start_alignment is far much than hw requirement, And
>>>> now, update to expereince value from window side.
>>>>
>>>> Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5
>>>> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
>>> Acked-by: Christian König <christian.koenig@amd.com>
>> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com>
>>
>> BTW, any issue it fixes?
> Yes, as talked in internal brahma list " whether ib_start_alignment is
> proper", which fixes some PAL assert checking.
>
> Regards,
> David Zhou
>>
>> Jerry
>>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28
>>>> ++++++++++++++---------
>>> -----
>>>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>>> index 392dd24e83f5..d041dddaad0c 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>>> @@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct
>>>> drm_device *dev,
>>> void *data, struct drm_file
>>>> type = AMD_IP_BLOCK_TYPE_GFX;
>>>> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>>>> ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0)
>>> << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 8;
>>>> + ib_start_alignment = 32;
>>>> + ib_size_alignment = 32;
>>>> break;
>>>> case AMDGPU_HW_IP_COMPUTE:
>>>> type = AMD_IP_BLOCK_TYPE_GFX;
>>>> for (i = 0; i < adev->gfx.num_compute_rings; i++)
>>>> ring_mask |= ((adev->gfx.compute_ring[i].ready ?
>>> 1 : 0) << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 8;
>>>> + ib_start_alignment = 32;
>>>> + ib_size_alignment = 32;
>>>> break;
>>>> case AMDGPU_HW_IP_DMA:
>>>> type = AMD_IP_BLOCK_TYPE_SDMA;
>>>> for (i = 0; i < adev->sdma.num_instances; i++)
>>>> ring_mask |= ((adev-
>>>> sdma.instance[i].ring.ready ? 1 : 0) << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 1;
>>>> + ib_start_alignment = 256;
>>>> + ib_size_alignment = 4;
>>>> break;
>>>> case AMDGPU_HW_IP_UVD:
>>>> type = AMD_IP_BLOCK_TYPE_UVD;
>>>> for (i = 0; i < adev->uvd.num_uvd_inst; i++)
>>>> ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1
>>>> : 0)
>>> << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 16;
>>>> + ib_start_alignment = 64;
>>>> + ib_size_alignment = 64;
>>>> break;
>>>> case AMDGPU_HW_IP_VCE:
>>>> type = AMD_IP_BLOCK_TYPE_VCE;
>>>> for (i = 0; i < adev->vce.num_rings; i++)
>>>> ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) <<
>>> i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> + ib_start_alignment = 4;
>>>> ib_size_alignment = 1;
>>>> break;
>>>> case AMDGPU_HW_IP_UVD_ENC:
>>>> @@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct
>>>> drm_device *dev,
>>> void *data, struct drm_file
>>>> ring_mask |=
>>>> ((adev->uvd.inst[i].ring_enc[j].ready ? 1 :
>>> 0) <<
>>>> (j + i * adev->uvd.num_enc_rings));
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 1;
>>>> + ib_start_alignment = 64;
>>>> + ib_size_alignment = 64;
>>>> break;
>>>> case AMDGPU_HW_IP_VCN_DEC:
>>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>>> ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> + ib_start_alignment = 16;
>>>> ib_size_alignment = 16;
>>>> break;
>>>> case AMDGPU_HW_IP_VCN_ENC:
>>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>>> for (i = 0; i < adev->vcn.num_enc_rings; i++)
>>>> ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0)
>>> << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> + ib_start_alignment = 64;
>>>> ib_size_alignment = 1;
>>>> break;
>>>> case AMDGPU_HW_IP_VCN_JPEG:
>>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>>> ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> + ib_start_alignment = 16;
>>>> ib_size_alignment = 16;
>>>> break;
>>>> default:
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used
[not found] ` <21a15654-b8f1-da9b-5771-bfd28c8a25ca-5C7GfCeVMHo@public.gmane.org>
2018-06-15 7:25 ` zhoucm1
@ 2018-06-15 7:29 ` Zhang, Jerry (Junwei)
1 sibling, 0 replies; 7+ messages in thread
From: Zhang, Jerry (Junwei) @ 2018-06-15 7:29 UTC (permalink / raw)
To: zhoucm1, Koenig, Christian, Zhou, David(ChunMing),
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Olsak, Marek, Ryan, Sean
On 06/15/2018 03:22 PM, zhoucm1 wrote:
>
>
> On 2018年06月15日 15:16, Zhang, Jerry wrote:
>>> -----Original Message-----
>>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of
>>> Christian K?nig
>>> Sent: Friday, June 15, 2018 15:09
>>> To: Zhou, David(ChunMing) <David1.Zhou@amd.com>; amd-
>>> gfx@lists.freedesktop.org
>>> Cc: Olsak, Marek <Marek.Olsak@amd.com>; Ryan, Sean <Sean.Ryan@amd.com>
>>> Subject: Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as
>>> windows used
>>>
>>> Am 15.06.2018 um 08:45 schrieb Chunming Zhou:
>>>> PAGE_SIZE for start_alignment is far much than hw requirement, And
>>>> now, update to expereince value from window side.
>>>>
>>>> Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5
>>>> Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
>>> Acked-by: Christian König <christian.koenig@amd.com>
>> Acked-by: Junwei Zhang <Jerry.Zhang@amd.com>
>>
>> BTW, any issue it fixes?
> Yes, as talked in internal brahma list " whether ib_start_alignment is proper",
> which fixes some PAL assert checking.
Yeah, got it.
Thanks for your explanation.
Jerry
>
> Regards,
> David Zhou
>>
>> Jerry
>>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28 ++++++++++++++---------
>>> -----
>>>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>>> index 392dd24e83f5..d041dddaad0c 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>>>> @@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>>> void *data, struct drm_file
>>>> type = AMD_IP_BLOCK_TYPE_GFX;
>>>> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
>>>> ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0)
>>> << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 8;
>>>> + ib_start_alignment = 32;
>>>> + ib_size_alignment = 32;
>>>> break;
>>>> case AMDGPU_HW_IP_COMPUTE:
>>>> type = AMD_IP_BLOCK_TYPE_GFX;
>>>> for (i = 0; i < adev->gfx.num_compute_rings; i++)
>>>> ring_mask |= ((adev->gfx.compute_ring[i].ready ?
>>> 1 : 0) << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 8;
>>>> + ib_start_alignment = 32;
>>>> + ib_size_alignment = 32;
>>>> break;
>>>> case AMDGPU_HW_IP_DMA:
>>>> type = AMD_IP_BLOCK_TYPE_SDMA;
>>>> for (i = 0; i < adev->sdma.num_instances; i++)
>>>> ring_mask |= ((adev-
>>>> sdma.instance[i].ring.ready ? 1 : 0) << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 1;
>>>> + ib_start_alignment = 256;
>>>> + ib_size_alignment = 4;
>>>> break;
>>>> case AMDGPU_HW_IP_UVD:
>>>> type = AMD_IP_BLOCK_TYPE_UVD;
>>>> for (i = 0; i < adev->uvd.num_uvd_inst; i++)
>>>> ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0)
>>> << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 16;
>>>> + ib_start_alignment = 64;
>>>> + ib_size_alignment = 64;
>>>> break;
>>>> case AMDGPU_HW_IP_VCE:
>>>> type = AMD_IP_BLOCK_TYPE_VCE;
>>>> for (i = 0; i < adev->vce.num_rings; i++)
>>>> ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) <<
>>> i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> + ib_start_alignment = 4;
>>>> ib_size_alignment = 1;
>>>> break;
>>>> case AMDGPU_HW_IP_UVD_ENC:
>>>> @@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev,
>>> void *data, struct drm_file
>>>> ring_mask |=
>>>> ((adev->uvd.inst[i].ring_enc[j].ready ? 1 :
>>> 0) <<
>>>> (j + i * adev->uvd.num_enc_rings));
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> - ib_size_alignment = 1;
>>>> + ib_start_alignment = 64;
>>>> + ib_size_alignment = 64;
>>>> break;
>>>> case AMDGPU_HW_IP_VCN_DEC:
>>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>>> ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> + ib_start_alignment = 16;
>>>> ib_size_alignment = 16;
>>>> break;
>>>> case AMDGPU_HW_IP_VCN_ENC:
>>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>>> for (i = 0; i < adev->vcn.num_enc_rings; i++)
>>>> ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0)
>>> << i);
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> + ib_start_alignment = 64;
>>>> ib_size_alignment = 1;
>>>> break;
>>>> case AMDGPU_HW_IP_VCN_JPEG:
>>>> type = AMD_IP_BLOCK_TYPE_VCN;
>>>> ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
>>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
>>>> + ib_start_alignment = 16;
>>>> ib_size_alignment = 16;
>>>> break;
>>>> default:
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used
[not found] ` <b4dcf392-e29b-ca30-12d8-69434c28e834-5C7GfCeVMHo@public.gmane.org>
@ 2018-06-15 16:15 ` Marek Olšák
0 siblings, 0 replies; 7+ messages in thread
From: Marek Olšák @ 2018-06-15 16:15 UTC (permalink / raw)
To: Chunming Zhou
Cc: Zhou, David(ChunMing),
Olsak, Marek, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Ryan,
Sean, Junwei Zhang, Christian König
[-- Attachment #1.1: Type: text/plain, Size: 7028 bytes --]
Acked-by: Marek Olšák <marek.olsak-5C7GfCeVMHo@public.gmane.org>
Marek
On Fri, Jun 15, 2018, 4:03 AM zhoucm1 <zhoucm1-5C7GfCeVMHo@public.gmane.org> wrote:
> Marek, Can I get your RB or Acked on this patches? Since these info are
> reported to UMD.
>
>
> Thanks,
>
> David Zhou
>
>
> On 2018年06月15日 15:22, zhoucm1 wrote:
> >
> >
> > On 2018年06月15日 15:16, Zhang, Jerry wrote:
> >>> -----Original Message-----
> >>> From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On
> >>> Behalf Of
> >>> Christian K?nig
> >>> Sent: Friday, June 15, 2018 15:09
> >>> To: Zhou, David(ChunMing) <David1.Zhou-5C7GfCeVMHo@public.gmane.org>; amd-
> >>> gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> >>> Cc: Olsak, Marek <Marek.Olsak-5C7GfCeVMHo@public.gmane.org>; Ryan, Sean <Sean.Ryan-5C7GfCeVMHo@public.gmane.org>
> >>> Subject: Re: [PATCH] drm/amdgpu: update ib_start/size_alignment same as
> >>> windows used
> >>>
> >>> Am 15.06.2018 um 08:45 schrieb Chunming Zhou:
> >>>> PAGE_SIZE for start_alignment is far much than hw requirement, And
> >>>> now, update to expereince value from window side.
> >>>>
> >>>> Change-Id: I08a7e72076386c32faf36ec4812b30e68dde23e5
> >>>> Signed-off-by: Chunming Zhou <david1.zhou-5C7GfCeVMHo@public.gmane.org>
> >>> Acked-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
> >> Acked-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
> >>
> >> BTW, any issue it fixes?
> > Yes, as talked in internal brahma list " whether ib_start_alignment is
> > proper", which fixes some PAL assert checking.
> >
> > Regards,
> > David Zhou
> >>
> >> Jerry
> >>
> >>>> ---
> >>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28
> >>>> ++++++++++++++---------
> >>> -----
> >>>> 1 file changed, 14 insertions(+), 14 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> >>>> index 392dd24e83f5..d041dddaad0c 100644
> >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> >>>> @@ -329,35 +329,35 @@ static int amdgpu_info_ioctl(struct
> >>>> drm_device *dev,
> >>> void *data, struct drm_file
> >>>> type = AMD_IP_BLOCK_TYPE_GFX;
> >>>> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> >>>> ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0)
> >>> << i);
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> - ib_size_alignment = 8;
> >>>> + ib_start_alignment = 32;
> >>>> + ib_size_alignment = 32;
> >>>> break;
> >>>> case AMDGPU_HW_IP_COMPUTE:
> >>>> type = AMD_IP_BLOCK_TYPE_GFX;
> >>>> for (i = 0; i < adev->gfx.num_compute_rings; i++)
> >>>> ring_mask |= ((adev->gfx.compute_ring[i].ready ?
> >>> 1 : 0) << i);
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> - ib_size_alignment = 8;
> >>>> + ib_start_alignment = 32;
> >>>> + ib_size_alignment = 32;
> >>>> break;
> >>>> case AMDGPU_HW_IP_DMA:
> >>>> type = AMD_IP_BLOCK_TYPE_SDMA;
> >>>> for (i = 0; i < adev->sdma.num_instances; i++)
> >>>> ring_mask |= ((adev-
> >>>> sdma.instance[i].ring.ready ? 1 : 0) << i);
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> - ib_size_alignment = 1;
> >>>> + ib_start_alignment = 256;
> >>>> + ib_size_alignment = 4;
> >>>> break;
> >>>> case AMDGPU_HW_IP_UVD:
> >>>> type = AMD_IP_BLOCK_TYPE_UVD;
> >>>> for (i = 0; i < adev->uvd.num_uvd_inst; i++)
> >>>> ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1
> >>>> : 0)
> >>> << i);
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> - ib_size_alignment = 16;
> >>>> + ib_start_alignment = 64;
> >>>> + ib_size_alignment = 64;
> >>>> break;
> >>>> case AMDGPU_HW_IP_VCE:
> >>>> type = AMD_IP_BLOCK_TYPE_VCE;
> >>>> for (i = 0; i < adev->vce.num_rings; i++)
> >>>> ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) <<
> >>> i);
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> + ib_start_alignment = 4;
> >>>> ib_size_alignment = 1;
> >>>> break;
> >>>> case AMDGPU_HW_IP_UVD_ENC:
> >>>> @@ -367,26 +367,26 @@ static int amdgpu_info_ioctl(struct
> >>>> drm_device *dev,
> >>> void *data, struct drm_file
> >>>> ring_mask |=
> >>>> ((adev->uvd.inst[i].ring_enc[j].ready ? 1 :
> >>> 0) <<
> >>>> (j + i * adev->uvd.num_enc_rings));
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> - ib_size_alignment = 1;
> >>>> + ib_start_alignment = 64;
> >>>> + ib_size_alignment = 64;
> >>>> break;
> >>>> case AMDGPU_HW_IP_VCN_DEC:
> >>>> type = AMD_IP_BLOCK_TYPE_VCN;
> >>>> ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> + ib_start_alignment = 16;
> >>>> ib_size_alignment = 16;
> >>>> break;
> >>>> case AMDGPU_HW_IP_VCN_ENC:
> >>>> type = AMD_IP_BLOCK_TYPE_VCN;
> >>>> for (i = 0; i < adev->vcn.num_enc_rings; i++)
> >>>> ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0)
> >>> << i);
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> + ib_start_alignment = 64;
> >>>> ib_size_alignment = 1;
> >>>> break;
> >>>> case AMDGPU_HW_IP_VCN_JPEG:
> >>>> type = AMD_IP_BLOCK_TYPE_VCN;
> >>>> ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
> >>>> - ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
> >>>> + ib_start_alignment = 16;
> >>>> ib_size_alignment = 16;
> >>>> break;
> >>>> default:
> >>> _______________________________________________
> >>> amd-gfx mailing list
> >>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
[-- Attachment #1.2: Type: text/html, Size: 11646 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-06-15 16:15 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-15 6:45 [PATCH] drm/amdgpu: update ib_start/size_alignment same as windows used Chunming Zhou
[not found] ` <20180615064542.16504-1-david1.zhou-5C7GfCeVMHo@public.gmane.org>
2018-06-15 7:09 ` Christian König
[not found] ` <dd3006dc-203f-9fb8-b43f-14151f01127a-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-06-15 7:16 ` Zhang, Jerry
[not found] ` <CY4PR12MB141405AC0D97B1A681203BC6FF7C0-rpdhrqHFk04b0eJBKAp/BwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-06-15 7:22 ` zhoucm1
[not found] ` <21a15654-b8f1-da9b-5771-bfd28c8a25ca-5C7GfCeVMHo@public.gmane.org>
2018-06-15 7:25 ` zhoucm1
[not found] ` <b4dcf392-e29b-ca30-12d8-69434c28e834-5C7GfCeVMHo@public.gmane.org>
2018-06-15 16:15 ` Marek Olšák
2018-06-15 7:29 ` Zhang, Jerry (Junwei)
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