* [PATCH 1/3] drm/amd/display: Use dcc_ind_blk value to set register directly
@ 2021-09-14 23:59 Joshua Ashton
2021-09-14 23:59 ` [PATCH 2/3] drm/amd/display: Handle GFX10_RBPLUS modifiers for dcc_ind_blk Joshua Ashton
2021-09-14 23:59 ` [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3 Joshua Ashton
0 siblings, 2 replies; 9+ messages in thread
From: Joshua Ashton @ 2021-09-14 23:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Joshua Ashton, Bas Nieuwenhuizen
We don't need to do this workaround if we start setting this value when we fill the plane attributes.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++++-
drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c | 6 ------
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8837259215d9..9c6f2863ba96 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4914,10 +4914,15 @@ fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
if (modifier_has_dcc(modifier) && !force_disable_dcc) {
uint64_t dcc_address = afb->address + afb->base.offsets[1];
+ bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
dcc->enable = 1;
dcc->meta_pitch = afb->base.pitches[1];
- dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
+ dcc->independent_64b_blks = independent_64b_blks;
+ if (independent_64b_blks)
+ dcc->dcc_ind_blk = hubp_ind_block_64b;
+ else
+ dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f58d3956f3e2..da360691e655 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -2008,7 +2008,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa
}
if (u->plane_info->dcc.enable != u->surface->dcc.enable
- || u->plane_info->dcc.independent_64b_blks != u->surface->dcc.independent_64b_blks
+ || u->plane_info->dcc.dcc_ind_blk != u->surface->dcc.dcc_ind_blk
|| u->plane_info->dcc.meta_pitch != u->surface->dcc.meta_pitch) {
/* During DCC on/off, stutter period is calculated before
* DCC has fully transitioned. This results in incorrect
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
index f24612523248..eac08926b574 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
@@ -356,12 +356,6 @@ void hubp3_dcc_control_sienna_cichlid(struct hubp *hubp,
{
struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
- /*Workaround until UMD fix the new dcc_ind_blk interface */
- if (dcc->independent_64b_blks && dcc->dcc_ind_blk == 0)
- dcc->dcc_ind_blk = 1;
- if (dcc->independent_64b_blks_c && dcc->dcc_ind_blk_c == 0)
- dcc->dcc_ind_blk_c = 1;
-
REG_UPDATE_6(DCSURF_SURFACE_CONTROL,
PRIMARY_SURFACE_DCC_EN, dcc->enable,
PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk,
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] drm/amd/display: Handle GFX10_RBPLUS modifiers for dcc_ind_blk
2021-09-14 23:59 [PATCH 1/3] drm/amd/display: Use dcc_ind_blk value to set register directly Joshua Ashton
@ 2021-09-14 23:59 ` Joshua Ashton
2021-09-14 23:59 ` [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3 Joshua Ashton
1 sibling, 0 replies; 9+ messages in thread
From: Joshua Ashton @ 2021-09-14 23:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Joshua Ashton, Bas Nieuwenhuizen
Adds the missing logic to set the correct value of dcc_ind_blk for this tiling version.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++++++++++++++----
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9c6f2863ba96..2a24e43623cb 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4915,14 +4915,26 @@ fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
if (modifier_has_dcc(modifier) && !force_disable_dcc) {
uint64_t dcc_address = afb->address + afb->base.offsets[1];
bool independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
+ bool independent_128b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
dcc->enable = 1;
dcc->meta_pitch = afb->base.pitches[1];
dcc->independent_64b_blks = independent_64b_blks;
- if (independent_64b_blks)
- dcc->dcc_ind_blk = hubp_ind_block_64b;
- else
- dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
+ if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) {
+ if (independent_64b_blks && independent_128b_blks)
+ dcc->dcc_ind_blk = hubp_ind_block_64b;
+ else if (independent_128b_blks)
+ dcc->dcc_ind_blk = hubp_ind_block_128b;
+ else if (independent_64b_blks && !independent_128b_blks)
+ dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl;
+ else
+ dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
+ } else {
+ if (independent_64b_blks)
+ dcc->dcc_ind_blk = hubp_ind_block_64b;
+ else
+ dcc->dcc_ind_blk = hubp_ind_block_unconstrained;
+ }
address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3
2021-09-14 23:59 [PATCH 1/3] drm/amd/display: Use dcc_ind_blk value to set register directly Joshua Ashton
2021-09-14 23:59 ` [PATCH 2/3] drm/amd/display: Handle GFX10_RBPLUS modifiers for dcc_ind_blk Joshua Ashton
@ 2021-09-14 23:59 ` Joshua Ashton
2021-09-15 18:02 ` Harry Wentland
2021-09-16 0:11 ` Marek Olšák
1 sibling, 2 replies; 9+ messages in thread
From: Joshua Ashton @ 2021-09-14 23:59 UTC (permalink / raw)
To: amd-gfx; +Cc: Joshua Ashton, Bas Nieuwenhuizen
Some games, ie. Doom Eternal, present from compute following compute
post-fx and would benefit from having DCC image stores available.
DCN on gfx10_3 doesn't need INDEPENDENT_128B_BLOCKS = 0 so we can expose
these modifiers capable of DCC image stores.
Signed-off-by: Joshua Ashton <joshua@froggi.es>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2a24e43623cb..a4e33a4336a0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4817,6 +4817,16 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
+ add_modifier(mods, size, capacity, AMD_FMT_MOD |
+ AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+ AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+ AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+ AMD_FMT_MOD_SET(PACKERS, pkrs) |
+ AMD_FMT_MOD_SET(DCC, 1) |
+ AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+ AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+ AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
+
add_modifier(mods, size, capacity, AMD_FMT_MOD |
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
@@ -4829,6 +4839,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
+ add_modifier(mods, size, capacity, AMD_FMT_MOD |
+ AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+ AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+ AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+ AMD_FMT_MOD_SET(PACKERS, pkrs) |
+ AMD_FMT_MOD_SET(DCC, 1) |
+ AMD_FMT_MOD_SET(DCC_RETILE, 1) |
+ AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+ AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+ AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
+
add_modifier(mods, size, capacity, AMD_FMT_MOD |
AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3
2021-09-14 23:59 ` [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3 Joshua Ashton
@ 2021-09-15 18:02 ` Harry Wentland
2021-09-15 18:22 ` Alex Deucher
2021-09-16 0:11 ` Marek Olšák
1 sibling, 1 reply; 9+ messages in thread
From: Harry Wentland @ 2021-09-15 18:02 UTC (permalink / raw)
To: Joshua Ashton, amd-gfx; +Cc: Bas Nieuwenhuizen
On 2021-09-14 19:59, Joshua Ashton wrote:
> Some games, ie. Doom Eternal, present from compute following compute
> post-fx and would benefit from having DCC image stores available.
>
> DCN on gfx10_3 doesn't need INDEPENDENT_128B_BLOCKS = 0 so we can expose
> these modifiers capable of DCC image stores.
>
> Signed-off-by: Joshua Ashton <joshua@froggi.es>
> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Series is
Acked-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 2a24e43623cb..a4e33a4336a0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4817,6 +4817,16 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
>
> + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> + AMD_FMT_MOD_SET(DCC, 1) |
> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
> +
> add_modifier(mods, size, capacity, AMD_FMT_MOD |
> AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> @@ -4829,6 +4839,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
>
> + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> + AMD_FMT_MOD_SET(DCC, 1) |
> + AMD_FMT_MOD_SET(DCC_RETILE, 1) |
> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
> +
> add_modifier(mods, size, capacity, AMD_FMT_MOD |
> AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3
2021-09-15 18:02 ` Harry Wentland
@ 2021-09-15 18:22 ` Alex Deucher
0 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2021-09-15 18:22 UTC (permalink / raw)
To: Harry Wentland; +Cc: Joshua Ashton, amd-gfx list, Bas Nieuwenhuizen
Applied. Thanks!
Alex
On Wed, Sep 15, 2021 at 2:02 PM Harry Wentland <harry.wentland@amd.com> wrote:
>
> On 2021-09-14 19:59, Joshua Ashton wrote:
> > Some games, ie. Doom Eternal, present from compute following compute
> > post-fx and would benefit from having DCC image stores available.
> >
> > DCN on gfx10_3 doesn't need INDEPENDENT_128B_BLOCKS = 0 so we can expose
> > these modifiers capable of DCC image stores.
> >
> > Signed-off-by: Joshua Ashton <joshua@froggi.es>
> > Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
>
> Series is
> Acked-by: Harry Wentland <harry.wentland@amd.com>
>
> Harry
>
> > ---
> > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 2a24e43623cb..a4e33a4336a0 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -4817,6 +4817,16 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
> > AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> > AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
> >
> > + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> > + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> > + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> > + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> > + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> > + AMD_FMT_MOD_SET(DCC, 1) |
> > + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> > + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> > + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
> > +
> > add_modifier(mods, size, capacity, AMD_FMT_MOD |
> > AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> > AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> > @@ -4829,6 +4839,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
> > AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> > AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
> >
> > + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> > + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> > + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> > + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> > + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> > + AMD_FMT_MOD_SET(DCC, 1) |
> > + AMD_FMT_MOD_SET(DCC_RETILE, 1) |
> > + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> > + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> > + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
> > +
> > add_modifier(mods, size, capacity, AMD_FMT_MOD |
> > AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> > AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> >
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3
2021-09-14 23:59 ` [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3 Joshua Ashton
2021-09-15 18:02 ` Harry Wentland
@ 2021-09-16 0:11 ` Marek Olšák
2021-09-16 0:20 ` Bas Nieuwenhuizen
2021-09-16 0:23 ` Joshua Ashton
1 sibling, 2 replies; 9+ messages in thread
From: Marek Olšák @ 2021-09-16 0:11 UTC (permalink / raw)
To: Joshua Ashton; +Cc: amd-gfx mailing list, Bas Nieuwenhuizen
[-- Attachment #1: Type: text/plain, Size: 3383 bytes --]
Based on the discussions we had about displayable DCC internally, only
MAX_COMPRESSED_BLOCK = 64B with both DCC_INDEPENDENT_64B_BLOCKS and
DCC_INDEPENDENT_128B_BLOCKS is supported by DCN on RDNA 2.
Is there something new on the hardware side that I missed?
Marek
On Tue, Sep 14, 2021 at 7:59 PM Joshua Ashton <joshua@froggi.es> wrote:
> Some games, ie. Doom Eternal, present from compute following compute
> post-fx and would benefit from having DCC image stores available.
>
> DCN on gfx10_3 doesn't need INDEPENDENT_128B_BLOCKS = 0 so we can expose
> these modifiers capable of DCC image stores.
>
> Signed-off-by: Joshua Ashton <joshua@froggi.es>
> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 2a24e43623cb..a4e33a4336a0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4817,6 +4817,16 @@ add_gfx10_3_modifiers(const struct amdgpu_device
> *adev,
> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> AMD_FMT_MOD_DCC_BLOCK_64B));
>
> + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> + AMD_FMT_MOD_SET(TILE_VERSION,
> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> + AMD_FMT_MOD_SET(DCC, 1) |
> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> AMD_FMT_MOD_DCC_BLOCK_128B));
> +
> add_modifier(mods, size, capacity, AMD_FMT_MOD |
> AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> AMD_FMT_MOD_SET(TILE_VERSION,
> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> @@ -4829,6 +4839,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device
> *adev,
> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> AMD_FMT_MOD_DCC_BLOCK_64B));
>
> + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> + AMD_FMT_MOD_SET(TILE_VERSION,
> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> + AMD_FMT_MOD_SET(DCC, 1) |
> + AMD_FMT_MOD_SET(DCC_RETILE, 1) |
> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> AMD_FMT_MOD_DCC_BLOCK_128B));
> +
> add_modifier(mods, size, capacity, AMD_FMT_MOD |
> AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> AMD_FMT_MOD_SET(TILE_VERSION,
> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> --
> 2.33.0
>
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3
2021-09-16 0:11 ` Marek Olšák
@ 2021-09-16 0:20 ` Bas Nieuwenhuizen
2021-09-16 0:23 ` Joshua Ashton
1 sibling, 0 replies; 9+ messages in thread
From: Bas Nieuwenhuizen @ 2021-09-16 0:20 UTC (permalink / raw)
To: Marek Olšák; +Cc: Joshua Ashton, amd-gfx mailing list
[-- Attachment #1: Type: text/plain, Size: 3773 bytes --]
On Thu, Sep 16, 2021, 2:12 AM Marek Olšák <maraeo@gmail.com> wrote:
> Based on the discussions we had about displayable DCC internally, only
> MAX_COMPRESSED_BLOCK = 64B with both DCC_INDEPENDENT_64B_BLOCKS and
> DCC_INDEPENDENT_128B_BLOCKS is supported by DCN on RDNA 2.
>
> Is there something new on the hardware side that I missed?
>
Per the comments you put in mesa that was only needed for 4k?
https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/amd/common/ac_surface.c#L1444
> Marek
>
> On Tue, Sep 14, 2021 at 7:59 PM Joshua Ashton <joshua@froggi.es> wrote:
>
>> Some games, ie. Doom Eternal, present from compute following compute
>> post-fx and would benefit from having DCC image stores available.
>>
>> DCN on gfx10_3 doesn't need INDEPENDENT_128B_BLOCKS = 0 so we can expose
>> these modifiers capable of DCC image stores.
>>
>> Signed-off-by: Joshua Ashton <joshua@froggi.es>
>> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
>> ---
>> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +++++++++++++++++++
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 2a24e43623cb..a4e33a4336a0 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -4817,6 +4817,16 @@ add_gfx10_3_modifiers(const struct amdgpu_device
>> *adev,
>> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
>> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
>> AMD_FMT_MOD_DCC_BLOCK_64B));
>>
>> + add_modifier(mods, size, capacity, AMD_FMT_MOD |
>> + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
>> + AMD_FMT_MOD_SET(TILE_VERSION,
>> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
>> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
>> + AMD_FMT_MOD_SET(PACKERS, pkrs) |
>> + AMD_FMT_MOD_SET(DCC, 1) |
>> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
>> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
>> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
>> AMD_FMT_MOD_DCC_BLOCK_128B));
>> +
>> add_modifier(mods, size, capacity, AMD_FMT_MOD |
>> AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
>> AMD_FMT_MOD_SET(TILE_VERSION,
>> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
>> @@ -4829,6 +4839,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device
>> *adev,
>> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
>> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
>> AMD_FMT_MOD_DCC_BLOCK_64B));
>>
>> + add_modifier(mods, size, capacity, AMD_FMT_MOD |
>> + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
>> + AMD_FMT_MOD_SET(TILE_VERSION,
>> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
>> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
>> + AMD_FMT_MOD_SET(PACKERS, pkrs) |
>> + AMD_FMT_MOD_SET(DCC, 1) |
>> + AMD_FMT_MOD_SET(DCC_RETILE, 1) |
>> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
>> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
>> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
>> AMD_FMT_MOD_DCC_BLOCK_128B));
>> +
>> add_modifier(mods, size, capacity, AMD_FMT_MOD |
>> AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
>> AMD_FMT_MOD_SET(TILE_VERSION,
>> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
>> --
>> 2.33.0
>>
>>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3
2021-09-16 0:11 ` Marek Olšák
2021-09-16 0:20 ` Bas Nieuwenhuizen
@ 2021-09-16 0:23 ` Joshua Ashton
2021-09-16 0:37 ` Marek Olšák
1 sibling, 1 reply; 9+ messages in thread
From: Joshua Ashton @ 2021-09-16 0:23 UTC (permalink / raw)
To: Marek Olšák; +Cc: amd-gfx mailing list, Bas Nieuwenhuizen
On 9/16/21 01:11, Marek Olšák wrote:
> Based on the discussions we had about displayable DCC internally, only
> MAX_COMPRESSED_BLOCK = 64B with both DCC_INDEPENDENT_64B_BLOCKS and
> DCC_INDEPENDENT_128B_BLOCKS is supported by DCN on RDNA 2.
>
From my testing:
It works fine when setting PRIMARY_SURFACE_DCC_IND_BLK to 2
(hubp_ind_block_128b) with 128b blocks alone.
Previously, PRIMARY_SURFACE_DCC_IND_BLK would only ever be 1 or 0, and
both of these values do not work for 128b.
This change has been tested with both Gamescope compositing and for Doom
Eternal.
I have validated that the modifiers are in use in both of these
scenarios and the register values were found and tested with
sudo umr -O bits -r vangogh.dcn301.mmHUBPREQ0_DCSURF_SURFACE_CONTROL
- Joshie 🐸✨
> Is there something new on the hardware side that I missed?
>
> Marek
>
> On Tue, Sep 14, 2021 at 7:59 PM Joshua Ashton <joshua@froggi.es
> <mailto:joshua@froggi.es>> wrote:
>
> Some games, ie. Doom Eternal, present from compute following compute
> post-fx and would benefit from having DCC image stores available.
>
> DCN on gfx10_3 doesn't need INDEPENDENT_128B_BLOCKS = 0 so we can expose
> these modifiers capable of DCC image stores.
>
> Signed-off-by: Joshua Ashton <joshua@froggi.es
> <mailto:joshua@froggi.es>>
> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
> <mailto:bas@basnieuwenhuizen.nl>>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 2a24e43623cb..a4e33a4336a0 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -4817,6 +4817,16 @@ add_gfx10_3_modifiers(const struct
> amdgpu_device *adev,
> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> AMD_FMT_MOD_DCC_BLOCK_64B));
>
> + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> + AMD_FMT_MOD_SET(TILE,
> AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> + AMD_FMT_MOD_SET(TILE_VERSION,
> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> + AMD_FMT_MOD_SET(DCC, 1) |
> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> AMD_FMT_MOD_DCC_BLOCK_128B));
> +
> add_modifier(mods, size, capacity, AMD_FMT_MOD |
> AMD_FMT_MOD_SET(TILE,
> AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> AMD_FMT_MOD_SET(TILE_VERSION,
> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> @@ -4829,6 +4839,17 @@ add_gfx10_3_modifiers(const struct
> amdgpu_device *adev,
> AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> AMD_FMT_MOD_DCC_BLOCK_64B));
>
> + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> + AMD_FMT_MOD_SET(TILE,
> AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> + AMD_FMT_MOD_SET(TILE_VERSION,
> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> + AMD_FMT_MOD_SET(DCC, 1) |
> + AMD_FMT_MOD_SET(DCC_RETILE, 1) |
> + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> AMD_FMT_MOD_DCC_BLOCK_128B));
> +
> add_modifier(mods, size, capacity, AMD_FMT_MOD |
> AMD_FMT_MOD_SET(TILE,
> AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> AMD_FMT_MOD_SET(TILE_VERSION,
> AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> --
> 2.33.0
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3
2021-09-16 0:23 ` Joshua Ashton
@ 2021-09-16 0:37 ` Marek Olšák
0 siblings, 0 replies; 9+ messages in thread
From: Marek Olšák @ 2021-09-16 0:37 UTC (permalink / raw)
To: Joshua Ashton; +Cc: amd-gfx mailing list, Bas Nieuwenhuizen
[-- Attachment #1: Type: text/plain, Size: 4792 bytes --]
Ah, I forgot about 4K. It looks good. Thanks!
Marek
On Wed, Sep 15, 2021 at 8:23 PM Joshua Ashton <joshua@froggi.es> wrote:
>
>
> On 9/16/21 01:11, Marek Olšák wrote:
> > Based on the discussions we had about displayable DCC internally, only
> > MAX_COMPRESSED_BLOCK = 64B with both DCC_INDEPENDENT_64B_BLOCKS and
> > DCC_INDEPENDENT_128B_BLOCKS is supported by DCN on RDNA 2.
> >
> From my testing:
>
> It works fine when setting PRIMARY_SURFACE_DCC_IND_BLK to 2
> (hubp_ind_block_128b) with 128b blocks alone.
>
> Previously, PRIMARY_SURFACE_DCC_IND_BLK would only ever be 1 or 0, and
> both of these values do not work for 128b.
>
> This change has been tested with both Gamescope compositing and for Doom
> Eternal.
>
> I have validated that the modifiers are in use in both of these
> scenarios and the register values were found and tested with
>
> sudo umr -O bits -r vangogh.dcn301.mmHUBPREQ0_DCSURF_SURFACE_CONTROL
>
> - Joshie 🐸✨
>
>
> > Is there something new on the hardware side that I missed?
> >
> > Marek
> >
> > On Tue, Sep 14, 2021 at 7:59 PM Joshua Ashton <joshua@froggi.es
> > <mailto:joshua@froggi.es>> wrote:
> >
> > Some games, ie. Doom Eternal, present from compute following compute
> > post-fx and would benefit from having DCC image stores available.
> >
> > DCN on gfx10_3 doesn't need INDEPENDENT_128B_BLOCKS = 0 so we can
> expose
> > these modifiers capable of DCC image stores.
> >
> > Signed-off-by: Joshua Ashton <joshua@froggi.es
> > <mailto:joshua@froggi.es>>
> > Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
> > <mailto:bas@basnieuwenhuizen.nl>>
> > ---
> > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21
> +++++++++++++++++++
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 2a24e43623cb..a4e33a4336a0 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -4817,6 +4817,16 @@ add_gfx10_3_modifiers(const struct
> > amdgpu_device *adev,
> > AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> > AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> > AMD_FMT_MOD_DCC_BLOCK_64B));
> >
> > + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> > + AMD_FMT_MOD_SET(TILE,
> > AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> > + AMD_FMT_MOD_SET(TILE_VERSION,
> > AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> > + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> > + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> > + AMD_FMT_MOD_SET(DCC, 1) |
> > + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> > + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> > + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> > AMD_FMT_MOD_DCC_BLOCK_128B));
> > +
> > add_modifier(mods, size, capacity, AMD_FMT_MOD |
> > AMD_FMT_MOD_SET(TILE,
> > AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> > AMD_FMT_MOD_SET(TILE_VERSION,
> > AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> > @@ -4829,6 +4839,17 @@ add_gfx10_3_modifiers(const struct
> > amdgpu_device *adev,
> > AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> > AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> > AMD_FMT_MOD_DCC_BLOCK_64B));
> >
> > + add_modifier(mods, size, capacity, AMD_FMT_MOD |
> > + AMD_FMT_MOD_SET(TILE,
> > AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> > + AMD_FMT_MOD_SET(TILE_VERSION,
> > AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> > + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
> > + AMD_FMT_MOD_SET(PACKERS, pkrs) |
> > + AMD_FMT_MOD_SET(DCC, 1) |
> > + AMD_FMT_MOD_SET(DCC_RETILE, 1) |
> > + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
> > + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
> > + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK,
> > AMD_FMT_MOD_DCC_BLOCK_128B));
> > +
> > add_modifier(mods, size, capacity, AMD_FMT_MOD |
> > AMD_FMT_MOD_SET(TILE,
> > AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
> > AMD_FMT_MOD_SET(TILE_VERSION,
> > AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
> > --
> > 2.33.0
> >
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-09-16 0:37 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-14 23:59 [PATCH 1/3] drm/amd/display: Use dcc_ind_blk value to set register directly Joshua Ashton
2021-09-14 23:59 ` [PATCH 2/3] drm/amd/display: Handle GFX10_RBPLUS modifiers for dcc_ind_blk Joshua Ashton
2021-09-14 23:59 ` [PATCH 3/3] drm/amd/display: Add modifiers capable of DCC image stores for gfx10_3 Joshua Ashton
2021-09-15 18:02 ` Harry Wentland
2021-09-15 18:22 ` Alex Deucher
2021-09-16 0:11 ` Marek Olšák
2021-09-16 0:20 ` Bas Nieuwenhuizen
2021-09-16 0:23 ` Joshua Ashton
2021-09-16 0:37 ` Marek Olšák
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