[U-Boot] some USB cleanup on EfikaMX

[U-Boot] some USB cleanup on EfikaMX

[Jana Rapava]

--- a/board/efikamx/efikamx-usb.c
+++ b/board/efikamx/efikamx-usb.c
@@ -154,6 +154,7 @@ void efika_usb_phy_reset(void)
        gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
 }

+
 /*
  * Configure control registers of the USB controller
  */
@@ -161,56 +162,56 @@ void control_regs_setup(void)
 {
        uint32_t tmp;

-       tmp = readl(OTG_BASE_ADDR + 0x800);
-       tmp &= ~((1 << 27) | (1 << 24) | (1 << 12) | (1 << 11));
-       tmp |= 1 << 8;
-       writel(tmp, OTG_BASE_ADDR + 0x800);
+       tmp = readl(OTG_BASE_ADDR + MX51_USB_CTRL_OFFSET);
+       tmp &= ~(MX51_OTG_WUE_BIT | MX51_OTG_PM_BIT | MX51_H1_ULPI_IE_BIT |
MX51_H1_WUE_BIT);
+       tmp |= MX51_H1_PM_BIT;
+       writel(tmp, OTG_BASE_ADDR + MX51_USB_CTRL_OFFSET);

-       tmp = readl(OTG_BASE_ADDR + 0x808);
-       tmp &= ~(1 << 8);
-       tmp |= 1 << 5;
-       writel(tmp, OTG_BASE_ADDR + 0x808);
+       tmp = readl(OTG_BASE_ADDR + MX51_PHY_CTRL0_OFFSET);
+       tmp &= ~MX51_OTG_OVERCURD_BIT;
+       tmp |= MX51_EHCI_POWERPINSE_BIT;
+       writel(tmp, OTG_BASE_ADDR + MX51_PHY_CTRL0_OFFSET);

-       tmp = readl(OTG_BASE_ADDR + 0x80c);
-       tmp &= ~0x3;
-       tmp |= 0x1;
-       writel(tmp, OTG_BASE_ADDR + 0x80c);
+       tmp = readl(OTG_BASE_ADDR + MX51_PHY_CTRL1_OFFSET);
+       tmp &= ~0x3; /* make sure bits 0 and 1 are set to zero */
+       tmp |= MX51_SYSCLOCK_24_MHZ_BIT;
+       writel(tmp, OTG_BASE_ADDR + MX51_PHY_CTRL1_OFFSET);

-       tmp = readl(OTG_BASE_ADDR + 0x810);
-       tmp |= 1 << 25;
-       writel(tmp, OTG_BASE_ADDR + 0x810);
+       tmp = readl(OTG_BASE_ADDR + MX51_USB_CTRL1_OFFSET);
+       tmp |= MX51_H1_EXTCLKE_BIT;
+       writel(tmp, OTG_BASE_ADDR + MX51_USB_CTRL1_OFFSET);

-       tmp = readl(OTG_BASE_ADDR + 0x814);
-       tmp &= ~((1 << 8) | (1 << 7));
-       tmp |= 1 << 4;
-       writel(tmp, OTG_BASE_ADDR + 0x814);
+       tmp = readl(OTG_BASE_ADDR + MX51_UH2_CTRL_OFFSET);
+       tmp &= ~(MX51_H2_ULPI_IE_BIT | MX51_H2_WUE_BIT);
+       //Host 2 VBUS enable controlled by Host 2 controller
+       tmp |= MX51_H2_PM_BIT;
+       writel(tmp, OTG_BASE_ADDR + MX51_UH2_CTRL_OFFSET);

        udelay(10000);
 }

-#define        ULPI_VIEWPORT(base)     (base + 0x170)

 void ulpi_write(u32 base, u32 reg, u32 value)
 {
-       if (!(readl(ULPI_VIEWPORT(base)) & (1 << 27))) {
-               writel(1 << 31, ULPI_VIEWPORT(base));
-               while (readl(ULPI_VIEWPORT(base)) & (1 << 31));
+       if (!(readl(ULPI_VIEWPORT(base)) & MX51_ULPI_SS_BIT)) {
+               writel(MX51_ULPI_WU_BIT, ULPI_VIEWPORT(base));
+               while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_WU_BIT);
        }
-       writel((1 << 30) | (1 << 29) | (reg << 16) | (value & 0xff),
ULPI_VIEWPORT(base));
-       while (readl(ULPI_VIEWPORT(base)) & (1 << 30));
+       writel(MX51_ULPI_RWRUN | MX51_ULPI_RWCTRL | (reg << 16) | (value &
0xff), ULPI_VIEWPORT(base));
+       while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_RWRUN);
 }

 u32 ulpi_read(u32 base, u32 reg)
 {
        u32 tmp;
-       if (!(readl(ULPI_VIEWPORT(base)) & (1 << 27))) {
-               writel(1 << 31, ULPI_VIEWPORT(base));
-               while (readl(ULPI_VIEWPORT(base)) & (1 << 31));
+       if (!(readl(ULPI_VIEWPORT(base)) & MX51_ULPI_SS_BIT)) {
+               writel(MX51_ULPI_WU_BIT, ULPI_VIEWPORT(base));
+               while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_WU_BIT);
        }
-       writel((1 << 30) | (reg << 16), ULPI_VIEWPORT(base));
+       writel(MX51_ULPI_RWRUN | (reg << 16), ULPI_VIEWPORT(base));
        do {
                tmp = readl(ULPI_VIEWPORT(base));
-       } while (tmp & (1 << 30));
+       } while (tmp & MX51_ULPI_RWRUN);
        return (tmp >> 8) & 0xff;
 }

diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..3af7928 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,9 +169,46 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif

+/* Register offsets for MX51 */
+#define MX51_USB_CTRL_OFFSET   0x800
+#define MX51_PHY_CTRL0_OFFSET  0x808
+#define MX51_PHY_CTRL1_OFFSET  0x80c
+#define MX51_USB_CTRL1_OFFSET  0x810
+#define MX51_UH2_CTRL_OFFSET   0x814
+
+/* Some USB_CTRL register bits*/
+#define MX51_OTG_WUE_BIT       (1 << 27)
+#define MX51_OTG_PM_BIT                (1 << 24)
+#define MX51_H1_ULPI_IE_BIT    (1 << 12)
+#define MX51_H1_WUE_BIT                (1 << 11)
+#define MX51_H1_PM_BIT         (1 << 8)
+
+/* Some PHY_CTRL_0 register bits */
+#define MX51_OTG_OVERCURD_BIT  (1 << 8)
+#define MX51_EHCI_POWERPINSE_BIT       (1 << 5)
+
+/* Some PHY_CTRL_1 register bits */
+#define MX51_SYSCLOCK_24_MHZ_BIT       (1 << 0)
+
+/* Some USB_CTRL_1 register bits*/
+#define MX51_H1_EXTCLKE_BIT    (1 << 25)
+
+/* Some USB Host 2 CTRL register bits*/
+#define MX51_H2_ULPI_IE_BIT    (1 << 8)
+#define MX51_H2_WUE_BIT                (1 << 7)
+#define MX51_H2_PM_BIT         (1 << 4)
+
+#define        ULPI_VIEWPORT(base)     (base + 0x170)
+/* ULPI viewport control bits */
+#define MX51_ULPI_WU_BIT       (1 << 31)
+#define MX51_ULPI_SS_BIT       (1 << 27)
+#define MX51_ULPI_RWRUN                (1 << 30)
+#define MX51_ULPI_RWCTRL       (1 << 29)
+
 /*
  * USB Registers
  */
+
 struct usb_ehci {
        u32     id;             /* 0x000 - Identification register */
        u32     hwgeneral;      /* 0x004 - General hardware parameters */
@@ -241,5 +278,4 @@ struct usb_ehci {
        u32     control;        /* 0x500 - Control */
        u8      res13[0xafc];
 };
-
 #endif /* _EHCI_FSL_H */

[U-Boot] some USB cleanup on EfikaMX

[Wolfgang Denk]

Dear Jana Rapava,

In message <CAB+7RbE2MXooOuN3pniuBw7+K71Q0avCfxzuZXuBFfCZpvdctA@mail.gmail.com> you wrote:
> --===============1315613369==
> Content-Type: multipart/alternative; boundary=00151744109ca7dd4e04ac7470e6
> 
> --00151744109ca7dd4e04ac7470e6
> Content-Type: text/plain; charset=ISO-8859-1

Please resubmit as a proper patch.
See http://www.denx.de/wiki/U-Boot/Patches for instructions.

Most important: your signed-off-by: line is missing, as is a
descriptionof which specific problem you are fixing.

> --- a/board/efikamx/efikamx-usb.c
> +++ b/board/efikamx/efikamx-usb.c
> @@ -154,6 +154,7 @@ void efika_usb_phy_reset(void)
>         gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
>  }
> 
> +

Please do not add random (and excessive) white space.

> +       tmp = readl(OTG_BASE_ADDR + MX51_USB_CTRL_OFFSET);
> +       tmp &= ~(MX51_OTG_WUE_BIT | MX51_OTG_PM_BIT | MX51_H1_ULPI_IE_BIT |
> MX51_H1_WUE_BIT);

Your mailer line-wrapped your patch and thus corrupted it.  Please
make sure to configure your mailer not to do that. Even better, use
"git format-patch" to create hte patch and "git send-email" to submit
it.

> -       tmp = readl(OTG_BASE_ADDR + 0x808);
> -       tmp &= ~(1 << 8);
> -       tmp |= 1 << 5;
> -       writel(tmp, OTG_BASE_ADDR + 0x808);
> +       tmp = readl(OTG_BASE_ADDR + MX51_PHY_CTRL0_OFFSET);
> +       tmp &= ~MX51_OTG_OVERCURD_BIT;
> +       tmp |= MX51_EHCI_POWERPINSE_BIT;
> +       writel(tmp, OTG_BASE_ADDR + MX51_PHY_CTRL0_OFFSET);

Please consider using clrsetbits_le32() here instead.

Please fix globally.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
This cultural mystique surrounding the  biological  function  --  you
realize humans are overly preoccupied with the subject.
	-- Kelinda the Kelvan, "By Any Other Name", stardate 4658.9

[U-Boot] some USB cleanup on EfikaMX

[Stefano Babic]

On 09/08/2011 11:06 PM, Jana Rapava wrote:
> --- a/board/efikamx/efikamx-usb.c
> +++ b/board/efikamx/efikamx-usb.c
> @@ -154,6 +154,7 @@ void efika_usb_phy_reset(void)
>         gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
>  }

Hi Jana,

Wolfgang has already addressed most of the issues in your patch. Some
further comments from my site:

> 
> -       tmp = readl(OTG_BASE_ADDR + 0x80c);
> -       tmp &= ~0x3;
> -       tmp |= 0x1;
> -       writel(tmp, OTG_BASE_ADDR + 0x80c);
> +       tmp = readl(OTG_BASE_ADDR + MX51_PHY_CTRL1_OFFSET);
> +       tmp &= ~0x3; /* make sure bits 0 and 1 are set to zero */

The comment adds no information - we already know that bits 0 and 1 are
set to 0, but we do not still know why. Substitute this comment with an
explanation about the meaning of the bits and the *reason* they must be
0. Or set defines as you have already done in the rest of the file.


> +       tmp &= ~(MX51_H2_ULPI_IE_BIT | MX51_H2_WUE_BIT);
> +       //Host 2 VBUS enable controlled by Host 2 controller

Do not use C++ comments.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 1/2 v2] USB cleanup for EfikaMX

[Jana Rapava]

/board/efikamx/efikamx-usb.c: cleanup

Signed-off-by: Jana Rapava <fermata7@gmail.com>
---
 board/efikamx/efikamx-usb.c |  111 +++++++++++++++++++++++--------------------
 include/usb/ehci-fsl.h      |   49 +++++++++++++++++++
 2 files changed, 108 insertions(+), 52 deletions(-)

diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
index 70d0daa..a94a64f 100644
--- a/board/efikamx/efikamx-usb.c
+++ b/board/efikamx/efikamx-usb.c
@@ -161,57 +161,70 @@ void control_regs_setup(void)
 {
 	uint32_t tmp;
 
-	tmp = readl(OTG_BASE_ADDR + 0x800);
-	tmp &= ~((1 << 27) | (1 << 24) | (1 << 12) | (1 << 11));
-	tmp |= 1 << 8;
-	writel(tmp, OTG_BASE_ADDR + 0x800);
-
-	tmp = readl(OTG_BASE_ADDR + 0x808);
-	tmp &= ~(1 << 8);
-	tmp |= 1 << 5;
-	writel(tmp, OTG_BASE_ADDR + 0x808);
-
-	tmp = readl(OTG_BASE_ADDR + 0x80c);
-	tmp &= ~0x3;
-	tmp |= 0x1;
-	writel(tmp, OTG_BASE_ADDR + 0x80c);
-
-	tmp = readl(OTG_BASE_ADDR + 0x810);
-	tmp |= 1 << 25;
-	writel(tmp, OTG_BASE_ADDR + 0x810);
-
-	tmp = readl(OTG_BASE_ADDR + 0x814);
-	tmp &= ~((1 << 8) | (1 << 7));
-	tmp |= 1 << 4;
-	writel(tmp, OTG_BASE_ADDR + 0x814);
+	tmp = readl(OTG_BASE_ADDR + MX51_USB_CTRL_OFFSET);
+	tmp &= ~(MX51_OTG_WUE_BIT | MX51_OTG_PM_BIT | MX51_H1_ULPI_IE_BIT | MX51_H1_WUE_BIT);
+	tmp |= MX51_H1_PM_BIT;
+	writel(tmp, OTG_BASE_ADDR + MX51_USB_CTRL_OFFSET);
+
+	tmp = readl(OTG_BASE_ADDR + MX51_PHY_CTRL0_OFFSET);
+	tmp &= ~MX51_OTG_OVERCURD_BIT;
+	tmp |= MX51_EHCI_POWERPINSE_BIT;
+	writel(tmp, OTG_BASE_ADDR + MX51_PHY_CTRL0_OFFSET);
+
+	tmp = readl(OTG_BASE_ADDR + MX51_PHY_CTRL1_OFFSET);
+	tmp &= MX51_SYSCLOCK_MASK;
+	tmp |= MX51_SYSCLOCK_24_MHZ_BIT;
+	writel(tmp, OTG_BASE_ADDR + MX51_PHY_CTRL1_OFFSET);
+
+	tmp = readl(OTG_BASE_ADDR + MX51_USB_CTRL1_OFFSET);
+	tmp |= MX51_H1_EXTCLKE_BIT;
+	writel(tmp, OTG_BASE_ADDR + MX51_USB_CTRL1_OFFSET);
+
+	tmp = readl(OTG_BASE_ADDR + MX51_UH2_CTRL_OFFSET);
+	tmp &= ~(MX51_H2_ULPI_IE_BIT | MX51_H2_WUE_BIT);
+	tmp |= MX51_H2_PM_BIT;
+	writel(tmp, OTG_BASE_ADDR + MX51_UH2_CTRL_OFFSET);
 
 	udelay(10000);
 }
 
-#define	ULPI_VIEWPORT(base)	(base + 0x170)
+
+#define ULPI_VIEWPORT(base)	(base + 0x170)
+
+/* ULPI viewport control bits */
+#define MX51_ULPI_WU_BIT	(1 << 31)
+#define MX51_ULPI_SS_BIT	(1 << 27)
+#define MX51_ULPI_RWRUN		(1 << 30)
+#define MX51_ULPI_RWCTRL	(1 << 29)
+
+#define shift_to_ulpiaddr(reg)	(reg << 16)
+#define ulpi_write_mask(value)	(value & 0xff)
+#define ulpi_read_mask(value)	((value >> 8) & 0xff)
+
 
 void ulpi_write(u32 base, u32 reg, u32 value)
 {
-	if (!(readl(ULPI_VIEWPORT(base)) & (1 << 27))) {
-		writel(1 << 31, ULPI_VIEWPORT(base));
-		while (readl(ULPI_VIEWPORT(base)) & (1 << 31));
+	if (!(readl(ULPI_VIEWPORT(base)) & MX51_ULPI_SS_BIT)) {
+		writel(MX51_ULPI_WU_BIT, ULPI_VIEWPORT(base));
+		while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_WU_BIT);
 	}
-	writel((1 << 30) | (1 << 29) | (reg << 16) | (value & 0xff), ULPI_VIEWPORT(base));
-	while (readl(ULPI_VIEWPORT(base)) & (1 << 30));
+	writel(MX51_ULPI_RWRUN | MX51_ULPI_RWCTRL | shift_to_ulpiaddr(reg) | ulpi_write_mask(value), ULPI_VIEWPORT(base));
+
+	while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_RWRUN);
 }
 
 u32 ulpi_read(u32 base, u32 reg)
 {
 	u32 tmp;
-	if (!(readl(ULPI_VIEWPORT(base)) & (1 << 27))) {
-		writel(1 << 31, ULPI_VIEWPORT(base));
-		while (readl(ULPI_VIEWPORT(base)) & (1 << 31));
+	if (!(readl(ULPI_VIEWPORT(base)) & MX51_ULPI_SS_BIT)) {
+		writel(MX51_ULPI_WU_BIT, ULPI_VIEWPORT(base));
+		while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_WU_BIT);
 	}
-	writel((1 << 30) | (reg << 16), ULPI_VIEWPORT(base));
+	writel(MX51_ULPI_RWRUN | shift_to_ulpiaddr(reg), ULPI_VIEWPORT(base));
 	do {
 		tmp = readl(ULPI_VIEWPORT(base));
-	} while (tmp & (1 << 30));
-	return (tmp >> 8) & 0xff;
+	} while (tmp & MX51_ULPI_RWRUN);
+	return ulpi_read_mask(tmp);
 }
 
 #define	ULPI_CTL_WRITE_OFF	0x00
@@ -229,8 +242,9 @@ void ehciX_init(u32 base)
 	int reg, i;
 
 	/* ULPI INIT */
-	for (reg = 3; reg >=0; reg--)
+	for (reg = MX51_USB_HOST_COUNT-1; reg >= 0; reg--)
 		tmp |= ulpi_read(base, reg) << (reg * 8);
+	/* split ID into first and second half */
 	printf("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
 
 	/* ULPI check integrity */
@@ -238,7 +252,6 @@ void ehciX_init(u32 base)
 		ulpi_write(base, ULPI_SCRATCH, 0x55 << i);
 		tmp = ulpi_read(base, ULPI_SCRATCH);
 
-		// check
 		if (tmp != (0x55 << i)) {
 			printf("ULPI integrity check failed\n");
 			return;
@@ -264,8 +277,7 @@ void ehciX_init(u32 base)
 
 void ehci0_init(void)
 {
-	/* Set PORTSC to 16b UTMI mode */
-	writel((1 << 28), OTG_BASE_ADDR + 0x184);
+	writel(MX51_16BIT_UTMI_BIT, OTG_BASE_ADDR + MX51_OTG_PORTSC1_OFFSET);
 }
 
 void ehci1_init(void)
@@ -284,24 +296,21 @@ void ehci1_init(void)
 	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
 	udelay(10000);
 
-	tmp = readl(OTG_BASE_ADDR + 0x340);
-	tmp &= ~(0xff << 16);
-	writel(tmp, OTG_BASE_ADDR + 0x340);
+	tmp = readl(OTG_BASE_ADDR + MX51_UH1_USBCMD_OFFSET);
+	tmp &= MX51_ITC_IMMEDIATE_MASK;
+	writel(tmp, OTG_BASE_ADDR + MX51_UH1_USBCMD_OFFSET);
 
 	udelay(10000);
 
-	/* Set PORTSC to ULPI mode */
-	writel((2 << 30), OTG_BASE_ADDR + 0x384);
+	writel(MX51_ULPI_MODE_MASK, OTG_BASE_ADDR + MX51_UH1_PORTSC1_OFFSET);
 	udelay(10000);
 
-	ehciX_init(OTG_BASE_ADDR + 0x200);
+	ehciX_init(OTG_BASE_ADDR + MX51_UH1_ID_OFFSET);
 }
 
 
 void ehci2_init(void)
 {
-	u32 tmp;
-
 	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
 	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
 				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
@@ -313,11 +322,10 @@ void ehci2_init(void)
 	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
 	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
 
-	/* Set PORTSC to ULPI mode */
-	writel((2 << 30), OTG_BASE_ADDR + 0x584);
+	writel(MX51_ULPI_MODE_MASK, OTG_BASE_ADDR + MX51_UH2_PORTSC1_OFFSET);
 	udelay(10000);
 
-	ehciX_init(OTG_BASE_ADDR + 0x400);
+	ehciX_init(OTG_BASE_ADDR + MX51_UH2_ID_OFFSET);
 }
 
 int ehci_hcd_init(void)
@@ -338,10 +346,9 @@ int ehci_hcd_init(void)
 	/* EfikaMX USB has issues ... */
 	udelay(10000);
 
-
 	/* Init EHCI core */
 	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
-		(0x200 * CONFIG_MXC_USB_PORT));
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
 	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
 	hcor = (struct ehci_hcor *)((uint32_t) hccr +
 			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..5617275 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,55 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+#define MX51_USB_HOST_COUNT	4
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_UH1_ID_OFFSET	0x200
+#define MX51_UH2_ID_OFFSET	0x400
+
+#define MX51_USB_CTRL_OFFSET	0x800
+#define MX51_PHY_CTRL0_OFFSET	0x808
+#define MX51_PHY_CTRL1_OFFSET	0x80c
+#define MX51_USB_CTRL1_OFFSET	0x810
+#define MX51_UH2_CTRL_OFFSET	0x814
+
+#define MX51_OTG_PORTSC1_OFFSET	0x184
+#define MX51_UH1_PORTSC1_OFFSET	0x384
+#define MX51_UH2_PORTSC1_OFFSET	0x584
+
+#define MX51_UH1_USBCMD_OFFSET	0x340
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_WUE_BIT	(1 << 27)
+#define MX51_OTG_PM_BIT		(1 << 24)
+#define MX51_H1_ULPI_IE_BIT	(1 << 12)
+#define MX51_H1_WUE_BIT		(1 << 11)
+#define MX51_H1_PM_BIT		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD_BIT		(1 << 8)
+#define MX51_EHCI_POWERPINSE_BIT	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ_BIT	(1 << 0)
+#define MX51_SYSCLOCK_MASK		(0xffffffff << 0)
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE_BIT	(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE_BIT	(1 << 8)
+#define MX51_H2_WUE_BIT		(1 << 7)
+#define MX51_H2_PM_BIT		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI_BIT	(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(~(0xff << 16))
+
 /*
  * USB Registers
  */
-- 
1.7.5.4

[U-Boot] [PATCH 1/2 v2] USB cleanup for EfikaMX

[Marek Vasut]

On Monday, September 12, 2011 07:20:40 PM Jana Rapava wrote:
> /board/efikamx/efikamx-usb.c: cleanup
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> ---
>  board/efikamx/efikamx-usb.c |  111
> +++++++++++++++++++++++-------------------- include/usb/ehci-fsl.h      | 
>  49 +++++++++++++++++++
>  2 files changed, 108 insertions(+), 52 deletions(-)

Dear Jana Rapava,

1) PATCH 2/2 is missing.
2) This doesn't apply on mainline, continue as discussed on IRC -- ie. by 
merging the patches.

> 
> diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
> index 70d0daa..a94a64f 100644
> --- a/board/efikamx/efikamx-usb.c
> +++ b/board/efikamx/efikamx-usb.c
> @@ -161,57 +161,70 @@ void control_regs_setup(void)
>  {

[...]

> +	tmp = readl(OTG_BASE_ADDR + MX51_USB_CTRL_OFFSET);
> +	tmp &= ~(MX51_OTG_WUE_BIT | MX51_OTG_PM_BIT | MX51_H1_ULPI_IE_BIT |
> MX51_H1_WUE_BIT); +	tmp |= MX51_H1_PM_BIT;

I assume this is ULPI specific, not MX51 specific.

> +	writel(tmp, OTG_BASE_ADDR + MX51_USB_CTRL_OFFSET);

Don't use offset-based access, but struct based access, please fix globally.

struct otg_regs {
uint32_t reg1;
uint32_t reg2;
...
};

then

struct otg_regs *regs = (struct otg_regs *)REG_ADDR;

writel(val, &regs->reg1);

[...]
> 
> -#define	ULPI_VIEWPORT(base)	(base + 0x170)
> +
> +#define ULPI_VIEWPORT(base)	(base + 0x170)

struct ehci probably already contains the correct offset of the ulpi viewport. 
You just need to cast struct ehci to correct offset of the port.

> +
> +/* ULPI viewport control bits */
> +#define MX51_ULPI_WU_BIT	(1 << 31)
> +#define MX51_ULPI_SS_BIT	(1 << 27)
> +#define MX51_ULPI_RWRUN		(1 << 30)
> +#define MX51_ULPI_RWCTRL	(1 << 29)

See above.

> +
> +#define shift_to_ulpiaddr(reg)	(reg << 16)

#define ULPI_something_ADDR_OFFSET	16 ?

> +#define ulpi_write_mask(value)	(value & 0xff)
> +#define ulpi_read_mask(value)	((value >> 8) & 0xff)

Missing parenthesis around value.

> +
> 
>  void ulpi_write(u32 base, u32 reg, u32 value)
>  {
> -	if (!(readl(ULPI_VIEWPORT(base)) & (1 << 27))) {
> -		writel(1 << 31, ULPI_VIEWPORT(base));
> -		while (readl(ULPI_VIEWPORT(base)) & (1 << 31));
> +	if (!(readl(ULPI_VIEWPORT(base)) & MX51_ULPI_SS_BIT)) {

See above.

> +		writel(MX51_ULPI_WU_BIT, ULPI_VIEWPORT(base));
> +		while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_WU_BIT);

Semicolon should be on the new line. Please fix globally.

>  	}
> -	writel((1 << 30) | (1 << 29) | (reg << 16) | (value & 0xff),
> ULPI_VIEWPORT(base)); -	while (readl(ULPI_VIEWPORT(base)) & (1 << 30));
> +	writel(MX51_ULPI_RWRUN | MX51_ULPI_RWCTRL | shift_to_ulpiaddr(reg) |
> ulpi_write_mask(value), ULPI_VIEWPORT(base)); +
> +	while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_RWRUN);
>  }
> 
>  u32 ulpi_read(u32 base, u32 reg)
>  {
>  	u32 tmp;
> -	if (!(readl(ULPI_VIEWPORT(base)) & (1 << 27))) {
> -		writel(1 << 31, ULPI_VIEWPORT(base));
> -		while (readl(ULPI_VIEWPORT(base)) & (1 << 31));
> +	if (!(readl(ULPI_VIEWPORT(base)) & MX51_ULPI_SS_BIT)) {
> +		writel(MX51_ULPI_WU_BIT, ULPI_VIEWPORT(base));
> +		while (readl(ULPI_VIEWPORT(base)) & MX51_ULPI_WU_BIT);
>  	}
> -	writel((1 << 30) | (reg << 16), ULPI_VIEWPORT(base));
> +	writel(MX51_ULPI_RWRUN | shift_to_ulpiaddr(reg), ULPI_VIEWPORT(base));
>  	do {
>  		tmp = readl(ULPI_VIEWPORT(base));
> -	} while (tmp & (1 << 30));
> -	return (tmp >> 8) & 0xff;
> +	} while (tmp & MX51_ULPI_RWRUN);
> +	return ulpi_read_mask(tmp);
>  }
> 
>  #define	ULPI_CTL_WRITE_OFF	0x00
> @@ -229,8 +242,9 @@ void ehciX_init(u32 base)
>  	int reg, i;
> 
>  	/* ULPI INIT */
> -	for (reg = 3; reg >=0; reg--)
> +	for (reg = MX51_USB_HOST_COUNT-1; reg >= 0; reg--)

COUNT-1 missing spaces.

>  		tmp |= ulpi_read(base, reg) << (reg * 8);
> +	/* split ID into first and second half */

debug() ?

What's "first" and "second" half, do you mean vendor and product ID ?

>  	printf("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
> 
>  	/* ULPI check integrity */
> @@ -238,7 +252,6 @@ void ehciX_init(u32 base)
>  		ulpi_write(base, ULPI_SCRATCH, 0x55 << i);
>  		tmp = ulpi_read(base, ULPI_SCRATCH);
> 
> -		// check
>  		if (tmp != (0x55 << i)) {
>  			printf("ULPI integrity check failed\n");
>  			return;
> @@ -264,8 +277,7 @@ void ehciX_init(u32 base)
> 
>  void ehci0_init(void)
>  {
> -	/* Set PORTSC to 16b UTMI mode */
> -	writel((1 << 28), OTG_BASE_ADDR + 0x184);
> +	writel(MX51_16BIT_UTMI_BIT, OTG_BASE_ADDR + MX51_OTG_PORTSC1_OFFSET);

See above.

>  }
> 
>  void ehci1_init(void)
> @@ -284,24 +296,21 @@ void ehci1_init(void)
>  	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
>  	udelay(10000);
> 
> -	tmp = readl(OTG_BASE_ADDR + 0x340);
> -	tmp &= ~(0xff << 16);
> -	writel(tmp, OTG_BASE_ADDR + 0x340);
> +	tmp = readl(OTG_BASE_ADDR + MX51_UH1_USBCMD_OFFSET);
> +	tmp &= MX51_ITC_IMMEDIATE_MASK;
> +	writel(tmp, OTG_BASE_ADDR + MX51_UH1_USBCMD_OFFSET);

Try clrsetbits_le32() and other calls from asm/io.h

> 
>  	udelay(10000);
> 
> -	/* Set PORTSC to ULPI mode */
> -	writel((2 << 30), OTG_BASE_ADDR + 0x384);
> +	writel(MX51_ULPI_MODE_MASK, OTG_BASE_ADDR + MX51_UH1_PORTSC1_OFFSET);
>  	udelay(10000);
> 
> -	ehciX_init(OTG_BASE_ADDR + 0x200);
> +	ehciX_init(OTG_BASE_ADDR + MX51_UH1_ID_OFFSET);
>  }
> 
> 
>  void ehci2_init(void)
>  {
> -	u32 tmp;
> -
>  	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
>  	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
>  				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> @@ -313,11 +322,10 @@ void ehci2_init(void)
>  	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
>  	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
> 
> -	/* Set PORTSC to ULPI mode */
> -	writel((2 << 30), OTG_BASE_ADDR + 0x584);
> +	writel(MX51_ULPI_MODE_MASK, OTG_BASE_ADDR + MX51_UH2_PORTSC1_OFFSET);

I think struct ehci defines this offset.

>  	udelay(10000);
> 
> -	ehciX_init(OTG_BASE_ADDR + 0x400);
> +	ehciX_init(OTG_BASE_ADDR + MX51_UH2_ID_OFFSET);
>  }
> 
>  int ehci_hcd_init(void)
> @@ -338,10 +346,9 @@ int ehci_hcd_init(void)
>  	/* EfikaMX USB has issues ... */
>  	udelay(10000);
> 
> -
>  	/* Init EHCI core */
>  	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> -		(0x200 * CONFIG_MXC_USB_PORT));
> +		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
>  	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
>  	hcor = (struct ehci_hcor *)((uint32_t) hccr +
>  			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
> index 67600ed..5617275 100644
> --- a/include/usb/ehci-fsl.h
> +++ b/include/usb/ehci-fsl.h
> @@ -169,6 +169,55 @@
>  #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
>  #endif
> 
> +#define MX51_USB_HOST_COUNT	4
> +#define MX51_REGISTER_LAYOUT_LENGTH	0x200
> +
> +/* Register offsets for MX51 */
> +#define MX51_UH1_ID_OFFSET	0x200
> +#define MX51_UH2_ID_OFFSET	0x400
> +
> +#define MX51_USB_CTRL_OFFSET	0x800
> +#define MX51_PHY_CTRL0_OFFSET	0x808
> +#define MX51_PHY_CTRL1_OFFSET	0x80c
> +#define MX51_USB_CTRL1_OFFSET	0x810
> +#define MX51_UH2_CTRL_OFFSET	0x814

MX5_, not MX51, I think this is valid for MX53 too.

> +
> +#define MX51_OTG_PORTSC1_OFFSET	0x184
> +#define MX51_UH1_PORTSC1_OFFSET	0x384
> +#define MX51_UH2_PORTSC1_OFFSET	0x584
> +
> +#define MX51_UH1_USBCMD_OFFSET	0x340

Use struct ehci where this is used with proper cast.
> +
> +/* USB_CTRL register bits of interest*/
> +#define MX51_OTG_WUE_BIT	(1 << 27)
> +#define MX51_OTG_PM_BIT		(1 << 24)
> +#define MX51_H1_ULPI_IE_BIT	(1 << 12)
> +#define MX51_H1_WUE_BIT		(1 << 11)
> +#define MX51_H1_PM_BIT		(1 << 8)
> +
> +/* PHY_CTRL_0 register bits of interest */
> +#define MX51_OTG_OVERCURD_BIT		(1 << 8)
> +#define MX51_EHCI_POWERPINSE_BIT	(1 << 5)
> +
> +/* PHY_CTRL_1 register bits of interest */
> +#define MX51_SYSCLOCK_24_MHZ_BIT	(1 << 0)
> +#define MX51_SYSCLOCK_MASK		(0xffffffff << 0)

don't use << 0 here. Is this even needed?

> +
> +/* USB_CTRL_1 register bits of interest */
> +#define MX51_H1_EXTCLKE_BIT	(1 << 25)
> +
> +/* USB Host 2 CTRL register bits of interest */
> +#define MX51_H2_ULPI_IE_BIT	(1 << 8)
> +#define MX51_H2_WUE_BIT		(1 << 7)
> +#define MX51_H2_PM_BIT		(1 << 4)
> +
> +/* PORTSCx bits of interest */
> +#define MX51_ULPI_MODE_MASK	(2 << 30)
> +#define MX51_16BIT_UTMI_BIT	(1 << 28)
> +
> +/* USBCMD bits of interest */
> +#define MX51_ITC_IMMEDIATE_MASK	(~(0xff << 16))
> +
>  /*
>   * USB Registers
>   */

Cheers

[U-Boot] [PATCH v3] Add USB support for Efika

[Jana Rapava]

From: Marek Vasut <marek.vasut@gmail.com>

This commit adds USB support for EfikaMX and EfikaSB. 

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Jana Rapava <fermata7@gmail.com>
---
Changes for v2:
	- changed to proper patch
Changes for v3:
	- merged other USB patches from u-boot-pxa/efikasb
	- offset-based access changed to struct-based access
	- use {clrset,clr,set}bits_le32() calls
	- CodingStyle and naming cleanup

 board/efikamx/Makefile      |    3 +
 board/efikamx/efikamx-usb.c |  349 +++++++++++++++++++++++++++++++++++++++++++
 board/efikamx/efikamx.c     |   10 ++
 drivers/usb/host/ehci-hcd.c |   19 +++
 drivers/usb/host/ehci-mxc.c |    9 +-
 include/configs/efikamx.h   |   35 ++++-
 include/usb/ehci-fsl.h      |  112 ++++++++++++++-
 7 files changed, 524 insertions(+), 13 deletions(-)
 create mode 100644 board/efikamx/efikamx-usb.c

diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
index ee4a16e..860e4d2 100644
--- a/board/efikamx/Makefile
+++ b/board/efikamx/Makefile
@@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= efikamx.o
+ifdef	CONFIG_CMD_USB
+COBJS	+= efikamx-usb.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
new file mode 100644
index 0000000..19227d4
--- /dev/null
+++ b/board/efikamx/efikamx-usb.c
@@ -0,0 +1,349 @@
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+
+#include "../../drivers/usb/host/ehci.h"
+#include "../../drivers/usb/host/ehci-core.h"
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX
+ */
+#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
+			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
+void setup_iomux_usb(void)
+{
+	/*
+	 * Configure USBH1 pads
+	 */
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
+
+	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
+
+	/*
+	 * Configure USBH1 control pads
+	 */
+
+	/* USB PHY reset */
+	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+	/* USB HUB reset */
+	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+
+#ifdef	CONFIG_MACH_EFIKASB
+	/*
+	 * Configure USBH2 pads (used on EfikaSB)
+	 */
+	/* USBH2_DATA */
+	mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
+
+	/* USBH2_CLK */
+	mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
+	/* USBH2_DIR */
+	mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
+	/* USBH2_STP */
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+	/* USBH2_NXT */
+	mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
+#endif
+
+	/* WIFI EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
+	/* WIFI RESET */
+	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
+	/* BT EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+}
+
+/*
+ * Enable devices connected to USB BUSes
+ */
+void efika_usb_enable_devices(void)
+{
+	/* Enable Bluetooth */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+
+	/* Enable WiFi */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	udelay(10000);
+
+	/* Reset the WiFi chip */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB)
+ */
+void efika_usb_hub_reset(void)
+{
+	/* HUB reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB)
+ */
+void efika_usb_phy_reset(void)
+{
+	/* SMSC 3317 PHY reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+}
+
+/*
+ * Configure control registers of the USB controller
+ */
+void control_regs_setup(struct usb_control_regs *control)
+{
+	clrsetbits_le32(&control->usbctrl,
+			(MXX1_OTG_WUE | MXX1_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
+			MX51_H1_PM);
+
+	clrsetbits_le32(&control->phyctrl0,
+			MX51_OTG_OVERCURD,
+			MX51_EHCI_POWERPINSE);
+
+	clrsetbits_le32(&control->phyctrl1,
+			MX51_SYSCLOCK_MASK,
+			MX51_SYSCLOCK_24_MHZ);
+
+	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
+
+	clrsetbits_le32(&control->uh2ctrl,
+			(MX51_H2_ULPI_IE | MX51_H2_WUE),
+			MX51_H2_PM);
+
+	udelay(10000);
+}
+
+#define ULPI_ADDR_SHIFT		16
+#define ulpi_write_mask(value)	((value) & 0xff)
+#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
+
+
+void ulpi_write(u32 reg, u32 value, struct usb_ehci *ehci)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		while (readl(&ehci->ulpi_viewpoint) & ULPI_WU)
+		;
+	}
+	writel(ULPI_RWRUN | ULPI_RWCTRL | reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
+		&ehci->ulpi_viewpoint);
+
+	while (readl(&ehci->ulpi_viewpoint) & ULPI_RWRUN)
+	;
+}
+
+u32 ulpi_read(u32 reg, struct usb_ehci *ehci)
+{
+	u32 tmp;
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		while (readl(&ehci->ulpi_viewpoint) & ULPI_WU)
+		;
+	}
+	writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
+	do {
+		tmp = readl(&ehci->ulpi_viewpoint);
+	} while (tmp & ULPI_RWRUN);
+	return ulpi_read_mask(tmp);
+}
+
+void ehciX_init(u32 base, struct ulpi_regs *ulpi, struct usb_ehci *ehci)
+{
+	u32 tmp = 0;
+	int reg, i;
+
+	/* get ID from ULPI immediate registers*/
+	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
+		tmp |= ulpi_read(reg, ehci) << (reg * 8);
+	/* split into vendor and product ID */
+	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
+
+	/* ULPI check integrity */
+	for (i = 0; i < 2; i++) {
+		ulpi_write(&ulpi->scratch_write, 0x55 << i, ehci);
+		tmp = ulpi_read(&ulpi->scratch_write, ehci);
+
+		if (tmp != (0x55 << i)) {
+			printf("ULPI integrity check failed\n");
+			return;
+		}
+	}
+
+	/* ULPI set flags */
+	ulpi_write(&ulpi->otg_ctrl_write,
+		ULPI_OTG_EXT_VBUS_IND | ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN, ehci);
+	ulpi_write(&ulpi->function_ctrl_write,
+		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL | ULPI_FC_SUSPENDM_PWRED, ehci);
+	ulpi_write(&ulpi->iface_ctrl_write, 0, ehci);
+	ulpi_write(&ulpi->otg_ctrl_set,
+		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT, ehci);
+
+	/*
+	 * NOTE: This violates USB specification, but otherwise, USB on Efika
+	 * doesn't work.
+	 */
+	ulpi_write(&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS, ehci);
+}
+
+void ehci0_init(struct usb_ehci *ehci)
+{
+	setbits_le32(&ehci->portsc, MX51_16BIT_UTMI);
+}
+
+void ehci1_init(struct usb_ehci *ehci, struct ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	udelay(10000);
+
+	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
+	udelay(10000);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ehciX_init(OTG_BASE_ADDR + MX51_UH1_ID, ulpi, ehci);
+}
+
+
+void ehci2_init(struct usb_ehci *ehci, struct ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+
+	setbits_le32(&ehci->portsc, MX51_ULPI_MODE_MASK);
+	udelay(10000);
+
+	ehciX_init(OTG_BASE_ADDR + MX51_UH2_ID, ulpi, ehci);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+	struct usb_control_regs *control;
+	struct ulpi_regs *ulpi;
+
+	/* Init iMX51 EHCI */
+	efika_usb_phy_reset();
+	efika_usb_hub_reset();
+	efika_usb_enable_devices();
+
+	control = (struct usb_control_regs *)(OTG_BASE_ADDR +
+		 MX51_CTRL_REGS);
+	control_regs_setup(control);
+
+	ulpi = (struct ulpi_regs *)(0);
+	/* Init EHCI core */
+	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+	setbits_le32(&ehci->control, USB_EN);
+
+	switch (CONFIG_MXC_USB_PORT) {
+	case 0:
+		ehci0_init(ehci);
+	case 1:
+		ehci1_init(ehci, ulpi);
+#ifdef	MACH_EFIKASB
+	case 2:
+		ehci2_init(ehci, ulpi);
+#endif
+	};
+
+	/* EfikaMX USB has issues ... */
+	udelay(10000);
+
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 5be1f6c..0f84ae0 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -489,6 +489,15 @@ static inline void setup_iomux_ata(void) { }
 #endif
 
 /*
+ * EHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+extern void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
+
+/*
  * LED configuration
  */
 void setup_iomux_led(void)
@@ -621,6 +630,7 @@ int board_late_init(void)
 
 	setup_iomux_led();
 	setup_iomux_ata();
+	setup_iomux_usb();
 
 	efikamx_toggle_led(EFIKAMX_LED_BLUE);
 
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..52b98c2 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -26,6 +26,7 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <watchdog.h>
+#include <usb/ehci-fsl.h>
 
 #include "ehci.h"
 
@@ -709,8 +710,26 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 				 * usb 2.0 specification say 50 ms resets on
 				 * root
 				 */
+				/* wait_ms(50); */
+
+#if 1
+	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH));
+	extern u32 ulpi_read(u32 reg, struct usb_ehci *ehci);
+	extern void ulpi_write(u32 reg, u32 value, struct usb_ehci *ehci);
+	#define XXBASE 0x73f80200
+	/* OTG |= 1 << 4 */
+	u32 tmp = ulpi_read(0x0a, ehci);
+	tmp |= (1 << 4);
+	ulpi_write(0x0a, tmp, ehci);
+
 				wait_ms(50);
+
+
 				/* terminate the reset */
+	reg = ehci_readl(status_reg);
+	reg |= EHCI_PS_PE;
+#endif
 				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 				/*
 				 * A host controller must terminate the reset
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..de7ed00 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -37,9 +37,6 @@
 #endif
 
 #ifdef CONFIG_MX31
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
 
 #define MX31_H2_SIC_SHIFT	21
 #define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
@@ -66,11 +63,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		switch (port) {
 		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+			v &= ~(MXX1_OTG_SIC_MASK | MXX1_OTG_PM_BIT);
 			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
+					<< MXX1_OTG_SIC_SHIFT;
 			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
+				v |= MXX1_OTG_PM_BIT;
 
 			break;
 		case 1: /* H1 port */
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index b90e342..9cbb024 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -40,6 +40,10 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
+#define	CONFIG_L2_OFF
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
 /*
  * Bootloader Components Configuration
  */
@@ -49,6 +53,8 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_IDE
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DATE
 #undef CONFIG_CMD_IMLS
 
 /*
@@ -168,17 +174,34 @@
 #endif
 
 /*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define	CONFIG_USB_HOST_ETHER
+#define	CONFIG_USB_KEYBOARD
+/* USB NET */
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_USB_ETHER_ASIX
+#define	CONFIG_NET_MULTI
+#define	CONFIG_CMD_PING
+#define	CONFIG_CMD_DHCP
+#endif
+#endif /* CONFIG_CMD_USB */
+
+/*
  * Filesystems
  */
 #ifdef CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
+#ifdef	CONFIG_CMD_NET
+#define	CONFIG_CMD_NFS
+#endif
 #endif
-
-#undef CONFIG_CMD_PING
-#undef CONFIG_CMD_DHCP
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#define CONFIG_CMD_DATE
 
 /*
  * Miscellaneous configurable options
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..9360ba5 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,78 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+
+#ifdef CONFIG_MX51 || CONFIG_MX31
+/* USB_CTRL register bits of interest*/
+#define MXX1_OTG_SIC_SHIFT	29
+#define MXX1_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
+#define MXX1_OTG_WUE		(1 << 27)
+#define MXX1_OTG_PM		(1 << 24)
+#endif
+
+#ifdef CONFIG_MX51
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_OTG_ID	0x000
+#define MX51_UH1_ID	0x200
+#define MX51_UH2_ID	0x400
+#define MX51_CTRL_REGS	0x800
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_PM		(1 << 24)
+#define MX51_H1_ULPI_IE		(1 << 12)
+#define MX51_H1_WUE		(1 << 11)
+#define MX51_H1_PM		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD	(1 << 8)
+#define MX51_EHCI_POWERPINSE	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ	(1 << 0)
+#define MX51_SYSCLOCK_MASK	(~(0xffffffff << 2))
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE		(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE		(1 << 8)
+#define MX51_H2_WUE		(1 << 7)
+#define MX51_H2_PM		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI		(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(0xff << 16)
+#endif
+
+/*
+* ULPI
+*/
+#define ULPI_ID_REGS_COUNT	4
+
+/* ULPI viewport control bits */
+#define ULPI_WU		(1 << 31)
+#define ULPI_SS		(1 << 27)
+#define ULPI_RWRUN	(1 << 30)
+#define ULPI_RWCTRL	(1 << 29)
+
+/* ULPI OTG Control bits of interest */
+#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
+#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
+#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
+#define	ULPI_OTG_DRV_VBUS	(1 << 5)
+#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
+#define ULPI_OTG_CHRG_VBUS	(1 << 4)
+
+/* ULPI Function Control bits of interest */
+#define ULPI_FC_XCVR_SELECT	(1 << 0)
+#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
+#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
+
 /*
  * USB Registers
  */
@@ -210,7 +282,7 @@ struct usb_ehci {
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
 					   pre-buffer packet tuning */
 	u8	res7[0x8];
-	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
 	u8	res8[0xc];
 	u32	config_flag;	/* 0x180 - Configured Flag Register */
 	u32	portsc;		/* 0x184 - Port status/control */
@@ -242,4 +314,42 @@ struct usb_ehci {
 	u8	res13[0xafc];
 };
 
+struct usb_control_regs {
+	u32	usbctrl;	/* 0x800 - USB Control */
+	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
+	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
+	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
+	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
+	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
+	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
+};
+
+struct ulpi_regs {
+	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
+	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
+	u8	product_id_low;		/* 0x02 - Product ID lower byte */
+	u8	product_id_high;	/* 0x03 - Product ID higher byte */
+	u8	function_ctrl_write;	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	u8	iface_ctrl_write;	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	u8	otg_ctrl_write;		/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	u8	usb_ie_rising_write;	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	u8	usb_ie_falling_write;	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
+	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
+	u8	debug;			/* 0x15 - Debug */
+	u8	scratch_write;		/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 */
+};
+
 #endif /* _EHCI_FSL_H */
-- 
1.7.6.3

[U-Boot] [PATCH v3] Add USB support for Efika

[Marek Vasut]

On Sunday, September 18, 2011 04:19:28 AM Jana Rapava wrote:
> From: Marek Vasut <marek.vasut@gmail.com>
> 
> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> ---
> Changes for v2:
> 	- changed to proper patch
> Changes for v3:
> 	- merged other USB patches from u-boot-pxa/efikasb
> 	- offset-based access changed to struct-based access
> 	- use {clrset,clr,set}bits_le32() calls
> 	- CodingStyle and naming cleanup

Dear Jana Rapava,

the patch doesn't pass checkpatch:
WARNING: line over 80 characters
#253: FILE: board/efikamx/efikamx-usb.c:163:
+                       (MXX1_OTG_WUE | MXX1_OTG_PM | MX51_H1_ULPI_IE | 
MX51_H1_WUE),
and a lot of other such stuff.

Also, CC Stefano Babic and Remy Bohmer for next iteration, they're imx custodian 
and usb custodian respectively.
> 
>  board/efikamx/Makefile      |    3 +
>  board/efikamx/efikamx-usb.c |  349
> +++++++++++++++++++++++++++++++++++++++++++ board/efikamx/efikamx.c     | 
>  10 ++
>  drivers/usb/host/ehci-hcd.c |   19 +++
>  drivers/usb/host/ehci-mxc.c |    9 +-
>  include/configs/efikamx.h   |   35 ++++-
>  include/usb/ehci-fsl.h      |  112 ++++++++++++++-
>  7 files changed, 524 insertions(+), 13 deletions(-)
>  create mode 100644 board/efikamx/efikamx-usb.c
> 
> diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
> index ee4a16e..860e4d2 100644
> --- a/board/efikamx/Makefile
> +++ b/board/efikamx/Makefile
> @@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
>  LIB	= $(obj)lib$(BOARD).o
> 
>  COBJS	:= efikamx.o
> +ifdef	CONFIG_CMD_USB
> +COBJS	+= efikamx-usb.o
> +endif
> 
>  SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
>  OBJS	:= $(addprefix $(obj),$(COBJS))
> diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
> new file mode 100644
> index 0000000..19227d4
> --- /dev/null
> +++ b/board/efikamx/efikamx-usb.c

[...]

> +
> +/*
> + * Configure control registers of the USB controller
> + */
> +void control_regs_setup(struct usb_control_regs *control)
> +{
> +	clrsetbits_le32(&control->usbctrl,
> +			(MXX1_OTG_WUE | MXX1_OTG_PM | MX51_H1_ULPI_IE | 
MX51_H1_WUE),

What's this MXX1_ stuff ?

> +			MX51_H1_PM);
> +
> +	clrsetbits_le32(&control->phyctrl0,
> +			MX51_OTG_OVERCURD,
> +			MX51_EHCI_POWERPINSE);
> +
> +	clrsetbits_le32(&control->phyctrl1,
> +			MX51_SYSCLOCK_MASK,
> +			MX51_SYSCLOCK_24_MHZ);
> +
> +	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
> +
> +	clrsetbits_le32(&control->uh2ctrl,
> +			(MX51_H2_ULPI_IE | MX51_H2_WUE),
> +			MX51_H2_PM);
> +
> +	udelay(10000);
> +}
> +
> +#define ULPI_ADDR_SHIFT		16
> +#define ulpi_write_mask(value)	((value) & 0xff)
> +#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
> +
> +
> +void ulpi_write(u32 reg, u32 value, struct usb_ehci *ehci)
> +{
> +	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +		writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +		while (readl(&ehci->ulpi_viewpoint) & ULPI_WU)
> +		;

Checkpatch issue here. Please fix globally.

> +	}
> +	writel(ULPI_RWRUN | ULPI_RWCTRL | reg << ULPI_ADDR_SHIFT |
> ulpi_write_mask(value), +		&ehci->ulpi_viewpoint);
> +
> +	while (readl(&ehci->ulpi_viewpoint) & ULPI_RWRUN)
> +	;

DTTO

> +}
> +
> +u32 ulpi_read(u32 reg, struct usb_ehci *ehci)
> +{
> +	u32 tmp;
> +	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +		writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +		while (readl(&ehci->ulpi_viewpoint) & ULPI_WU)
> +		;

Please avoid endless loops. Please fix globally.

> +	}
> +	writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
> +	do {
> +		tmp = readl(&ehci->ulpi_viewpoint);
> +	} while (tmp & ULPI_RWRUN);
> +	return ulpi_read_mask(tmp);
> +}
> +
> +void ehciX_init(u32 base, struct ulpi_regs *ulpi, struct usb_ehci *ehci)

Rename to something more sensible? ulpi_init ? Is "base" unused?

> +{
> +	u32 tmp = 0;
> +	int reg, i;
> +
> +	/* get ID from ULPI immediate registers*/

space before closing comment.

> +	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
> +		tmp |= ulpi_read(reg, ehci) << (reg * 8);
> +	/* split into vendor and product ID */
> +	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
> +
> +	/* ULPI check integrity */
> +	for (i = 0; i < 2; i++) {
> +		ulpi_write(&ulpi->scratch_write, 0x55 << i, ehci);

Magic constant should be documented.

> +		tmp = ulpi_read(&ulpi->scratch_write, ehci);
> +
> +		if (tmp != (0x55 << i)) {
> +			printf("ULPI integrity check failed\n");
> +			return;
> +		}
> +	}

[...]

> +
> +int ehci_hcd_init(void)
> +{
> +	struct usb_ehci *ehci;
> +	struct usb_control_regs *control;
> +	struct ulpi_regs *ulpi;
> +
> +	/* Init iMX51 EHCI */
> +	efika_usb_phy_reset();
> +	efika_usb_hub_reset();
> +	efika_usb_enable_devices();
> +
> +	control = (struct usb_control_regs *)(OTG_BASE_ADDR +
> +		 MX51_CTRL_REGS);

mx5_usb_control_regs might be a more fitting name for the structure.

> +	control_regs_setup(control);
> +
> +	ulpi = (struct ulpi_regs *)(0);

No need for parenthesis around 0.

> +	/* Init EHCI core */
> +	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
> +	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
> +	hcor = (struct ehci_hcor *)((uint32_t) hccr +
> +			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> +	setbits_le32(&ehci->usbmode, CM_HOST);
> +	setbits_le32(&ehci->control, USB_EN);
> +
> +	switch (CONFIG_MXC_USB_PORT) {
> +	case 0:
> +		ehci0_init(ehci);
> +	case 1:
> +		ehci1_init(ehci, ulpi);
> +#ifdef	MACH_EFIKASB
> +	case 2:
> +		ehci2_init(ehci, ulpi);
> +#endif
> +	};

Fallthrough here isn't intended I presume.

> +
> +	/* EfikaMX USB has issues ... */
> +	udelay(10000);
> +

Too many newlines.

> +
> +	return 0;
> +}
> +
> +int ehci_hcd_stop(void)
> +{
> +	return 0;
> +}
> diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
> index 5be1f6c..0f84ae0 100644
> --- a/board/efikamx/efikamx.c
> +++ b/board/efikamx/efikamx.c
> @@ -489,6 +489,15 @@ static inline void setup_iomux_ata(void) { }
>  #endif
> 
>  /*
> + * EHCI USB
> + */
> +#ifdef	CONFIG_CMD_USB
> +extern void setup_iomux_usb(void);
> +#else
> +static inline void setup_iomux_usb(void) { }
> +#endif

Avoid using extern.

> +
> +/*
>   * LED configuration
>   */
>  void setup_iomux_led(void)
> @@ -621,6 +630,7 @@ int board_late_init(void)
> 
>  	setup_iomux_led();
>  	setup_iomux_ata();
> +	setup_iomux_usb();
> 
>  	efikamx_toggle_led(EFIKAMX_LED_BLUE);
> 
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index 2197119..52b98c2 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -26,6 +26,7 @@
>  #include <asm/io.h>
>  #include <malloc.h>
>  #include <watchdog.h>
> +#include <usb/ehci-fsl.h>
> 
>  #include "ehci.h"
> 
> @@ -709,8 +710,26 @@ ehci_submit_root(struct usb_device *dev, unsigned long
> pipe, void *buffer, * usb 2.0 specification say 50 ms resets on
>  				 * root
>  				 */
> +				/* wait_ms(50); */
> +
> +#if 1
> +	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +		(MX51_REGISTER_LAYOUT_LENGTH));
> +	extern u32 ulpi_read(u32 reg, struct usb_ehci *ehci);
> +	extern void ulpi_write(u32 reg, u32 value, struct usb_ehci *ehci);
> +	#define XXBASE 0x73f80200
> +	/* OTG |= 1 << 4 */
> +	u32 tmp = ulpi_read(0x0a, ehci);
> +	tmp |= (1 << 4);
> +	ulpi_write(0x0a, tmp, ehci);
> +
>  				wait_ms(50);
> +
> +
>  				/* terminate the reset */
> +	reg = ehci_readl(status_reg);
> +	reg |= EHCI_PS_PE;
> +#endif

UGH, no. This needs to be fixed !!

Remy, how are we supposed to handle such cases? For this hardware, when doing 
usb port reset without this code fails the port reset (the VBUS is disabled on 
the ulpi xmitter and it's all over). That's why you need to restart the vbus 
here.

>  				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
>  				/*
>  				 * A host controller must terminate the reset
> diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
> index a0cfbb7..de7ed00 100644
> --- a/drivers/usb/host/ehci-mxc.c
> +++ b/drivers/usb/host/ehci-mxc.c
> @@ -37,9 +37,6 @@
>  #endif
> 
>  #ifdef CONFIG_MX31
> -#define MX31_OTG_SIC_SHIFT	29
> -#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
> -#define MX31_OTG_PM_BIT		(1 << 24)
> 
>  #define MX31_H2_SIC_SHIFT	21
>  #define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
> @@ -66,11 +63,11 @@ static int mxc_set_usbcontrol(int port, unsigned int
> flags)
> 
>  		switch (port) {
>  		case 0:	/* OTG port */
> -			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
> +			v &= ~(MXX1_OTG_SIC_MASK | MXX1_OTG_PM_BIT);

Replace MXX1 with MXC?

>  			v |= (flags & MXC_EHCI_INTERFACE_MASK)
> -					<< MX31_OTG_SIC_SHIFT;
> +					<< MXX1_OTG_SIC_SHIFT;
>  			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
> -				v |= MX31_OTG_PM_BIT;
> +				v |= MXX1_OTG_PM_BIT;
> 
>  			break;
>  		case 1: /* H1 port */

Cheers

[U-Boot] [PATCH v3] Add USB support for Efika

[Stefano Babic]

On 09/18/2011 04:19 AM, Jana Rapava wrote:
> From: Marek Vasut <marek.vasut@gmail.com>
> 
> This commit adds USB support for EfikaMX and EfikaSB. 
> 
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> ---
> Changes for v2:
> 	- changed to proper patch
> Changes for v3:
> 	- merged other USB patches from u-boot-pxa/efikasb
> 	- offset-based access changed to struct-based access
> 	- use {clrset,clr,set}bits_le32() calls
> 	- CodingStyle and naming cleanup

Hi Jana,

you change several files, some of them in the general USB support. You
must then split your patch into a patchset, and each patch must address
a single issue. Really with your patch you do not only add USB support
to the EfikaMX board, but you want to add support for MX5 Soc and maybe
fix some issues. And if you change some general USB files, you should
add in CC the USB maintainer (Remy, I have already added him in my answer).

> diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
> index ee4a16e..860e4d2 100644
> --- a/board/efikamx/Makefile
> +++ b/board/efikamx/Makefile
> @@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
>  LIB	= $(obj)lib$(BOARD).o
>  
>  COBJS	:= efikamx.o
> +ifdef	CONFIG_CMD_USB
> +COBJS	+= efikamx-usb.o
> +endif
>  
>  SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
>  OBJS	:= $(addprefix $(obj),$(COBJS))
> diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
> new file mode 100644
> index 0000000..19227d4
> --- /dev/null
> +++ b/board/efikamx/efikamx-usb.c
> @@ -0,0 +1,349 @@
> +#include <common.h>
> +#include <usb.h>
> +#include <asm/io.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/arch/mx5x_pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/gpio.h>
> +#include <usb/ehci-fsl.h>
> +#include <errno.h>
> +
> +#include "../../drivers/usb/host/ehci.h"
> +#include "../../drivers/usb/host/ehci-core.h"

This seems to me pretty nasty - but it is not the only example in u-boot
including files from drivers/. Can we imagine to move these files into
the include directory ?

> +
> +	/*
> +	 * Configure USBH1 control pads
> +	 */
> +
> +	/* USB PHY reset */
> +	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
> +	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
> +			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
> +
> +	/* USB HUB reset */
> +	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
> +	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
> +			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
> +
> +
> +#ifdef	CONFIG_MACH_EFIKASB

Have I missed something ? In U-Boot I see only MACH_TYPE_MX51_EFIKAMX.
And I cannot find any patch on the ML for the EfikaSB board.
If you add support for a EfikaMX variant, you should add this variant in
your patchset, else this stuff is only dead code and must be removed.

> +	/* WIFI EN (act low) */
> +	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
> +	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);

I think it is more readable if you exchange the fix "0" value with the
constants we have already defined, using maybe clrset* function for
PAD_CTL_PKE_ENABLE and PAD_CTL_PUE_KEEPER (the bits you want to clear).

> +	/* WIFI RESET */
> +	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
> +	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);

Ditto, check globally.

> +/*
> + * Enable devices connected to USB BUSes
> + */
> +void efika_usb_enable_devices(void)
> +{
> +	/* Enable Bluetooth */
> +	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
> +	udelay(10000);
> +	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
> +
> +	/* Enable WiFi */
> +	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
> +	udelay(10000);
> +
> +	/* Reset the WiFi chip */
> +	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
> +	udelay(10000);
> +	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
> +}

Is it ok to wait in this function 30mSec or the value can be tuned ? It
seems to me quite high. In the rest of code you wait for 1mSec. Is it ok ?

> +
> +/*
> + * Reset USB PHY (or PHYs on EfikaSB)

As already said: I do not see support for EfikaSB. Please explain or add
support for this variant of the board.

> + */
> +void efika_usb_phy_reset(void)
> +{
> +	/* SMSC 3317 PHY reset */
> +	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
> +	udelay(1000);
> +	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
> +}

Here you wait 1mSec...

> +
> +/*
> + * Configure control registers of the USB controller
> + */
> +void control_regs_setup(struct usb_control_regs *control)
> +{
> +	clrsetbits_le32(&control->usbctrl,
> +			(MXX1_OTG_WUE | MXX1_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
> +			MX51_H1_PM);

Because these bits are valid for both MX5 and MX3, maybe you can call
them MXC_OTG_WUE, MXC_OTG_PM, and so on. MXX1_ let me think there is a
MXX1 Soc.

> +
> +	clrsetbits_le32(&control->phyctrl0,
> +			MX51_OTG_OVERCURD,
> +			MX51_EHCI_POWERPINSE);
> +
> +	clrsetbits_le32(&control->phyctrl1,
> +			MX51_SYSCLOCK_MASK,
> +			MX51_SYSCLOCK_24_MHZ);
> +
> +	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
> +
> +	clrsetbits_le32(&control->uh2ctrl,
> +			(MX51_H2_ULPI_IE | MX51_H2_WUE),
> +			MX51_H2_PM);
> +
> +	udelay(10000);
> +}

Please explain all these magic delays. If they are really needed, add a
comment to explain why it is necessary. And again, 10mSec seems to me a
lot of time.

> +
> +#define ULPI_ADDR_SHIFT		16
> +#define ulpi_write_mask(value)	((value) & 0xff)
> +#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)


> +
> +
> +void ulpi_write(u32 reg, u32 value, struct usb_ehci *ehci)
> +{
> +	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {

Why is writing into this structure so specific to the efikamx ? It seems
to me this could be general code.


> +		writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +		while (readl(&ehci->ulpi_viewpoint) & ULPI_WU)
> +		;

This is an endless loop. It is better to add a timeout (even with a
counter) and print something if the timeout elapses. This should be
fixed globally.


> +u32 ulpi_read(u32 reg, struct usb_ehci *ehci)

A ulpi_read() as ulpi_write() is not strictly related to the Efika board.



> +
> +void ehciX_init(u32 base, struct ulpi_regs *ulpi, struct usb_ehci *ehci)

What is the meaning of X ?

> +{
> +	u32 tmp = 0;
> +	int reg, i;
> +
> +	/* get ID from ULPI immediate registers*/
> +	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
> +		tmp |= ulpi_read(reg, ehci) << (reg * 8);
> +	/* split into vendor and product ID */
> +	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);

IMHO we should add this stuff globally. It is taken (or very similar) to
the OTG support under Linux - why do not sync it with the kernel drivers ?

> +
> +	/* ULPI check integrity */
> +	for (i = 0; i < 2; i++) {
> +		ulpi_write(&ulpi->scratch_write, 0x55 << i, ehci);
> +		tmp = ulpi_read(&ulpi->scratch_write, ehci);
> +
> +		if (tmp != (0x55 << i)) {
> +			printf("ULPI integrity check failed\n");
> +			return;
> +		}
> +	}

Also this stuff is general code - why do we not take otg/ulpi.c from
Linux ?

> +
> +	/* ULPI set flags */
> +	ulpi_write(&ulpi->otg_ctrl_write,
> +		ULPI_OTG_EXT_VBUS_IND | ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN, ehci);
> +	ulpi_write(&ulpi->function_ctrl_write,
> +		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL | ULPI_FC_SUSPENDM_PWRED, ehci);
> +	ulpi_write(&ulpi->iface_ctrl_write, 0, ehci);
> +	ulpi_write(&ulpi->otg_ctrl_set,
> +		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT, ehci);
> +
> +	/*
> +	 * NOTE: This violates USB specification, but otherwise, USB on Efika
> +	 * doesn't work.
> +	 */
> +	ulpi_write(&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS, ehci);

Ok - I understand it does not work. It is not explained why. Is it not
the workaround we find in the kernel ?

"* Workaround: b_host can't driver
 * vbus, but PP in PORTSC needs to
 * be 1 for host to work.
 * So we set drv_vbus bit in
 * transceiver to 0 thru ULPI."

> +}
> +
> +void ehci0_init(struct usb_ehci *ehci)
> +{
> +	setbits_le32(&ehci->portsc, MX51_16BIT_UTMI);
> +}
> +
> +void ehci1_init(struct usb_ehci *ehci, struct ulpi_regs *ulpi)
> +{
> +	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
> +	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
> +				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> +	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
> +	udelay(1000);
> +	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
> +	udelay(1000);
> +
> +	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
> +	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
> +	udelay(10000);
> +
> +	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
> +	udelay(10000);
> +
> +	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
> +	udelay(10000);
> +
> +	ehciX_init(OTG_BASE_ADDR + MX51_UH1_ID, ulpi, ehci);
> +}

I do not see any magic delays in kernel, and the driver is working, too.

> +int ehci_hcd_init(void)
> +{
> +	struct usb_ehci *ehci;
> +	struct usb_control_regs *control;
> +	struct ulpi_regs *ulpi;
> +
> +	/* Init iMX51 EHCI */
> +	efika_usb_phy_reset();
> +	efika_usb_hub_reset();
> +	efika_usb_enable_devices();
> +
> +	control = (struct usb_control_regs *)(OTG_BASE_ADDR +
> +		 MX51_CTRL_REGS);
> +	control_regs_setup(control);
> +
> +	ulpi = (struct ulpi_regs *)(0);
> +	/* Init EHCI core */
> +	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
> +	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
> +	hcor = (struct ehci_hcor *)((uint32_t) hccr +
> +			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> +	setbits_le32(&ehci->usbmode, CM_HOST);
> +	setbits_le32(&ehci->control, USB_EN);
> +
> +	switch (CONFIG_MXC_USB_PORT) {
> +	case 0:
> +		ehci0_init(ehci);
> +	case 1:
> +		ehci1_init(ehci, ulpi);
> +#ifdef	MACH_EFIKASB

Already explained: MACH_EFIKASB does not (yet ?) exist. Why do we have a
"special" ehci_hcd_init and do we not fix the functions in ehci-mxc.c ?

>  
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index 2197119..52b98c2 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -26,6 +26,7 @@
>  #include <asm/io.h>
>  #include <malloc.h>
>  #include <watchdog.h>
> +#include <usb/ehci-fsl.h>
>  
>  #include "ehci.h"
>  
> @@ -709,8 +710,26 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
>  				 * usb 2.0 specification say 50 ms resets on
>  				 * root

I do not see this code in ML file. Does your patch apply ?

>  				 */
> +				/* wait_ms(50); */
> +
> +#if 1

There must be no #if 1 or #if 0 in mainline code.

> +	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +		(MX51_REGISTER_LAYOUT_LENGTH));
> +	extern u32 ulpi_read(u32 reg, struct usb_ehci *ehci);
> +	extern void ulpi_write(u32 reg, u32 value, struct usb_ehci *ehci);
> +	#define XXBASE 0x73f80200

You are mixing some general code with some MX specific code. XXBASE
makes no sense on most architectures. maybe you need a callback, but it
seems to me wrong to add this code here.

> diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
> index a0cfbb7..de7ed00 100644
> --- a/drivers/usb/host/ehci-mxc.c
> +++ b/drivers/usb/host/ehci-mxc.c
> @@ -37,9 +37,6 @@
>  #endif
>  
>  #ifdef CONFIG_MX31
> -#define MX31_OTG_SIC_SHIFT	29
> -#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
> -#define MX31_OTG_PM_BIT		(1 << 24)
>  
>  #define MX31_H2_SIC_SHIFT	21
>  #define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
> @@ -66,11 +63,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
>  
>  		switch (port) {
>  		case 0:	/* OTG port */
> -			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
> +			v &= ~(MXX1_OTG_SIC_MASK | MXX1_OTG_PM_BIT);

Agree the bit must be general and not SOC specific, I find only the
chosen name not particulary good.

> diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
> index b90e342..9cbb024 100644
> --- a/include/configs/efikamx.h
> +++ b/include/configs/efikamx.h
> @@ -40,6 +40,10 @@
>  
>  #define CONFIG_SYS_TEXT_BASE		0x97800000
>  
> +#define	CONFIG_L2_OFF
> +#define	CONFIG_SYS_ICACHE_OFF
> +#define	CONFIG_SYS_DCACHE_OFF
> +
>  /*
>   * Bootloader Components Configuration
>   */
> @@ -49,6 +53,8 @@
>  #define CONFIG_CMD_FAT
>  #define CONFIG_CMD_EXT2
>  #define CONFIG_CMD_IDE
> +#define CONFIG_CMD_NET

This has nothing to do with the goal of your patch. If you commit
message is "add USB", it is odd to find you add network support. Please
split your patch.

> +#define CONFIG_CMD_DATE

Ditto. This has nothing to do with USB. You coul add a separate patch in
your patchset for the efikamx.h, explaining you update the configuration
for the board.

>  
>  /*
>   * Miscellaneous configurable options
> diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
> index 67600ed..9360ba5 100644
> --- a/include/usb/ehci-fsl.h
> +++ b/include/usb/ehci-fsl.h
> @@ -169,6 +169,78 @@
>  #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
>  #endif
>  
> +
> +#ifdef CONFIG_MX51 || CONFIG_MX31

I do not know, but do we need this #ifdef ? Does not apply for MX53, for
example ?

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH v3] Add USB support for Efika

[Marek Vasut]

On Monday, September 19, 2011 10:43:14 AM Stefano Babic wrote:
> On 09/18/2011 04:19 AM, Jana Rapava wrote:
> > From: Marek Vasut <marek.vasut@gmail.com>
> > 
> > This commit adds USB support for EfikaMX and EfikaSB.
> > 
> > Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> > Signed-off-by: Jana Rapava <fermata7@gmail.com>
> > ---

[...]

> > +
> > +
> > +#ifdef	CONFIG_MACH_EFIKASB
> 
> Have I missed something ? In U-Boot I see only MACH_TYPE_MX51_EFIKAMX.
> And I cannot find any patch on the ML for the EfikaSB board.
> If you add support for a EfikaMX variant, you should add this variant in
> your patchset, else this stuff is only dead code and must be removed.

I'd prefer this to stay where it is. It's a code for another version of efika 
which I plan to add very soon (after I clean it up):

http://git.denx.de/?p=u-boot/u-boot-
pxa.git;a=commit;h=3d5f5c53819eeddf2088237e592c49bf97a5764c
http://git.denx.de/?p=u-boot/u-boot-
pxa.git;a=commit;h=d1298fdce8ff4ee3d6a485c935e231b9d0d6189e

I might actually submit those on wednesday or so.

[...]

> > +u32 ulpi_read(u32 reg, struct usb_ehci *ehci)
> 
> A ulpi_read() as ulpi_write() is not strictly related to the Efika board.

We're missing generic ulpi infrastructure and adding it is way beyond scope of 
this patch.

Cheers

[U-Boot] [PATCH v3] Add USB support for Efika

[Remy Bohmer]

Hi Stefano,

2011/9/19 Stefano Babic <sbabic@denx.de>:
> you change several files, some of them in the general USB support. You
> must then split your patch into a patchset, and each patch must address
> a single issue. Really with your patch you do not only add USB support
> to the EfikaMX board, but you want to add support for MX5 Soc and maybe
> fix some issues. And if you change some general USB files, you should

I agree that this patch must be split up into a patchset.

> add in CC the USB maintainer (Remy, I have already added him in my answer).

Thanks.

>> +#include "../../drivers/usb/host/ehci.h"
>> +#include "../../drivers/usb/host/ehci-core.h"
>
> This seems to me pretty nasty - but it is not the only example in u-boot
> including files from drivers/. Can we imagine to move these files into
> the include directory ?

I think it is a good idea to move these headers to include/usb.
Patches are welcome.

Kind regards,

Remy

[U-Boot] [PATCH v3] Add USB support for Efika

[Fabio Estevam]

On Sat, Sep 24, 2011 at 12:57 PM, Remy Bohmer <linux@bohmer.net> wrote:
...
> I think it is a good idea to move these headers to include/usb.
> Patches are welcome.

Will send a patch for this.

Regards,

Fabio Estevam

[U-Boot] [PATCH v3] Add USB support for Efika

[Marek Vasut]

On Saturday, September 24, 2011 09:07:14 PM Fabio Estevam wrote:
> On Sat, Sep 24, 2011 at 12:57 PM, Remy Bohmer <linux@bohmer.net> wrote:
> ...
> 
> > I think it is a good idea to move these headers to include/usb.
> > Patches are welcome.
> 
> Will send a patch for this.

No you won't, it's already in the works.

> 
> Regards,
> 
> Fabio Estevam

[U-Boot] [PATCH v3] Add USB support for Efika

[Fabio Estevam]

On Sat, Sep 24, 2011 at 4:19 PM, Marek Vasut <marek.vasut@gmail.com> wrote:
> On Saturday, September 24, 2011 09:07:14 PM Fabio Estevam wrote:
>> On Sat, Sep 24, 2011 at 12:57 PM, Remy Bohmer <linux@bohmer.net> wrote:
>> ...
>>
>> > I think it is a good idea to move these headers to include/usb.
>> > Patches are welcome.
>>
>> Will send a patch for this.
>
> No you won't, it's already in the works.

Sorry, just saw your email after sending the patch.

[U-Boot] [PATCH v3] Add USB support for Efika

[Marek Vasut]

On Sunday, September 18, 2011 04:19:28 AM Jana Rapava wrote:
> From: Marek Vasut <marek.vasut@gmail.com>
> 
> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> ---
> Changes for v2:
> 	- changed to proper patch
> Changes for v3:
> 	- merged other USB patches from u-boot-pxa/efikasb
> 	- offset-based access changed to struct-based access
> 	- use {clrset,clr,set}bits_le32() calls
> 	- CodingStyle and naming cleanup
> 
>  board/efikamx/Makefile      |    3 +
>  board/efikamx/efikamx-usb.c |  349
> +++++++++++++++++++++++++++++++++++++++++++ board/efikamx/efikamx.c     | 
>  10 ++
>  drivers/usb/host/ehci-hcd.c |   19 +++
>  drivers/usb/host/ehci-mxc.c |    9 +-
>  include/configs/efikamx.h   |   35 ++++-
>  include/usb/ehci-fsl.h      |  112 ++++++++++++++-
>  7 files changed, 524 insertions(+), 13 deletions(-)
>  create mode 100644 board/efikamx/efikamx-usb.c
> 

Compile-testing shows the following mess:

In file included from ehci-hcd.c:29:
/home/marex/U-Boot/u-boot-marex/include/usb/ehci-fsl.h:173:20: warning: extra 
tokens at end of #ifdef directive

In file included from efikamx-usb.c:8:
/home/marex/U-Boot/u-boot-marex/include/usb/ehci-fsl.h:173:20: warning: extra 
tokens at end of #ifdef directive
efikamx-usb.c: In function ?ehciX_init?:
efikamx-usb.c:230: warning: passing argument 1 of ?ulpi_write? makes integer 
from pointer without a cast
efikamx-usb.c:188: note: expected ?u32? but argument is of type ?u8 *?
efikamx-usb.c:231: warning: passing argument 1 of ?ulpi_read? makes integer from 
pointer without a cast
efikamx-usb.c:202: note: expected ?u32? but argument is of type ?u8 *?
efikamx-usb.c:241: warning: passing argument 1 of ?ulpi_write? makes integer 
from pointer without a cast
efikamx-usb.c:188: note: expected ?u32? but argument is of type ?u8 *?
efikamx-usb.c:243: warning: passing argument 1 of ?ulpi_write? makes integer 
from pointer without a cast
efikamx-usb.c:188: note: expected ?u32? but argument is of type ?u8 *?
efikamx-usb.c:244: warning: passing argument 1 of ?ulpi_write? makes integer 
from pointer without a cast
efikamx-usb.c:188: note: expected ?u32? but argument is of type ?u8 *?
efikamx-usb.c:246: warning: passing argument 1 of ?ulpi_write? makes integer 
from pointer without a cast
efikamx-usb.c:188: note: expected ?u32? but argument is of type ?u8 *?
efikamx-usb.c:252: warning: passing argument 1 of ?ulpi_write? makes integer 
from pointer without a cast
efikamx-usb.c:188: note: expected ?u32? but argument is of type ?u8 *?

[U-Boot] [PATCH v4 1/5] EHCI: add callback ehci_fixup

[Jana Rapava]

EHCI: add callback ehci_fixup to solve VBUS reset
issue for Efika.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
       - changed to proper patch
Changes for v3:
       - merged other USB patches from u-boot-pxa/efikasb
       - offset-based access changed to struct-based access
       - use {clrset,clr,set}bits_le32() calls
       - CodingStyle and naming cleanup
Changes for v4:
	- split into patchset
	- add callback ehci_fixup

 drivers/usb/host/ehci-hcd.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..f420279 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -26,6 +26,7 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <watchdog.h>
+#include <usb/ehci-fsl.h>
 
 #include "ehci.h"
 
@@ -536,6 +537,14 @@ static inline int min3(int a, int b, int c)
 	return a;
 }
 
+inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	wait_ms(50);
+}
+
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+	 __attribute__((weak, alias("__ehci_fixup")));
+
 int
 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 		 int length, struct devrequest *req)
@@ -709,8 +718,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 				 * usb 2.0 specification say 50 ms resets on
 				 * root
 				 */
-				wait_ms(50);
-				/* terminate the reset */
+				ehci_fixup(status_reg, &reg);
 				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 				/*
 				 * A host controller must terminate the reset
-- 
1.7.6.3

[U-Boot] [PATCH v4 2/5] Add USB support for Efika

[Jana Rapava]

This commit adds USB support for EfikaMX and EfikaSB.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
       - changed to proper patch
Changes for v3:
       - merged other USB patches from u-boot-pxa/efikasb
       - offset-based access changed to struct-based access
       - use {clrset,clr,set}bits_le32() calls
       - CodingStyle and naming cleanup
Changes for v4:
	- split into patchset
	- CodingStyle and naming cleanup
	- remove endless loops
	- silence compiler warnings

 board/efikamx/Makefile      |    3 +
 board/efikamx/efikamx-usb.c |  380 +++++++++++++++++++++++++++++++++++++++++++
 board/efikamx/efikamx.c     |   10 +
 include/configs/efikamx.h   |   16 ++
 include/usb/ehci-fsl.h      |  119 +++++++++++++-
 5 files changed, 527 insertions(+), 1 deletions(-)
 create mode 100644 board/efikamx/efikamx-usb.c

diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
index ee4a16e..860e4d2 100644
--- a/board/efikamx/Makefile
+++ b/board/efikamx/Makefile
@@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= efikamx.o
+ifdef	CONFIG_CMD_USB
+COBJS	+= efikamx-usb.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
new file mode 100644
index 0000000..559470f
--- /dev/null
+++ b/board/efikamx/efikamx-usb.c
@@ -0,0 +1,380 @@
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#include "../../drivers/usb/host/ehci.h"
+#include "../../drivers/usb/host/ehci-core.h"
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX
+ */
+#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
+			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
+void setup_iomux_usb(void)
+{
+	/*
+	 * Configure USBH1 pads
+	 */
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
+
+	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
+
+	/*
+	 * Configure USBH1 control pads
+	 */
+
+	/* USB PHY reset */
+	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+	/* USB HUB reset */
+	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+
+#ifdef	CONFIG_MACH_EFIKASB
+	/*
+	 * Configure USBH2 pads (used on EfikaSB)
+	 */
+	/* USBH2_DATA */
+	mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
+
+	/* USBH2_CLK */
+	mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
+	/* USBH2_DIR */
+	mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
+	/* USBH2_STP */
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+	/* USBH2_NXT */
+	mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
+#endif
+
+	/* WIFI EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
+	/* WIFI RESET */
+	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
+	/* BT EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+}
+
+/*
+ * Enable devices connected to USB BUSes
+ */
+void efika_usb_enable_devices(void)
+{
+	/* Enable Bluetooth */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+
+	/* Enable WiFi */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	udelay(10000);
+
+	/* Reset the WiFi chip */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB)
+ */
+void efika_usb_hub_reset(void)
+{
+	/* HUB reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB)
+ */
+void efika_usb_phy_reset(void)
+{
+	/* SMSC 3317 PHY reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+}
+
+/*
+ * Configure control registers of the USB controller
+ */
+void control_regs_setup(struct usb_control_regs *control)
+{
+	clrsetbits_le32(&control->usbctrl,
+		(MXC_OTG_WUE | MXC_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
+		MX51_H1_PM);
+
+	clrsetbits_le32(&control->phyctrl0,
+			MX51_OTG_OVERCURD,
+			MX51_EHCI_POWERPINSE);
+
+	clrsetbits_le32(&control->phyctrl1,
+			MX51_SYSCLOCK_MASK,
+			MX51_SYSCLOCK_24_MHZ);
+
+	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
+
+	clrsetbits_le32(&control->uh2ctrl,
+			(MX51_H2_ULPI_IE | MX51_H2_WUE),
+			MX51_H2_PM);
+
+	udelay(10000);
+}
+
+#define ULPI_ADDR_SHIFT		16
+#define ulpi_write_mask(value)	((value) & 0xff)
+#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
+
+u32 ulpi_wait(u32 ulpi_bit, const char *operation, struct usb_ehci *ehci)
+{
+	int timeout = ULPI_TIMEOUT;
+	u32 tmp;
+	while (--timeout) {
+		tmp = readl(&ehci->ulpi_viewpoint);
+		if (!(tmp & ulpi_bit))
+			break;
+		WATCHDOG_RESET();
+	}
+	if (!timeout) {
+		printf("ULPI %s timed out\n", operation);
+		return 0;
+	}
+	return tmp;
+}
+
+void ulpi_write(u8 *reg, u32 value, struct usb_ehci *ehci)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		ulpi_wait(ULPI_WU, "wakeup", ehci);
+	}
+	writel(ULPI_RWRUN | ULPI_RWCTRL |
+		(u32)reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
+		&ehci->ulpi_viewpoint);
+
+	ulpi_wait(ULPI_RWRUN, "write", ehci);
+}
+
+u32 ulpi_read(u8 *reg, struct usb_ehci *ehci)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		ulpi_wait(ULPI_WU, "wakeup", ehci);
+	}
+	writel(ULPI_RWRUN | (u32)reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
+	return ulpi_read_mask(ulpi_wait(ULPI_RWRUN, "read", ehci));
+}
+
+void ulpi_init(struct ulpi_regs *ulpi, struct usb_ehci *ehci)
+{
+	u32 tmp = 0;
+	int reg, i;
+
+	/* get ID from ULPI immediate registers */
+	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
+		tmp |= ulpi_read((u8 *)reg, ehci) << (reg * 8);
+	/* split into vendor and product ID */
+	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
+
+	/* ULPI check integrity */
+	for (i = 0; i < 2; i++) {
+		ulpi_write(&ulpi->scratch_write, ULPI_TEST_VALUE << i, ehci);
+		tmp = ulpi_read(&ulpi->scratch_write, ehci);
+
+		if (tmp != (ULPI_TEST_VALUE << i)) {
+			printf("ULPI integrity check failed\n");
+			return;
+		}
+	}
+
+	/* ULPI set flags */
+	ulpi_write(&ulpi->otg_ctrl_write,
+		ULPI_OTG_EXT_VBUS_IND |
+		ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN, ehci);
+	ulpi_write(&ulpi->function_ctrl_write,
+		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL |
+		ULPI_FC_SUSPENDM_PWRED, ehci);
+	ulpi_write(&ulpi->iface_ctrl_write, 0, ehci);
+	ulpi_write(&ulpi->otg_ctrl_set,
+		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT, ehci);
+
+	/*
+	 * NOTE: This violates USB specification, but otherwise, USB on Efika
+	 * doesn't charge VBUS and as a result, USB doesn't work.
+	 */
+	ulpi_write(&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS, ehci);
+}
+
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+
+	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH));
+	struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
+	u32 tmp = ulpi_read(&ulpi->otg_ctrl_write, ehci);
+	tmp |= (1 << 4);
+	ulpi_write(&ulpi->otg_ctrl_write, tmp, ehci);
+	wait_ms(50);
+	/* terminate the reset */
+	*reg_ref = ehci_readl(status_reg);
+	*reg_ref |= EHCI_PS_PE;
+}
+
+void ehci0_init(struct usb_ehci *ehci)
+{
+	writel(MX51_16BIT_UTMI, &ehci->portsc);
+}
+
+void ehci1_init(struct usb_ehci *ehci, struct ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	udelay(10000);
+
+	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
+	udelay(10000);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ulpi, ehci);
+}
+
+
+void ehci2_init(struct usb_ehci *ehci, struct ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ulpi, ehci);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+	struct usb_control_regs *mx5_usb_control_regs;
+	struct ulpi_regs *ulpi;
+
+	/* Init iMX51 EHCI */
+	efika_usb_phy_reset();
+	efika_usb_hub_reset();
+	efika_usb_enable_devices();
+
+	mx5_usb_control_regs = (struct usb_control_regs *)(OTG_BASE_ADDR +
+		 MX51_CTRL_REGS);
+	control_regs_setup(mx5_usb_control_regs);
+
+	ulpi = (struct ulpi_regs *)0;
+	/* Init EHCI core */
+	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+	setbits_le32(&ehci->control, USB_EN);
+
+	switch (CONFIG_MXC_USB_PORT) {
+	case 0:
+		ehci0_init(ehci);
+		break;
+	case 1:
+		ehci1_init(ehci, ulpi);
+		break;
+#ifdef	MACH_EFIKASB
+	case 2:
+		ehci2_init(ehci, ulpi);
+		break;
+#endif
+	};
+
+	/* EfikaMX USB has issues ... */
+	udelay(10000);
+
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 5be1f6c..51c1854 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -489,6 +489,15 @@ static inline void setup_iomux_ata(void) { }
 #endif
 
 /*
+ * EHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
+
+/*
  * LED configuration
  */
 void setup_iomux_led(void)
@@ -621,6 +630,7 @@ int board_late_init(void)
 
 	setup_iomux_led();
 	setup_iomux_ata();
+	setup_iomux_usb();
 
 	efikamx_toggle_led(EFIKAMX_LED_BLUE);
 
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index fdd0a14..9632b5d 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -40,6 +40,10 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
+#define	CONFIG_L2_OFF
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
 /*
  * Bootloader Components Configuration
  */
@@ -168,6 +172,18 @@
 #endif
 
 /*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define	CONFIG_USB_KEYBOARD
+#endif /* CONFIG_CMD_USB */
+
+/*
  * Filesystems
  */
 #ifdef CONFIG_CMD_FAT
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..b107f71 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,79 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+#if defined(CONFIG_MX51) || defined(CONFIG_MX31)
+/* USB_CTRL register bits of interest*/
+#define MXC_OTG_SIC_SHIFT	29
+#define MXC_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
+#define MXC_OTG_WUE		(1 << 27)
+#define MXC_OTG_PM		(1 << 24)
+#endif
+
+#ifdef CONFIG_MX51
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_OTG_ID	0x000
+#define MX51_UH1_ID	0x200
+#define MX51_UH2_ID	0x400
+#define MX51_CTRL_REGS	0x800
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_PM		(1 << 24)
+#define MX51_H1_ULPI_IE		(1 << 12)
+#define MX51_H1_WUE		(1 << 11)
+#define MX51_H1_PM		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD	(1 << 8)
+#define MX51_EHCI_POWERPINSE	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ	(1 << 0)
+#define MX51_SYSCLOCK_MASK	(~(0xffffffff << 2))
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE		(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE		(1 << 8)
+#define MX51_H2_WUE		(1 << 7)
+#define MX51_H2_PM		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI		(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(0xff << 16)
+#endif
+
+/*
+* ULPI
+*/
+#define ULPI_ID_REGS_COUNT	4
+#define ULPI_TEST_VALUE		0x55
+#define ULPI_TIMEOUT		1000 /* some reasonable value */
+
+/* ULPI viewport control bits */
+#define ULPI_WU		(1 << 31)
+#define ULPI_SS		(1 << 27)
+#define ULPI_RWRUN	(1 << 30)
+#define ULPI_RWCTRL	(1 << 29)
+
+/* ULPI OTG Control bits of interest */
+#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
+#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
+#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
+#define	ULPI_OTG_DRV_VBUS	(1 << 5)
+#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
+#define ULPI_OTG_CHRG_VBUS	(1 << 4)
+
+/* ULPI Function Control bits of interest */
+#define ULPI_FC_XCVR_SELECT	(1 << 0)
+#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
+#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
+
 /*
  * USB Registers
  */
@@ -210,7 +283,7 @@ struct usb_ehci {
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
 					   pre-buffer packet tuning */
 	u8	res7[0x8];
-	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
 	u8	res8[0xc];
 	u32	config_flag;	/* 0x180 - Configured Flag Register */
 	u32	portsc;		/* 0x184 - Port status/control */
@@ -242,4 +315,48 @@ struct usb_ehci {
 	u8	res13[0xafc];
 };
 
+struct usb_control_regs {
+	u32	usbctrl;	/* 0x800 - USB Control */
+	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
+	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
+	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
+	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
+	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
+	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
+};
+
+struct ulpi_regs {
+	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
+	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
+	u8	product_id_low;		/* 0x02 - Product ID lower byte */
+	u8	product_id_high;	/* 0x03 - Product ID higher byte */
+	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
+	u8	function_ctrl_write;
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
+	u8	iface_ctrl_write;
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
+	u8	otg_ctrl_write;
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
+	u8	usb_ie_rising_write;
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
+	u8	usb_ie_falling_write;
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
+	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
+	u8	debug;			/* 0x15 - Debug */
+	/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
+	u8	scratch_write;
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 Clear*/
+};
+
 #endif /* _EHCI_FSL_H */
-- 
1.7.6.3

[U-Boot] [PATCH v4 3/5] /drivers/usb/host/ehci-mxc.c: naming cleanup

[Jana Rapava]

This commit changes MX31 prefix in common USB_CTRL bits to MXC.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>
---
Changes for v2:
       - changed to proper patch
Changes for v3:
       - merged other USB patches from u-boot-pxa/efikasb
       - offset-based access changed to struct-based access
       - use {clrset,clr,set}bits_le32() calls
       - CodingStyle and naming cleanup
Changes for v4:
	- split into patchset

 drivers/usb/host/ehci-mxc.c |    9 +++------
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..973bb4f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -37,9 +37,6 @@
 #endif
 
 #ifdef CONFIG_MX31
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
 
 #define MX31_H2_SIC_SHIFT	21
 #define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
@@ -66,11 +63,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		switch (port) {
 		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+			v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT);
 			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
+					<< MXC_OTG_SIC_SHIFT;
 			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
+				v |= MXC_OTG_PM_BIT;
 
 			break;
 		case 1: /* H1 port */
-- 
1.7.6.3

[U-Boot] [PATCH v4 4/5] USB: Add usb_event_poll() to get keyboards working with EHCI

[Jana Rapava]

From: Marek Vasut <marek.vasut@gmail.com>

USB: Add usb_event_poll() to get keyboards working with
 EHCI

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
       - changed to proper patch
Changes for v3:
       - merged other USB patches from u-boot-pxa/efikasb
       - offset-based access changed to struct-based access
       - use {clrset,clr,set}bits_le32() calls
       - CodingStyle and naming cleanup
Changes for v4:
	- split into patchset
	- added usb_event_poll()

 drivers/usb/host/ehci-hcd.c |   33 ++++++++++++++++++++++++++++++++-
 1 files changed, 32 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index f420279..36f21f9 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -27,6 +27,10 @@
 #include <malloc.h>
 #include <watchdog.h>
 #include <usb/ehci-fsl.h>
+#ifdef CONFIG_USB_KEYBOARD
+#include <stdio_dev.h>
+extern unsigned char new[];
+#endif
 
 #include "ehci.h"
 
@@ -903,5 +907,32 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
 
 	debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
 	      dev, pipe, buffer, length, interval);
-	return -1;
+	return ehci_submit_async(dev, pipe, buffer, length, NULL);
+}
+
+#ifdef CONFIG_SYS_USB_EVENT_POLL
+/*
+ * This function polls for USB keyboard data.
+ */
+void usb_event_poll()
+{
+	struct stdio_dev *dev;
+	struct usb_device *usb_kbd_dev;
+	struct usb_interface *iface;
+	struct usb_endpoint_descriptor *ep;
+	int pipe;
+	int maxp;
+
+	/* Get the pointer to USB Keyboard device pointer */
+	dev = stdio_get_by_name("usbkbd");
+	usb_kbd_dev = (struct usb_device *)dev->priv;
+	iface = &usb_kbd_dev->config.if_desc[0];
+	ep = &iface->ep_desc[0];
+	pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
+
+	/* Submit a interrupt transfer request */
+	maxp = usb_maxpacket(usb_kbd_dev, pipe);
+	usb_submit_int_msg(usb_kbd_dev, pipe, &new[0],
+			maxp > 8 ? 8 : maxp, ep->bInterval);
 }
+#endif /* CONFIG_SYS_USB_EVENT_POLL */
-- 
1.7.6.3

[U-Boot] [PATCH v4 4/5] USB: Add usb_event_poll() to get keyboards working with EHCI

[Marek Vasut]

On Sunday, September 25, 2011 01:55:57 PM Jana Rapava wrote:
> From: Marek Vasut <marek.vasut@gmail.com>
> 
> USB: Add usb_event_poll() to get keyboards working with
>  EHCI
> 
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>

This patch is not part of this patchset.

[U-Boot] [PATCH v4 5/5] USB: move ehci.h and ehci-core.h into /include/usb/

[Jana Rapava]

USB: move ehci.h and ehci-core.h into /include/usb/

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
---
Changes for v2:
       - changed to proper patch
Changes for v3:
       - merged other USB patches from u-boot-pxa/efikasb
       - offset-based access changed to struct-based access
       - use {clrset,clr,set}bits_le32() calls
       - CodingStyle and naming cleanup
Changes for v4:
	- split into patchset
	- move ehci.h and ehci-core.h into /include/usb/

 board/efikamx/efikamx-usb.c      |    4 +-
 drivers/usb/host/ehci-core.h     |   29 ------
 drivers/usb/host/ehci-fsl.c      |    4 +-
 drivers/usb/host/ehci-hcd.c      |    2 +-
 drivers/usb/host/ehci-kirkwood.c |    4 +-
 drivers/usb/host/ehci-mpc512x.c  |    4 +-
 drivers/usb/host/ehci-pci.c      |    4 +-
 drivers/usb/host/ehci-ppc4xx.c   |    4 +-
 drivers/usb/host/ehci.h          |  203 --------------------------------------
 include/usb/ehci-core.h          |   29 ++++++
 include/usb/ehci.h               |  203 ++++++++++++++++++++++++++++++++++++++
 11 files changed, 245 insertions(+), 245 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-core.h
 delete mode 100644 drivers/usb/host/ehci.h
 create mode 100644 include/usb/ehci-core.h
 create mode 100644 include/usb/ehci.h

diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
index 559470f..4e5390f 100644
--- a/board/efikamx/efikamx-usb.c
+++ b/board/efikamx/efikamx-usb.c
@@ -9,8 +9,8 @@
 #include <errno.h>
 #include <watchdog.h>
 
-#include "../../drivers/usb/host/ehci.h"
-#include "../../drivers/usb/host/ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Configure the USB H1 and USB H2 IOMUX
diff --git a/drivers/usb/host/ehci-core.h b/drivers/usb/host/ehci-core.h
deleted file mode 100644
index 39e5c5e..0000000
--- a/drivers/usb/host/ehci-core.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6e0043a..19b97ee 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,8 +27,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 36f21f9..68d157b 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -32,7 +32,7 @@
 extern unsigned char new[];
 #endif
 
-#include "ehci.h"
+#include <usb/ehci.h>
 
 int rootdev;
 struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc6..ab75acd 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -25,8 +25,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <usb.h>
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index d360108..8d2c93b 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 static void fsl_setup_phy(volatile struct ehci_hcor *);
 static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 020ab11..e1f84d9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,8 +22,8 @@
 #include <pci.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 1179919..1a1fae1 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
deleted file mode 100644
index 3d0ad0c..0000000
--- a/drivers/usb/host/ehci.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
-	uint32_t cr_capbase;
-#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
-#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
-#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed, aligned(4)));
-
-struct ehci_hcor {
-	uint32_t or_usbcmd;
-#define CMD_PARK	(1 << 11)		/* enable "park" */
-#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
-#define CMD_ASE		(1 << 5)		/* async schedule enable */
-#define CMD_LRESET	(1 << 7)		/* partial reset */
-#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
-#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
-#define CMD_RESET	(1 << 1)		/* reset HC not bus */
-#define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
-#define	STD_ASS		(1 << 15)
-#define STS_HALT	(1 << 12)
-	uint32_t or_usbintr;
-#define INTR_UE         (1 << 0)                /* USB interrupt enable */
-#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
-#define INTR_PCE        (1 << 2)                /* Port change detect enable */
-#define INTR_SEE        (1 << 4)                /* system error enable */
-#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
-#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
-} __attribute__ ((packed, aligned(4)));
-
-#define USBMODE		0x68		/* USB Device mode */
-#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
-#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
-#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
-					cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x)		be32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
-#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
-	/* this part defined by EHCI spec */
-	uint32_t qt_next;		/* see EHCI 3.5.1 */
-#define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
-	uint32_t qt_token;		/* see EHCI 3.5.3 */
-	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
-	uint32_t qt_buffer_hi[5];	/* Appendix B */
-	/* pad struct for 32 byte alignment */
-	uint32_t unused[3];
-};
-
-/* Queue Head (QH). */
-struct QH {
-	uint32_t qh_link;
-#define	QH_LINK_TERMINATE	1
-#define	QH_LINK_TYPE_ITD	0
-#define	QH_LINK_TYPE_QH		2
-#define	QH_LINK_TYPE_SITD	4
-#define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
diff --git a/include/usb/ehci-core.h b/include/usb/ehci-core.h
new file mode 100644
index 0000000..39e5c5e
--- /dev/null
+++ b/include/usb/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
new file mode 100644
index 0000000..3d0ad0c
--- /dev/null
+++ b/include/usb/ehci.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed, aligned(4)));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed, aligned(4)));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+
+#endif /* USB_EHCI_H */
-- 
1.7.6.3

[U-Boot] [PATCH v5 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

From: festevam@gmail.com (Fabio Estevam)

Move ehci.h and ehci-core.h to include/usb directory.

Cc: Remy Bohmer <linux@bohmer.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes for v2:
      - changed to proper patch
Changes for v3:
      - merged other USB patches from u-boot-pxa/efikasb
      - offset-based access changed to struct-based access
      - use {clrset,clr,set}bits_le32() calls
      - CodingStyle and naming cleanup
Changes for v4:
       - split into patchset
       - move ehci.h and ehci-core.h into /include/usb/
Changes for v5:
	- reorder patches in patchset
	- use patch from Fabio Estevam

 drivers/usb/host/ehci-core.h     |   29 ------
 drivers/usb/host/ehci-fsl.c      |    4 +-
 drivers/usb/host/ehci-hcd.c      |    2 +-
 drivers/usb/host/ehci-ixp4xx.c   |    4 +-
 drivers/usb/host/ehci-kirkwood.c |    4 +-
 drivers/usb/host/ehci-mpc512x.c  |    4 +-
 drivers/usb/host/ehci-mxc.c      |    4 +-
 drivers/usb/host/ehci-pci.c      |    4 +-
 drivers/usb/host/ehci-ppc4xx.c   |    4 +-
 drivers/usb/host/ehci-vct.c      |    4 +-
 drivers/usb/host/ehci.h          |  203 --------------------------------------
 include/usb/ehci-core.h          |   29 ++++++
 include/usb/ehci.h               |  203 ++++++++++++++++++++++++++++++++++++++
 13 files changed, 249 insertions(+), 249 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-core.h
 delete mode 100644 drivers/usb/host/ehci.h
 create mode 100644 include/usb/ehci-core.h
 create mode 100644 include/usb/ehci.h

diff --git a/drivers/usb/host/ehci-core.h b/drivers/usb/host/ehci-core.h
deleted file mode 100644
index 39e5c5e..0000000
--- a/drivers/usb/host/ehci-core.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6e0043a..19b97ee 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,8 +27,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..bdadd46 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -27,7 +27,7 @@
 #include <malloc.h>
 #include <watchdog.h>
 
-#include "ehci.h"
+#include <usb/ehci.h>
 
 int rootdev;
 struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index b8f15ae..d15237b 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc6..ab75acd 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -25,8 +25,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <usb.h>
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index d360108..8d2c93b 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 static void fsl_setup_phy(volatile struct ehci_hcor *);
 static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..fde1f0f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -24,8 +24,8 @@
 #include <usb/ehci-fsl.h>
 #include <errno.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 020ab11..e1f84d9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,8 +22,8 @@
 #include <pci.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 1179919..1a1fae1 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c
index 3063dd1..e73cf38 100644
--- a/drivers/usb/host/ehci-vct.c
+++ b/drivers/usb/host/ehci-vct.c
@@ -20,8 +20,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
 
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
deleted file mode 100644
index 3d0ad0c..0000000
--- a/drivers/usb/host/ehci.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
-	uint32_t cr_capbase;
-#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
-#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
-#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed, aligned(4)));
-
-struct ehci_hcor {
-	uint32_t or_usbcmd;
-#define CMD_PARK	(1 << 11)		/* enable "park" */
-#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
-#define CMD_ASE		(1 << 5)		/* async schedule enable */
-#define CMD_LRESET	(1 << 7)		/* partial reset */
-#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
-#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
-#define CMD_RESET	(1 << 1)		/* reset HC not bus */
-#define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
-#define	STD_ASS		(1 << 15)
-#define STS_HALT	(1 << 12)
-	uint32_t or_usbintr;
-#define INTR_UE         (1 << 0)                /* USB interrupt enable */
-#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
-#define INTR_PCE        (1 << 2)                /* Port change detect enable */
-#define INTR_SEE        (1 << 4)                /* system error enable */
-#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
-#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
-} __attribute__ ((packed, aligned(4)));
-
-#define USBMODE		0x68		/* USB Device mode */
-#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
-#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
-#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
-					cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x)		be32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
-#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
-	/* this part defined by EHCI spec */
-	uint32_t qt_next;		/* see EHCI 3.5.1 */
-#define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
-	uint32_t qt_token;		/* see EHCI 3.5.3 */
-	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
-	uint32_t qt_buffer_hi[5];	/* Appendix B */
-	/* pad struct for 32 byte alignment */
-	uint32_t unused[3];
-};
-
-/* Queue Head (QH). */
-struct QH {
-	uint32_t qh_link;
-#define	QH_LINK_TERMINATE	1
-#define	QH_LINK_TYPE_ITD	0
-#define	QH_LINK_TYPE_QH		2
-#define	QH_LINK_TYPE_SITD	4
-#define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
diff --git a/include/usb/ehci-core.h b/include/usb/ehci-core.h
new file mode 100644
index 0000000..39e5c5e
--- /dev/null
+++ b/include/usb/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
new file mode 100644
index 0000000..3d0ad0c
--- /dev/null
+++ b/include/usb/ehci.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed, aligned(4)));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed, aligned(4)));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+
+#endif /* USB_EHCI_H */
-- 
1.7.1

[U-Boot] [PATCH v5 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Fabio Estevam]

On Tue, Sep 27, 2011 at 7:45 AM, Jana Rapava <fermata7@gmail.com> wrote:
> From: festevam at gmail.com (Fabio Estevam)

It should be:

From: Fabio Estevam <festevam@gmail.com>

Regards,

Fabio Estevam

[U-Boot] [PATCH v5 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

Add callback to ehci_fixup to prepare
for solving the problem with VBUS reset on Efika.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
     - changed to proper patch
Changes for v3:
     - merged other USB patches from u-boot-pxa/efikasb
     - offset-based access changed to struct-based access
     - use {clrset,clr,set}bits_le32() calls
     - CodingStyle and naming cleanup
Changes for v4:
      - split into patchset
      - add callback ehci_fixup
Changes for v5:
	- reorder the patches
	- add coments

 drivers/usb/host/ehci-hcd.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index bdadd46..2030a40 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -26,6 +26,7 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <watchdog.h>
+#include <usb/ehci-fsl.h>
 
 #include <usb/ehci.h>
 
@@ -536,6 +537,17 @@ static inline int min3(int a, int b, int c)
 	return a;
 }
 
+inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	wait_ms(50);
+}
+
+/* this function will alias to __ehci_fixup,
+ * unless function ehci_fixup is defined somewhere
+*/
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+	 __attribute__((weak, alias("__ehci_fixup")));
+
 int
 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 		 int length, struct devrequest *req)
@@ -709,7 +721,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 				 * usb 2.0 specification say 50 ms resets on
 				 * root
 				 */
-				wait_ms(50);
+				ehci_fixup(status_reg, &reg);
 				/* terminate the reset */
 				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 				/*
-- 
1.7.6.3

[U-Boot] [PATCH v5 3/4] EHCI: adjust for mx5

[Jana Rapava]

Add macros and structures needed by Efika USB support code.
Move shared offset and bits definitions into common header file.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
     - changed to proper patch
Changes for v3:
     - merged other USB patches from u-boot-pxa/efikasb
     - offset-based access changed to struct-based access
     - use {clrset,clr,set}bits_le32() calls
     - CodingStyle and naming cleanup
Changes for v4:
      - split into patchset
Changes for v5:
	- reorder the patches
	- move all #define's from ehci-mxc.c to ehci-fsl.h
	- rename structures

 drivers/usb/host/ehci-mxc.c |   31 +--------
 include/usb/ehci-fsl.h      |  146 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 148 insertions(+), 29 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index fde1f0f..2c1295f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -27,31 +27,6 @@
 #include <usb/ehci.h>
 #include <usb/ehci-core.h>
 
-#define USBCTRL_OTGBASE_OFFSET	0x600
-
-#ifdef CONFIG_MX25
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
-
-#ifdef CONFIG_MX31
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
-
-#define MX31_H2_SIC_SHIFT	21
-#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT		(1 << 16)
-#define MX31_H2_DT_BIT		(1 << 5)
-
-#define MX31_H1_SIC_SHIFT	13
-#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT		(1 << 8)
-#define MX31_H1_DT_BIT		(1 << 4)
-#endif
-
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
@@ -66,11 +41,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		switch (port) {
 		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+			v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT);
 			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
+					<< MXC_OTG_SIC_SHIFT;
 			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
+				v |= MXC_OTG_PM_BIT;
 
 			break;
 		case 1: /* H1 port */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..727134f 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,106 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
+#define USBCTRL_OTGBASE_OFFSET	0x600
+#endif
+
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
+#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
+#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#endif
+
+#ifdef CONFIG_MX31
+#define MX31_H2_SIC_SHIFT	21
+#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT		(1 << 16)
+#define MX31_H2_DT_BIT		(1 << 5)
+
+#define MX31_H1_SIC_SHIFT	13
+#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT		(1 << 8)
+#define MX31_H1_DT_BIT		(1 << 4)
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+/* offset for first USB CTRL register */
+#define MX5_CTRL_REGS_OFFSET	0x800
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX31)
+/* USB_CTRL register bits of interest*/
+#define MXC_OTG_SIC_SHIFT	29
+#define MXC_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
+#define MXC_OTG_WUE		(1 << 27)
+#define MXC_OTG_PM		(1 << 24)
+#endif
+
+#ifdef CONFIG_MX51
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_OTG_ID	0x000
+#define MX51_UH1_ID	0x200
+#define MX51_UH2_ID	0x400
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_PM		(1 << 24)
+#define MX51_H1_ULPI_IE		(1 << 12)
+#define MX51_H1_WUE		(1 << 11)
+#define MX51_H1_PM		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD	(1 << 8)
+#define MX51_EHCI_POWERPINSE	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ	(1 << 0)
+#define MX51_SYSCLOCK_MASK	(~(0xffffffff << 2))
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE		(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE		(1 << 8)
+#define MX51_H2_WUE		(1 << 7)
+#define MX51_H2_PM		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI		(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(0xff << 16)
+#endif
+
+/*
+* ULPI
+*/
+#define ULPI_ID_REGS_COUNT	4
+#define ULPI_TEST_VALUE		0x55
+#define ULPI_TIMEOUT		1000 /* some reasonable value */
+
+/* ULPI viewport control bits */
+#define ULPI_WU		(1 << 31)
+#define ULPI_SS		(1 << 27)
+#define ULPI_RWRUN	(1 << 30)
+#define ULPI_RWCTRL	(1 << 29)
+
+/* ULPI OTG Control bits of interest */
+#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
+#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
+#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
+#define	ULPI_OTG_DRV_VBUS	(1 << 5)
+#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
+#define ULPI_OTG_CHRG_VBUS	(1 << 4)
+
+/* ULPI Function Control bits of interest */
+#define ULPI_FC_XCVR_SELECT	(1 << 0)
+#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
+#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
+
 /*
  * USB Registers
  */
@@ -210,7 +310,7 @@ struct usb_ehci {
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
 					   pre-buffer packet tuning */
 	u8	res7[0x8];
-	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
 	u8	res8[0xc];
 	u32	config_flag;	/* 0x180 - Configured Flag Register */
 	u32	portsc;		/* 0x184 - Port status/control */
@@ -242,4 +342,48 @@ struct usb_ehci {
 	u8	res13[0xafc];
 };
 
+struct mx5_usb_control_regs {
+	u32	usbctrl;	/* 0x800 - USB Control */
+	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
+	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
+	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
+	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
+	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
+	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
+};
+
+struct mxc_ulpi_regs {
+	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
+	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
+	u8	product_id_low;		/* 0x02 - Product ID lower byte */
+	u8	product_id_high;	/* 0x03 - Product ID higher byte */
+	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
+	u8	function_ctrl_write;
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
+	u8	iface_ctrl_write;
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
+	u8	otg_ctrl_write;
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
+	u8	usb_ie_rising_write;
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
+	u8	usb_ie_falling_write;
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
+	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
+	u8	debug;			/* 0x15 - Debug */
+	/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
+	u8	scratch_write;
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 Clear*/
+};
+
 #endif /* _EHCI_FSL_H */
-- 
1.7.6.3

[U-Boot] [PATCH v5 4/4] Add USB support for Efika

[Jana Rapava]

This commit adds USB support for EfikaMX and EfikaSB.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
     - changed to proper patch
Changes for v3:
     - merged other USB patches from u-boot-pxa/efikasb
     - offset-based access changed to struct-based access
     - use {clrset,clr,set}bits_le32() calls
     - CodingStyle and naming cleanup
Changes for v4:
      - split into patchset
      - CodingStyle and naming cleanup
      - remove endless loops
      - silence compiler warnings
Changes for v5:
	- change order of arguments in ulpi* functions
	- change type of reg argument
	- rename offset macro

 board/efikamx/Makefile      |    3 +
 board/efikamx/efikamx-usb.c |  391 +++++++++++++++++++++++++++++++++++++++++++
 board/efikamx/efikamx.c     |   10 +
 include/configs/efikamx.h   |   16 ++
 4 files changed, 420 insertions(+), 0 deletions(-)
 create mode 100644 board/efikamx/efikamx-usb.c

diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
index ee4a16e..860e4d2 100644
--- a/board/efikamx/Makefile
+++ b/board/efikamx/Makefile
@@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= efikamx.o
+ifdef	CONFIG_CMD_USB
+COBJS	+= efikamx-usb.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
new file mode 100644
index 0000000..c91a08b
--- /dev/null
+++ b/board/efikamx/efikamx-usb.c
@@ -0,0 +1,391 @@
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX
+ */
+#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
+			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
+void setup_iomux_usb(void)
+{
+	/*
+	 * Configure USBH1 pads
+	 */
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
+
+	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
+
+	/*
+	 * Configure USBH1 control pads
+	 */
+
+	/* USB PHY reset */
+	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+	/* USB HUB reset */
+	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+
+#ifdef	CONFIG_MACH_EFIKASB
+	/*
+	 * Configure USBH2 pads (used on EfikaSB)
+	 */
+	/* USBH2_DATA */
+	mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
+
+	/* USBH2_CLK */
+	mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
+	/* USBH2_DIR */
+	mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
+	/* USBH2_STP */
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+	/* USBH2_NXT */
+	mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
+#endif
+
+	/* WIFI EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
+	/* WIFI RESET */
+	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
+	/* BT EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+}
+
+/*
+ * Enable devices connected to USB BUSes
+ */
+void efika_usb_enable_devices(void)
+{
+	/* Enable Bluetooth */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+
+	/* Enable WiFi */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	udelay(10000);
+
+	/* Reset the WiFi chip */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB)
+ */
+void efika_usb_hub_reset(void)
+{
+	/* HUB reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB)
+ */
+void efika_usb_phy_reset(void)
+{
+	/* SMSC 3317 PHY reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+}
+
+/*
+ * Configure control registers of the USB controller
+ */
+void control_regs_setup(struct mx5_usb_control_regs *control)
+{
+	clrsetbits_le32(&control->usbctrl,
+		(MXC_OTG_WUE | MXC_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
+		MX51_H1_PM);
+
+	clrsetbits_le32(&control->phyctrl0,
+			MX51_OTG_OVERCURD,
+			MX51_EHCI_POWERPINSE);
+
+	clrsetbits_le32(&control->phyctrl1,
+			MX51_SYSCLOCK_MASK,
+			MX51_SYSCLOCK_24_MHZ);
+
+	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
+
+	clrsetbits_le32(&control->uh2ctrl,
+			(MX51_H2_ULPI_IE | MX51_H2_WUE),
+			MX51_H2_PM);
+
+	udelay(10000);
+}
+
+#define ULPI_ADDR_SHIFT		16
+#define ulpi_write_mask(value)	((value) & 0xff)
+#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
+
+u32 ulpi_wait(struct usb_ehci *ehci, u32 ulpi_bit, const char *operation)
+{
+	int timeout = ULPI_TIMEOUT;
+	u32 tmp;
+
+	/* wait for the ulpi_bit to become zero */
+	while (--timeout) {
+		tmp = readl(&ehci->ulpi_viewpoint);
+		if (!(tmp & ulpi_bit))
+			break;
+		WATCHDOG_RESET();
+	}
+
+	if (!timeout) {
+		printf("ULPI %s timed out\n", operation);
+		return 0;
+	}
+	return tmp;
+}
+
+void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		ulpi_wait(ehci, ULPI_WU, "wakeup");
+	}
+
+	writel(ULPI_RWRUN | ULPI_RWCTRL |
+		reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
+		&ehci->ulpi_viewpoint);
+	ulpi_wait(ehci, ULPI_RWRUN, "write");
+}
+
+u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		ulpi_wait(ehci, ULPI_WU, "wakeup");
+	}
+
+	writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
+	return ulpi_read_mask(ulpi_wait(ehci, ULPI_RWRUN, "read"));
+}
+
+void ulpi_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	u32 tmp = 0;
+	int reg, i;
+
+	/* get ID from ULPI immediate registers */
+	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
+		tmp |= ulpi_read(ehci, (u32)reg) << (reg * 8);
+	/* split into vendor and product ID */
+	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
+
+	/* ULPI check integrity */
+	for (i = 0; i < 2; i++) {
+		ulpi_write(ehci, (u32)&ulpi->scratch_write,
+			ULPI_TEST_VALUE << i);
+		tmp = ulpi_read(ehci, (u32)&ulpi->scratch_write);
+
+		if (tmp != (ULPI_TEST_VALUE << i)) {
+			printf("ULPI integrity check failed\n");
+			return;
+		}
+	}
+
+	/* ULPI set flags */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write,
+		ULPI_OTG_EXT_VBUS_IND |
+		ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN);
+	ulpi_write(ehci, (u32)&ulpi->function_ctrl_write,
+		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL |
+		ULPI_FC_SUSPENDM_PWRED);
+	ulpi_write(ehci, (u32)&ulpi->iface_ctrl_write, 0);
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set,
+		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT);
+
+	/*
+	 * NOTE: This violates USB specification, but otherwise, USB on Efika
+	 * doesn't charge VBUS and as a result, USB doesn't work.
+	 */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS);
+}
+
+/*
+ * solve the VBUS reset problem on Efika
+ * by setting the CHRG_VBUS bit in the reset
+ */
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH));
+	struct mxc_ulpi_regs *ulpi = (struct mxc_ulpi_regs *)0;
+
+	u32 tmp = ulpi_read(ehci, (u32)&ulpi->otg_ctrl_write);
+	tmp |= ULPI_OTG_CHRG_VBUS;
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write, tmp);
+
+	/* usb 2.0 specification say 50 ms resets on root */
+	wait_ms(50);
+
+	/* terminate the reset */
+	*reg_ref = ehci_readl(status_reg);
+	*reg_ref |= EHCI_PS_PE;
+}
+
+void ehci0_init(struct usb_ehci *ehci)
+{
+	writel(MX51_16BIT_UTMI, &ehci->portsc);
+}
+
+void ehci1_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	udelay(10000);
+
+	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
+	udelay(10000);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+
+void ehci2_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+	struct mx5_usb_control_regs *mx5_usb_control_regs;
+	struct mxc_ulpi_regs *ulpi;
+
+	/* Init iMX51 EHCI */
+	efika_usb_phy_reset();
+	efika_usb_hub_reset();
+	efika_usb_enable_devices();
+
+	mx5_usb_control_regs = (struct mx5_usb_control_regs *)(OTG_BASE_ADDR +
+		 MX5_CTRL_REGS_OFFSET);
+	control_regs_setup(mx5_usb_control_regs);
+	ulpi = (struct mxc_ulpi_regs *)0;
+
+	/* Init EHCI core */
+	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+	setbits_le32(&ehci->control, USB_EN);
+
+	switch (CONFIG_MXC_USB_PORT) {
+	case 0:
+		ehci0_init(ehci);
+		break;
+	case 1:
+		ehci1_init(ehci, ulpi);
+		break;
+#ifdef	MACH_EFIKASB
+	case 2:
+		ehci2_init(ehci, ulpi);
+		break;
+#endif
+	};
+
+	/* EfikaMX USB has issues ... */
+	udelay(10000);
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 5be1f6c..51c1854 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -489,6 +489,15 @@ static inline void setup_iomux_ata(void) { }
 #endif
 
 /*
+ * EHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
+
+/*
  * LED configuration
  */
 void setup_iomux_led(void)
@@ -621,6 +630,7 @@ int board_late_init(void)
 
 	setup_iomux_led();
 	setup_iomux_ata();
+	setup_iomux_usb();
 
 	efikamx_toggle_led(EFIKAMX_LED_BLUE);
 
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index fdd0a14..9632b5d 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -40,6 +40,10 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
+#define	CONFIG_L2_OFF
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
 /*
  * Bootloader Components Configuration
  */
@@ -168,6 +172,18 @@
 #endif
 
 /*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define	CONFIG_USB_KEYBOARD
+#endif /* CONFIG_CMD_USB */
+
+/*
  * Filesystems
  */
 #ifdef CONFIG_CMD_FAT
-- 
1.7.6.3

[U-Boot] [PATCH v5 4/4] Add USB support for Efika

[Marek Vasut]

On Tuesday, September 27, 2011 01:01:36 PM Jana Rapava wrote:
> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

[...]

> +
> +#ifdef	CONFIG_MACH_EFIKASB

Please update to mainline, use if (machine_is_efikasb()) { ... } .

> +	/*
> +	 * Configure USBH2 pads (used on EfikaSB)
> +	 */

[...]

> +/*
> + * solve the VBUS reset problem on Efika
> + * by setting the CHRG_VBUS bit in the reset
> + */
> +void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +{
> +	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +		(MX51_REGISTER_LAYOUT_LENGTH));

Too many parenthesis.

> +	struct mxc_ulpi_regs *ulpi = (struct mxc_ulpi_regs *)0;
> +
> +	u32 tmp = ulpi_read(ehci, (u32)&ulpi->otg_ctrl_write);
> +	tmp |= ULPI_OTG_CHRG_VBUS;
> +	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write, tmp);
> +
> +	/* usb 2.0 specification say 50 ms resets on root */
> +	wait_ms(50);
> +
> +	/* terminate the reset */

Write a whole sentence, which begins with a capital letter and ends with dot ... 
fix globally.


> +	*reg_ref = ehci_readl(status_reg);
> +	*reg_ref |= EHCI_PS_PE;
> +}
> +
> +void ehci0_init(struct usb_ehci *ehci)
> +{
> +	writel(MX51_16BIT_UTMI, &ehci->portsc);
> +}
> +
> +void ehci1_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
> +{
> +	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
> +	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
> +				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> +	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
> +	udelay(1000);
> +	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
> +	udelay(1000);
> +
> +	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
> +	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
> +	udelay(10000);
> +
> +	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
> +	udelay(10000);
> +
> +	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
> +	udelay(10000);
> +
> +	ulpi_init(ehci, ulpi);
> +}
> +
> +
> +void ehci2_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
> +{
> +	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
> +	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
> +				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> +	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
> +	udelay(1000);
> +	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
> +	udelay(1000);
> +
> +	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
> +	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
> +
> +	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
> +	udelay(10000);
> +
> +	ulpi_init(ehci, ulpi);
> +}
> +
> +int ehci_hcd_init(void)
> +{
> +	struct usb_ehci *ehci;
> +	struct mx5_usb_control_regs *mx5_usb_control_regs;
> +	struct mxc_ulpi_regs *ulpi;
> +
> +	/* Init iMX51 EHCI */
> +	efika_usb_phy_reset();
> +	efika_usb_hub_reset();
> +	efika_usb_enable_devices();
> +
> +	mx5_usb_control_regs = (struct mx5_usb_control_regs *)(OTG_BASE_ADDR +
> +		 MX5_CTRL_REGS_OFFSET);
> +	control_regs_setup(mx5_usb_control_regs);
> +	ulpi = (struct mxc_ulpi_regs *)0;

Move this assignment at the begining.
> +
> +	/* Init EHCI core */
> +	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
> +	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
> +	hcor = (struct ehci_hcor *)((uint32_t) hccr +
> +			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));

DTTO

> +	setbits_le32(&ehci->usbmode, CM_HOST);
> +	setbits_le32(&ehci->control, USB_EN);
> +
> +	switch (CONFIG_MXC_USB_PORT) {
> +	case 0:
> +		ehci0_init(ehci);
> +		break;
> +	case 1:
> +		ehci1_init(ehci, ulpi);
> +		break;
> +#ifdef	MACH_EFIKASB
> +	case 2:
> +		ehci2_init(ehci, ulpi);
> +		break;
> +#endif
> +	};
> +
> +	/* EfikaMX USB has issues ... */
> +	udelay(10000);
> +
> +	return 0;
> +}
> +
> +int ehci_hcd_stop(void)
> +{
> +	return 0;
> +}
> diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
> index 5be1f6c..51c1854 100644
> --- a/board/efikamx/efikamx.c
> +++ b/board/efikamx/efikamx.c
> @@ -489,6 +489,15 @@ static inline void setup_iomux_ata(void) { }
>  #endif
> 
>  /*
> + * EHCI USB
> + */
> +#ifdef	CONFIG_CMD_USB
> +void setup_iomux_usb(void);
> +#else
> +static inline void setup_iomux_usb(void) { }
> +#endif
> +

Can you introduce efika.h header and move this to the header please.

> +/*
>   * LED configuration
>   */
>  void setup_iomux_led(void)
> @@ -621,6 +630,7 @@ int board_late_init(void)
> 
>  	setup_iomux_led();
>  	setup_iomux_ata();
> +	setup_iomux_usb();
> 
>  	efikamx_toggle_led(EFIKAMX_LED_BLUE);
> 
> diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
> index fdd0a14..9632b5d 100644
> --- a/include/configs/efikamx.h
> +++ b/include/configs/efikamx.h
> @@ -40,6 +40,10 @@
> 
>  #define CONFIG_SYS_TEXT_BASE		0x97800000
> 
> +#define	CONFIG_L2_OFF
> +#define	CONFIG_SYS_ICACHE_OFF
> +#define	CONFIG_SYS_DCACHE_OFF
> +
>  /*
>   * Bootloader Components Configuration
>   */
> @@ -168,6 +172,18 @@
>  #endif
> 
>  /*
> + * USB
> + */
> +#define CONFIG_CMD_USB
> +#ifdef CONFIG_CMD_USB
> +#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
> +#define CONFIG_MXC_USB_PORT	1
> +#define CONFIG_EHCI_IS_TDI
> +#define CONFIG_USB_STORAGE
> +#define	CONFIG_USB_KEYBOARD

The indent looks wrong, please fix.

> +#endif /* CONFIG_CMD_USB */
> +
> +/*
>   * Filesystems
>   */
>  #ifdef CONFIG_CMD_FAT

Cheers

[U-Boot] [PATCH v5 4/4] Add USB support for Efika

[Jana Rapava]

2011/9/27 Marek Vasut <marek.vasut@gmail.com>

>
> >  /*
> > + * EHCI USB
> > + */
> > +#ifdef       CONFIG_CMD_USB
> > +void setup_iomux_usb(void);
> > +#else
> > +static inline void setup_iomux_usb(void) { }
> > +#endif
> > +
>
> Can you introduce efika.h header and move this to the header please.
>

Should I move all #define's and #ifdef's, or only this?

Regards,
Jana Rapava

[U-Boot] [PATCH v5 4/4] Add USB support for Efika

[Marek Vasut]

On Tuesday, September 27, 2011 04:12:18 PM Jana Rapava wrote:
> 2011/9/27 Marek Vasut <marek.vasut@gmail.com>
> 
> > >  /*
> > > 
> > > + * EHCI USB
> > > + */
> > > +#ifdef       CONFIG_CMD_USB
> > > +void setup_iomux_usb(void);
> > > +#else
> > > +static inline void setup_iomux_usb(void) { }
> > > +#endif
> > > +
> > 
> > Can you introduce efika.h header and move this to the header please.
> 
> Should I move all #define's and #ifdef's, or only this?

The defines are local, move only this
> 
> Regards,
> Jana Rapava

[U-Boot] [PATCH v5 4/4] Add USB support for Efika

[Jana Rapava]

> > +
> > +#ifdef       CONFIG_MACH_EFIKASB

Please update to mainline, use if (machine_is_efikasb()) { ... } .
>

To get macro machine_is_efikasb() working, I have to get into mainline these
two of your patches in u-boot-marex:

430eacfcf35b1f54b0a1ead989aefe63e2996846  EfikaMX: Add imximage config for
Efika SB

 da3e51089d2b899a8b487b40fa63a04919927351 EfikaSB: Add preliminary EfikaSB
support

I don't know if they should be part of this patchset, but I don't think so.
I would like to try to get them into mainline - with your permission of
course, but they would probably need some changes and I can't test them
because I haven't EfikaSB.
Regards,
Jana Rapava

[U-Boot] [PATCH v5 4/4] Add USB support for Efika

[Marek Vasut]

On Tuesday, September 27, 2011 08:17:27 PM Jana Rapava wrote:
> > > +
> > > +#ifdef       CONFIG_MACH_EFIKASB
> 
> Please update to mainline, use if (machine_is_efikasb()) { ... } .
> 
> 
> To get macro machine_is_efikasb() working, I have to get into mainline
> these two of your patches in u-boot-marex:
> 
> 430eacfcf35b1f54b0a1ead989aefe63e2996846  EfikaMX: Add imximage config for
> Efika SB
> 
>  da3e51089d2b899a8b487b40fa63a04919927351 EfikaSB: Add preliminary EfikaSB
> support
> 
> I don't know if they should be part of this patchset, but I don't think so.
> I would like to try to get them into mainline - with your permission of
> course, but they would probably need some changes and I can't test them
> because I haven't EfikaSB.

They were already added to u-boot-imx/next:

http://git.denx.de/?p=u-boot/u-boot-imx.git;a=shortlog;h=refs/heads/next

You should rebase your patchset on top of u-boot-imx/next.

> Regards,
> Jana Rapava

[U-Boot] [PATCH v5 4/4] Add USB support for Efika

[Stefano Babic]

On 09/27/2011 08:17 PM, Jana Rapava wrote:
> 
>     > +
>     > +#ifdef       CONFIG_MACH_EFIKASB 
> 
>     Please update to mainline, use if (machine_is_efikasb()) { ... } .
> 
> 
> To get macro machine_is_efikasb() working, I have to get into mainline
> these two of your patches in u-boot-marex:
> 
> 430eacfcf35b1f54b0a1ead989aefe63e2996846  EfikaMX: Add imximage config
> for Efika SB
> 
>  da3e51089d2b899a8b487b40fa63a04919927351 EfikaSB: Add preliminary
> EfikaSB support

This two patches are already accepted and integrated into
u-boot-imx/next and in u-boot-arm/next.
You can take u-boot-imx/next as reference for your patchset

> 
> I don't know if they should be part of this patchset,

No, they don't

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH v5 4/4] Add USB support for Efika

[Jana Rapava]

2011/9/28 Stefano Babic <sbabic@denx.de>

> This two patches are already accepted and integrated into
> u-boot-imx/next and in u-boot-arm/next.
> You can take u-boot-imx/next as reference for your patchset
>
> >
> > I don't know if they should be part of this patchset,
>
> No, they don't
>

Thanks, Marek already told me.

Regards,
Jana Rapava


> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
> =====================================================================
>

[U-Boot] [PATCH v5 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

On Tuesday, September 27, 2011 01:01:34 PM Jana Rapava wrote:
> Add callback to ehci_fixup to prepare
> for solving the problem with VBUS reset on Efika.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>      - changed to proper patch
> Changes for v3:
>      - merged other USB patches from u-boot-pxa/efikasb
>      - offset-based access changed to struct-based access
>      - use {clrset,clr,set}bits_le32() calls
>      - CodingStyle and naming cleanup
> Changes for v4:
>       - split into patchset
>       - add callback ehci_fixup
> Changes for v5:
> 	- reorder the patches
> 	- add coments

Dear Jana Rapava,

what's the _EXACT_ change in this patch since the last revision? I see you're 
adding the changes for whole patchset, not for each single patch, that's wrong.

> 
>  drivers/usb/host/ehci-hcd.c |   14 +++++++++++++-
>  1 files changed, 13 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index bdadd46..2030a40 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -26,6 +26,7 @@
>  #include <asm/io.h>
>  #include <malloc.h>
>  #include <watchdog.h>
> +#include <usb/ehci-fsl.h>

Do you need this change ?

> 
>  #include <usb/ehci.h>
> 
> @@ -536,6 +537,17 @@ static inline int min3(int a, int b, int c)
>  	return a;
>  }
> 
> +inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +{
> +	wait_ms(50);
> +}
> +
> +/* this function will alias to __ehci_fixup,
> + * unless function ehci_fixup is defined somewhere
> +*/

This comment is wrong, it should start on next line:

/*
 * comment ...
 */
> +void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +	 __attribute__((weak, alias("__ehci_fixup")));
> +
>  int
>  ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
>  		 int length, struct devrequest *req)
> @@ -709,7 +721,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long
> pipe, void *buffer, * usb 2.0 specification say 50 ms resets on
>  				 * root
>  				 */
> -				wait_ms(50);
> +				ehci_fixup(status_reg, &reg);
>  				/* terminate the reset */
>  				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
>  				/*

Cheers

[U-Boot] [PATCH v5 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

> what's the _EXACT_ change in this patch since the last revision? I see
> you're
> adding the changes for whole patchset, not for each single patch, that's
> wrong.
>
> In this changelog are only changes, which touches this single patch and
reordering all patches in this patchset is one of them. When I repost this
patch, I'll try to express this more clearly.
Thanks for your comments.

Cheers,
Jana Rapava

[U-Boot] [PATCH v6 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

Add callback to ehci_fixup to prepare
for solving the problem with VBUS reset on Efika.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v4:
     - split into patchset
     - add callback ehci_fixup
Changes for v5:
       - make this the second patch in series
       - add comment to alias ehci_fixup
Changes for v6:
	- make the comment a sentence
	- rebase patch on top of u-boot-imx/next

 drivers/usb/host/ehci-hcd.c |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index bdadd46..da09f51 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -536,6 +536,17 @@ static inline int min3(int a, int b, int c)
 	return a;
 }
 
+inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	wait_ms(50);
+}
+
+/* This function will alias to __ehci_fixup,
+ * unless function ehci_fixup is defined somewhere.
+*/
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+	 __attribute__((weak, alias("__ehci_fixup")));
+
 int
 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 		 int length, struct devrequest *req)
@@ -709,7 +720,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 				 * usb 2.0 specification say 50 ms resets on
 				 * root
 				 */
-				wait_ms(50);
+				ehci_fixup(status_reg, &reg);
 				/* terminate the reset */
 				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 				/*
-- 
1.7.6.3

[U-Boot] [PATCH v6 3/4] EHCI: adjust for mx5

[Jana Rapava]

Add macros and structures needed by Efika USB support code.
Move shared offset and bits definitions into common header file.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v4:
     - split into patchset
Changes for v5:
       - make this the third patch in series
       - move all #define's from ehci-mxc.c to ehci-fsl.h
       - rename structures
Changes for v6:
	- rebase on top of u-boot-imx/next

 drivers/usb/host/ehci-mxc.c |   31 +--------
 include/usb/ehci-fsl.h      |  146 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 148 insertions(+), 29 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index fde1f0f..2c1295f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -27,31 +27,6 @@
 #include <usb/ehci.h>
 #include <usb/ehci-core.h>
 
-#define USBCTRL_OTGBASE_OFFSET	0x600
-
-#ifdef CONFIG_MX25
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
-
-#ifdef CONFIG_MX31
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
-
-#define MX31_H2_SIC_SHIFT	21
-#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT		(1 << 16)
-#define MX31_H2_DT_BIT		(1 << 5)
-
-#define MX31_H1_SIC_SHIFT	13
-#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT		(1 << 8)
-#define MX31_H1_DT_BIT		(1 << 4)
-#endif
-
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
@@ -66,11 +41,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		switch (port) {
 		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+			v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT);
 			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
+					<< MXC_OTG_SIC_SHIFT;
 			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
+				v |= MXC_OTG_PM_BIT;
 
 			break;
 		case 1: /* H1 port */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..727134f 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,106 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
+#define USBCTRL_OTGBASE_OFFSET	0x600
+#endif
+
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
+#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
+#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#endif
+
+#ifdef CONFIG_MX31
+#define MX31_H2_SIC_SHIFT	21
+#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT		(1 << 16)
+#define MX31_H2_DT_BIT		(1 << 5)
+
+#define MX31_H1_SIC_SHIFT	13
+#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT		(1 << 8)
+#define MX31_H1_DT_BIT		(1 << 4)
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+/* offset for first USB CTRL register */
+#define MX5_CTRL_REGS_OFFSET	0x800
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX31)
+/* USB_CTRL register bits of interest*/
+#define MXC_OTG_SIC_SHIFT	29
+#define MXC_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
+#define MXC_OTG_WUE		(1 << 27)
+#define MXC_OTG_PM		(1 << 24)
+#endif
+
+#ifdef CONFIG_MX51
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_OTG_ID	0x000
+#define MX51_UH1_ID	0x200
+#define MX51_UH2_ID	0x400
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_PM		(1 << 24)
+#define MX51_H1_ULPI_IE		(1 << 12)
+#define MX51_H1_WUE		(1 << 11)
+#define MX51_H1_PM		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD	(1 << 8)
+#define MX51_EHCI_POWERPINSE	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ	(1 << 0)
+#define MX51_SYSCLOCK_MASK	(~(0xffffffff << 2))
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE		(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE		(1 << 8)
+#define MX51_H2_WUE		(1 << 7)
+#define MX51_H2_PM		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI		(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(0xff << 16)
+#endif
+
+/*
+* ULPI
+*/
+#define ULPI_ID_REGS_COUNT	4
+#define ULPI_TEST_VALUE		0x55
+#define ULPI_TIMEOUT		1000 /* some reasonable value */
+
+/* ULPI viewport control bits */
+#define ULPI_WU		(1 << 31)
+#define ULPI_SS		(1 << 27)
+#define ULPI_RWRUN	(1 << 30)
+#define ULPI_RWCTRL	(1 << 29)
+
+/* ULPI OTG Control bits of interest */
+#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
+#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
+#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
+#define	ULPI_OTG_DRV_VBUS	(1 << 5)
+#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
+#define ULPI_OTG_CHRG_VBUS	(1 << 4)
+
+/* ULPI Function Control bits of interest */
+#define ULPI_FC_XCVR_SELECT	(1 << 0)
+#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
+#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
+
 /*
  * USB Registers
  */
@@ -210,7 +310,7 @@ struct usb_ehci {
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
 					   pre-buffer packet tuning */
 	u8	res7[0x8];
-	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
 	u8	res8[0xc];
 	u32	config_flag;	/* 0x180 - Configured Flag Register */
 	u32	portsc;		/* 0x184 - Port status/control */
@@ -242,4 +342,48 @@ struct usb_ehci {
 	u8	res13[0xafc];
 };
 
+struct mx5_usb_control_regs {
+	u32	usbctrl;	/* 0x800 - USB Control */
+	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
+	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
+	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
+	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
+	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
+	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
+};
+
+struct mxc_ulpi_regs {
+	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
+	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
+	u8	product_id_low;		/* 0x02 - Product ID lower byte */
+	u8	product_id_high;	/* 0x03 - Product ID higher byte */
+	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
+	u8	function_ctrl_write;
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
+	u8	iface_ctrl_write;
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
+	u8	otg_ctrl_write;
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
+	u8	usb_ie_rising_write;
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
+	u8	usb_ie_falling_write;
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
+	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
+	u8	debug;			/* 0x15 - Debug */
+	/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
+	u8	scratch_write;
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 Clear*/
+};
+
 #endif /* _EHCI_FSL_H */
-- 
1.7.6.3

[U-Boot] [PATCH v6 3/4] EHCI: adjust for mx5

[Marek Vasut]

On Tuesday, September 27, 2011 09:24:16 PM Jana Rapava wrote:
> Add macros and structures needed by Efika USB support code.
> Move shared offset and bits definitions into common header file.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v4:
>      - split into patchset
> Changes for v5:
>        - make this the third patch in series
>        - move all #define's from ehci-mxc.c to ehci-fsl.h
>        - rename structures
> Changes for v6:
> 	- rebase on top of u-boot-imx/next
> 

What's the actual change in here ? Or is it just a resend? If this is a resend, 
please say so. Also, keep the whole changelog.

[U-Boot] [PATCH v6 3/4] EHCI: adjust for mx5

[Jana Rapava]

2011/9/27 Marek Vasut <marek.vasut@gmail.com>

>
> > Changes for v4:
> >      - split into patchset
> > Changes for v5:
> >        - make this the third patch in series
> >        - move all #define's from ehci-mxc.c to ehci-fsl.h
> >        - rename structures
> > Changes for v6:
> >       - rebase on top of u-boot-imx/next
> >
>
> What's the actual change in here ? Or is it just a resend? If this is a
> resend,
> please say so. Also, keep the whole changelog.
>

I talked to Fabio Estevam and he said that in changelog shouldn't be entries
with version numbers before the patch was introduced (v4 for this patch).
It looks reasonable to me, but if you would insist on keeping the whole
changelog, there is no problem.

Cheers,
Jana Rapava

[U-Boot] [PATCH v6 3/4] EHCI: adjust for mx5

[Marek Vasut]

On Tuesday, September 27, 2011 10:19:31 PM Jana Rapava wrote:
> 2011/9/27 Marek Vasut <marek.vasut@gmail.com>
> 
> > > Changes for v4:
> > >      - split into patchset
> > > 
> > > Changes for v5:
> > >        - make this the third patch in series
> > >        - move all #define's from ehci-mxc.c to ehci-fsl.h
> > >        - rename structures
> > > 
> > > Changes for v6:
> > >       - rebase on top of u-boot-imx/next
> > 
> > What's the actual change in here ? Or is it just a resend? If this is a
> > resend,
> > please say so. Also, keep the whole changelog.
> 
> I talked to Fabio Estevam and he said that in changelog shouldn't be
> entries with version numbers before the patch was introduced (v4 for this
> patch). It looks reasonable to me, but if you would insist on keeping the
> whole changelog, there is no problem.

Ok, now I see the problem. You're not versioning this stuff per-patch, but per-
patchset. That's not ok.

> 
> Cheers,
> Jana Rapava

[U-Boot] [PATCH v6 4/4] Add USB support for Efika

[Jana Rapava]

This commit adds USB support for EfikaMX and EfikaSB.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
    - changed to proper patch
Changes for v3:
    - merged other USB patches from u-boot-pxa/efikasb
    - offset-based access changed to struct-based access
    - use {clrset,clr,set}bits_le32() calls
    - CodingStyle and naming cleanup
Changes for v4:
     - split into patchset
     - CodingStyle and naming cleanup
     - remove endless loops
     - silence compiler warnings
Changes for v5:
       - change order of arguments in ulpi* functions
       - change type of reg argument
       - rename offset macro
Changes for v6:
	- rebase on top of u-boot-imx/next
	- cleanup of CodingStyle and comments
	- use macro machine_is_efikasb()
	- introduce header file efika.h

 board/efikamx/Makefile      |    3 +
 board/efikamx/efika.h       |    8 +
 board/efikamx/efikamx-usb.c |  391 +++++++++++++++++++++++++++++++++++++++++++
 board/efikamx/efikamx.c     |    1 +
 include/configs/efikamx.h   |   16 ++
 5 files changed, 419 insertions(+), 0 deletions(-)
 create mode 100644 board/efikamx/efika.h
 create mode 100644 board/efikamx/efikamx-usb.c

diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
index ee4a16e..860e4d2 100644
--- a/board/efikamx/Makefile
+++ b/board/efikamx/Makefile
@@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= efikamx.o
+ifdef	CONFIG_CMD_USB
+COBJS	+= efikamx-usb.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/efikamx/efika.h b/board/efikamx/efika.h
new file mode 100644
index 0000000..2134e75
--- /dev/null
+++ b/board/efikamx/efika.h
@@ -0,0 +1,8 @@
+/*
+ * EHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
new file mode 100644
index 0000000..86f7619
--- /dev/null
+++ b/board/efikamx/efikamx-usb.c
@@ -0,0 +1,391 @@
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX.
+ */
+#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
+			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
+void setup_iomux_usb(void)
+{
+	/*
+	 * Configure USBH1 pads
+	 */
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
+
+	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
+
+	/*
+	 * Configure USBH1 control pads
+	 */
+
+	/* USB PHY reset */
+	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+	/* USB HUB reset */
+	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+
+	if (machine_is_efikasb()) {
+		/*
+		 * Configure USBH2 pads (used on EfikaSB)
+		 */
+		/* USBH2_DATA */
+		mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
+
+		/* USBH2_CLK */
+		mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
+		/* USBH2_DIR */
+		mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
+		/* USBH2_STP */
+		mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+		/* USBH2_NXT */
+		mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
+	}
+
+	/* WIFI EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
+	/* WIFI RESET */
+	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
+	/* BT EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+}
+
+/*
+ * Enable devices connected to USB BUSes.
+ */
+void efika_usb_enable_devices(void)
+{
+	/* Enable Bluetooth */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+
+	/* Enable WiFi */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	udelay(10000);
+
+	/* Reset the WiFi chip */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB).
+ */
+void efika_usb_hub_reset(void)
+{
+	/* HUB reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB).
+ */
+void efika_usb_phy_reset(void)
+{
+	/* SMSC 3317 PHY reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+}
+
+/*
+ * Configure control registers of the USB controller.
+ */
+void control_regs_setup(struct mx5_usb_control_regs *control)
+{
+	clrsetbits_le32(&control->usbctrl,
+		(MXC_OTG_WUE | MXC_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
+		MX51_H1_PM);
+
+	clrsetbits_le32(&control->phyctrl0,
+			MX51_OTG_OVERCURD,
+			MX51_EHCI_POWERPINSE);
+
+	clrsetbits_le32(&control->phyctrl1,
+			MX51_SYSCLOCK_MASK,
+			MX51_SYSCLOCK_24_MHZ);
+
+	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
+
+	clrsetbits_le32(&control->uh2ctrl,
+			(MX51_H2_ULPI_IE | MX51_H2_WUE),
+			MX51_H2_PM);
+
+	udelay(10000);
+}
+
+#define ULPI_ADDR_SHIFT		16
+#define ulpi_write_mask(value)	((value) & 0xff)
+#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
+
+u32 ulpi_wait(struct usb_ehci *ehci, u32 ulpi_bit, const char *operation)
+{
+	int timeout = ULPI_TIMEOUT;
+	u32 tmp;
+
+	/* Wait for the ulpi_bit to become zero. */
+	while (--timeout) {
+		tmp = readl(&ehci->ulpi_viewpoint);
+		if (!(tmp & ulpi_bit))
+			break;
+		WATCHDOG_RESET();
+	}
+
+	if (!timeout) {
+		printf("ULPI %s timed out\n", operation);
+		return 0;
+	}
+	return tmp;
+}
+
+void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		ulpi_wait(ehci, ULPI_WU, "wakeup");
+	}
+
+	writel(ULPI_RWRUN | ULPI_RWCTRL |
+		reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
+		&ehci->ulpi_viewpoint);
+	ulpi_wait(ehci, ULPI_RWRUN, "write");
+}
+
+u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		ulpi_wait(ehci, ULPI_WU, "wakeup");
+	}
+
+	writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
+	return ulpi_read_mask(ulpi_wait(ehci, ULPI_RWRUN, "read"));
+}
+
+void ulpi_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	u32 tmp = 0;
+	int reg, i;
+
+	/* get ID from ULPI immediate registers */
+	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
+		tmp |= ulpi_read(ehci, (u32)reg) << (reg * 8);
+	/* split into vendor and product ID */
+	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
+
+	/* ULPI check integrity */
+	for (i = 0; i < 2; i++) {
+		ulpi_write(ehci, (u32)&ulpi->scratch_write,
+			ULPI_TEST_VALUE << i);
+		tmp = ulpi_read(ehci, (u32)&ulpi->scratch_write);
+
+		if (tmp != (ULPI_TEST_VALUE << i)) {
+			printf("ULPI integrity check failed\n");
+			return;
+		}
+	}
+
+	/* ULPI set flags */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write,
+		ULPI_OTG_EXT_VBUS_IND |
+		ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN);
+	ulpi_write(ehci, (u32)&ulpi->function_ctrl_write,
+		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL |
+		ULPI_FC_SUSPENDM_PWRED);
+	ulpi_write(ehci, (u32)&ulpi->iface_ctrl_write, 0);
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set,
+		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT);
+
+	/*
+	 * NOTE: This violates USB specification, but otherwise, USB on Efika
+	 * doesn't charge VBUS and as a result, USB doesn't work.
+	 */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS);
+}
+
+/*
+ * Solve the VBUS reset problem on Efika
+ * by setting the CHRG_VBUS bit in the reset.
+ */
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		MX51_REGISTER_LAYOUT_LENGTH);
+	struct mxc_ulpi_regs *ulpi = (struct mxc_ulpi_regs *)0;
+
+	u32 tmp = ulpi_read(ehci, (u32)&ulpi->otg_ctrl_write);
+	tmp |= ULPI_OTG_CHRG_VBUS;
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write, tmp);
+
+	/* USB 2.0 specification say 50 ms resets on root. */
+	wait_ms(50);
+
+	/* Now terminate the reset. */
+	*reg_ref = ehci_readl(status_reg);
+	*reg_ref |= EHCI_PS_PE;
+}
+
+void ehci0_init(struct usb_ehci *ehci)
+{
+	writel(MX51_16BIT_UTMI, &ehci->portsc);
+}
+
+void ehci1_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	udelay(10000);
+
+	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
+	udelay(10000);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+
+void ehci2_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+	struct mx5_usb_control_regs *mx5_usb_control_regs;
+	struct mxc_ulpi_regs *ulpi;
+
+	mx5_usb_control_regs = (struct mx5_usb_control_regs *)(OTG_BASE_ADDR +
+		 MX5_CTRL_REGS_OFFSET);
+	control_regs_setup(mx5_usb_control_regs);
+	ulpi = (struct mxc_ulpi_regs *)0;
+
+	/* Init EHCI core */
+	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+	setbits_le32(&ehci->control, USB_EN);
+	
+	/* Init iMX51 EHCI */
+	efika_usb_phy_reset();
+	efika_usb_hub_reset();
+	efika_usb_enable_devices();
+
+	switch (CONFIG_MXC_USB_PORT) {
+	case 0:
+		ehci0_init(ehci);
+		break;
+	case 1:
+		ehci1_init(ehci, ulpi);
+		break;
+	case 2:
+		if (machine_is_efikasb()) {
+			ehci2_init(ehci, ulpi);
+			break;
+		}
+	};
+
+	/* EfikaMX USB has issues ... */
+	udelay(10000);
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 0c4e24b..09208ca 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -678,6 +678,7 @@ int board_late_init(void)
 
 	setup_iomux_led();
 	setup_iomux_ata();
+	setup_iomux_usb();
 
 	efikamx_toggle_led(EFIKAMX_LED_BLUE);
 
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index 54f48e4..010a16a 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -44,6 +44,10 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
+#define	CONFIG_L2_OFF
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
 /*
  * Bootloader Components Configuration
  */
@@ -172,6 +176,18 @@
 #endif
 
 /*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#endif /* CONFIG_CMD_USB */
+
+/*
  * Filesystems
  */
 #ifdef CONFIG_CMD_FAT
-- 
1.7.6.3

[U-Boot] [PATCH v6 4/4] Add USB support for Efika

[Marek Vasut]

On Tuesday, September 27, 2011 09:24:17 PM Jana Rapava wrote:
> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>     - changed to proper patch
> Changes for v3:
>     - merged other USB patches from u-boot-pxa/efikasb
>     - offset-based access changed to struct-based access
>     - use {clrset,clr,set}bits_le32() calls
>     - CodingStyle and naming cleanup
> Changes for v4:
>      - split into patchset
>      - CodingStyle and naming cleanup
>      - remove endless loops
>      - silence compiler warnings
> Changes for v5:
>        - change order of arguments in ulpi* functions
>        - change type of reg argument
>        - rename offset macro
> Changes for v6:
> 	- rebase on top of u-boot-imx/next
> 	- cleanup of CodingStyle and comments
> 	- use macro machine_is_efikasb()
> 	- introduce header file efika.h
> 
>  board/efikamx/Makefile      |    3 +
>  board/efikamx/efika.h       |    8 +
>  board/efikamx/efikamx-usb.c |  391
> +++++++++++++++++++++++++++++++++++++++++++ board/efikamx/efikamx.c     | 
>   1 +
>  include/configs/efikamx.h   |   16 ++
>  5 files changed, 419 insertions(+), 0 deletions(-)
>  create mode 100644 board/efikamx/efika.h
>  create mode 100644 board/efikamx/efikamx-usb.c
> 

Dear Jana Rapava,

[...]

> diff --git a/board/efikamx/efika.h b/board/efikamx/efika.h
> new file mode 100644
> index 0000000..2134e75
> --- /dev/null
> +++ b/board/efikamx/efika.h
> @@ -0,0 +1,8 @@

Proper header is missing here, with license, author etc.

> +/*
> + * EHCI USB
> + */
> +#ifdef	CONFIG_CMD_USB
> +void setup_iomux_usb(void);
> +#else
> +static inline void setup_iomux_usb(void) { }
> +#endif

[...]

> +u32 ulpi_wait(struct usb_ehci *ehci, u32 ulpi_bit, const char *operation)
> +{
> +	int timeout = ULPI_TIMEOUT;
> +	u32 tmp;
> +
> +	/* Wait for the ulpi_bit to become zero. */
> +	while (--timeout) {
> +		tmp = readl(&ehci->ulpi_viewpoint);
> +		if (!(tmp & ulpi_bit))
> +			break;
> +		WATCHDOG_RESET();
> +	}
> +
> +	if (!timeout) {
> +		printf("ULPI %s timed out\n", operation);
> +		return 0;
> +	}
> +	return tmp;
> +}
> +
> +void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
> +{
> +	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +		writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +		ulpi_wait(ehci, ULPI_WU, "wakeup");

This function returns some value, but you're not checking it. It's probably if 
the wait timed out, right ? Why aren't you checking it ?

> +	}
> +
> +	writel(ULPI_RWRUN | ULPI_RWCTRL |
> +		reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
> +		&ehci->ulpi_viewpoint);
> +	ulpi_wait(ehci, ULPI_RWRUN, "write");

DTTO

> +}
> +
> +u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
> +{
> +	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +		writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +		ulpi_wait(ehci, ULPI_WU, "wakeup");
> +	}
> +
> +	writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
> +	return ulpi_read_mask(ulpi_wait(ehci, ULPI_RWRUN, "read"));

This seems wrong ?

Cheers

[U-Boot] [PATCH v6 4/4] Add USB support for Efika

[Jana Rapava]

2011/9/27 Marek Vasut <marek.vasut@gmail.com>


> > diff --git a/board/efikamx/efika.h b/board/efikamx/efika.h
> > new file mode 100644
> > index 0000000..2134e75
> > --- /dev/null
> > +++ b/board/efikamx/efika.h
> > @@ -0,0 +1,8 @@
>
> Proper header is missing here, with license, author etc.
>

What should I write into copyright field, if I copied your code into this
header file?


> > +void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
> > +{
> > +     if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> > +             writel(ULPI_WU, &ehci->ulpi_viewpoint);
> > +             ulpi_wait(ehci, ULPI_WU, "wakeup");
>
> This function returns some value, but you're not checking it. It's probably
> if
> the wait timed out, right ? Why aren't you checking it ?
>

I''ll check it, but I don't know what function calling ulpi_write/read/wait
should do if call fails. Should it write error message and return, should it
write message and return error value...?

Cheers

[U-Boot] [PATCH v6 4/4] Add USB support for Efika

[Marek Vasut]

On Tuesday, September 27, 2011 10:40:26 PM Jana Rapava wrote:
> 2011/9/27 Marek Vasut <marek.vasut@gmail.com>
> 
> > > diff --git a/board/efikamx/efika.h b/board/efikamx/efika.h
> > > new file mode 100644
> > > index 0000000..2134e75
> > > --- /dev/null
> > > +++ b/board/efikamx/efika.h
> > > @@ -0,0 +1,8 @@
> > 
> > Proper header is missing here, with license, author etc.
> 
> What should I write into copyright field, if I copied your code into this
> header file?

You're introducing your file here, it's your stuff.

> 
> > > +void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
> > > +{
> > > +     if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> > > +             writel(ULPI_WU, &ehci->ulpi_viewpoint);
> > > +             ulpi_wait(ehci, ULPI_WU, "wakeup");
> > 
> > This function returns some value, but you're not checking it. It's
> > probably if
> > the wait timed out, right ? Why aren't you checking it ?
> 
> I''ll check it, but I don't know what function calling ulpi_write/read/wait
> should do if call fails. Should it write error message and return, should
> it write message and return error value...?

Return error value until you reach ulpi_{read/write}, write error message there 
?

[U-Boot] [PATCH v6 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

On Tuesday, September 27, 2011 09:24:15 PM Jana Rapava wrote:
> Add callback to ehci_fixup to prepare
> for solving the problem with VBUS reset on Efika.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v4:
>      - split into patchset
>      - add callback ehci_fixup
> Changes for v5:
>        - make this the second patch in series
>        - add comment to alias ehci_fixup
> Changes for v6:
> 	- make the comment a sentence
> 	- rebase patch on top of u-boot-imx/next
> 
>  drivers/usb/host/ehci-hcd.c |   13 ++++++++++++-
>  1 files changed, 12 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index bdadd46..da09f51 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -536,6 +536,17 @@ static inline int min3(int a, int b, int c)
>  	return a;
>  }
> 
> +inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +{
> +	wait_ms(50);
> +}
> +
> +/* This function will alias to __ehci_fixup,
> + * unless function ehci_fixup is defined somewhere.
> +*/

Dear Jana Rapava,

this is still wrong, the comment starts one line below the opening.

[U-Boot] [PATCH v7 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

Add callback to ehci_fixup to prepare
for solving the problem with VBUS reset on Efika.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v1:
    - split into patchset
    - add callback ehci_fixup
Changes for v2:
      - make this the second patch in series
      - add comment to alias ehci_fixup
Changes for v3:
       - make the comment a sentence
       - rebase patch on top of u-boot-imx/next
Changes for v4:
	- change the versioning of changelog
	from per patchset to per patch
	- fix the appearance of comment

 drivers/usb/host/ehci-hcd.c |   13 ++++++++++++-
 1 files changed, 12 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index bdadd46..ef0c578 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -536,6 +536,17 @@ static inline int min3(int a, int b, int c)
 	return a;
 }
 
+inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	wait_ms(50);
+}
+/*
+ * this function will alias to __ehci_fixup,
+ * unless function ehci_fixup is defined somewhere
+ */
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+	 __attribute__((weak, alias("__ehci_fixup")));
+
 int
 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 		 int length, struct devrequest *req)
@@ -709,7 +720,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 				 * usb 2.0 specification say 50 ms resets on
 				 * root
 				 */
-				wait_ms(50);
+				ehci_fixup(status_reg, &reg);
 				/* terminate the reset */
 				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 				/*
-- 
1.7.6.3

[U-Boot] [PATCH v7 3/4] EHCI: adjust for mx5

[Jana Rapava]

Add macros and structures needed by Efika USB support code.
Move shared offset and bits definitions into common header file.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v1:
    - split into patchset
Changes for v2:
      - make this the third patch in series
      - move all #define's from ehci-mxc.c to ehci-fsl.h
      - rename structures
Changes for v3:
       - rebase on top of u-boot-imx/next
	(no actual changes)
Changes for v4:
	- change changelog versioning from per patchset to per patch
	- no changes

 drivers/usb/host/ehci-mxc.c |   31 +--------
 include/usb/ehci-fsl.h      |  146 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 148 insertions(+), 29 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index fde1f0f..2c1295f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -27,31 +27,6 @@
 #include <usb/ehci.h>
 #include <usb/ehci-core.h>
 
-#define USBCTRL_OTGBASE_OFFSET	0x600
-
-#ifdef CONFIG_MX25
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
-
-#ifdef CONFIG_MX31
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
-
-#define MX31_H2_SIC_SHIFT	21
-#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT		(1 << 16)
-#define MX31_H2_DT_BIT		(1 << 5)
-
-#define MX31_H1_SIC_SHIFT	13
-#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT		(1 << 8)
-#define MX31_H1_DT_BIT		(1 << 4)
-#endif
-
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
@@ -66,11 +41,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		switch (port) {
 		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+			v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT);
 			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
+					<< MXC_OTG_SIC_SHIFT;
 			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
+				v |= MXC_OTG_PM_BIT;
 
 			break;
 		case 1: /* H1 port */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..727134f 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,106 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
+#define USBCTRL_OTGBASE_OFFSET	0x600
+#endif
+
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
+#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
+#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#endif
+
+#ifdef CONFIG_MX31
+#define MX31_H2_SIC_SHIFT	21
+#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT		(1 << 16)
+#define MX31_H2_DT_BIT		(1 << 5)
+
+#define MX31_H1_SIC_SHIFT	13
+#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT		(1 << 8)
+#define MX31_H1_DT_BIT		(1 << 4)
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+/* offset for first USB CTRL register */
+#define MX5_CTRL_REGS_OFFSET	0x800
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX31)
+/* USB_CTRL register bits of interest*/
+#define MXC_OTG_SIC_SHIFT	29
+#define MXC_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
+#define MXC_OTG_WUE		(1 << 27)
+#define MXC_OTG_PM		(1 << 24)
+#endif
+
+#ifdef CONFIG_MX51
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_OTG_ID	0x000
+#define MX51_UH1_ID	0x200
+#define MX51_UH2_ID	0x400
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_PM		(1 << 24)
+#define MX51_H1_ULPI_IE		(1 << 12)
+#define MX51_H1_WUE		(1 << 11)
+#define MX51_H1_PM		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD	(1 << 8)
+#define MX51_EHCI_POWERPINSE	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ	(1 << 0)
+#define MX51_SYSCLOCK_MASK	(~(0xffffffff << 2))
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE		(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE		(1 << 8)
+#define MX51_H2_WUE		(1 << 7)
+#define MX51_H2_PM		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI		(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(0xff << 16)
+#endif
+
+/*
+* ULPI
+*/
+#define ULPI_ID_REGS_COUNT	4
+#define ULPI_TEST_VALUE		0x55
+#define ULPI_TIMEOUT		1000 /* some reasonable value */
+
+/* ULPI viewport control bits */
+#define ULPI_WU		(1 << 31)
+#define ULPI_SS		(1 << 27)
+#define ULPI_RWRUN	(1 << 30)
+#define ULPI_RWCTRL	(1 << 29)
+
+/* ULPI OTG Control bits of interest */
+#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
+#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
+#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
+#define	ULPI_OTG_DRV_VBUS	(1 << 5)
+#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
+#define ULPI_OTG_CHRG_VBUS	(1 << 4)
+
+/* ULPI Function Control bits of interest */
+#define ULPI_FC_XCVR_SELECT	(1 << 0)
+#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
+#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
+
 /*
  * USB Registers
  */
@@ -210,7 +310,7 @@ struct usb_ehci {
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
 					   pre-buffer packet tuning */
 	u8	res7[0x8];
-	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
 	u8	res8[0xc];
 	u32	config_flag;	/* 0x180 - Configured Flag Register */
 	u32	portsc;		/* 0x184 - Port status/control */
@@ -242,4 +342,48 @@ struct usb_ehci {
 	u8	res13[0xafc];
 };
 
+struct mx5_usb_control_regs {
+	u32	usbctrl;	/* 0x800 - USB Control */
+	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
+	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
+	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
+	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
+	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
+	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
+};
+
+struct mxc_ulpi_regs {
+	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
+	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
+	u8	product_id_low;		/* 0x02 - Product ID lower byte */
+	u8	product_id_high;	/* 0x03 - Product ID higher byte */
+	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
+	u8	function_ctrl_write;
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
+	u8	iface_ctrl_write;
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
+	u8	otg_ctrl_write;
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
+	u8	usb_ie_rising_write;
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
+	u8	usb_ie_falling_write;
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
+	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
+	u8	debug;			/* 0x15 - Debug */
+	/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
+	u8	scratch_write;
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 Clear*/
+};
+
 #endif /* _EHCI_FSL_H */
-- 
1.7.6.3

[U-Boot] [PATCH v7 4/4] Add USB support for Efika

[Jana Rapava]

This commit adds USB support for EfikaMX and EfikaSB.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
   - changed to proper patch
Changes for v3:
   - merged other USB patches from u-boot-pxa/efikasb
   - offset-based access changed to struct-based access
   - use {clrset,clr,set}bits_le32() calls
   - CodingStyle and naming cleanup
Changes for v4:
    - split into patchset
    - CodingStyle and naming cleanup
    - remove endless loops
    - silence compiler warnings
Changes for v5:
      - change order of arguments in ulpi* functions
      - change type of reg argument
      - rename offset macro
Changes for v6:
       - rebase on top of u-boot-imx/next
       - cleanup of CodingStyle and comments
       - use macro machine_is_efikasb()
       - introduce header file efika.h
Changes for v7:
	- add proper header to efika.h
	- include efika.h into efikamx.c
	- check return values from ulpi_wait()

 board/efikamx/Makefile      |    3 +
 board/efikamx/efika.h       |   30 ++++
 board/efikamx/efikamx-usb.c |  397 +++++++++++++++++++++++++++++++++++++++++++
 board/efikamx/efikamx.c     |    3 +
 include/configs/efikamx.h   |   16 ++
 5 files changed, 449 insertions(+), 0 deletions(-)
 create mode 100644 board/efikamx/efika.h
 create mode 100644 board/efikamx/efikamx-usb.c

diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
index ee4a16e..860e4d2 100644
--- a/board/efikamx/Makefile
+++ b/board/efikamx/Makefile
@@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= efikamx.o
+ifdef	CONFIG_CMD_USB
+COBJS	+= efikamx-usb.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/efikamx/efika.h b/board/efikamx/efika.h
new file mode 100644
index 0000000..b3532e2
--- /dev/null
+++ b/board/efikamx/efika.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2011 Jana Rapava <fermata7@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * EHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
new file mode 100644
index 0000000..06a4cdc
--- /dev/null
+++ b/board/efikamx/efikamx-usb.c
@@ -0,0 +1,397 @@
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX.
+ */
+#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
+			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
+void setup_iomux_usb(void)
+{
+	/*
+	 * Configure USBH1 pads
+	 */
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
+
+	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
+
+	/*
+	 * Configure USBH1 control pads
+	 */
+
+	/* USB PHY reset */
+	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+	/* USB HUB reset */
+	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+
+	if (machine_is_efikasb()) {
+		/*
+		 * Configure USBH2 pads (used on EfikaSB)
+		 */
+		/* USBH2_DATA */
+		mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
+
+		/* USBH2_CLK */
+		mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
+		/* USBH2_DIR */
+		mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
+		/* USBH2_STP */
+		mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+		/* USBH2_NXT */
+		mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
+	}
+
+	/* WIFI EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
+	/* WIFI RESET */
+	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
+	/* BT EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+}
+
+/*
+ * Enable devices connected to USB BUSes.
+ */
+void efika_usb_enable_devices(void)
+{
+	/* Enable Bluetooth */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+
+	/* Enable WiFi */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	udelay(10000);
+
+	/* Reset the WiFi chip */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB).
+ */
+void efika_usb_hub_reset(void)
+{
+	/* HUB reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB).
+ */
+void efika_usb_phy_reset(void)
+{
+	/* SMSC 3317 PHY reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+}
+
+/*
+ * Configure control registers of the USB controller.
+ */
+void control_regs_setup(struct mx5_usb_control_regs *control)
+{
+	clrsetbits_le32(&control->usbctrl,
+		(MXC_OTG_WUE | MXC_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
+		MX51_H1_PM);
+
+	clrsetbits_le32(&control->phyctrl0,
+			MX51_OTG_OVERCURD,
+			MX51_EHCI_POWERPINSE);
+
+	clrsetbits_le32(&control->phyctrl1,
+			MX51_SYSCLOCK_MASK,
+			MX51_SYSCLOCK_24_MHZ);
+
+	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
+
+	clrsetbits_le32(&control->uh2ctrl,
+			(MX51_H2_ULPI_IE | MX51_H2_WUE),
+			MX51_H2_PM);
+
+	udelay(10000);
+}
+
+#define ULPI_ADDR_SHIFT		16
+#define ulpi_write_mask(value)	((value) & 0xff)
+#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
+
+u32 ulpi_wait(struct usb_ehci *ehci, u32 ulpi_bit)
+{
+	int timeout = ULPI_TIMEOUT;
+	u32 tmp;
+
+	/* Wait for the ulpi_bit to become zero. */
+	while (--timeout) {
+		tmp = readl(&ehci->ulpi_viewpoint);
+		if (!(tmp & ulpi_bit))
+			break;
+		WATCHDOG_RESET();
+	}
+
+	if (!timeout)
+		return 0;
+	else
+		return tmp;
+}
+
+void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		if (!ulpi_wait(ehci, ULPI_WU))
+			printf("ULPI wakeup timed out\n");
+	}
+
+	writel(ULPI_RWRUN | ULPI_RWCTRL |
+		reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
+		&ehci->ulpi_viewpoint);
+	if (!ulpi_wait(ehci, ULPI_RWRUN))
+		printf("ULPI write timed out\n");
+}
+
+u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
+{
+	u32 tmp;
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		if (!ulpi_wait(ehci, ULPI_WU))
+			printf("ULPI wakeup timed out\n");
+	}
+
+	writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
+	tmp = ulpi_wait(ehci, ULPI_RWRUN);
+	if (!tmp)
+		printf("ULPI read timed out\n");
+	return ulpi_read_mask(tmp);
+}
+
+void ulpi_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	u32 tmp = 0;
+	int reg, i;
+
+	/* get ID from ULPI immediate registers */
+	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
+		tmp |= ulpi_read(ehci, (u32)reg) << (reg * 8);
+	/* split into vendor and product ID */
+	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
+
+	/* ULPI check integrity */
+	for (i = 0; i < 2; i++) {
+		ulpi_write(ehci, (u32)&ulpi->scratch_write,
+			ULPI_TEST_VALUE << i);
+		tmp = ulpi_read(ehci, (u32)&ulpi->scratch_write);
+
+		if (tmp != (ULPI_TEST_VALUE << i)) {
+			printf("ULPI integrity check failed\n");
+			return;
+		}
+	}
+
+	/* ULPI set flags */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write,
+		ULPI_OTG_EXT_VBUS_IND |
+		ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN);
+	ulpi_write(ehci, (u32)&ulpi->function_ctrl_write,
+		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL |
+		ULPI_FC_SUSPENDM_PWRED);
+	ulpi_write(ehci, (u32)&ulpi->iface_ctrl_write, 0);
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set,
+		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT);
+
+	/*
+	 * NOTE: This violates USB specification, but otherwise, USB on Efika
+	 * doesn't charge VBUS and as a result, USB doesn't work.
+	 */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS);
+}
+
+/*
+ * Solve the VBUS reset problem on Efika
+ * by setting the CHRG_VBUS bit in the reset.
+ */
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		MX51_REGISTER_LAYOUT_LENGTH);
+	struct mxc_ulpi_regs *ulpi = (struct mxc_ulpi_regs *)0;
+
+	u32 tmp = ulpi_read(ehci, (u32)&ulpi->otg_ctrl_write);
+	tmp |= ULPI_OTG_CHRG_VBUS;
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write, tmp);
+
+	/* USB 2.0 specification say 50 ms resets on root. */
+	wait_ms(50);
+
+	/* Now terminate the reset. */
+	*reg_ref = ehci_readl(status_reg);
+	*reg_ref |= EHCI_PS_PE;
+}
+
+void ehci0_init(struct usb_ehci *ehci)
+{
+	writel(MX51_16BIT_UTMI, &ehci->portsc);
+}
+
+void ehci1_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	udelay(10000);
+
+	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
+	udelay(10000);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+
+void ehci2_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+	struct mx5_usb_control_regs *mx5_usb_control_regs;
+	struct mxc_ulpi_regs *ulpi;
+
+	mx5_usb_control_regs = (struct mx5_usb_control_regs *)(OTG_BASE_ADDR +
+		 MX5_CTRL_REGS_OFFSET);
+	control_regs_setup(mx5_usb_control_regs);
+	ulpi = (struct mxc_ulpi_regs *)0;
+
+	/* Init EHCI core */
+	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+	setbits_le32(&ehci->control, USB_EN);
+	
+	/* Init iMX51 EHCI */
+	efika_usb_phy_reset();
+	efika_usb_hub_reset();
+	efika_usb_enable_devices();
+
+	switch (CONFIG_MXC_USB_PORT) {
+	case 0:
+		ehci0_init(ehci);
+		break;
+	case 1:
+		ehci1_init(ehci, ulpi);
+		break;
+	case 2:
+		if (machine_is_efikasb()) {
+			ehci2_init(ehci, ulpi);
+			break;
+		}
+	};
+
+	/* EfikaMX USB has issues ... */
+	udelay(10000);
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 0c4e24b..8e9b42b 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -37,6 +37,8 @@
 #include <fsl_pmic.h>
 #include <mc13892.h>
 
+#include "efika.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -678,6 +680,7 @@ int board_late_init(void)
 
 	setup_iomux_led();
 	setup_iomux_ata();
+	setup_iomux_usb();
 
 	efikamx_toggle_led(EFIKAMX_LED_BLUE);
 
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index 54f48e4..010a16a 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -44,6 +44,10 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
+#define	CONFIG_L2_OFF
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
 /*
  * Bootloader Components Configuration
  */
@@ -172,6 +176,18 @@
 #endif
 
 /*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#endif /* CONFIG_CMD_USB */
+
+/*
  * Filesystems
  */
 #ifdef CONFIG_CMD_FAT
-- 
1.7.6.3

[U-Boot] [PATCH v7 4/4] Add USB support for Efika

[Marek Vasut]

> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>? ? ?  - changed to proper patch
> Changes for v3:
>? ? ?  - merged other USB patches from u-boot-pxa/efikasb
>? ? ?  - offset-based access changed to struct-based access
>? ? ?  - use {clrset,clr,set}bits_le32() calls
>? ? ?  - CodingStyle and naming cleanup
> Changes for v4:
>? ? ? ?  - split into patchset
>? ? ? ?  - CodingStyle and naming cleanup
>? ? ? ?  - remove endless loops
>? ? ? ?  - silence compiler warnings
> Changes for v5:
>? ? ? ? ? ?  - change order of arguments in ulpi* functions
>? ? ? ? ? ?  - change type of reg argument
>? ? ? ? ? ?  - rename offset macro
> Changes for v6:
>? ? ? ? ? ? ?  - rebase on top of u-boot-imx/next
>? ? ? ? ? ? ?  - cleanup of CodingStyle and comments
>? ? ? ? ? ? ?  - use macro machine_is_efikasb()
>? ? ? ? ? ? ?  - introduce header file efika.h
> Changes for v7:
> ??? - add proper header to efika.h
> ??? - include efika.h into efikamx.c
> ??? - check return values from ulpi_wait()
> 
>?  board/efikamx/Makefile? ? ? ? ?  |? ? ?  3 +
>?  board/efikamx/efika.h? ? ? ? ? ?  |? ?  30 ++++
>?  board/efikamx/efikamx-usb.c |?  397
> +++++++++++++++++++++++++++++++++++++++++++ board/efikamx/efikamx.c? ? ?  
> |? ? ?  3 + include/configs/efikamx.h? ?  |? ?  16 ++
>?  5 files changed, 449 insertions(+), 0 deletions(-)
>?  create mode 100644 board/efikamx/efika.h
>?  create mode 100644 board/efikamx/efikamx-usb.c
> 
Dear Jana Rapava,

[...]

> +u32 ulpi_wait(struct usb_ehci *ehci, u32 ulpi_bit)
> +{
> +??? int timeout = ULPI_TIMEOUT;
> +??? u32 tmp;
> +
> +??? /* Wait for the ulpi_bit to become zero. */
> +??? while (--timeout) {
> +??? ??? tmp = readl(&ehci->ulpi_viewpoint);
> +??? ??? if (!(tmp & ulpi_bit))
> +??? ??? ??? break;
> +??? ??? WATCHDOG_RESET();
> +??? }
> +
> +??? if (!timeout)
> +??? ??? return 0;
> +??? else
> +??? ??? return tmp;

The logic here seems bogus, if the register is zero, this function returns zero either way.

> +}
> +
> +void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
> +{
> +??? if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +??? ??? writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +??? ??? if (!ulpi_wait(ehci, ULPI_WU))
> +??? ??? ??? printf("ULPI wakeup timed out\n");
> +??? }
> +
> +??? writel(ULPI_RWRUN | ULPI_RWCTRL |
> +??? ??? reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
> +??? ??? &ehci->ulpi_viewpoint);
> +??? if (!ulpi_wait(ehci, ULPI_RWRUN))
> +??? ??? printf("ULPI write timed out\n");
> +}
> +
> +u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
> +{
> +??? u32 tmp;
> +??? if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +??? ??? writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +??? ??? if (!ulpi_wait(ehci, ULPI_WU))
> +??? ??? ??? printf("ULPI wakeup timed out\n");
> +??? }
> +
> +??? writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
> +??? tmp = ulpi_wait(ehci, ULPI_RWRUN);
> +??? if (!tmp)
> +??? ??? printf("ULPI read timed out\n");
> +??? return ulpi_read_mask(tmp);
> +}
> +
> +void ulpi_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
> +{
> +??? u32 tmp = 0;
> +??? int reg, i;
> +
> +??? /* get ID from ULPI immediate registers */
> +??? for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
> +??? ??? tmp |= ulpi_read(ehci, (u32)reg) << (reg * 8);

Are you ignoring my comment and picking only some of them? Is the cast here necessary?

> +??? /* split into vendor and product ID */
> +??? debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
> +
> +??? /* ULPI check integrity */
> +??? for (i = 0; i < 2; i++) {
> +??? ??? ulpi_write(ehci, (u32)&ulpi->scratch_write,
> +??? ??? ??? ULPI_TEST_VALUE << i);
> +??? ??? tmp = ulpi_read(ehci, (u32)&ulpi->scratch_write);
> +
> +??? ??? if (tmp != (ULPI_TEST_VALUE << i)) {
> +??? ??? ??? printf("ULPI integrity check failed\n");
> +??? ??? ??? return;
> +??? ??? }
> +??? }
> +
> +??? /* ULPI set flags */
> +??? ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write,
> +??? ??? ULPI_OTG_EXT_VBUS_IND |
> +??? ??? ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN);
> +??? ulpi_write(ehci, (u32)&ulpi->function_ctrl_write,
> +??? ??? ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL |
> +??? ??? ULPI_FC_SUSPENDM_PWRED);
> +??? ulpi_write(ehci, (u32)&ulpi->iface_ctrl_write, 0);
> +??? ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set,
> +??? ??? ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT);
> +
> +??? /*
> +???  * NOTE: This violates USB specification, but otherwise, USB on Efika
> +???  * doesn't charge VBUS and as a result, USB doesn't work.
> +???  */
> +??? ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS);
> +}
> +
> +/*
> + * Solve the VBUS reset problem on Efika
> + * by setting the CHRG_VBUS bit in the reset.
> + */
> +void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +{
> +??? struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +??? ??? MX51_REGISTER_LAYOUT_LENGTH);
> +??? struct mxc_ulpi_regs *ulpi = (struct mxc_ulpi_regs *)0;
> +
> +??? u32 tmp = ulpi_read(ehci, (u32)&ulpi->otg_ctrl_write);
> +??? tmp |= ULPI_OTG_CHRG_VBUS;
> +??? ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write, tmp);
> +
> +??? /* USB 2.0 specification say 50 ms resets on root. */

Where can I read about this please?

> +??? wait_ms(50);
> +
> +??? /* Now terminate the reset. */
> +??? *reg_ref = ehci_readl(status_reg);
> +??? *reg_ref |= EHCI_PS_PE;
> +}
> +
> +void ehci0_init(struct usb_ehci *ehci)
> +{
> +??? writel(MX51_16BIT_UTMI, &ehci->portsc);
> +}
> +
> +void ehci1_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
> +{
> +??? mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
> +??? mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
> +??? ??? ??? ??? PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> +??? gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
> +??? udelay(1000);
> +??? gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
> +??? udelay(1000);
> +
> +??? mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
> +??? mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
> +??? udelay(10000);
> +
> +??? clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
> +??? udelay(10000);
> +
> +??? writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
> +??? udelay(10000);
> +
> +??? ulpi_init(ehci, ulpi);
> +}
> +
> +

remove newline

> +void ehci2_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
> +{
> +??? mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
> +??? mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
> +??? ??? ??? ??? PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
> +??? gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
> +??? udelay(1000);
> +??? gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
> +??? udelay(1000);
> +
> +??? mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
> +??? mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
> +
> +??? writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
> +??? udelay(10000);
> +
> +??? ulpi_init(ehci, ulpi);
> +}
> +
> +int ehci_hcd_init(void)
> +{
> +??? struct usb_ehci *ehci;
> +??? struct mx5_usb_control_regs *mx5_usb_control_regs;
> +??? struct mxc_ulpi_regs *ulpi;
> +
> +??? mx5_usb_control_regs = (struct mx5_usb_control_regs *)(OTG_BASE_ADDR +
> +??? ???  MX5_CTRL_REGS_OFFSET);
> +??? control_regs_setup(mx5_usb_control_regs);
> +??? ulpi = (struct mxc_ulpi_regs *)0;
> +
> +??? /* Init EHCI core */
> +??? ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +??? ??? (MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
> +??? hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
> +??? hcor = (struct ehci_hcor *)((uint32_t) hccr +
> +??? ??? ??? HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> +??? setbits_le32(&ehci->usbmode, CM_HOST);
> +??? setbits_le32(&ehci->control, USB_EN);
> +???
> +??? /* Init iMX51 EHCI */
> +??? efika_usb_phy_reset();
> +??? efika_usb_hub_reset();
> +??? efika_usb_enable_devices();
> +
> +??? switch (CONFIG_MXC_USB_PORT) {
> +??? case 0:
> +??? ??? ehci0_init(ehci);
> +??? ??? break;
> +??? case 1:
> +??? ??? ehci1_init(ehci, ulpi);
> +??? ??? break;
> +??? case 2:
> +??? ??? if (machine_is_efikasb()) {
> +??? ??? ??? ehci2_init(ehci, ulpi);
> +??? ??? ??? break;
> +??? ??? }

the break should be past the if, also you can drop the braces then.

> +??? };
> +
> +??? /* EfikaMX USB has issues ... */
> +??? udelay(10000);
> +
> +??? return 0;
> +}
> +
> +int ehci_hcd_stop(void)
> +{
> +??? return 0;
> +}

[U-Boot] [PATCH v7 4/4] Add USB support for Efika

[Jana Rapava]

2011/9/28 Marek Vasut <marek.vasut.n900@gmail.com>

> > +    /* get ID from ULPI immediate registers */
> > +    for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
> > +        tmp |= ulpi_read(ehci, (u32)reg) << (reg * 8);
>
> Are you ignoring my comment and picking only some of them? Is the cast here
> necessary?
>

Sorry, I try to change patches according to your requests, but sometimes I
overlook something.
Also, it looks like I forgot to add proper header to efikamx-usb.c. Should I
add it in the next version?

>
> > +    /* USB 2.0 specification say 50 ms resets on root. */
>
> Where can I read about this please?
>

Universal Serial Bus Specification Revision 2.0, chapter 7.1.7.5 Reset
Signaling says: "It is required that resets from root ports have a duration
of at least 50 ms (TDRSTR)."

Regards,
Jana Rapava

[U-Boot] [PATCH v7 4/4] Add USB support for Efika

[Marek Vasut]

On Wednesday, September 28, 2011 02:25:14 PM Jana Rapava wrote:
> 2011/9/28 Marek Vasut <marek.vasut.n900@gmail.com>
> 
> > > +    /* get ID from ULPI immediate registers */
> > > +    for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
> > > +        tmp |= ulpi_read(ehci, (u32)reg) << (reg * 8);
> > 
> > Are you ignoring my comment and picking only some of them? Is the cast
> > here necessary?
> 
> Sorry, I try to change patches according to your requests, but sometimes I
> overlook something.
> Also, it looks like I forgot to add proper header to efikamx-usb.c. Should
> I add it in the next version?

yes ... 

Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
Copyright (C) 2011 Jana Rapava <fermata7@gmail.com>

> 
> > > +    /* USB 2.0 specification say 50 ms resets on root. */
> > 
> > Where can I read about this please?
> 
> Universal Serial Bus Specification Revision 2.0, chapter 7.1.7.5 Reset
> Signaling says: "It is required that resets from root ports have a duration
> of at least 50 ms (TDRSTR)."

OK

> 
> Regards,
> Jana Rapava

[U-Boot] [PATCH v7 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

> Add callback to ehci_fixup

Dear Jana Rapava,

you mean ehci-hcd.c ?

 to prepare
> for solving the problem with VBUS reset on Efika.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v1:
>? ? ? ?  - split into patchset
>? ? ? ?  - add callback ehci_fixup
> Changes for v2:
>? ? ? ? ? ?  - make this the second patch in series
>? ? ? ? ? ?  - add comment to alias ehci_fixup
> Changes for v3:
>? ? ? ? ? ? ?  - make the comment a sentence
>? ? ? ? ? ? ?  - rebase patch on top of u-boot-imx/next
> Changes for v4:
> ??? - change the versioning of changelog
> ??? from per patchset to per patch
> ??? - fix the appearance of comment

so this is a resend?

> 
>?  drivers/usb/host/ehci-hcd.c |? ?  13 ++++++++++++-
>?  1 files changed, 12 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index bdadd46..ef0c578 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -536,6 +536,17 @@ static inline int min3(int a, int b, int c)
>?  ??? return a;
>?  }
>?  
> +inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +{
> +??? wait_ms(50);
> +}
> +/*
> + * this function will alias to __ehci_fixup,
> + * unless function ehci_fixup is defined somewhere

mske this a sentence please ... 'this is a default behaviour unless the user redefines this ...', Something along those lines, be creative.

> + */
> +void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +???  __attribute__((weak, alias("__ehci_fixup")));
> +
>?  int
>?  ehci_submit_root(struct usb_device *dev, unsigned long pipe, void
> *buffer, ??? ???  int length, struct devrequest *req)
> @@ -709,7 +720,7 @@ ehci_submit_root(struct usb_device *dev, unsigned
> long pipe, void *buffer, ??? ??? ??? ???  * usb 2.0 specification say 50 ms resets on
>?  ??? ??? ??? ???  * root
>?  ??? ??? ??? ???  */
> -??? ??? ??? ??? wait_ms(50);
> +??? ??? ??? ??? ehci_fixup(status_reg, &reg);
>?  ??? ??? ??? ??? /* terminate the reset */
>?  ??? ??? ??? ??? ehci_writel(status_reg, reg & ~EHCI_PS_PR);
>?  ??? ??? ??? ??? /*
> -- 
> 1.7.6.3
> 

[U-Boot] [PATCH v7 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

On Wednesday, September 28, 2011 12:21:16 AM Jana Rapava wrote:
> Add callback to ehci_fixup to prepare
> for solving the problem with VBUS reset on Efika.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v1:
>     - split into patchset
>     - add callback ehci_fixup
> Changes for v2:
>       - make this the second patch in series
>       - add comment to alias ehci_fixup
> Changes for v3:
>        - make the comment a sentence
>        - rebase patch on top of u-boot-imx/next
> Changes for v4:
> 	- change the versioning of changelog
> 	from per patchset to per patch
> 	- fix the appearance of comment
> 

Sentence -- starts with a capital letter and ends with a dot ... please fix 
already. Otherwise:

Acked-by: Marek Vasut <marek.vasut@gmail.com>

(please add this line to the final revision of this patch.)

[U-Boot] [PATCH v7 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

> Otherwise:
> Acked-by: Marek Vasut <marek.vasut@gmail.com>
>
> (please add this line to the final revision of this patch.)
>

Thanks, should I add this line also to the first two patches of this
patchset? There weren't any change requests for the last version of them.

Regards,
Jana Rapava

[U-Boot] [PATCH v7 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

On Wednesday, September 28, 2011 01:52:39 PM Jana Rapava wrote:
> > Otherwise:
> > Acked-by: Marek Vasut <marek.vasut@gmail.com>
> > 
> > (please add this line to the final revision of this patch.)
> 
> Thanks, should I add this line also to the first two patches of this
> patchset? There weren't any change requests for the last version of them.

This is 2/4 patch ... how can there be "first two patches" ? Am I missing 
something ? Ok, this is starting to be a mess, can you resubmit the whole series 
? And no, add Acked-by only to Acked-by patches.

Cheers
> 
> Regards,
> Jana Rapava

[U-Boot] [PATCH v8 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

Add callback to ehci_hcd.c to prepare
for solving the problem with VBUS reset on Efika.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>

Acked-by: Marek Vasut <marek.vasut@gmail.com>
---
Changes for v1:
   - split into patchset
   - add callback ehci_fixup
Changes for v2:
     - make this the second patch in series
     - add comment to alias ehci_fixup
     - no actual changes
Changes for v3:
      - no actual changes
      - make the comment a sentence
      - rebase patch on top of u-boot-imx/next
Changes for v4:
       - no actual changes
       - change the versioning of changelog
       from per patchset to per patch
       - fix the appearance of comment
Changes for v5:
	- no actual changes
	- reword the comment

 drivers/usb/host/ehci-hcd.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index bdadd46..fb64f23 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -536,6 +536,18 @@ static inline int min3(int a, int b, int c)
 	return a;
 }
 
+inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	wait_ms(50);
+}
+
+/*
+ * This is an alias to __ehci_fixup
+ * unless user provides other definition of ehci_fixup function.
+ */
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+	 __attribute__((weak, alias("__ehci_fixup")));
+
 int
 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 		 int length, struct devrequest *req)
@@ -709,7 +721,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 				 * usb 2.0 specification say 50 ms resets on
 				 * root
 				 */
-				wait_ms(50);
+				ehci_fixup(status_reg, &reg);
 				/* terminate the reset */
 				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 				/*
-- 
1.7.6.3

[U-Boot] [PATCH v8 3/4] EHCI: adjust for mx5

[Jana Rapava]

Add macros and structures needed by Efika USB support code.
Move shared offset and bits definitions into common header file.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v1:
   - split into patchset
Changes for v2:
     - make this the third patch in series
     - move all #define's from ehci-mxc.c to ehci-fsl.h
     - rename structures
Changes for v3:
      - rebase on top of u-boot-imx/next
       (no actual changes)
Changes for v4:
       - no changes
       - change changelog versioning from per patchset to per patch
Changes for v5:
	- whitespace changes (no actual changes)

 drivers/usb/host/ehci-mxc.c |   31 +--------
 include/usb/ehci-fsl.h      |  146 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 148 insertions(+), 29 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index fde1f0f..2c1295f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -27,31 +27,6 @@
 #include <usb/ehci.h>
 #include <usb/ehci-core.h>
 
-#define USBCTRL_OTGBASE_OFFSET	0x600
-
-#ifdef CONFIG_MX25
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
-
-#ifdef CONFIG_MX31
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
-
-#define MX31_H2_SIC_SHIFT	21
-#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT		(1 << 16)
-#define MX31_H2_DT_BIT		(1 << 5)
-
-#define MX31_H1_SIC_SHIFT	13
-#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT		(1 << 8)
-#define MX31_H1_DT_BIT		(1 << 4)
-#endif
-
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
@@ -66,11 +41,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		switch (port) {
 		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+			v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT);
 			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
+					<< MXC_OTG_SIC_SHIFT;
 			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
+				v |= MXC_OTG_PM_BIT;
 
 			break;
 		case 1: /* H1 port */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..727134f 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,106 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
+#define USBCTRL_OTGBASE_OFFSET	0x600
+#endif
+
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
+#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
+#define MX25_USB_CTRL_USBTE_BIT	(1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#endif
+
+#ifdef CONFIG_MX31
+#define MX31_H2_SIC_SHIFT	21
+#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT		(1 << 16)
+#define MX31_H2_DT_BIT		(1 << 5)
+
+#define MX31_H1_SIC_SHIFT	13
+#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT		(1 << 8)
+#define MX31_H1_DT_BIT		(1 << 4)
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+/* offset for first USB CTRL register */
+#define MX5_CTRL_REGS_OFFSET	0x800
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX31)
+/* USB_CTRL register bits of interest*/
+#define MXC_OTG_SIC_SHIFT	29
+#define MXC_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
+#define MXC_OTG_WUE		(1 << 27)
+#define MXC_OTG_PM		(1 << 24)
+#endif
+
+#ifdef CONFIG_MX51
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_OTG_ID	0x000
+#define MX51_UH1_ID	0x200
+#define MX51_UH2_ID	0x400
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_PM		(1 << 24)
+#define MX51_H1_ULPI_IE	(1 << 12)
+#define MX51_H1_WUE		(1 << 11)
+#define MX51_H1_PM		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD	(1 << 8)
+#define MX51_EHCI_POWERPINSE	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ	(1 << 0)
+#define MX51_SYSCLOCK_MASK	(~(0xffffffff << 2))
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE	(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE	(1 << 8)
+#define MX51_H2_WUE		(1 << 7)
+#define MX51_H2_PM		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI	(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(0xff << 16)
+#endif
+
+/*
+* ULPI
+*/
+#define ULPI_ID_REGS_COUNT	4
+#define ULPI_TEST_VALUE	0x55
+#define ULPI_TIMEOUT		1000 /* some reasonable value */
+
+/* ULPI viewport control bits */
+#define ULPI_WU	(1 << 31)
+#define ULPI_SS	(1 << 27)
+#define ULPI_RWRUN	(1 << 30)
+#define ULPI_RWCTRL	(1 << 29)
+
+/* ULPI OTG Control bits of interest */
+#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
+#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
+#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
+#define ULPI_OTG_DRV_VBUS	(1 << 5)
+#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
+#define ULPI_OTG_CHRG_VBUS	(1 << 4)
+
+/* ULPI Function Control bits of interest */
+#define ULPI_FC_XCVR_SELECT	(1 << 0)
+#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
+#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
+
 /*
  * USB Registers
  */
@@ -210,7 +310,7 @@ struct usb_ehci {
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
 					   pre-buffer packet tuning */
 	u8	res7[0x8];
-	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
 	u8	res8[0xc];
 	u32	config_flag;	/* 0x180 - Configured Flag Register */
 	u32	portsc;		/* 0x184 - Port status/control */
@@ -242,4 +342,48 @@ struct usb_ehci {
 	u8	res13[0xafc];
 };
 
+struct mx5_usb_control_regs {
+	u32	usbctrl;	/* 0x800 - USB Control */
+	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
+	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
+	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
+	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
+	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
+	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
+};
+
+struct mxc_ulpi_regs {
+	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
+	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
+	u8	product_id_low;		/* 0x02 - Product ID lower byte */
+	u8	product_id_high;	/* 0x03 - Product ID higher byte */
+	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
+	u8	function_ctrl_write;
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
+	u8	iface_ctrl_write;
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
+	u8	otg_ctrl_write;
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
+	u8	usb_ie_rising_write;
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
+	u8	usb_ie_falling_write;
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
+	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
+	u8	debug;			/* 0x15 - Debug */
+	/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
+	u8	scratch_write;
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 Clear*/
+};
+
 #endif /* _EHCI_FSL_H */
-- 
1.7.6.3

[U-Boot] [PATCH v8 4/4] Add USB support for Efika

[Jana Rapava]

This commit adds USB support for EfikaMX and EfikaSB.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
  - changed to proper patch
Changes for v3:
  - merged other USB patches from u-boot-pxa/efikasb
  - offset-based access changed to struct-based access
  - use {clrset,clr,set}bits_le32() calls
  - CodingStyle and naming cleanup
Changes for v4:
   - split into patchset
   - CodingStyle and naming cleanup
   - remove endless loops
   - silence compiler warnings
Changes for v5:
     - change order of arguments in ulpi* functions
     - change type of reg argument
     - rename offset macro
Changes for v6:
      - rebase on top of u-boot-imx/next
      - cleanup of CodingStyle and comments
      - use macro machine_is_efikasb()
      - introduce header file efika.h
Changes for v7:
       - add proper header to efika.h
       - include efika.h into efikamx.c
       - check return values from ulpi_wait()
Changes for v8:
	- change the return value of ulpi_wait()
	- CodingStyle cleanup
	- add proper header to efikamx-usb.c

 board/efikamx/Makefile      |    3 +
 board/efikamx/efika.h       |   30 +++
 board/efikamx/efikamx-usb.c |  420 +++++++++++++++++++++++++++++++++++++++++++
 board/efikamx/efikamx.c     |    3 +
 include/configs/efikamx.h   |   16 ++
 5 files changed, 472 insertions(+), 0 deletions(-)
 create mode 100644 board/efikamx/efika.h
 create mode 100644 board/efikamx/efikamx-usb.c

diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
index ee4a16e..860e4d2 100644
--- a/board/efikamx/Makefile
+++ b/board/efikamx/Makefile
@@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= efikamx.o
+ifdef	CONFIG_CMD_USB
+COBJS	+= efikamx-usb.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/efikamx/efika.h b/board/efikamx/efika.h
new file mode 100644
index 0000000..b3532e2
--- /dev/null
+++ b/board/efikamx/efika.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2011 Jana Rapava <fermata7@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * EHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
new file mode 100644
index 0000000..fc4ebfa
--- /dev/null
+++ b/board/efikamx/efikamx-usb.c
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2011 Jana Rapava <fermata7@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX.
+ */
+#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
+			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
+void setup_iomux_usb(void)
+{
+	/*
+	 * Configure USBH1 pads
+	 */
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
+
+	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
+
+	/*
+	 * Configure USBH1 control pads
+	 */
+
+	/* USB PHY reset */
+	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+	/* USB HUB reset */
+	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+
+	if (machine_is_efikasb()) {
+		/*
+		 * Configure USBH2 pads (used on EfikaSB)
+		 */
+		/* USBH2_DATA */
+		mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
+
+		/* USBH2_CLK */
+		mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
+		/* USBH2_DIR */
+		mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
+		/* USBH2_STP */
+		mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+		/* USBH2_NXT */
+		mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
+	}
+
+	/* WIFI EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
+	/* WIFI RESET */
+	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
+	/* BT EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+}
+
+/*
+ * Enable devices connected to USB BUSes.
+ */
+void efika_usb_enable_devices(void)
+{
+	/* Enable Bluetooth */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+
+	/* Enable WiFi */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	udelay(10000);
+
+	/* Reset the WiFi chip */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB).
+ */
+void efika_usb_hub_reset(void)
+{
+	/* HUB reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB).
+ */
+void efika_usb_phy_reset(void)
+{
+	/* SMSC 3317 PHY reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+}
+
+/*
+ * Configure control registers of the USB controller.
+ */
+void control_regs_setup(struct mx5_usb_control_regs *control)
+{
+	clrsetbits_le32(&control->usbctrl,
+		(MXC_OTG_WUE | MXC_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
+		MX51_H1_PM);
+
+	clrsetbits_le32(&control->phyctrl0,
+			MX51_OTG_OVERCURD,
+			MX51_EHCI_POWERPINSE);
+
+	clrsetbits_le32(&control->phyctrl1,
+			MX51_SYSCLOCK_MASK,
+			MX51_SYSCLOCK_24_MHZ);
+
+	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
+
+	clrsetbits_le32(&control->uh2ctrl,
+			(MX51_H2_ULPI_IE | MX51_H2_WUE),
+			MX51_H2_PM);
+
+	udelay(10000);
+}
+
+#define ULPI_ADDR_SHIFT		16
+#define ulpi_write_mask(value)	((value) & 0xff)
+#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
+
+int ulpi_wait(struct usb_ehci *ehci, u32 ulpi_bit)
+{
+	int timeout = ULPI_TIMEOUT;
+	u32 tmp;
+
+	/* Wait for the ulpi_bit to become zero. */
+	while (--timeout) {
+		tmp = readl(&ehci->ulpi_viewpoint);
+		if (!(tmp & ulpi_bit))
+			break;
+		WATCHDOG_RESET();
+	}
+
+	if (!timeout)
+		return -1;
+	else
+		return tmp;
+}
+
+void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		if (ulpi_wait(ehci, ULPI_WU) == -1)
+			printf("ULPI wakeup timed out\n");
+	}
+
+	writel(ULPI_RWRUN | ULPI_RWCTRL |
+		reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
+		&ehci->ulpi_viewpoint);
+	if (ulpi_wait(ehci, ULPI_RWRUN) == -1)
+		printf("ULPI write timed out\n");
+}
+
+u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
+{
+	u32 tmp;
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		if (ulpi_wait(ehci, ULPI_WU) == -1)
+			printf("ULPI wakeup timed out\n");
+	}
+
+	writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
+	tmp = ulpi_wait(ehci, ULPI_RWRUN);
+	if (tmp == -1) {
+		printf("ULPI read timed out\n");
+		return 0;
+	}
+	return ulpi_read_mask(tmp);
+}
+
+void ulpi_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	u32 tmp = 0;
+	int reg, i;
+
+	/* get ID from ULPI immediate registers */
+	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
+		tmp |= ulpi_read(ehci, reg) << (reg * 8);
+	/* split into vendor and product ID */
+	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
+
+	/* ULPI check integrity */
+	for (i = 0; i < 2; i++) {
+		ulpi_write(ehci, (u32)&ulpi->scratch_write,
+			ULPI_TEST_VALUE << i);
+		tmp = ulpi_read(ehci, (u32)&ulpi->scratch_write);
+
+		if (tmp != (ULPI_TEST_VALUE << i)) {
+			printf("ULPI integrity check failed\n");
+			return;
+		}
+	}
+
+	/* ULPI set flags */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write,
+		ULPI_OTG_EXT_VBUS_IND |
+		ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN);
+	ulpi_write(ehci, (u32)&ulpi->function_ctrl_write,
+		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL |
+		ULPI_FC_SUSPENDM_PWRED);
+	ulpi_write(ehci, (u32)&ulpi->iface_ctrl_write, 0);
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set,
+		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT);
+
+	/*
+	 * NOTE: This violates USB specification, but otherwise, USB on Efika
+	 * doesn't charge VBUS and as a result, USB doesn't work.
+	 */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS);
+}
+
+/*
+ * Solve the VBUS reset problem on Efika
+ * by setting the CHRG_VBUS bit in the reset.
+ */
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		MX51_REGISTER_LAYOUT_LENGTH);
+	struct mxc_ulpi_regs *ulpi = (struct mxc_ulpi_regs *)0;
+
+	u32 tmp = ulpi_read(ehci, (u32)&ulpi->otg_ctrl_write);
+	tmp |= ULPI_OTG_CHRG_VBUS;
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write, tmp);
+
+	/* USB 2.0 specification say 50 ms resets on root. */
+	wait_ms(50);
+
+	/* Now terminate the reset. */
+	*reg_ref = ehci_readl(status_reg);
+	*reg_ref |= EHCI_PS_PE;
+}
+
+void ehci0_init(struct usb_ehci *ehci)
+{
+	writel(MX51_16BIT_UTMI, &ehci->portsc);
+}
+
+void ehci1_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	udelay(10000);
+
+	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
+	udelay(10000);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+void ehci2_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+	struct mx5_usb_control_regs *mx5_usb_control_regs;
+	struct mxc_ulpi_regs *ulpi;
+
+	mx5_usb_control_regs = (struct mx5_usb_control_regs *)(OTG_BASE_ADDR +
+		 MX5_CTRL_REGS_OFFSET);
+	control_regs_setup(mx5_usb_control_regs);
+	ulpi = (struct mxc_ulpi_regs *)0;
+
+	/* Init EHCI core */
+	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+	setbits_le32(&ehci->control, USB_EN);
+	
+	/* Init iMX51 EHCI */
+	efika_usb_phy_reset();
+	efika_usb_hub_reset();
+	efika_usb_enable_devices();
+
+	switch (CONFIG_MXC_USB_PORT) {
+	case 0:
+		ehci0_init(ehci);
+		break;
+	case 1:
+		ehci1_init(ehci, ulpi);
+		break;
+	case 2:
+		if (machine_is_efikasb())
+			ehci2_init(ehci, ulpi);
+		break;
+	};
+
+	/* EfikaMX USB has issues ... */
+	udelay(10000);
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 0c4e24b..8e9b42b 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -37,6 +37,8 @@
 #include <fsl_pmic.h>
 #include <mc13892.h>
 
+#include "efika.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -678,6 +680,7 @@ int board_late_init(void)
 
 	setup_iomux_led();
 	setup_iomux_ata();
+	setup_iomux_usb();
 
 	efikamx_toggle_led(EFIKAMX_LED_BLUE);
 
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index 54f48e4..010a16a 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -44,6 +44,10 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
+#define	CONFIG_L2_OFF
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
 /*
  * Bootloader Components Configuration
  */
@@ -172,6 +176,18 @@
 #endif
 
 /*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#endif /* CONFIG_CMD_USB */
+
+/*
  * Filesystems
  */
 #ifdef CONFIG_CMD_FAT
-- 
1.7.6.3

[U-Boot] [PATCH v8 4/4] Add USB support for Efika

[Marek Vasut]

> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>? ?  - changed to proper patch
> Changes for v3:
>? ?  - merged other USB patches from u-boot-pxa/efikasb
>? ?  - offset-based access changed to struct-based access
>? ?  - use {clrset,clr,set}bits_le32() calls
>? ?  - CodingStyle and naming cleanup
> Changes for v4:
>? ? ?  - split into patchset
>? ? ?  - CodingStyle and naming cleanup
>? ? ?  - remove endless loops
>? ? ?  - silence compiler warnings
> Changes for v5:
>? ? ? ? ?  - change order of arguments in ulpi* functions
>? ? ? ? ?  - change type of reg argument
>? ? ? ? ?  - rename offset macro
> Changes for v6:
>? ? ? ? ? ?  - rebase on top of u-boot-imx/next
>? ? ? ? ? ?  - cleanup of CodingStyle and comments
>? ? ? ? ? ?  - use macro machine_is_efikasb()
>? ? ? ? ? ?  - introduce header file efika.h
> Changes for v7:
>? ? ? ? ? ? ?  - add proper header to efika.h
>? ? ? ? ? ? ?  - include efika.h into efikamx.c
>? ? ? ? ? ? ?  - check return values from ulpi_wait()
> Changes for v8:
> ??? - change the return value of ulpi_wait()
> ??? - CodingStyle cleanup
> ??? - add proper header to efikamx-usb.c

Dear Jana Rapava,

[...]

> +int ulpi_wait(struct usb_ehci *ehci, u32 ulpi_bit)
> +{
> +??? int timeout = ULPI_TIMEOUT;
> +??? u32 tmp;
> +
> +??? /* Wait for the ulpi_bit to become zero. */
> +??? while (--timeout) {
> +??? ??? tmp = readl(&ehci->ulpi_viewpoint);
> +??? ??? if (!(tmp & ulpi_bit))
> +??? ??? ??? break;
> +??? ??? WATCHDOG_RESET();
> +??? }
> +
> +??? if (!timeout)
> +??? ??? return -1;
> +??? else
> +??? ??? return tmp;
> +}

Won't 'return !timeout;' be enough?

Also, can you change 'ulpi_bit' to 'ulpi_mask'? That seems more appropriate.

Maybe this can be even changed to ulpi_wait(ehci, value_to_be_written, bit_to_be_polled), then you won't need those writel()s before every write to ulpi anymore.

> +
> +void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
> +{
> +??? if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +??? ??? writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +??? ??? if (ulpi_wait(ehci, ULPI_WU) == -1)
> +??? ??? ??? printf("ULPI wakeup timed out\n");
> +??? }
> +
> +??? writel(ULPI_RWRUN | ULPI_RWCTRL |
> +??? ??? reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
> +??? ??? &ehci->ulpi_viewpoint);
> +??? if (ulpi_wait(ehci, ULPI_RWRUN) == -1)
> +??? ??? printf("ULPI write timed out\n");
> +}


aha here - if(ulpi_wait(ehci, ULPI_RWRUN | ULPI_RWCTRL ..., uLPI_RWRUN))...

> +
> +u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
> +{
> +??? u32 tmp;
> +??? if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +??? ??? writel(ULPI_WU, &ehci->ulpi_viewpoint);
> +??? ??? if (ulpi_wait(ehci, ULPI_WU) == -1)
> +??? ??? ??? printf("ULPI wakeup timed out\n");
> +??? }
> +
> +??? writel(ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
> +??? tmp = ulpi_wait(ehci, ULPI_RWRUN);
> +??? if (tmp == -1) {
> +??? ??? printf("ULPI read timed out\n");
> +??? ??? return 0;
> +??? }
> +??? return ulpi_read_mask(tmp);
> +}
> +
> +void ulpi_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
> +{
> +??? u32 tmp = 0;
> +??? int reg, i;
> +
> +??? /* get ID from ULPI immediate registers */
> +??? for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
> +??? ??? tmp |= ulpi_read(ehci, reg) << (reg * 8);

Still (three revs already) no newline here!!

> +??? /* split into vendor and product ID */
> +??? debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);

cheers

[U-Boot] [PATCH v8 4/4] Add USB support for Efika

[Jana Rapava]

2011/9/28 Marek Vasut <marek.vasut.n900@gmail.com>

> > +    if (!timeout)
> > +        return -1;
> > +    else
> > +        return tmp;
> > +}
>
> Won't 'return !timeout;' be enough?
>
> > +    tmp = ulpi_wait(ehci, ULPI_RWRUN);
> +    if (tmp == -1) {
> +        printf("ULPI read timed out\n");
> +        return 0;
> +    }
> +    return ulpi_read_mask(tmp);
> +}

Here in ulpi_read() I need to store and return value which was read in
ulpi_wait(). What is the proper way to do this, If ulpi_wait() should return
!timeout ?


> Also, can you change 'ulpi_bit' to 'ulpi_mask'? That seems more
> appropriate.
>
> Maybe this can be even changed to ulpi_wait(ehci, value_to_be_written,
> bit_to_be_polled), then you won't need those writel()s before every write to
> ulpi anymore.
>

Ok.


> cheers
>

[U-Boot] [PATCH v8 4/4] Add USB support for Efika

[Marek Vasut]

On Wednesday, September 28, 2011 08:12:08 PM Jana Rapava wrote:
> 2011/9/28 Marek Vasut <marek.vasut.n900@gmail.com>
> 
> > > +    if (!timeout)
> > > +        return -1;
> > > +    else
> > > +        return tmp;
> > > +}
> > 
> > Won't 'return !timeout;' be enough?
> > 
> > > +    tmp = ulpi_wait(ehci, ULPI_RWRUN);
> > 
> > +    if (tmp == -1) {
> > +        printf("ULPI read timed out\n");
> > +        return 0;
> > +    }
> > +    return ulpi_read_mask(tmp);
> > +}
> 
> Here in ulpi_read() I need to store and return value which was read in
> ulpi_wait(). What is the proper way to do this, If ulpi_wait() should
> return !timeout ?

You can read again ... it's more systematic. Anyway ... use the approach below, 
it seems better.

> 
> > Also, can you change 'ulpi_bit' to 'ulpi_mask'? That seems more
> > appropriate.
> > 
> > Maybe this can be even changed to ulpi_wait(ehci, value_to_be_written,
> > bit_to_be_polled), then you won't need those writel()s before every write
> > to ulpi anymore.
> 
> Ok.
> 
> > cheers

[U-Boot] [PATCH v8 4/4] Add USB support for Efika

[Wolfgang Denk]

Dear Jana Rapava,

In message <1317222457-18412-1-git-send-email-fermata7@gmail.com> you wrote:
> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>   - changed to proper patch
> Changes for v3:
>   - merged other USB patches from u-boot-pxa/efikasb
>   - offset-based access changed to struct-based access
>   - use {clrset,clr,set}bits_le32() calls
>   - CodingStyle and naming cleanup
> Changes for v4:
>    - split into patchset
>    - CodingStyle and naming cleanup
>    - remove endless loops
>    - silence compiler warnings
> Changes for v5:
>      - change order of arguments in ulpi* functions
>      - change type of reg argument
>      - rename offset macro
> Changes for v6:
>       - rebase on top of u-boot-imx/next
>       - cleanup of CodingStyle and comments
>       - use macro machine_is_efikasb()
>       - introduce header file efika.h
> Changes for v7:
>        - add proper header to efika.h
>        - include efika.h into efikamx.c
>        - check return values from ulpi_wait()
> Changes for v8:
> 	- change the return value of ulpi_wait()
> 	- CodingStyle cleanup
> 	- add proper header to efikamx-usb.c
> 
>  board/efikamx/Makefile      |    3 +
>  board/efikamx/efika.h       |   30 +++
>  board/efikamx/efikamx-usb.c |  420 +++++++++++++++++++++++++++++++++++++++++++
>  board/efikamx/efikamx.c     |    3 +
>  include/configs/efikamx.h   |   16 ++
>  5 files changed, 472 insertions(+), 0 deletions(-)
>  create mode 100644 board/efikamx/efika.h
>  create mode 100644 board/efikamx/efikamx-usb.c

Checkpatch says:

total: 1 errors, 0 warnings, 502 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Every little picofarad has a nanohenry all its own.      - Don Vonada

[U-Boot] [PATCH v8 4/4] Add USB support for Efika

[Jana Rapava]

2011/10/6 Wolfgang Denk <wd@denx.de>

>
> Checkpatch says:
>
> total: 1 errors, 0 warnings, 502 lines checked
>
> Please clean up and resubmit.  Thanks.
>
>
Last version of this patch is here:
http://lists.denx.de/pipermail/u-boot/2011-September/102803.html
(sorry for breaking the thread but I messed up some In-Reply-To: headers).
On the last version checkpatch says only two warnings, both are about
including files not from <linux/*> and doesn't make sense in this case.
Regards,
Jana Rapava

[U-Boot] [PATCH v8 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

> Add callback to ehci_hcd.c to prepare
> for solving the problem with VBUS reset on Efika.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> 
> Acked-by: Marek Vasut <marek.vasut@gmail.com>
> ---
> Changes for v1:
>? ? ?  - split into patchset
>? ? ?  - add callback ehci_fixup
> Changes for v2:
>? ? ? ? ?  - make this the second patch in series
>? ? ? ? ?  - add comment to alias ehci_fixup
>? ? ? ? ?  - no actual changes
> Changes for v3:
>? ? ? ? ? ?  - no actual changes
>? ? ? ? ? ?  - make the comment a sentence
>? ? ? ? ? ?  - rebase patch on top of u-boot-imx/next
> Changes for v4:
>? ? ? ? ? ? ?  - no actual changes
>? ? ? ? ? ? ?  - change the versioning of changelog
>? ? ? ? ? ? ?  from per patchset to per patch
>? ? ? ? ? ? ?  - fix the appearance of comment
> Changes for v5:
> ??? - no actual changes
> ??? - reword the comment
> 
>?  drivers/usb/host/ehci-hcd.c |? ?  14 +++++++++++++-
>?  1 files changed, 13 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index bdadd46..fb64f23 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -536,6 +536,18 @@ static inline int min3(int a, int b, int c)
>?  ??? return a;
>?  }
>?  
> +inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +{
> +??? wait_ms(50);
> +}
> +
> +/*
> + * This is an alias to __ehci_fixup

__ehci_fixup() and why do you break the line there so early?

> + * unless user provides other definition of ehci_fixup function.
> + */
> +void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +???  __attribute__((weak, alias("__ehci_fixup")));
> +
>?  int
>?  ehci_submit_root(struct usb_device *dev, unsigned long pipe, void
> *buffer, ??? ???  int length, struct devrequest *req)
> @@ -709,7 +721,7 @@ ehci_submit_root(struct usb_device *dev, unsigned
> long pipe, void *buffer, ??? ??? ??? ???  * usb 2.0 specification say 50 ms resets on
>?  ??? ??? ??? ???  * root
>?  ??? ??? ??? ???  */
> -??? ??? ??? ??? wait_ms(50);
> +??? ??? ??? ??? ehci_fixup(status_reg, &reg);
>?  ??? ??? ??? ??? /* terminate the reset */
>?  ??? ??? ??? ??? ehci_writel(status_reg, reg & ~EHCI_PS_PR);
>?  ??? ??? ??? ??? /*
> -- 
> 1.7.6.3
> 

[U-Boot] [PATCH v5 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Fabio Estevam]

From: festevam@gmail.com (Fabio Estevam)

Move ehci.h and ehci-core.h to include/usb directory.

Cc: Remy Bohmer <linux@bohmer.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes for v2:
      - changed to proper patch
Changes for v3:
      - merged other USB patches from u-boot-pxa/efikasb
      - offset-based access changed to struct-based access
      - use {clrset,clr,set}bits_le32() calls
      - CodingStyle and naming cleanup
Changes for v4:
       - split into patchset
       - move ehci.h and ehci-core.h into /include/usb/
Changes for v5:
	- reorder patches in patchset
	- use patch from Fabio Estevam

 drivers/usb/host/ehci-core.h     |   29 ------
 drivers/usb/host/ehci-fsl.c      |    4 +-
 drivers/usb/host/ehci-hcd.c      |    2 +-
 drivers/usb/host/ehci-ixp4xx.c   |    4 +-
 drivers/usb/host/ehci-kirkwood.c |    4 +-
 drivers/usb/host/ehci-mpc512x.c  |    4 +-
 drivers/usb/host/ehci-mxc.c      |    4 +-
 drivers/usb/host/ehci-pci.c      |    4 +-
 drivers/usb/host/ehci-ppc4xx.c   |    4 +-
 drivers/usb/host/ehci-vct.c      |    4 +-
 drivers/usb/host/ehci.h          |  203 --------------------------------------
 include/usb/ehci-core.h          |   29 ++++++
 include/usb/ehci.h               |  203 ++++++++++++++++++++++++++++++++++++++
 13 files changed, 249 insertions(+), 249 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-core.h
 delete mode 100644 drivers/usb/host/ehci.h
 create mode 100644 include/usb/ehci-core.h
 create mode 100644 include/usb/ehci.h

diff --git a/drivers/usb/host/ehci-core.h b/drivers/usb/host/ehci-core.h
deleted file mode 100644
index 39e5c5e..0000000
--- a/drivers/usb/host/ehci-core.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6e0043a..19b97ee 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,8 +27,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..bdadd46 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -27,7 +27,7 @@
 #include <malloc.h>
 #include <watchdog.h>
 
-#include "ehci.h"
+#include <usb/ehci.h>
 
 int rootdev;
 struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index b8f15ae..d15237b 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc6..ab75acd 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -25,8 +25,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <usb.h>
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index d360108..8d2c93b 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 static void fsl_setup_phy(volatile struct ehci_hcor *);
 static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..fde1f0f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -24,8 +24,8 @@
 #include <usb/ehci-fsl.h>
 #include <errno.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 020ab11..e1f84d9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,8 +22,8 @@
 #include <pci.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 1179919..1a1fae1 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c
index 3063dd1..e73cf38 100644
--- a/drivers/usb/host/ehci-vct.c
+++ b/drivers/usb/host/ehci-vct.c
@@ -20,8 +20,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
 
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
deleted file mode 100644
index 3d0ad0c..0000000
--- a/drivers/usb/host/ehci.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
-	uint32_t cr_capbase;
-#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
-#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
-#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed, aligned(4)));
-
-struct ehci_hcor {
-	uint32_t or_usbcmd;
-#define CMD_PARK	(1 << 11)		/* enable "park" */
-#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
-#define CMD_ASE		(1 << 5)		/* async schedule enable */
-#define CMD_LRESET	(1 << 7)		/* partial reset */
-#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
-#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
-#define CMD_RESET	(1 << 1)		/* reset HC not bus */
-#define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
-#define	STD_ASS		(1 << 15)
-#define STS_HALT	(1 << 12)
-	uint32_t or_usbintr;
-#define INTR_UE         (1 << 0)                /* USB interrupt enable */
-#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
-#define INTR_PCE        (1 << 2)                /* Port change detect enable */
-#define INTR_SEE        (1 << 4)                /* system error enable */
-#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
-#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
-} __attribute__ ((packed, aligned(4)));
-
-#define USBMODE		0x68		/* USB Device mode */
-#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
-#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
-#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
-					cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x)		be32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
-#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
-	/* this part defined by EHCI spec */
-	uint32_t qt_next;		/* see EHCI 3.5.1 */
-#define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
-	uint32_t qt_token;		/* see EHCI 3.5.3 */
-	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
-	uint32_t qt_buffer_hi[5];	/* Appendix B */
-	/* pad struct for 32 byte alignment */
-	uint32_t unused[3];
-};
-
-/* Queue Head (QH). */
-struct QH {
-	uint32_t qh_link;
-#define	QH_LINK_TERMINATE	1
-#define	QH_LINK_TYPE_ITD	0
-#define	QH_LINK_TYPE_QH		2
-#define	QH_LINK_TYPE_SITD	4
-#define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
diff --git a/include/usb/ehci-core.h b/include/usb/ehci-core.h
new file mode 100644
index 0000000..39e5c5e
--- /dev/null
+++ b/include/usb/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
new file mode 100644
index 0000000..3d0ad0c
--- /dev/null
+++ b/include/usb/ehci.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed, aligned(4)));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed, aligned(4)));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+
+#endif /* USB_EHCI_H */
-- 
1.7.1

[U-Boot] [PATCH v5 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Fabio Estevam]

Jana,

On Tue, Sep 27, 2011 at 8:07 AM, Fabio Estevam <fermata7@gmail.com> wrote:

This is even worse: you sent an email with my name. fermata7 at gmail.com
is your email address, not mine.

You should not change your From field of your gitconfig.

> From: festevam at gmail.com (Fabio Estevam)

The only required change is here.

From: Fabio Estevam <festevam@gmail.com>

[U-Boot] [PATCH v5 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

2011/9/27 Fabio Estevam <festevam@gmail.com>

> Jana,
>
> On Tue, Sep 27, 2011 at 8:07 AM, Fabio Estevam <fermata7@gmail.com> wrote:
>
> This is even worse: you sent an email with my name. fermata7 at gmail.com
> is your email address, not mine.
>

Now I really don't understand where it went wrong. My git send-email log
says "From: Fabio Estevam <festevam@gmail.com>" and I left your e-mail
address in the body of patch too. If you could say me what I should do in
some other way I would be thankful, because now I really don't know.

You should not change your From field of your gitconfig.
>

I only wrote your e-mail address into the From: field, I didn't change my
gitconfig at all.

[U-Boot] [PATCH v6 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

From: Fabio Estevam <festevam@gmail.com>

Move ehci.h and ehci-core.h to include/usb directory.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
---
Changes for v5:
	- reorder patches in patchset
	- use patch from Fabio Estevam
Changes for v6:
	- fix From field

 drivers/usb/host/ehci-core.h     |   29 ------
 drivers/usb/host/ehci-fsl.c      |    4 +-
 drivers/usb/host/ehci-hcd.c      |    2 +-
 drivers/usb/host/ehci-ixp4xx.c   |    4 +-
 drivers/usb/host/ehci-kirkwood.c |    4 +-
 drivers/usb/host/ehci-mpc512x.c  |    4 +-
 drivers/usb/host/ehci-mxc.c      |    4 +-
 drivers/usb/host/ehci-pci.c      |    4 +-
 drivers/usb/host/ehci-ppc4xx.c   |    4 +-
 drivers/usb/host/ehci-vct.c      |    4 +-
 drivers/usb/host/ehci.h          |  203 --------------------------------------
 include/usb/ehci-core.h          |   29 ++++++
 include/usb/ehci.h               |  203 ++++++++++++++++++++++++++++++++++++++
 13 files changed, 249 insertions(+), 249 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-core.h
 delete mode 100644 drivers/usb/host/ehci.h
 create mode 100644 include/usb/ehci-core.h
 create mode 100644 include/usb/ehci.h

diff --git a/drivers/usb/host/ehci-core.h b/drivers/usb/host/ehci-core.h
deleted file mode 100644
index 39e5c5e..0000000
--- a/drivers/usb/host/ehci-core.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6e0043a..19b97ee 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,8 +27,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..bdadd46 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -27,7 +27,7 @@
 #include <malloc.h>
 #include <watchdog.h>
 
-#include "ehci.h"
+#include <usb/ehci.h>
 
 int rootdev;
 struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index b8f15ae..d15237b 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc6..ab75acd 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -25,8 +25,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <usb.h>
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index d360108..8d2c93b 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 static void fsl_setup_phy(volatile struct ehci_hcor *);
 static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..fde1f0f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -24,8 +24,8 @@
 #include <usb/ehci-fsl.h>
 #include <errno.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 020ab11..e1f84d9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,8 +22,8 @@
 #include <pci.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 1179919..1a1fae1 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c
index 3063dd1..e73cf38 100644
--- a/drivers/usb/host/ehci-vct.c
+++ b/drivers/usb/host/ehci-vct.c
@@ -20,8 +20,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
 
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
deleted file mode 100644
index 3d0ad0c..0000000
--- a/drivers/usb/host/ehci.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
-	uint32_t cr_capbase;
-#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
-#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
-#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed, aligned(4)));
-
-struct ehci_hcor {
-	uint32_t or_usbcmd;
-#define CMD_PARK	(1 << 11)		/* enable "park" */
-#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
-#define CMD_ASE		(1 << 5)		/* async schedule enable */
-#define CMD_LRESET	(1 << 7)		/* partial reset */
-#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
-#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
-#define CMD_RESET	(1 << 1)		/* reset HC not bus */
-#define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
-#define	STD_ASS		(1 << 15)
-#define STS_HALT	(1 << 12)
-	uint32_t or_usbintr;
-#define INTR_UE         (1 << 0)                /* USB interrupt enable */
-#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
-#define INTR_PCE        (1 << 2)                /* Port change detect enable */
-#define INTR_SEE        (1 << 4)                /* system error enable */
-#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
-#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
-} __attribute__ ((packed, aligned(4)));
-
-#define USBMODE		0x68		/* USB Device mode */
-#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
-#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
-#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
-					cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x)		be32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
-#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
-	/* this part defined by EHCI spec */
-	uint32_t qt_next;		/* see EHCI 3.5.1 */
-#define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
-	uint32_t qt_token;		/* see EHCI 3.5.3 */
-	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
-	uint32_t qt_buffer_hi[5];	/* Appendix B */
-	/* pad struct for 32 byte alignment */
-	uint32_t unused[3];
-};
-
-/* Queue Head (QH). */
-struct QH {
-	uint32_t qh_link;
-#define	QH_LINK_TERMINATE	1
-#define	QH_LINK_TYPE_ITD	0
-#define	QH_LINK_TYPE_QH		2
-#define	QH_LINK_TYPE_SITD	4
-#define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
diff --git a/include/usb/ehci-core.h b/include/usb/ehci-core.h
new file mode 100644
index 0000000..39e5c5e
--- /dev/null
+++ b/include/usb/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
new file mode 100644
index 0000000..3d0ad0c
--- /dev/null
+++ b/include/usb/ehci.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed, aligned(4)));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed, aligned(4)));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+
+#endif /* USB_EHCI_H */
-- 
1.7.1

[U-Boot] [PATCH v7 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

From: Fabio Estevam <festevam@gmail.com>

Move ehci.h and ehci-core.h to include/usb directory.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
---
Changes for v1:
	- reorder patches in patchset
	- use patch from Fabio Estevam
Changes for v2:
	- fix From field
	- rebase on top of u-boot-imx/next(no actual changes)
Changes for v3:
	- change versioning in changelog from per patchset to per patch
	- no actual changes

 drivers/usb/host/ehci-core.h     |   29 ------
 drivers/usb/host/ehci-fsl.c      |    4 +-
 drivers/usb/host/ehci-hcd.c      |    2 +-
 drivers/usb/host/ehci-ixp4xx.c   |    4 +-
 drivers/usb/host/ehci-kirkwood.c |    4 +-
 drivers/usb/host/ehci-mpc512x.c  |    4 +-
 drivers/usb/host/ehci-mxc.c      |    4 +-
 drivers/usb/host/ehci-pci.c      |    4 +-
 drivers/usb/host/ehci-ppc4xx.c   |    4 +-
 drivers/usb/host/ehci-vct.c      |    4 +-
 drivers/usb/host/ehci.h          |  203 --------------------------------------
 include/usb/ehci-core.h          |   29 ++++++
 include/usb/ehci.h               |  203 ++++++++++++++++++++++++++++++++++++++
 13 files changed, 249 insertions(+), 249 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-core.h
 delete mode 100644 drivers/usb/host/ehci.h
 create mode 100644 include/usb/ehci-core.h
 create mode 100644 include/usb/ehci.h

diff --git a/drivers/usb/host/ehci-core.h b/drivers/usb/host/ehci-core.h
deleted file mode 100644
index 39e5c5e..0000000
--- a/drivers/usb/host/ehci-core.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6e0043a..19b97ee 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,8 +27,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..bdadd46 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -27,7 +27,7 @@
 #include <malloc.h>
 #include <watchdog.h>
 
-#include "ehci.h"
+#include <usb/ehci.h>
 
 int rootdev;
 struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index b8f15ae..d15237b 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc6..ab75acd 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -25,8 +25,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <usb.h>
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index d360108..8d2c93b 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 static void fsl_setup_phy(volatile struct ehci_hcor *);
 static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..fde1f0f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -24,8 +24,8 @@
 #include <usb/ehci-fsl.h>
 #include <errno.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 020ab11..e1f84d9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,8 +22,8 @@
 #include <pci.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 1179919..1a1fae1 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c
index 3063dd1..e73cf38 100644
--- a/drivers/usb/host/ehci-vct.c
+++ b/drivers/usb/host/ehci-vct.c
@@ -20,8 +20,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
 
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
deleted file mode 100644
index 3d0ad0c..0000000
--- a/drivers/usb/host/ehci.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
-	uint32_t cr_capbase;
-#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
-#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
-#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed, aligned(4)));
-
-struct ehci_hcor {
-	uint32_t or_usbcmd;
-#define CMD_PARK	(1 << 11)		/* enable "park" */
-#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
-#define CMD_ASE		(1 << 5)		/* async schedule enable */
-#define CMD_LRESET	(1 << 7)		/* partial reset */
-#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
-#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
-#define CMD_RESET	(1 << 1)		/* reset HC not bus */
-#define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
-#define	STD_ASS		(1 << 15)
-#define STS_HALT	(1 << 12)
-	uint32_t or_usbintr;
-#define INTR_UE         (1 << 0)                /* USB interrupt enable */
-#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
-#define INTR_PCE        (1 << 2)                /* Port change detect enable */
-#define INTR_SEE        (1 << 4)                /* system error enable */
-#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
-#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
-} __attribute__ ((packed, aligned(4)));
-
-#define USBMODE		0x68		/* USB Device mode */
-#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
-#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
-#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
-					cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x)		be32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
-#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
-	/* this part defined by EHCI spec */
-	uint32_t qt_next;		/* see EHCI 3.5.1 */
-#define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
-	uint32_t qt_token;		/* see EHCI 3.5.3 */
-	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
-	uint32_t qt_buffer_hi[5];	/* Appendix B */
-	/* pad struct for 32 byte alignment */
-	uint32_t unused[3];
-};
-
-/* Queue Head (QH). */
-struct QH {
-	uint32_t qh_link;
-#define	QH_LINK_TERMINATE	1
-#define	QH_LINK_TYPE_ITD	0
-#define	QH_LINK_TYPE_QH		2
-#define	QH_LINK_TYPE_SITD	4
-#define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
diff --git a/include/usb/ehci-core.h b/include/usb/ehci-core.h
new file mode 100644
index 0000000..39e5c5e
--- /dev/null
+++ b/include/usb/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
new file mode 100644
index 0000000..3d0ad0c
--- /dev/null
+++ b/include/usb/ehci.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed, aligned(4)));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed, aligned(4)));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+
+#endif /* USB_EHCI_H */
-- 
1.7.1

[U-Boot] [PATCH v8 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

From: Fabio Estevam <festevam@gmail.com>

Move ehci.h and ehci-core.h to include/usb directory.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
---
Changes for v1:
	- reorder patches in patchset
	- use patch from Fabio Estevam
Changes for v2:
	- fix From field
	- rebase on top of u-boot-imx/next(no actual changes)
Changes for v3:
	- change versioning in changelog from per patchset to per patch
	- no actual changes
Changes for v4:
	- no changes

 drivers/usb/host/ehci-core.h     |   29 ------
 drivers/usb/host/ehci-fsl.c      |    4 +-
 drivers/usb/host/ehci-hcd.c      |    2 +-
 drivers/usb/host/ehci-ixp4xx.c   |    4 +-
 drivers/usb/host/ehci-kirkwood.c |    4 +-
 drivers/usb/host/ehci-mpc512x.c  |    4 +-
 drivers/usb/host/ehci-mxc.c      |    4 +-
 drivers/usb/host/ehci-pci.c      |    4 +-
 drivers/usb/host/ehci-ppc4xx.c   |    4 +-
 drivers/usb/host/ehci-vct.c      |    4 +-
 drivers/usb/host/ehci.h          |  203 --------------------------------------
 include/usb/ehci-core.h          |   29 ++++++
 include/usb/ehci.h               |  203 ++++++++++++++++++++++++++++++++++++++
 13 files changed, 249 insertions(+), 249 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-core.h
 delete mode 100644 drivers/usb/host/ehci.h
 create mode 100644 include/usb/ehci-core.h
 create mode 100644 include/usb/ehci.h

diff --git a/drivers/usb/host/ehci-core.h b/drivers/usb/host/ehci-core.h
deleted file mode 100644
index 39e5c5e..0000000
--- a/drivers/usb/host/ehci-core.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6e0043a..19b97ee 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,8 +27,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..bdadd46 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -27,7 +27,7 @@
 #include <malloc.h>
 #include <watchdog.h>
 
-#include "ehci.h"
+#include <usb/ehci.h>
 
 int rootdev;
 struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index b8f15ae..d15237b 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc6..ab75acd 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -25,8 +25,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <usb.h>
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index d360108..8d2c93b 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 static void fsl_setup_phy(volatile struct ehci_hcor *);
 static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..fde1f0f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -24,8 +24,8 @@
 #include <usb/ehci-fsl.h>
 #include <errno.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 020ab11..e1f84d9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,8 +22,8 @@
 #include <pci.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 1179919..1a1fae1 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c
index 3063dd1..e73cf38 100644
--- a/drivers/usb/host/ehci-vct.c
+++ b/drivers/usb/host/ehci-vct.c
@@ -20,8 +20,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
 
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
deleted file mode 100644
index 3d0ad0c..0000000
--- a/drivers/usb/host/ehci.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
-	uint32_t cr_capbase;
-#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
-#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
-#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed, aligned(4)));
-
-struct ehci_hcor {
-	uint32_t or_usbcmd;
-#define CMD_PARK	(1 << 11)		/* enable "park" */
-#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
-#define CMD_ASE		(1 << 5)		/* async schedule enable */
-#define CMD_LRESET	(1 << 7)		/* partial reset */
-#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
-#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
-#define CMD_RESET	(1 << 1)		/* reset HC not bus */
-#define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
-#define	STD_ASS		(1 << 15)
-#define STS_HALT	(1 << 12)
-	uint32_t or_usbintr;
-#define INTR_UE         (1 << 0)                /* USB interrupt enable */
-#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
-#define INTR_PCE        (1 << 2)                /* Port change detect enable */
-#define INTR_SEE        (1 << 4)                /* system error enable */
-#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
-#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
-} __attribute__ ((packed, aligned(4)));
-
-#define USBMODE		0x68		/* USB Device mode */
-#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
-#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
-#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
-					cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x)		be32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
-#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
-	/* this part defined by EHCI spec */
-	uint32_t qt_next;		/* see EHCI 3.5.1 */
-#define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
-	uint32_t qt_token;		/* see EHCI 3.5.3 */
-	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
-	uint32_t qt_buffer_hi[5];	/* Appendix B */
-	/* pad struct for 32 byte alignment */
-	uint32_t unused[3];
-};
-
-/* Queue Head (QH). */
-struct QH {
-	uint32_t qh_link;
-#define	QH_LINK_TERMINATE	1
-#define	QH_LINK_TYPE_ITD	0
-#define	QH_LINK_TYPE_QH		2
-#define	QH_LINK_TYPE_SITD	4
-#define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
diff --git a/include/usb/ehci-core.h b/include/usb/ehci-core.h
new file mode 100644
index 0000000..39e5c5e
--- /dev/null
+++ b/include/usb/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
new file mode 100644
index 0000000..3d0ad0c
--- /dev/null
+++ b/include/usb/ehci.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed, aligned(4)));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed, aligned(4)));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+
+#endif /* USB_EHCI_H */
-- 
1.7.1

[U-Boot] [PATCH v9 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

From: Fabio Estevam <festevam@gmail.com>

Move ehci.h and ehci-core.h to include/usb directory.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
---
Changes for v1:
	- reorder patches in patchset
	- use patch from Fabio Estevam
Changes for v2:
	- fix From field
	- rebase on top of u-boot-imx/next(no actual changes)
Changes for v3:
	- change versioning in changelog from per patchset to per patch
	- no actual changes
Changes for v4:
	- no changes
Changes for v5:
	- no changes

 drivers/usb/host/ehci-core.h     |   29 ------
 drivers/usb/host/ehci-fsl.c      |    4 +-
 drivers/usb/host/ehci-hcd.c      |    2 +-
 drivers/usb/host/ehci-ixp4xx.c   |    4 +-
 drivers/usb/host/ehci-kirkwood.c |    4 +-
 drivers/usb/host/ehci-mpc512x.c  |    4 +-
 drivers/usb/host/ehci-mxc.c      |    4 +-
 drivers/usb/host/ehci-pci.c      |    4 +-
 drivers/usb/host/ehci-ppc4xx.c   |    4 +-
 drivers/usb/host/ehci-vct.c      |    4 +-
 drivers/usb/host/ehci.h          |  203 --------------------------------------
 include/usb/ehci-core.h          |   29 ++++++
 include/usb/ehci.h               |  203 ++++++++++++++++++++++++++++++++++++++
 13 files changed, 249 insertions(+), 249 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-core.h
 delete mode 100644 drivers/usb/host/ehci.h
 create mode 100644 include/usb/ehci-core.h
 create mode 100644 include/usb/ehci.h

diff --git a/drivers/usb/host/ehci-core.h b/drivers/usb/host/ehci-core.h
deleted file mode 100644
index 39e5c5e..0000000
--- a/drivers/usb/host/ehci-core.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6e0043a..19b97ee 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,8 +27,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..bdadd46 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -27,7 +27,7 @@
 #include <malloc.h>
 #include <watchdog.h>
 
-#include "ehci.h"
+#include <usb/ehci.h>
 
 int rootdev;
 struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index b8f15ae..d15237b 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 /*
  * Create the appropriate control structures to manage
  * a new EHCI host controller.
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc6..ab75acd 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -25,8 +25,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <usb.h>
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index d360108..8d2c93b 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 static void fsl_setup_phy(volatile struct ehci_hcor *);
 static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..fde1f0f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -24,8 +24,8 @@
 #include <usb/ehci-fsl.h>
 #include <errno.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #define USBCTRL_OTGBASE_OFFSET	0x600
 
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 020ab11..e1f84d9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,8 +22,8 @@
 #include <pci.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 1179919..1a1fae1 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c
index 3063dd1..e73cf38 100644
--- a/drivers/usb/host/ehci-vct.c
+++ b/drivers/usb/host/ehci-vct.c
@@ -20,8 +20,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
 
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
deleted file mode 100644
index 3d0ad0c..0000000
--- a/drivers/usb/host/ehci.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
-	uint32_t cr_capbase;
-#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
-#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
-#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed, aligned(4)));
-
-struct ehci_hcor {
-	uint32_t or_usbcmd;
-#define CMD_PARK	(1 << 11)		/* enable "park" */
-#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
-#define CMD_ASE		(1 << 5)		/* async schedule enable */
-#define CMD_LRESET	(1 << 7)		/* partial reset */
-#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
-#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
-#define CMD_RESET	(1 << 1)		/* reset HC not bus */
-#define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
-#define	STD_ASS		(1 << 15)
-#define STS_HALT	(1 << 12)
-	uint32_t or_usbintr;
-#define INTR_UE         (1 << 0)                /* USB interrupt enable */
-#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
-#define INTR_PCE        (1 << 2)                /* Port change detect enable */
-#define INTR_SEE        (1 << 4)                /* system error enable */
-#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
-#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
-} __attribute__ ((packed, aligned(4)));
-
-#define USBMODE		0x68		/* USB Device mode */
-#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
-#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
-#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
-					cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x)		be32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
-#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
-	/* this part defined by EHCI spec */
-	uint32_t qt_next;		/* see EHCI 3.5.1 */
-#define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
-	uint32_t qt_token;		/* see EHCI 3.5.3 */
-	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
-	uint32_t qt_buffer_hi[5];	/* Appendix B */
-	/* pad struct for 32 byte alignment */
-	uint32_t unused[3];
-};
-
-/* Queue Head (QH). */
-struct QH {
-	uint32_t qh_link;
-#define	QH_LINK_TERMINATE	1
-#define	QH_LINK_TYPE_ITD	0
-#define	QH_LINK_TYPE_QH		2
-#define	QH_LINK_TYPE_SITD	4
-#define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
diff --git a/include/usb/ehci-core.h b/include/usb/ehci-core.h
new file mode 100644
index 0000000..39e5c5e
--- /dev/null
+++ b/include/usb/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
new file mode 100644
index 0000000..3d0ad0c
--- /dev/null
+++ b/include/usb/ehci.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed, aligned(4)));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed, aligned(4)));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+
+#endif /* USB_EHCI_H */
-- 
1.7.1

[U-Boot] [PATCH v9 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Marek Vasut]

On Wednesday, September 28, 2011 09:49:45 PM Jana Rapava wrote:
> From: Fabio Estevam <festevam@gmail.com>
> 
> Move ehci.h and ehci-core.h to include/usb directory.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> ---
> Changes for v1:
> 	- reorder patches in patchset
> 	- use patch from Fabio Estevam
> Changes for v2:
> 	- fix From field
> 	- rebase on top of u-boot-imx/next(no actual changes)
> Changes for v3:
> 	- change versioning in changelog from per patchset to per patch
> 	- no actual changes
> Changes for v4:
> 	- no changes
> Changes for v5:
> 	- no changes
> 

What the hell ... the patch is V9, but changelog ends with V5 ... well what the 
hell.

So please, if you submit a series and then update only SOME patches, you have to 
send only the updated patches. And the email in-reply-to should be set per-patch 
to it's predecesor.

[U-Boot] [PATCH v9 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

2011/9/28 Marek Vasut <marek.vasut@gmail.com>

> > ---
> > Changes for v1:
> >       - reorder patches in patchset
> >       - use patch from Fabio Estevam
> > Changes for v2:
> >       - fix From field
> >       - rebase on top of u-boot-imx/next(no actual changes)
> > Changes for v3:
> >       - change versioning in changelog from per patchset to per patch
> >       - no actual changes
> > Changes for v4:
> >       - no changes
> > Changes for v5:
> >       - no changes
> >
>
> What the hell ... the patch is V9, but changelog ends with V5 ... well what
> the
> hell.
>

When I started to use in changelog versioning per-patch, I didn't change the
versioning in subjects, because I was afraid it would mess up with previous
patches, which had the same version number.
But I can repost the patchset with proper version numbers if you want.

>
> So please, if you submit a series and then update only SOME patches, you
> have to
> send only the updated patches. And the email in-reply-to should be set
> per-patch
> to it's predecesor.
>

Ok.
Regards,
Jana Rapava

[U-Boot] [PATCH v9 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Marek Vasut]

On Wednesday, September 28, 2011 11:10:50 PM Jana Rapava wrote:
> 2011/9/28 Marek Vasut <marek.vasut@gmail.com>
> 
> > > ---
> > > 
> > > Changes for v1:
> > >       - reorder patches in patchset
> > >       - use patch from Fabio Estevam
> > > 
> > > Changes for v2:
> > >       - fix From field
> > >       - rebase on top of u-boot-imx/next(no actual changes)
> > > 
> > > Changes for v3:
> > >       - change versioning in changelog from per patchset to per patch
> > >       - no actual changes
> > > 
> > > Changes for v4:
> > >       - no changes
> > > 
> > > Changes for v5:
> > >       - no changes
> > 
> > What the hell ... the patch is V9, but changelog ends with V5 ... well
> > what the
> > hell.
> 
> When I started to use in changelog versioning per-patch, I didn't change
> the versioning in subjects, because I was afraid it would mess up with
> previous patches, which had the same version number.
> But I can repost the patchset with proper version numbers if you want.

Can you repost the whole series with proper cover letter explaining you're 
burying this mess and all ? Start versioning from V1 then.

Thanks

> 
> > So please, if you submit a series and then update only SOME patches, you
> > have to
> > send only the updated patches. And the email in-reply-to should be set
> > per-patch
> > to it's predecesor.
> 
> Ok.
> Regards,
> Jana Rapava

[U-Boot] [PATCH v9 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

2011/9/28 Marek Vasut <marek.vasut@gmail.com>

> Can you repost the whole series with proper cover letter explaining you're
> burying this mess and all ? Start versioning from V1 then.
>
> Thanks
>
>
Ok, what Message-ID should I then use for In-Reply-To field?

Regards,
Jana Rapava

[U-Boot] [PATCH v9 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Marek Vasut]

On Thursday, September 29, 2011 01:04:38 AM Jana Rapava wrote:
> 2011/9/28 Marek Vasut <marek.vasut@gmail.com>
> 
> > Can you repost the whole series with proper cover letter explaining
> > you're burying this mess and all ? Start versioning from V1 then.
> > 
> > Thanks
> 
> Ok, what Message-ID should I then use for In-Reply-To field?

None in this case ... did you actually read the patch submission rules?

> 
> Regards,
> Jana Rapava

[U-Boot] [PATCH v9 1/4] usb: Move ehci.h and ehci-core.h to include/usb directory

[Jana Rapava]

2011/9/29 Marek Vasut <marek.vasut@gmail.com>

>
> > Ok, what Message-ID should I then use for In-Reply-To field?
>
> None in this case ... did you actually read the patch submission rules?
>
>
I read this and didn't find this information here:
http://www.denx.de/wiki/U-Boot/Patches
Is there anything else I should read?

[U-Boot] [PATCH v9 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

Add callback to ehci_fixup to prepare
for solving the problem with VBUS reset on Efika.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>

Acked-by: Marek Vasut <marek.vasut@gmail.com>
---
Changes for v1:
  - split into patchset
  - add callback ehci_fixup
Changes for v2:
    - make this the second patch in series
    - add comment to alias ehci_fixup
    - no actual changes
Changes for v3:
     - no actual changes
     - make the comment a sentence
     - rebase patch on top of u-boot-imx/next
Changes for v4:
      - no actual changes
      - change the versioning of changelog
      from per patchset to per patch
      - fix the appearance of comment
Changes for v5:
       - no actual changes
       - reword the comment
Changes for v6:
	- no actual changes
	- fix the comment

 drivers/usb/host/ehci-hcd.c |   14 +++++++++++++-
 1 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index bdadd46..c548276 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -536,6 +536,18 @@ static inline int min3(int a, int b, int c)
 	return a;
 }
 
+inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	wait_ms(50);
+}
+
+/*
+ * This is an alias to __ehci_fixup() unless user provides other definition
+ * of ehci_fixup function.
+ */
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+	 __attribute__((weak, alias("__ehci_fixup")));
+
 int
 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 		 int length, struct devrequest *req)
@@ -709,7 +721,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 				 * usb 2.0 specification say 50 ms resets on
 				 * root
 				 */
-				wait_ms(50);
+				ehci_fixup(status_reg, &reg);
 				/* terminate the reset */
 				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 				/*
-- 
1.7.6.3

[U-Boot] [PATCH v9 3/4] EHCI: adjust for mx5

[Jana Rapava]

Add macros and structures needed by Efika USB support code.
Move shared offset and bits definitions into common header file.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v1:
  - split into patchset
Changes for v2:
    - make this the third patch in series
    - move all #define's from ehci-mxc.c to ehci-fsl.h
    - rename structures
Changes for v3:
     - rebase on top of u-boot-imx/next
      (no actual changes)
Changes for v4:
      - no changes
      - change changelog versioning from per patchset to per patch
Changes for v5:
       - whitespace changes (no actual changes)
Changes for v6:
	- no changes

 drivers/usb/host/ehci-mxc.c |   31 +--------
 include/usb/ehci-fsl.h      |  146 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 148 insertions(+), 29 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index fde1f0f..2c1295f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -27,31 +27,6 @@
 #include <usb/ehci.h>
 #include <usb/ehci-core.h>
 
-#define USBCTRL_OTGBASE_OFFSET	0x600
-
-#ifdef CONFIG_MX25
-#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
-#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
-#define MX25_USB_CTRL_USBTE_BIT		(1<<4)
-#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
-#endif
-
-#ifdef CONFIG_MX31
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
-
-#define MX31_H2_SIC_SHIFT	21
-#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT		(1 << 16)
-#define MX31_H2_DT_BIT		(1 << 5)
-
-#define MX31_H1_SIC_SHIFT	13
-#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT		(1 << 8)
-#define MX31_H1_DT_BIT		(1 << 4)
-#endif
-
 static int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
@@ -66,11 +41,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		switch (port) {
 		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+			v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT);
 			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
+					<< MXC_OTG_SIC_SHIFT;
 			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
+				v |= MXC_OTG_PM_BIT;
 
 			break;
 		case 1: /* H1 port */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..727134f 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,106 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
+#define USBCTRL_OTGBASE_OFFSET	0x600
+#endif
+
+#ifdef CONFIG_MX25
+#define MX25_USB_CTRL_IP_PUE_DOWN_BIT	(1<<6)
+#define MX25_USB_CTRL_HSTD_BIT		(1<<5)
+#define MX25_USB_CTRL_USBTE_BIT	(1<<4)
+#define MX25_USB_CTRL_OCPOL_OTG_BIT	(1<<3)
+#endif
+
+#ifdef CONFIG_MX31
+#define MX31_H2_SIC_SHIFT	21
+#define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT		(1 << 16)
+#define MX31_H2_DT_BIT		(1 << 5)
+
+#define MX31_H1_SIC_SHIFT	13
+#define MX31_H1_SIC_MASK	(0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT		(1 << 8)
+#define MX31_H1_DT_BIT		(1 << 4)
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+/* offset for first USB CTRL register */
+#define MX5_CTRL_REGS_OFFSET	0x800
+#endif
+
+#if defined(CONFIG_MX51) || defined(CONFIG_MX31)
+/* USB_CTRL register bits of interest*/
+#define MXC_OTG_SIC_SHIFT	29
+#define MXC_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
+#define MXC_OTG_WUE		(1 << 27)
+#define MXC_OTG_PM		(1 << 24)
+#endif
+
+#ifdef CONFIG_MX51
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_OTG_ID	0x000
+#define MX51_UH1_ID	0x200
+#define MX51_UH2_ID	0x400
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_PM		(1 << 24)
+#define MX51_H1_ULPI_IE	(1 << 12)
+#define MX51_H1_WUE		(1 << 11)
+#define MX51_H1_PM		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD	(1 << 8)
+#define MX51_EHCI_POWERPINSE	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ	(1 << 0)
+#define MX51_SYSCLOCK_MASK	(~(0xffffffff << 2))
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE	(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE	(1 << 8)
+#define MX51_H2_WUE		(1 << 7)
+#define MX51_H2_PM		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI	(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(0xff << 16)
+#endif
+
+/*
+* ULPI
+*/
+#define ULPI_ID_REGS_COUNT	4
+#define ULPI_TEST_VALUE	0x55
+#define ULPI_TIMEOUT		1000 /* some reasonable value */
+
+/* ULPI viewport control bits */
+#define ULPI_WU	(1 << 31)
+#define ULPI_SS	(1 << 27)
+#define ULPI_RWRUN	(1 << 30)
+#define ULPI_RWCTRL	(1 << 29)
+
+/* ULPI OTG Control bits of interest */
+#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
+#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
+#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
+#define ULPI_OTG_DRV_VBUS	(1 << 5)
+#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
+#define ULPI_OTG_CHRG_VBUS	(1 << 4)
+
+/* ULPI Function Control bits of interest */
+#define ULPI_FC_XCVR_SELECT	(1 << 0)
+#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
+#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
+
 /*
  * USB Registers
  */
@@ -210,7 +310,7 @@ struct usb_ehci {
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
 					   pre-buffer packet tuning */
 	u8	res7[0x8];
-	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
 	u8	res8[0xc];
 	u32	config_flag;	/* 0x180 - Configured Flag Register */
 	u32	portsc;		/* 0x184 - Port status/control */
@@ -242,4 +342,48 @@ struct usb_ehci {
 	u8	res13[0xafc];
 };
 
+struct mx5_usb_control_regs {
+	u32	usbctrl;	/* 0x800 - USB Control */
+	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
+	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
+	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
+	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
+	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
+	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
+};
+
+struct mxc_ulpi_regs {
+	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
+	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
+	u8	product_id_low;		/* 0x02 - Product ID lower byte */
+	u8	product_id_high;	/* 0x03 - Product ID higher byte */
+	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
+	u8	function_ctrl_write;
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
+	u8	iface_ctrl_write;
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
+	u8	otg_ctrl_write;
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
+	u8	usb_ie_rising_write;
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
+	u8	usb_ie_falling_write;
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
+	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
+	u8	debug;			/* 0x15 - Debug */
+	/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
+	u8	scratch_write;
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 Clear*/
+};
+
 #endif /* _EHCI_FSL_H */
-- 
1.7.6.3

[U-Boot] [PATCH v9 4/4] Add USB support for Efika

[Jana Rapava]

This commit adds USB support for EfikaMX and EfikaSB.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
 - changed to proper patch
Changes for v3:
 - merged other USB patches from u-boot-pxa/efikasb
 - offset-based access changed to struct-based access
 - use {clrset,clr,set}bits_le32() calls
 - CodingStyle and naming cleanup
Changes for v4:
  - split into patchset
  - CodingStyle and naming cleanup
  - remove endless loops
  - silence compiler warnings
Changes for v5:
    - change order of arguments in ulpi* functions
    - change type of reg argument
    - rename offset macro
Changes for v6:
     - rebase on top of u-boot-imx/next
     - cleanup of CodingStyle and comments
     - use macro machine_is_efikasb()
     - introduce header file efika.h
Changes for v7:
      - add proper header to efika.h
      - include efika.h into efikamx.c
      - check return values from ulpi_wait()
Changes for v8:
       - change the return value of ulpi_wait()
       - CodingStyle cleanup
       - add proper header to efikamx-usb.c
Changes for v9:
	- rewrite function ulpi_wait()

 board/efikamx/Makefile      |    3 +
 board/efikamx/efika.h       |   30 +++
 board/efikamx/efikamx-usb.c |  412 +++++++++++++++++++++++++++++++++++++++++++
 board/efikamx/efikamx.c     |    3 +
 include/configs/efikamx.h   |   16 ++
 5 files changed, 464 insertions(+), 0 deletions(-)
 create mode 100644 board/efikamx/efika.h
 create mode 100644 board/efikamx/efikamx-usb.c

diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
index ee4a16e..860e4d2 100644
--- a/board/efikamx/Makefile
+++ b/board/efikamx/Makefile
@@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= efikamx.o
+ifdef	CONFIG_CMD_USB
+COBJS	+= efikamx-usb.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/efikamx/efika.h b/board/efikamx/efika.h
new file mode 100644
index 0000000..b3532e2
--- /dev/null
+++ b/board/efikamx/efika.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2011 Jana Rapava <fermata7@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * EHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
new file mode 100644
index 0000000..aa0d68a
--- /dev/null
+++ b/board/efikamx/efikamx-usb.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * Copyright (C) 2011 Jana Rapava <fermata7@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX.
+ */
+#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
+			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
+void setup_iomux_usb(void)
+{
+	/*
+	 * Configure USBH1 pads
+	 */
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
+
+	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
+
+	/*
+	 * Configure USBH1 control pads
+	 */
+
+	/* USB PHY reset */
+	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+	/* USB HUB reset */
+	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+
+	if (machine_is_efikasb()) {
+		/*
+		 * Configure USBH2 pads (used on EfikaSB)
+		 */
+		/* USBH2_DATA */
+		mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
+		mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
+
+		/* USBH2_CLK */
+		mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
+		/* USBH2_DIR */
+		mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
+		/* USBH2_STP */
+		mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+		/* USBH2_NXT */
+		mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
+		mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
+	}
+
+	/* WIFI EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
+	/* WIFI RESET */
+	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
+	/* BT EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+}
+
+/*
+ * Enable devices connected to USB BUSes.
+ */
+void efika_usb_enable_devices(void)
+{
+	/* Enable Bluetooth */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+
+	/* Enable WiFi */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	udelay(10000);
+
+	/* Reset the WiFi chip */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB).
+ */
+void efika_usb_hub_reset(void)
+{
+	/* HUB reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB).
+ */
+void efika_usb_phy_reset(void)
+{
+	/* SMSC 3317 PHY reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+}
+
+/*
+ * Configure control registers of the USB controller.
+ */
+void control_regs_setup(struct mx5_usb_control_regs *control)
+{
+	clrsetbits_le32(&control->usbctrl,
+		(MXC_OTG_WUE | MXC_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
+		MX51_H1_PM);
+
+	clrsetbits_le32(&control->phyctrl0,
+			MX51_OTG_OVERCURD,
+			MX51_EHCI_POWERPINSE);
+
+	clrsetbits_le32(&control->phyctrl1,
+			MX51_SYSCLOCK_MASK,
+			MX51_SYSCLOCK_24_MHZ);
+
+	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
+
+	clrsetbits_le32(&control->uh2ctrl,
+			(MX51_H2_ULPI_IE | MX51_H2_WUE),
+			MX51_H2_PM);
+
+	udelay(10000);
+}
+
+#define ULPI_ADDR_SHIFT		16
+#define ulpi_write_mask(value)	((value) & 0xff)
+#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
+
+int ulpi_wait(struct usb_ehci *ehci, u32 ulpi_value, u32 ulpi_mask)
+{
+	int timeout = ULPI_TIMEOUT;
+	u32 tmp;
+
+	writel(ulpi_value, &ehci->ulpi_viewpoint);
+	/* Wait for the ulpi_bit to become zero. */
+	while (--timeout) {
+		tmp = readl(&ehci->ulpi_viewpoint);
+		if (!(tmp & ulpi_mask))
+			break;
+		WATCHDOG_RESET();
+	}
+
+	return !timeout;
+}
+
+void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		if (ulpi_wait(ehci, ULPI_WU, ULPI_WU))
+			printf("ULPI wakeup timed out\n");
+	}
+
+	if (ulpi_wait(ehci, ULPI_RWRUN | ULPI_RWCTRL |
+	reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value), ULPI_RWRUN))
+		printf("ULPI write timed out\n");
+}
+
+u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		if (ulpi_wait(ehci, ULPI_WU, ULPI_WU))
+			printf("ULPI wakeup timed out\n");
+	}
+
+	if (ulpi_wait(ehci, ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, ULPI_RWRUN)) {
+		printf("ULPI read timed out\n");
+		return 0;
+	}
+	return ulpi_read_mask(readl(&ehci->ulpi_viewpoint));
+}
+
+void ulpi_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	u32 tmp = 0;
+	int reg, i;
+
+	/* get ID from ULPI immediate registers */
+	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
+		tmp |= ulpi_read(ehci, reg) << (reg * 8);
+
+	/* split into vendor and product ID */
+	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
+
+	/* ULPI check integrity */
+	for (i = 0; i < 2; i++) {
+		ulpi_write(ehci, (u32)&ulpi->scratch_write,
+			ULPI_TEST_VALUE << i);
+		tmp = ulpi_read(ehci, (u32)&ulpi->scratch_write);
+
+		if (tmp != (ULPI_TEST_VALUE << i)) {
+			printf("ULPI integrity check failed\n");
+			return;
+		}
+	}
+
+	/* ULPI set flags */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write,
+		ULPI_OTG_EXT_VBUS_IND |
+		ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN);
+	ulpi_write(ehci, (u32)&ulpi->function_ctrl_write,
+		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL |
+		ULPI_FC_SUSPENDM_PWRED);
+	ulpi_write(ehci, (u32)&ulpi->iface_ctrl_write, 0);
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set,
+		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT);
+
+	/*
+	 * NOTE: This violates USB specification, but otherwise, USB on Efika
+	 * doesn't charge VBUS and as a result, USB doesn't work.
+	 */
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS);
+}
+
+/*
+ * Solve the VBUS reset problem on Efika
+ * by setting the CHRG_VBUS bit in the reset.
+ */
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		MX51_REGISTER_LAYOUT_LENGTH);
+	struct mxc_ulpi_regs *ulpi = (struct mxc_ulpi_regs *)0;
+
+	u32 tmp = ulpi_read(ehci, (u32)&ulpi->otg_ctrl_write);
+	tmp |= ULPI_OTG_CHRG_VBUS;
+	ulpi_write(ehci, (u32)&ulpi->otg_ctrl_write, tmp);
+
+	/* USB 2.0 specification say 50 ms resets on root. */
+	wait_ms(50);
+
+	/* Now terminate the reset. */
+	*reg_ref = ehci_readl(status_reg);
+	*reg_ref |= EHCI_PS_PE;
+}
+
+void ehci0_init(struct usb_ehci *ehci)
+{
+	writel(MX51_16BIT_UTMI, &ehci->portsc);
+}
+
+void ehci1_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	udelay(10000);
+
+	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
+	udelay(10000);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+void ehci2_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ehci, ulpi);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+	struct mx5_usb_control_regs *mx5_usb_control_regs;
+	struct mxc_ulpi_regs *ulpi;
+
+	mx5_usb_control_regs = (struct mx5_usb_control_regs *)(OTG_BASE_ADDR +
+		 MX5_CTRL_REGS_OFFSET);
+	control_regs_setup(mx5_usb_control_regs);
+	ulpi = (struct mxc_ulpi_regs *)0;
+
+	/* Init EHCI core */
+	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+	setbits_le32(&ehci->control, USB_EN);
+	
+	/* Init iMX51 EHCI */
+	efika_usb_phy_reset();
+	efika_usb_hub_reset();
+	efika_usb_enable_devices();
+
+	switch (CONFIG_MXC_USB_PORT) {
+	case 0:
+		ehci0_init(ehci);
+		break;
+	case 1:
+		ehci1_init(ehci, ulpi);
+		break;
+	case 2:
+		if (machine_is_efikasb())
+			ehci2_init(ehci, ulpi);
+		break;
+	};
+
+	/* EfikaMX USB has issues ... */
+	udelay(10000);
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 0c4e24b..8e9b42b 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -37,6 +37,8 @@
 #include <fsl_pmic.h>
 #include <mc13892.h>
 
+#include "efika.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -678,6 +680,7 @@ int board_late_init(void)
 
 	setup_iomux_led();
 	setup_iomux_ata();
+	setup_iomux_usb();
 
 	efikamx_toggle_led(EFIKAMX_LED_BLUE);
 
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index 54f48e4..010a16a 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -44,6 +44,10 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
+#define	CONFIG_L2_OFF
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
 /*
  * Bootloader Components Configuration
  */
@@ -172,6 +176,18 @@
 #endif
 
 /*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#endif /* CONFIG_CMD_USB */
+
+/*
  * Filesystems
  */
 #ifdef CONFIG_CMD_FAT
-- 
1.7.6.3

[U-Boot] [PATCH v9 4/4] Add USB support for Efika

[Marek Vasut]

On Wednesday, September 28, 2011 09:54:41 PM Jana Rapava wrote:
> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>

Dear Jana Rapava,

[...]
> +/*
> + * Enable devices connected to USB BUSes.

BUS isn't written in capital letters, it's normal english word.

> + */
> +void efika_usb_enable_devices(void)
> +{

[...]
> +
> +#define ULPI_ADDR_SHIFT		16
> +#define ulpi_write_mask(value)	((value) & 0xff)
> +#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
> +
> +int ulpi_wait(struct usb_ehci *ehci, u32 ulpi_value, u32 ulpi_mask)
> +{
> +	int timeout = ULPI_TIMEOUT;
> +	u32 tmp;
> +
> +	writel(ulpi_value, &ehci->ulpi_viewpoint);

Newline

> +	/* Wait for the ulpi_bit to become zero. */

ulpi_mask ? There's no ulpi_bit ... ?

> +	while (--timeout) {
> +		tmp = readl(&ehci->ulpi_viewpoint);
> +		if (!(tmp & ulpi_mask))
> +			break;
> +		WATCHDOG_RESET();
> +	}
> +
> +	return !timeout;
> +}
> +
> +void ulpi_write(struct usb_ehci *ehci, u32 reg, u32 value)
> +{
> +	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +		if (ulpi_wait(ehci, ULPI_WU, ULPI_WU))
> +			printf("ULPI wakeup timed out\n");

Exit here if the wait fails.

Also, this seems also like a common pattern, can we abstract it to ulpi_wakeup() 
?

> +	}
> +
> +	if (ulpi_wait(ehci, ULPI_RWRUN | ULPI_RWCTRL |
> +	reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value), ULPI_RWRUN))
> +		printf("ULPI write timed out\n");
> +}
> +
> +u32 ulpi_read(struct usb_ehci *ehci, u32 reg)
> +{
> +	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
> +		if (ulpi_wait(ehci, ULPI_WU, ULPI_WU))
> +			printf("ULPI wakeup timed out\n");
> +	}

Like here ...

int ret = ulpi_wakeup();
if (ret)
	return;

ulpi wakeup being something like
{
if (readl() & ...)
	return 0; // already awake

return ulpi_wait();
}

> +
> +	if (ulpi_wait(ehci, ULPI_RWRUN | reg << ULPI_ADDR_SHIFT, ULPI_RWRUN)) {
> +		printf("ULPI read timed out\n");
> +		return 0;
> +	}
> +	return ulpi_read_mask(readl(&ehci->ulpi_viewpoint));
> +}
> +
> +void ulpi_init(struct usb_ehci *ehci, struct mxc_ulpi_regs *ulpi)
> +{
> +	u32 tmp = 0;
> +	int reg, i;
> +
> +	/* get ID from ULPI immediate registers */

English sentence ... capital letter, dot ... please fix globally!

Nearly there.

BR, MV

[U-Boot] [PATCH v9 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

On Wednesday, September 28, 2011 09:51:15 PM Jana Rapava wrote:
> Add callback to ehci_fixup to prepare
> for solving the problem with VBUS reset on Efika.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> 
> Acked-by: Marek Vasut <marek.vasut@gmail.com>
> ---
> Changes for v1:
>   - split into patchset
>   - add callback ehci_fixup
> Changes for v2:
>     - make this the second patch in series
>     - add comment to alias ehci_fixup
>     - no actual changes
> Changes for v3:
>      - no actual changes
>      - make the comment a sentence
>      - rebase patch on top of u-boot-imx/next
> Changes for v4:
>       - no actual changes
>       - change the versioning of changelog
>       from per patchset to per patch
>       - fix the appearance of comment
> Changes for v5:
>        - no actual changes
>        - reword the comment
> Changes for v6:
> 	- no actual changes
> 	- fix the comment

So are there any changes or not ?!

[U-Boot] [PATCH v9 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

2011/9/28 Marek Vasut <marek.vasut@gmail.com>

> > Changes for v6:
> >       - no actual changes
> >       - fix the comment
>
> So are there any changes or not ?!
>

I only fixed the comment to look better, there were no actual changes.
Sorry, I really don't know how I could express it more clearly. I'll be glad
for any suggestions.

Regards,
Jana Rapava

[U-Boot] [PATCH v9 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

On Wednesday, September 28, 2011 11:14:06 PM Jana Rapava wrote:
> 2011/9/28 Marek Vasut <marek.vasut@gmail.com>
> 
> > > Changes for v6:
> > >       - no actual changes
> > >       - fix the comment
> > 
> > So are there any changes or not ?!
> 
> I only fixed the comment to look better, there were no actual changes.
> Sorry, I really don't know how I could express it more clearly. I'll be
> glad for any suggestions.

Ok then ... "no change in code, updated comment" ... but whatever, it's clear 
now.

[U-Boot] [PATCH v4 1/5] EHCI: add callback ehci_fixup

[Marek Vasut]

On Sunday, September 25, 2011 01:55:54 PM Jana Rapava wrote:
> EHCI: add callback ehci_fixup to solve VBUS reset
> issue for Efika.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>

5/5 is missing ... ok, I'm not reviewing this until correctly submitted.

[U-Boot] [PATCH v4 1/4] USB: move ehci.h and ehci-core.h into /include/usb/

[Jana Rapava]

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Fabio Estevam <festevam@gmail.com>
---
Changes for v2:
      - changed to proper patch
Changes for v3:
      - merged other USB patches from u-boot-pxa/efikasb
      - offset-based access changed to struct-based access
      - use {clrset,clr,set}bits_le32() calls
      - CodingStyle and naming cleanup
Changes for v4:
       - split into patchset
       - move ehci.h and ehci-core.h into /include/usb/

 drivers/usb/host/ehci-core.h     |   29 ------
 drivers/usb/host/ehci-fsl.c      |    4 +-
 drivers/usb/host/ehci-hcd.c      |    2 +-
 drivers/usb/host/ehci-kirkwood.c |    4 +-
 drivers/usb/host/ehci-mpc512x.c  |    4 +-
 drivers/usb/host/ehci-pci.c      |    4 +-
 drivers/usb/host/ehci-ppc4xx.c   |    4 +-
 drivers/usb/host/ehci.h          |  203 --------------------------------------
 include/usb/ehci-core.h          |   29 ++++++
 include/usb/ehci.h               |  203 ++++++++++++++++++++++++++++++++++++++
 10 files changed, 243 insertions(+), 243 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-core.h
 delete mode 100644 drivers/usb/host/ehci.h
 create mode 100644 include/usb/ehci-core.h
 create mode 100644 include/usb/ehci.h

diff --git a/drivers/usb/host/ehci-core.h b/drivers/usb/host/ehci-core.h
deleted file mode 100644
index 39e5c5e..0000000
--- a/drivers/usb/host/ehci-core.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Sk?ne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6e0043a..19b97ee 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,8 +27,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 2197119..bdadd46 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -27,7 +27,7 @@
 #include <malloc.h>
 #include <watchdog.h>
 
-#include "ehci.h"
+#include <usb/ehci.h>
 
 int rootdev;
 struct ehci_hccr *hccr;	/* R/O registers, not need for volatile */
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc6..ab75acd 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -25,8 +25,8 @@
 #include <common.h>
 #include <asm/io.h>
 #include <usb.h>
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/usb/host/ehci-mpc512x.c b/drivers/usb/host/ehci-mpc512x.c
index d360108..8d2c93b 100644
--- a/drivers/usb/host/ehci-mpc512x.c
+++ b/drivers/usb/host/ehci-mpc512x.c
@@ -32,8 +32,8 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 static void fsl_setup_phy(volatile struct ehci_hcor *);
 static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 020ab11..e1f84d9 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -22,8 +22,8 @@
 #include <pci.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 #ifdef CONFIG_PCI_EHCI_DEVICE
 static struct pci_device_id ehci_pci_ids[] = {
diff --git a/drivers/usb/host/ehci-ppc4xx.c b/drivers/usb/host/ehci-ppc4xx.c
index 1179919..1a1fae1 100644
--- a/drivers/usb/host/ehci-ppc4xx.c
+++ b/drivers/usb/host/ehci-ppc4xx.c
@@ -22,8 +22,8 @@
 #include <common.h>
 #include <usb.h>
 
-#include "ehci.h"
-#include "ehci-core.h"
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
 
 /*
  * Create the appropriate control structures to manage
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
deleted file mode 100644
index 3d0ad0c..0000000
--- a/drivers/usb/host/ehci.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_H
-#define USB_EHCI_H
-
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
-
-/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
-#define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
-
-#define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-#define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
-
-/*
- * Register Space.
- */
-struct ehci_hccr {
-	uint32_t cr_capbase;
-#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
-#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
-#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
-#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
-} __attribute__ ((packed, aligned(4)));
-
-struct ehci_hcor {
-	uint32_t or_usbcmd;
-#define CMD_PARK	(1 << 11)		/* enable "park" */
-#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
-#define CMD_ASE		(1 << 5)		/* async schedule enable */
-#define CMD_LRESET	(1 << 7)		/* partial reset */
-#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
-#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
-#define CMD_RESET	(1 << 1)		/* reset HC not bus */
-#define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
-#define	STD_ASS		(1 << 15)
-#define STS_HALT	(1 << 12)
-	uint32_t or_usbintr;
-#define INTR_UE         (1 << 0)                /* USB interrupt enable */
-#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
-#define INTR_PCE        (1 << 2)                /* Port change detect enable */
-#define INTR_SEE        (1 << 4)                /* system error enable */
-#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
-#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
-} __attribute__ ((packed, aligned(4)));
-
-#define USBMODE		0x68		/* USB Device mode */
-#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
-#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
-#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
-
-/* Interface descriptor */
-struct usb_linux_interface_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
-} __attribute__ ((packed));
-
-/* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
-} __attribute__ ((packed));
-
-#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
-#else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
-					cpu_to_le32(((volatile u32)b)))
-#endif
-
-#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
-#define hc32_to_cpu(x)		be32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_be32((x))
-#else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
-#endif
-
-#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
-#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
-#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
-#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
-
-#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
-
-/*
- * Schedule Interface Space.
- *
- * IMPORTANT: Software must ensure that no interface data structure
- * reachable by the EHCI host controller spans a 4K page boundary!
- *
- * Periodic transfers (i.e. isochronous and interrupt transfers) are
- * not supported.
- */
-
-/* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
-	/* this part defined by EHCI spec */
-	uint32_t qt_next;		/* see EHCI 3.5.1 */
-#define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
-	uint32_t qt_token;		/* see EHCI 3.5.3 */
-	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
-	uint32_t qt_buffer_hi[5];	/* Appendix B */
-	/* pad struct for 32 byte alignment */
-	uint32_t unused[3];
-};
-
-/* Queue Head (QH). */
-struct QH {
-	uint32_t qh_link;
-#define	QH_LINK_TERMINATE	1
-#define	QH_LINK_TYPE_ITD	0
-#define	QH_LINK_TYPE_QH		2
-#define	QH_LINK_TYPE_SITD	4
-#define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
-};
-
-/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
-
-#endif /* USB_EHCI_H */
diff --git a/include/usb/ehci-core.h b/include/usb/ehci-core.h
new file mode 100644
index 0000000..17b6854
--- /dev/null
+++ b/include/usb/ehci-core.h
@@ -0,0 +1,29 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Excito Elektronik i Skane AB
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_CORE_H
+#define USB_EHCI_CORE_H
+
+extern int rootdev;
+extern struct ehci_hccr *hccr;
+extern volatile struct ehci_hcor *hcor;
+
+#endif
diff --git a/include/usb/ehci.h b/include/usb/ehci.h
new file mode 100644
index 0000000..3d0ad0c
--- /dev/null
+++ b/include/usb/ehci.h
@@ -0,0 +1,203 @@
+/*-
+ * Copyright (c) 2007-2008, Juniper Networks, Inc.
+ * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef USB_EHCI_H
+#define USB_EHCI_H
+
+#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#endif
+
+/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
+#define DeviceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define DeviceOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+
+#define InterfaceRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointRequest \
+	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+#define EndpointOutRequest \
+	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+
+/*
+ * Register Space.
+ */
+struct ehci_hccr {
+	uint32_t cr_capbase;
+#define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
+#define HC_VERSION(p)		(((p) >> 16) & 0xffff)
+	uint32_t cr_hcsparams;
+#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
+#define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
+	uint32_t cr_hccparams;
+	uint8_t cr_hcsp_portrt[8];
+} __attribute__ ((packed, aligned(4)));
+
+struct ehci_hcor {
+	uint32_t or_usbcmd;
+#define CMD_PARK	(1 << 11)		/* enable "park" */
+#define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
+#define CMD_ASE		(1 << 5)		/* async schedule enable */
+#define CMD_LRESET	(1 << 7)		/* partial reset */
+#define CMD_IAAD	(1 << 5)		/* "doorbell" interrupt */
+#define CMD_PSE		(1 << 4)		/* periodic schedule enable */
+#define CMD_RESET	(1 << 1)		/* reset HC not bus */
+#define CMD_RUN		(1 << 0)		/* start/stop HC */
+	uint32_t or_usbsts;
+#define	STD_ASS		(1 << 15)
+#define STS_HALT	(1 << 12)
+	uint32_t or_usbintr;
+#define INTR_UE         (1 << 0)                /* USB interrupt enable */
+#define INTR_UEE        (1 << 1)                /* USB error interrupt enable */
+#define INTR_PCE        (1 << 2)                /* Port change detect enable */
+#define INTR_SEE        (1 << 4)                /* system error enable */
+#define INTR_AAE        (1 << 5)                /* Interrupt on async adavance enable */
+	uint32_t or_frindex;
+	uint32_t or_ctrldssegment;
+	uint32_t or_periodiclistbase;
+	uint32_t or_asynclistaddr;
+	uint32_t _reserved_[9];
+	uint32_t or_configflag;
+#define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
+	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+	uint32_t or_systune;
+} __attribute__ ((packed, aligned(4)));
+
+#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE_SDIS	(1 << 3)	/* Stream disable */
+#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
+#define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
+
+/* Interface descriptor */
+struct usb_linux_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+} __attribute__ ((packed));
+
+/* Configuration descriptor information.. */
+struct usb_linux_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+} __attribute__ ((packed));
+
+#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
+#define	ehci_readl(x)		(*((volatile u32 *)(x)))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#else
+#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
+#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = \
+					cpu_to_le32(((volatile u32)b)))
+#endif
+
+#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define hc32_to_cpu(x)		be32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_be32((x))
+#else
+#define hc32_to_cpu(x)		le32_to_cpu((x))
+#define cpu_to_hc32(x)		cpu_to_le32((x))
+#endif
+
+#define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
+#define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
+#define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
+#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS		(3 << 10)	/* RO line status */
+#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
+
+#define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
+
+/*
+ * Schedule Interface Space.
+ *
+ * IMPORTANT: Software must ensure that no interface data structure
+ * reachable by the EHCI host controller spans a 4K page boundary!
+ *
+ * Periodic transfers (i.e. isochronous and interrupt transfers) are
+ * not supported.
+ */
+
+/* Queue Element Transfer Descriptor (qTD). */
+struct qTD {
+	/* this part defined by EHCI spec */
+	uint32_t qt_next;		/* see EHCI 3.5.1 */
+#define	QT_NEXT_TERMINATE	1
+	uint32_t qt_altnext;		/* see EHCI 3.5.2 */
+	uint32_t qt_token;		/* see EHCI 3.5.3 */
+	uint32_t qt_buffer[5];		/* see EHCI 3.5.4 */
+	uint32_t qt_buffer_hi[5];	/* Appendix B */
+	/* pad struct for 32 byte alignment */
+	uint32_t unused[3];
+};
+
+/* Queue Head (QH). */
+struct QH {
+	uint32_t qh_link;
+#define	QH_LINK_TERMINATE	1
+#define	QH_LINK_TYPE_ITD	0
+#define	QH_LINK_TYPE_QH		2
+#define	QH_LINK_TYPE_SITD	4
+#define	QH_LINK_TYPE_FSTN	6
+	uint32_t qh_endpt1;
+	uint32_t qh_endpt2;
+	uint32_t qh_curtd;
+	struct qTD qh_overlay;
+	/*
+	 * Add dummy fill value to make the size of this struct
+	 * aligned to 32 bytes
+	 */
+	uint8_t fill[16];
+};
+
+/* Low level init functions */
+int ehci_hcd_init(void);
+int ehci_hcd_stop(void);
+
+#endif /* USB_EHCI_H */
-- 
1.7.6.3

[U-Boot] [PATCH v4 2/4] EHCI: add callback ehci_fixup

[Jana Rapava]

Add callback to ehci_fixup to prepare
for solving the problem with VBUS reset on Efika.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
      - changed to proper patch
Changes for v3:
      - merged other USB patches from u-boot-pxa/efikasb
      - offset-based access changed to struct-based access
      - use {clrset,clr,set}bits_le32() calls
      - CodingStyle and naming cleanup
Changes for v4:
       - split into patchset
       - add callback ehci_fixup

 drivers/usb/host/ehci-hcd.c |   12 ++++++++++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index bdadd46..8d31921 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -26,6 +26,7 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <watchdog.h>
+#include <usb/ehci-fsl.h>
 
 #include <usb/ehci.h>
 
@@ -536,6 +537,14 @@ static inline int min3(int a, int b, int c)
 	return a;
 }
 
+inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+	wait_ms(50);
+}
+
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+	 __attribute__((weak, alias("__ehci_fixup")));
+
 int
 ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 		 int length, struct devrequest *req)
@@ -709,8 +718,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
 				 * usb 2.0 specification say 50 ms resets on
 				 * root
 				 */
-				wait_ms(50);
-				/* terminate the reset */
+				ehci_fixup(status_reg, &reg);
 				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
 				/*
 				 * A host controller must terminate the reset
-- 
1.7.6.3

[U-Boot] [PATCH v4 2/4] EHCI: add callback ehci_fixup

[Marek Vasut]

On Sunday, September 25, 2011 07:25:08 PM Jana Rapava wrote:
> Add callback to ehci_fixup to prepare
> for solving the problem with VBUS reset on Efika.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>       - changed to proper patch
> Changes for v3:
>       - merged other USB patches from u-boot-pxa/efikasb
>       - offset-based access changed to struct-based access
>       - use {clrset,clr,set}bits_le32() calls
>       - CodingStyle and naming cleanup
> Changes for v4:
>        - split into patchset
>        - add callback ehci_fixup
> 
>  drivers/usb/host/ehci-hcd.c |   12 ++++++++++--
>  1 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index bdadd46..8d31921 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -26,6 +26,7 @@
>  #include <asm/io.h>
>  #include <malloc.h>
>  #include <watchdog.h>
> +#include <usb/ehci-fsl.h>
> 
>  #include <usb/ehci.h>
> 
> @@ -536,6 +537,14 @@ static inline int min3(int a, int b, int c)
>  	return a;
>  }
> 
> +inline void __ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +{
> +	wait_ms(50);
> +}
> +
> +void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
> +	 __attribute__((weak, alias("__ehci_fixup")));
> +
>  int
>  ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
>  		 int length, struct devrequest *req)
> @@ -709,8 +718,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long
> pipe, void *buffer, * usb 2.0 specification say 50 ms resets on
>  				 * root
>  				 */
> -				wait_ms(50);
> -				/* terminate the reset */
> +				ehci_fixup(status_reg, &reg);
>  				ehci_writel(status_reg, reg & ~EHCI_PS_PR);
>  				/*
>  				 * A host controller must terminate the reset

Dear Jana Rapava,

please document this properly and don't drop comments.

Cheers

[U-Boot] [PATCH v4 3/4] EHCI: adjust for mx5

[Jana Rapava]

Add into ./include/usb/ehci-fsl.h macros and structures
needed by following patch; change prefix of common MX31 USB_CTRL bits
to MXC.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
      - changed to proper patch
Changes for v3:
      - merged other USB patches from u-boot-pxa/efikasb
      - offset-based access changed to struct-based access
      - use {clrset,clr,set}bits_le32() calls
      - CodingStyle and naming cleanup
Changes for v4:
       - split into patchset

 drivers/usb/host/ehci-mxc.c |    9 +--
 include/usb/ehci-fsl.h      |  119 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 121 insertions(+), 7 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index a0cfbb7..973bb4f 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -37,9 +37,6 @@
 #endif
 
 #ifdef CONFIG_MX31
-#define MX31_OTG_SIC_SHIFT	29
-#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT		(1 << 24)
 
 #define MX31_H2_SIC_SHIFT	21
 #define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)
@@ -66,11 +63,11 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 
 		switch (port) {
 		case 0:	/* OTG port */
-			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+			v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT);
 			v |= (flags & MXC_EHCI_INTERFACE_MASK)
-					<< MX31_OTG_SIC_SHIFT;
+					<< MXC_OTG_SIC_SHIFT;
 			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-				v |= MX31_OTG_PM_BIT;
+				v |= MXC_OTG_PM_BIT;
 
 			break;
 		case 1: /* H1 port */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 67600ed..b107f71 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -169,6 +169,79 @@
 #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
 #endif
 
+#if defined(CONFIG_MX51) || defined(CONFIG_MX31)
+/* USB_CTRL register bits of interest*/
+#define MXC_OTG_SIC_SHIFT	29
+#define MXC_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
+#define MXC_OTG_WUE		(1 << 27)
+#define MXC_OTG_PM		(1 << 24)
+#endif
+
+#ifdef CONFIG_MX51
+#define MX51_REGISTER_LAYOUT_LENGTH	0x200
+
+/* Register offsets for MX51 */
+#define MX51_OTG_ID	0x000
+#define MX51_UH1_ID	0x200
+#define MX51_UH2_ID	0x400
+#define MX51_CTRL_REGS	0x800
+
+/* USB_CTRL register bits of interest*/
+#define MX51_OTG_PM		(1 << 24)
+#define MX51_H1_ULPI_IE		(1 << 12)
+#define MX51_H1_WUE		(1 << 11)
+#define MX51_H1_PM		(1 << 8)
+
+/* PHY_CTRL_0 register bits of interest */
+#define MX51_OTG_OVERCURD	(1 << 8)
+#define MX51_EHCI_POWERPINSE	(1 << 5)
+
+/* PHY_CTRL_1 register bits of interest */
+#define MX51_SYSCLOCK_24_MHZ	(1 << 0)
+#define MX51_SYSCLOCK_MASK	(~(0xffffffff << 2))
+
+/* USB_CTRL_1 register bits of interest */
+#define MX51_H1_EXTCLKE		(1 << 25)
+
+/* USB Host 2 CTRL register bits of interest */
+#define MX51_H2_ULPI_IE		(1 << 8)
+#define MX51_H2_WUE		(1 << 7)
+#define MX51_H2_PM		(1 << 4)
+
+/* PORTSCx bits of interest */
+#define MX51_ULPI_MODE_MASK	(2 << 30)
+#define MX51_16BIT_UTMI		(1 << 28)
+
+/* USBCMD bits of interest */
+#define MX51_ITC_IMMEDIATE_MASK	(0xff << 16)
+#endif
+
+/*
+* ULPI
+*/
+#define ULPI_ID_REGS_COUNT	4
+#define ULPI_TEST_VALUE		0x55
+#define ULPI_TIMEOUT		1000 /* some reasonable value */
+
+/* ULPI viewport control bits */
+#define ULPI_WU		(1 << 31)
+#define ULPI_SS		(1 << 27)
+#define ULPI_RWRUN	(1 << 30)
+#define ULPI_RWCTRL	(1 << 29)
+
+/* ULPI OTG Control bits of interest */
+#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
+#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
+#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
+#define	ULPI_OTG_DRV_VBUS	(1 << 5)
+#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
+#define ULPI_OTG_CHRG_VBUS	(1 << 4)
+
+/* ULPI Function Control bits of interest */
+#define ULPI_FC_XCVR_SELECT	(1 << 0)
+#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
+#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
+
 /*
  * USB Registers
  */
@@ -210,7 +283,7 @@ struct usb_ehci {
 	u32	txfilltuning;	/* 0x164 - Host TT Transmit
 					   pre-buffer packet tuning */
 	u8	res7[0x8];
-	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
 	u8	res8[0xc];
 	u32	config_flag;	/* 0x180 - Configured Flag Register */
 	u32	portsc;		/* 0x184 - Port status/control */
@@ -242,4 +315,48 @@ struct usb_ehci {
 	u8	res13[0xafc];
 };
 
+struct usb_control_regs {
+	u32	usbctrl;	/* 0x800 - USB Control */
+	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
+	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
+	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
+	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
+	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
+	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
+};
+
+struct ulpi_regs {
+	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
+	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
+	u8	product_id_low;		/* 0x02 - Product ID lower byte */
+	u8	product_id_high;	/* 0x03 - Product ID higher byte */
+	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
+	u8	function_ctrl_write;
+	u8	function_ctrl_set;	/* 0x05 Set */
+	u8	function_ctrl_clear;	/* 0x06 Clear */
+	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
+	u8	iface_ctrl_write;
+	u8	iface_ctrl_set;		/* 0x08 Set */
+	u8	iface_ctrl_clear;	/* 0x09 Clear */
+	/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
+	u8	otg_ctrl_write;
+	u8	otg_ctrl_set;		/* 0x0B Set */
+	u8	otg_ctrl_clear;		/* 0x0C Clear */
+	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
+	u8	usb_ie_rising_write;
+	u8	usb_ie_rising_set;	/* 0x0E Set */
+	u8	usb_ie_rising_clear;	/* 0x0F Clear */
+	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
+	u8	usb_ie_falling_write;
+	u8	usb_ie_falling_set;	/* 0x11 Set */
+	u8	usb_ie_falling_clear;	/* 0x12 Clear */
+	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
+	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
+	u8	debug;			/* 0x15 - Debug */
+	/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
+	u8	scratch_write;
+	u8	scratch_set;		/* 0x17 Set */
+	u8	scratch_clear;		/* 0x18 Clear*/
+};
+
 #endif /* _EHCI_FSL_H */
-- 
1.7.6.3

[U-Boot] [PATCH v4 3/4] EHCI: adjust for mx5

[Marek Vasut]

On Sunday, September 25, 2011 07:25:09 PM Jana Rapava wrote:

Dear Jana Rapava,

> Add into ./include/usb/ehci-fsl.h macros and structures
> needed by following patch; change prefix of common MX31 USB_CTRL bits
> to MXC.

The commit message doesn't make too much sense. The intention is to move 
definitions shared across multiple drivers into common header file? If so, 
please express this properly.

> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>       - changed to proper patch
> Changes for v3:
>       - merged other USB patches from u-boot-pxa/efikasb
>       - offset-based access changed to struct-based access
>       - use {clrset,clr,set}bits_le32() calls
>       - CodingStyle and naming cleanup
> Changes for v4:
>        - split into patchset
> 
>  drivers/usb/host/ehci-mxc.c |    9 +--
>  include/usb/ehci-fsl.h      |  119
> ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 121
> insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
> index a0cfbb7..973bb4f 100644
> --- a/drivers/usb/host/ehci-mxc.c
> +++ b/drivers/usb/host/ehci-mxc.c
> @@ -37,9 +37,6 @@
>  #endif
> 
>  #ifdef CONFIG_MX31
> -#define MX31_OTG_SIC_SHIFT	29
> -#define MX31_OTG_SIC_MASK	(0x3 << MX31_OTG_SIC_SHIFT)
> -#define MX31_OTG_PM_BIT		(1 << 24)
> 
>  #define MX31_H2_SIC_SHIFT	21
>  #define MX31_H2_SIC_MASK	(0x3 << MX31_H2_SIC_SHIFT)

You should move this all into ehci-fsl.h then.

> @@ -66,11 +63,11 @@ static int mxc_set_usbcontrol(int port, unsigned int
> flags)
> 
>  		switch (port) {
>  		case 0:	/* OTG port */
> -			v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
> +			v &= ~(MXC_OTG_SIC_MASK | MXC_OTG_PM_BIT);
>  			v |= (flags & MXC_EHCI_INTERFACE_MASK)
> -					<< MX31_OTG_SIC_SHIFT;
> +					<< MXC_OTG_SIC_SHIFT;
>  			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
> -				v |= MX31_OTG_PM_BIT;
> +				v |= MXC_OTG_PM_BIT;
> 
>  			break;
>  		case 1: /* H1 port */
> diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
> index 67600ed..b107f71 100644
> --- a/include/usb/ehci-fsl.h
> +++ b/include/usb/ehci-fsl.h
> @@ -169,6 +169,79 @@
>  #define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR
>  #endif

[...]

> +/* ULPI OTG Control bits of interest */
> +#define ULPI_OTG_EXT_VBUS_IND	(1 << 7)
> +#define ULPI_OTG_DM_PULLDOWN	(1 << 2)
> +#define ULPI_OTG_DP_PULLDOWN	(1 << 1)
> +#define	ULPI_OTG_DRV_VBUS	(1 << 5)

Use space/tab consistently ... space is the prefered thing to use.

> +#define ULPI_OTG_DRV_VBUS_EXT	(1 << 6)
> +#define ULPI_OTG_CHRG_VBUS	(1 << 4)
> +
> +/* ULPI Function Control bits of interest */
> +#define ULPI_FC_XCVR_SELECT	(1 << 0)
> +#define ULPI_FC_OPMODE_NORMAL	(0 << 3)
> +#define ULPI_FC_SUSPENDM_PWRED	(1 << 6)
> +
>  /*
>   * USB Registers
>   */
> @@ -210,7 +283,7 @@ struct usb_ehci {
>  	u32	txfilltuning;	/* 0x164 - Host TT Transmit
>  					   pre-buffer packet tuning */
>  	u8	res7[0x8];
> -	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
> +	u32	ulpi_viewpoint;	/* 0x170 - ULPI Register Access */
>  	u8	res8[0xc];
>  	u32	config_flag;	/* 0x180 - Configured Flag Register */
>  	u32	portsc;		/* 0x184 - Port status/control */
> @@ -242,4 +315,48 @@ struct usb_ehci {
>  	u8	res13[0xafc];
>  };
> 
> +struct usb_control_regs {
> +	u32	usbctrl;	/* 0x800 - USB Control */
> +	u32	otgmirror;	/* 0x804 - OTG Port Mirror */
> +	u32	phyctrl0;	/* 0x808 - UTMI PHY Control Register 0 */
> +	u32	phyctrl1;	/* 0x80C - UTMI PHY Control Register 1 */
> +	u32	usbctrl1;	/* 0x810 - USB Control Register 1 */
> +	u32	uh2ctrl;	/* 0x814 - USB Host2 Control */
> +	u32	uh3ctrl;	/* 0x818 - USB Host3 Control */
> +};

mx5_usb_control_regs ... this is not the same on all mxc chips.

> +
> +struct ulpi_regs {
> +	u8	vendor_id_low;		/* 0x00 - Vendor ID lower byte */
> +	u8	vendor_id_high;		/* 0x01 - Vendor ID upper byte */
> +	u8	product_id_low;		/* 0x02 - Product ID lower byte */
> +	u8	product_id_high;	/* 0x03 - Product ID higher byte */
> +	/* Function Control; 0x04 - 0x06 Read, 0x04 Write */
> +	u8	function_ctrl_write;
> +	u8	function_ctrl_set;	/* 0x05 Set */
> +	u8	function_ctrl_clear;	/* 0x06 Clear */
> +	/* Interface Control; 0x07 - 0x09 Read, 0x07 Write */
> +	u8	iface_ctrl_write;
> +	u8	iface_ctrl_set;		/* 0x08 Set */
> +	u8	iface_ctrl_clear;	/* 0x09 Clear */
> +	/* OTG Control; 0x0A - 0x0C Read, 0x0A Write */
> +	u8	otg_ctrl_write;
> +	u8	otg_ctrl_set;		/* 0x0B Set */
> +	u8	otg_ctrl_clear;		/* 0x0C Clear */
> +	/* USB Interrupt Enable Rising; 0x0D - 0x0F Read, 0x0D Write */
> +	u8	usb_ie_rising_write;
> +	u8	usb_ie_rising_set;	/* 0x0E Set */
> +	u8	usb_ie_rising_clear;	/* 0x0F Clear */
> +	/* USB Interrupt Enable Falling; 0x10 - 0x12 Read, 0x10 Write */
> +	u8	usb_ie_falling_write;
> +	u8	usb_ie_falling_set;	/* 0x11 Set */
> +	u8	usb_ie_falling_clear;	/* 0x12 Clear */
> +	u8	usb_int_status;		/* 0x13 - USB Interrupt Status */
> +	u8	usb_int_latch;		/* 0x14 - USB Interrupt Latch */
> +	u8	debug;			/* 0x15 - Debug */
> +	/* Scratch Register; 0x16 - 0x18 Read, 0x16 Write */
> +	u8	scratch_write;
> +	u8	scratch_set;		/* 0x17 Set */
> +	u8	scratch_clear;		/* 0x18 Clear*/
> +};

Hm, we should keep this here only until we get a decent ULPI implementation. 
Also, rename to something like mxc_ulpi_regs at least.

> +
>  #endif /* _EHCI_FSL_H */

[U-Boot] [PATCH v4 4/4] Add USB support for Efika

[Jana Rapava]

This commit adds USB support for EfikaMX and EfikaSB.

Signed-off-by: Jana Rapava <fermata7@gmail.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Remy Bohmer <linux@bohmer.net>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes for v2:
      - changed to proper patch
Changes for v3:
      - merged other USB patches from u-boot-pxa/efikasb
      - offset-based access changed to struct-based access
      - use {clrset,clr,set}bits_le32() calls
      - CodingStyle and naming cleanup
Changes for v4:
       - split into patchset
       - CodingStyle and naming cleanup
       - remove endless loops
       - silence compiler warnings

 board/efikamx/Makefile      |    3 +
 board/efikamx/efikamx-usb.c |  380 +++++++++++++++++++++++++++++++++++++++++++
 board/efikamx/efikamx.c     |   10 +
 include/configs/efikamx.h   |   16 ++
 4 files changed, 409 insertions(+), 0 deletions(-)
 create mode 100644 board/efikamx/efikamx-usb.c

diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile
index ee4a16e..860e4d2 100644
--- a/board/efikamx/Makefile
+++ b/board/efikamx/Makefile
@@ -28,6 +28,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).o
 
 COBJS	:= efikamx.o
+ifdef	CONFIG_CMD_USB
+COBJS	+= efikamx-usb.o
+endif
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c
new file mode 100644
index 0000000..4e5390f
--- /dev/null
+++ b/board/efikamx/efikamx-usb.c
@@ -0,0 +1,380 @@
+#include <common.h>
+#include <usb.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <usb/ehci-fsl.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#include <usb/ehci.h>
+#include <usb/ehci-core.h>
+
+/*
+ * Configure the USB H1 and USB H2 IOMUX
+ */
+#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
+			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
+			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
+void setup_iomux_usb(void)
+{
+	/*
+	 * Configure USBH1 pads
+	 */
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
+
+	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
+
+	/*
+	 * Configure USBH1 control pads
+	 */
+
+	/* USB PHY reset */
+	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+	/* USB HUB reset */
+	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE |
+			PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH);
+
+
+#ifdef	CONFIG_MACH_EFIKASB
+	/*
+	 * Configure USBH2 pads (used on EfikaSB)
+	 */
+	/* USBH2_DATA */
+	mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
+	mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
+
+	/* USBH2_CLK */
+	mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
+	/* USBH2_DIR */
+	mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
+	/* USBH2_STP */
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+	/* USBH2_NXT */
+	mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
+#endif
+
+	/* WIFI EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0);
+	/* WIFI RESET */
+	mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0);
+	/* BT EN (act low) */
+	mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0);
+}
+
+/*
+ * Enable devices connected to USB BUSes
+ */
+void efika_usb_enable_devices(void)
+{
+	/* Enable Bluetooth */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);
+
+	/* Enable WiFi */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+	udelay(10000);
+
+	/* Reset the WiFi chip */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+	udelay(10000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+}
+
+/*
+ * Reset USB HUB (or HUBs on EfikaSB)
+ */
+void efika_usb_hub_reset(void)
+{
+	/* HUB reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
+}
+
+/*
+ * Reset USB PHY (or PHYs on EfikaSB)
+ */
+void efika_usb_phy_reset(void)
+{
+	/* SMSC 3317 PHY reset */
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);
+}
+
+/*
+ * Configure control registers of the USB controller
+ */
+void control_regs_setup(struct usb_control_regs *control)
+{
+	clrsetbits_le32(&control->usbctrl,
+		(MXC_OTG_WUE | MXC_OTG_PM | MX51_H1_ULPI_IE | MX51_H1_WUE),
+		MX51_H1_PM);
+
+	clrsetbits_le32(&control->phyctrl0,
+			MX51_OTG_OVERCURD,
+			MX51_EHCI_POWERPINSE);
+
+	clrsetbits_le32(&control->phyctrl1,
+			MX51_SYSCLOCK_MASK,
+			MX51_SYSCLOCK_24_MHZ);
+
+	setbits_le32(&control->usbctrl1, MX51_H1_EXTCLKE);
+
+	clrsetbits_le32(&control->uh2ctrl,
+			(MX51_H2_ULPI_IE | MX51_H2_WUE),
+			MX51_H2_PM);
+
+	udelay(10000);
+}
+
+#define ULPI_ADDR_SHIFT		16
+#define ulpi_write_mask(value)	((value) & 0xff)
+#define ulpi_read_mask(value)	(((value) >> 8) & 0xff)
+
+u32 ulpi_wait(u32 ulpi_bit, const char *operation, struct usb_ehci *ehci)
+{
+	int timeout = ULPI_TIMEOUT;
+	u32 tmp;
+	while (--timeout) {
+		tmp = readl(&ehci->ulpi_viewpoint);
+		if (!(tmp & ulpi_bit))
+			break;
+		WATCHDOG_RESET();
+	}
+	if (!timeout) {
+		printf("ULPI %s timed out\n", operation);
+		return 0;
+	}
+	return tmp;
+}
+
+void ulpi_write(u8 *reg, u32 value, struct usb_ehci *ehci)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		ulpi_wait(ULPI_WU, "wakeup", ehci);
+	}
+	writel(ULPI_RWRUN | ULPI_RWCTRL |
+		(u32)reg << ULPI_ADDR_SHIFT | ulpi_write_mask(value),
+		&ehci->ulpi_viewpoint);
+
+	ulpi_wait(ULPI_RWRUN, "write", ehci);
+}
+
+u32 ulpi_read(u8 *reg, struct usb_ehci *ehci)
+{
+	if (!(readl(&ehci->ulpi_viewpoint) & ULPI_SS)) {
+		writel(ULPI_WU, &ehci->ulpi_viewpoint);
+		ulpi_wait(ULPI_WU, "wakeup", ehci);
+	}
+	writel(ULPI_RWRUN | (u32)reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);
+	return ulpi_read_mask(ulpi_wait(ULPI_RWRUN, "read", ehci));
+}
+
+void ulpi_init(struct ulpi_regs *ulpi, struct usb_ehci *ehci)
+{
+	u32 tmp = 0;
+	int reg, i;
+
+	/* get ID from ULPI immediate registers */
+	for (reg = ULPI_ID_REGS_COUNT - 1; reg >= 0; reg--)
+		tmp |= ulpi_read((u8 *)reg, ehci) << (reg * 8);
+	/* split into vendor and product ID */
+	debug("Found ULPI TX, ID %04x:%04x\n", tmp >> 16, tmp & 0xffff);
+
+	/* ULPI check integrity */
+	for (i = 0; i < 2; i++) {
+		ulpi_write(&ulpi->scratch_write, ULPI_TEST_VALUE << i, ehci);
+		tmp = ulpi_read(&ulpi->scratch_write, ehci);
+
+		if (tmp != (ULPI_TEST_VALUE << i)) {
+			printf("ULPI integrity check failed\n");
+			return;
+		}
+	}
+
+	/* ULPI set flags */
+	ulpi_write(&ulpi->otg_ctrl_write,
+		ULPI_OTG_EXT_VBUS_IND |
+		ULPI_OTG_DM_PULLDOWN | ULPI_OTG_DP_PULLDOWN, ehci);
+	ulpi_write(&ulpi->function_ctrl_write,
+		ULPI_FC_XCVR_SELECT | ULPI_FC_OPMODE_NORMAL |
+		ULPI_FC_SUSPENDM_PWRED, ehci);
+	ulpi_write(&ulpi->iface_ctrl_write, 0, ehci);
+	ulpi_write(&ulpi->otg_ctrl_set,
+		ULPI_OTG_DRV_VBUS | ULPI_OTG_DRV_VBUS_EXT, ehci);
+
+	/*
+	 * NOTE: This violates USB specification, but otherwise, USB on Efika
+	 * doesn't charge VBUS and as a result, USB doesn't work.
+	 */
+	ulpi_write(&ulpi->otg_ctrl_set, ULPI_OTG_CHRG_VBUS, ehci);
+}
+
+void ehci_fixup(uint32_t *status_reg, uint32_t *reg_ref)
+{
+
+	struct usb_ehci *ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH));
+	struct ulpi_regs *ulpi = (struct ulpi_regs *)0;
+	u32 tmp = ulpi_read(&ulpi->otg_ctrl_write, ehci);
+	tmp |= (1 << 4);
+	ulpi_write(&ulpi->otg_ctrl_write, tmp, ehci);
+	wait_ms(50);
+	/* terminate the reset */
+	*reg_ref = ehci_readl(status_reg);
+	*reg_ref |= EHCI_PS_PE;
+}
+
+void ehci0_init(struct usb_ehci *ehci)
+{
+	writel(MX51_16BIT_UTMI, &ehci->portsc);
+}
+
+void ehci1_init(struct usb_ehci *ehci, struct ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
+	udelay(10000);
+
+	clrbits_le32(&ehci->usbcmd, MX51_ITC_IMMEDIATE_MASK);
+	udelay(10000);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ulpi, ehci);
+}
+
+
+void ehci2_init(struct usb_ehci *ehci, struct ulpi_regs *ulpi)
+{
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT1);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, PAD_CTL_DRV_HIGH |
+				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 0);
+	udelay(1000);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A26), 1);
+	udelay(1000);
+
+	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
+	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
+
+	writel(MX51_ULPI_MODE_MASK, &ehci->portsc);
+	udelay(10000);
+
+	ulpi_init(ulpi, ehci);
+}
+
+int ehci_hcd_init(void)
+{
+	struct usb_ehci *ehci;
+	struct usb_control_regs *mx5_usb_control_regs;
+	struct ulpi_regs *ulpi;
+
+	/* Init iMX51 EHCI */
+	efika_usb_phy_reset();
+	efika_usb_hub_reset();
+	efika_usb_enable_devices();
+
+	mx5_usb_control_regs = (struct usb_control_regs *)(OTG_BASE_ADDR +
+		 MX51_CTRL_REGS);
+	control_regs_setup(mx5_usb_control_regs);
+
+	ulpi = (struct ulpi_regs *)0;
+	/* Init EHCI core */
+	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
+		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
+	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr +
+			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+	setbits_le32(&ehci->usbmode, CM_HOST);
+	setbits_le32(&ehci->control, USB_EN);
+
+	switch (CONFIG_MXC_USB_PORT) {
+	case 0:
+		ehci0_init(ehci);
+		break;
+	case 1:
+		ehci1_init(ehci, ulpi);
+		break;
+#ifdef	MACH_EFIKASB
+	case 2:
+		ehci2_init(ehci, ulpi);
+		break;
+#endif
+	};
+
+	/* EfikaMX USB has issues ... */
+	udelay(10000);
+
+
+	return 0;
+}
+
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c
index 5be1f6c..51c1854 100644
--- a/board/efikamx/efikamx.c
+++ b/board/efikamx/efikamx.c
@@ -489,6 +489,15 @@ static inline void setup_iomux_ata(void) { }
 #endif
 
 /*
+ * EHCI USB
+ */
+#ifdef	CONFIG_CMD_USB
+void setup_iomux_usb(void);
+#else
+static inline void setup_iomux_usb(void) { }
+#endif
+
+/*
  * LED configuration
  */
 void setup_iomux_led(void)
@@ -621,6 +630,7 @@ int board_late_init(void)
 
 	setup_iomux_led();
 	setup_iomux_ata();
+	setup_iomux_usb();
 
 	efikamx_toggle_led(EFIKAMX_LED_BLUE);
 
diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h
index fdd0a14..9632b5d 100644
--- a/include/configs/efikamx.h
+++ b/include/configs/efikamx.h
@@ -40,6 +40,10 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x97800000
 
+#define	CONFIG_L2_OFF
+#define	CONFIG_SYS_ICACHE_OFF
+#define	CONFIG_SYS_DCACHE_OFF
+
 /*
  * Bootloader Components Configuration
  */
@@ -168,6 +172,18 @@
 #endif
 
 /*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_MXC_USB_PORT	1
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define	CONFIG_USB_KEYBOARD
+#endif /* CONFIG_CMD_USB */
+
+/*
  * Filesystems
  */
 #ifdef CONFIG_CMD_FAT
-- 
1.7.6.3

[U-Boot] [PATCH v4 4/4] Add USB support for Efika

[Marek Vasut]

On Sunday, September 25, 2011 07:25:10 PM Jana Rapava wrote:
> This commit adds USB support for EfikaMX and EfikaSB.
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes for v2:
>       - changed to proper patch
> Changes for v3:
>       - merged other USB patches from u-boot-pxa/efikasb
>       - offset-based access changed to struct-based access
>       - use {clrset,clr,set}bits_le32() calls
>       - CodingStyle and naming cleanup
> Changes for v4:
>        - split into patchset
>        - CodingStyle and naming cleanup
>        - remove endless loops
>        - silence compiler warnings
> 

Dear Jana Rapava,

[...]
> +
> +u32 ulpi_wait(u32 ulpi_bit, const char *operation, struct usb_ehci *ehci)

Put struct usb_ehci * at the first place.

> +{
> +	int timeout = ULPI_TIMEOUT;
> +	u32 tmp;

Better separation of chunks of code with newlines will help readability. Please 
fix globally.

> +	while (--timeout) {
> +		tmp = readl(&ehci->ulpi_viewpoint);
> +		if (!(tmp & ulpi_bit))
> +			break;
> +		WATCHDOG_RESET();
> +	}
> +	if (!timeout) {
> +		printf("ULPI %s timed out\n", operation);
> +		return 0;
> +	}
> +	return tmp;
> +}
> +
> +void ulpi_write(u8 *reg, u32 value, struct usb_ehci *ehci)

ulpi_write(ehci, reg, value), please fix globally and in similar functions.

Also, change u8 *reg to u8 reg, why are you passing a pointer?

[...]

> +
> +int ehci_hcd_init(void)
> +{
> +	struct usb_ehci *ehci;
> +	struct usb_control_regs *mx5_usb_control_regs;
> +	struct ulpi_regs *ulpi;
> +
> +	/* Init iMX51 EHCI */
> +	efika_usb_phy_reset();
> +	efika_usb_hub_reset();
> +	efika_usb_enable_devices();
> +
> +	mx5_usb_control_regs = (struct usb_control_regs *)(OTG_BASE_ADDR +
> +		 MX51_CTRL_REGS);

rename to MX5_CTRL_REGS_OFFSET.

> +	control_regs_setup(mx5_usb_control_regs);
> +
> +	ulpi = (struct ulpi_regs *)0;
> +	/* Init EHCI core */
> +	ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
> +		(MX51_REGISTER_LAYOUT_LENGTH * CONFIG_MXC_USB_PORT));
> +	hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
> +	hcor = (struct ehci_hcor *)((uint32_t) hccr +
> +			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> +	setbits_le32(&ehci->usbmode, CM_HOST);
> +	setbits_le32(&ehci->control, USB_EN);
> +
> +	switch (CONFIG_MXC_USB_PORT) {
> +	case 0:
> +		ehci0_init(ehci);
> +		break;
> +	case 1:
> +		ehci1_init(ehci, ulpi);
> +		break;
> +#ifdef	MACH_EFIKASB
> +	case 2:
> +		ehci2_init(ehci, ulpi);
> +		break;
> +#endif
> +	};
> +
> +	/* EfikaMX USB has issues ... */
> +	udelay(10000);
> +
> +

One newline is enough.

> +	return 0;
> +}
> +

Cheers

[U-Boot] [PATCH v4 4/4] Add USB support for Efika

[Jana Rapava]

> > +     while (--timeout) {
> > +             tmp = readl(&ehci->ulpi_viewpoint);
> > +             if (!(tmp & ulpi_bit))
> > +                     break;
> > +             WATCHDOG_RESET();
> > +     }
> > +     if (!timeout) {
> > +             printf("ULPI %s timed out\n", operation);
> > +             return 0;
> > +     }
> > +     return tmp;
> > +}
> > +
> > +void ulpi_write(u8 *reg, u32 value, struct usb_ehci *ehci)
>
> ulpi_write(ehci, reg, value), please fix globally and in similar functions.
>
> Also, change u8 *reg to u8 reg, why are you passing a pointer?
>

Is it really important in ulpi_read/write function to use u8 reg instead of
u8 *reg?
When I rewrite this, usb reset starts giving me ULPI operations timeout, and
I couldn't find a source of that.
The problem is in the middle of usb_new_device, but it looks like no
function calling ULPI operations is called from that function.

Regards,
Jana Rapava

[U-Boot] [PATCH v4 4/4] Add USB support for Efika

[Marek Vasut]

On Monday, September 26, 2011 10:28:17 PM Jana Rapava wrote:
> > > +     while (--timeout) {
> > > +             tmp = readl(&ehci->ulpi_viewpoint);
> > > +             if (!(tmp & ulpi_bit))
> > > +                     break;
> > > +             WATCHDOG_RESET();
> > > +     }
> > > +     if (!timeout) {
> > > +             printf("ULPI %s timed out\n", operation);
> > > +             return 0;
> > > +     }
> > > +     return tmp;
> > > +}
> > > +
> > > +void ulpi_write(u8 *reg, u32 value, struct usb_ehci *ehci)
> > 
> > ulpi_write(ehci, reg, value), please fix globally and in similar
> > functions.
> > 
> > Also, change u8 *reg to u8 reg, why are you passing a pointer?
> 
> Is it really important in ulpi_read/write function to use u8 reg instead of
> u8 *reg?

Yes

> When I rewrite this, usb reset starts giving me ULPI operations timeout,
> and I couldn't find a source of that.
> The problem is in the middle of usb_new_device, but it looks like no
> function calling ULPI operations is called from that function.

No idea, verify what you're passing to the functions.

Cheers
> 
> Regards,
> Jana Rapava

[U-Boot] [PATCH v4 4/4] Add USB support for Efika

[Marek Vasut]

On Monday, September 26, 2011 10:28:17 PM Jana Rapava wrote:
> > > +     while (--timeout) {
> > > +             tmp = readl(&ehci->ulpi_viewpoint);
> > > +             if (!(tmp & ulpi_bit))
> > > +                     break;
> > > +             WATCHDOG_RESET();
> > > +     }
> > > +     if (!timeout) {
> > > +             printf("ULPI %s timed out\n", operation);
> > > +             return 0;
> > > +     }
> > > +     return tmp;
> > > +}
> > > +
> > > +void ulpi_write(u8 *reg, u32 value, struct usb_ehci *ehci)
> > 
> > ulpi_write(ehci, reg, value), please fix globally and in similar
> > functions.
> > 
> > Also, change u8 *reg to u8 reg, why are you passing a pointer?
> 
> Is it really important in ulpi_read/write function to use u8 reg instead of
> u8 *reg?
> When I rewrite this, usb reset starts giving me ULPI operations timeout,
> and I couldn't find a source of that.
> The problem is in the middle of usb_new_device, but it looks like no
> function calling ULPI operations is called from that function.

Actually I think this is the problem:
       writel(ULPI_RWRUN | (u32)reg << ULPI_ADDR_SHIFT, &ehci->ulpi_viewpoint);

You cast the u8 * to u32, making the whole first argument of writel() an u32. 
Whereas in the other case, when passing u8, the first argument stays u8 and the 
result is truncated.
> 
> Regards,
> Jana Rapava

[U-Boot] [PATCH v4 4/4] Add USB support for Efika

[Jana Rapava]

> Actually I think this is the problem:
>       writel(ULPI_RWRUN | (u32)reg << ULPI_ADDR_SHIFT,
> &ehci->ulpi_viewpoint);
>
> You cast the u8 * to u32, making the whole first argument of writel() an
> u32.
> Whereas in the other case, when passing u8, the first argument stays u8 and
> the
> result is truncated.
>
Thanks, but I had to change the type from u8 to u32 to silence compiler
warnings and it's solved the problem too.

Regards,
Jana Rapava

[U-Boot] [PATCH v4 1/4] USB: move ehci.h and ehci-core.h into /include/usb/

[Fabio Estevam]

Jana,

On Sun, Sep 25, 2011 at 2:25 PM, Jana Rapava <fermata7@gmail.com> wrote:
...
> ?drivers/usb/host/ehci-core.h ? ? | ? 29 ------
> ?drivers/usb/host/ehci-fsl.c ? ? ?| ? ?4 +-
> ?drivers/usb/host/ehci-hcd.c ? ? ?| ? ?2 +-
> ?drivers/usb/host/ehci-kirkwood.c | ? ?4 +-
> ?drivers/usb/host/ehci-mpc512x.c ?| ? ?4 +-
> ?drivers/usb/host/ehci-pci.c ? ? ?| ? ?4 +-
> ?drivers/usb/host/ehci-ppc4xx.c ? | ? ?4 +-
> ?drivers/usb/host/ehci.h ? ? ? ? ?| ?203 --------------------------------------
> ?include/usb/ehci-core.h ? ? ? ? ?| ? 29 ++++++
> ?include/usb/ehci.h ? ? ? ? ? ? ? | ?203 ++++++++++++++++++++++++++++++++++++++
> ?10 files changed, 243 insertions(+), 243 deletions(-)
> ?delete mode 100644 drivers/usb/host/ehci-core.h
> ?delete mode 100644 drivers/usb/host/ehci.h
> ?create mode 100644 include/usb/ehci-core.h
> ?create mode 100644 include/usb/ehci.h

This will break some drivers as you missed to update:

drivers/usb/host/ehci-ixp4xx.c
drivers/usb/host/ehci-mxc.c
drivers/usb/host/ehci-vct.c

Why don?t you just resend my original patch (put my name in the From:
field) as part of this series?
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/109335

My original patch is complete.

Regards,

Fabio Estevam

[U-Boot] [PATCH v4 1/4] USB: move ehci.h and ehci-core.h into /include/usb/

[Jana Rapava]

Why don?t you just resend my original patch (put my name in the From:

> field) as part of this series?
> http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/109335
>

Thanks, I'll be glad to use it.

Regards,
Jana Rapava

[U-Boot] [PATCH v4 1/4] USB: move ehci.h and ehci-core.h into /include/usb/

[Marek Vasut]

On Sunday, September 25, 2011 07:25:07 PM Jana Rapava wrote:
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Remy Bohmer <linux@bohmer.net>
> Cc: Fabio Estevam <festevam@gmail.com>
> ---
> Changes for v2:
>       - changed to proper patch
> Changes for v3:
>       - merged other USB patches from u-boot-pxa/efikasb
>       - offset-based access changed to struct-based access
>       - use {clrset,clr,set}bits_le32() calls
>       - CodingStyle and naming cleanup
> Changes for v4:
>        - split into patchset
>        - move ehci.h and ehci-core.h into /include/usb/
> 

Uh,

I have totally no idea which is the last set of patches here now anymore. 
Anyway, is there any update or is this plain stuck ?

Cheers

[U-Boot] [PATCH v4 1/4] USB: move ehci.h and ehci-core.h into /include/usb/

[Jana Rapava]

2011/10/9 Marek Vasut <marek.vasut@gmail.com>

> On Sunday, September 25, 2011 07:25:07 PM Jana Rapava wrote:
> > Signed-off-by: Jana Rapava <fermata7@gmail.com>
> > Cc: Marek Vasut <marek.vasut@gmail.com>
> > Cc: Remy Bohmer <linux@bohmer.net>
> > Cc: Fabio Estevam <festevam@gmail.com>
> > ---
> > Changes for v2:
> >       - changed to proper patch
> > Changes for v3:
> >       - merged other USB patches from u-boot-pxa/efikasb
> >       - offset-based access changed to struct-based access
> >       - use {clrset,clr,set}bits_le32() calls
> >       - CodingStyle and naming cleanup
> > Changes for v4:
> >        - split into patchset
> >        - move ehci.h and ehci-core.h into /include/usb/
> >
>
> Uh,
>
> I have totally no idea which is the last set of patches here now anymore.
> Anyway, is there any update or is this plain stuck ?
>
> Cheers
>

Last set of patches is there:
[0/4] http://lists.denx.de/pipermail/u-boot/2011-September/102729.html
[1/4] http://lists.denx.de/pipermail/u-boot/2011-September/102720.html
[2/4] http://lists.denx.de/pipermail/u-boot/2011-September/102719.html
[3/4] http://lists.denx.de/pipermail/u-boot/2011-September/102721.html
[4/4] http://lists.denx.de/pipermail/u-boot/2011-September/102803.html

I haven't found time to work on this recently, I have some problems in
school which I absolutely have to solve first.
Regards,
Jana Rapava

[U-Boot] [PATCH v4 1/4] USB: move ehci.h and ehci-core.h into /include/usb/

[Fabio Estevam]

Jana,

On Sun, Oct 9, 2011 at 5:22 PM, Jana Rapava <fermata7@gmail.com> wrote:

> I haven't found time to work on this recently, I have some problems in
> school which I absolutely have to solve first.

I have just resent an updated 1/4 after getting feedback from the list.

Let's wait and see if it gets merged and then you resend your series
without 1/4.

Regards,

Fabio Estevam

[U-Boot] [PATCH v4 1/4] USB: move ehci.h and ehci-core.h into /include/usb/

[Marek Vasut]

On Friday, October 14, 2011 05:49:50 PM Fabio Estevam wrote:
> Jana,
> 
> On Sun, Oct 9, 2011 at 5:22 PM, Jana Rapava <fermata7@gmail.com> wrote:
> > I haven't found time to work on this recently, I have some problems in
> > school which I absolutely have to solve first.
> 
> I have just resent an updated 1/4 after getting feedback from the list.
> 
> Let's wait and see if it gets merged and then you resend your series
> without 1/4.

I'm quite eagerly waiting for this to be mainlined, honestly. It'd close one 
whole chapter in the efika storyline.

Cheers

[U-Boot] [PATCH v4 1/4] USB: move ehci.h and ehci-core.h into /include/usb/

[Marek Vasut]

On Sunday, October 09, 2011 10:22:03 PM Jana Rapava wrote:
> 2011/10/9 Marek Vasut <marek.vasut@gmail.com>
> 
> > On Sunday, September 25, 2011 07:25:07 PM Jana Rapava wrote:
> > > Signed-off-by: Jana Rapava <fermata7@gmail.com>
> > > Cc: Marek Vasut <marek.vasut@gmail.com>
> > > Cc: Remy Bohmer <linux@bohmer.net>
> > > Cc: Fabio Estevam <festevam@gmail.com>
> > > ---
> > > 
> > > Changes for v2:
> > >       - changed to proper patch
> > > 
> > > Changes for v3:
> > >       - merged other USB patches from u-boot-pxa/efikasb
> > >       - offset-based access changed to struct-based access
> > >       - use {clrset,clr,set}bits_le32() calls
> > >       - CodingStyle and naming cleanup
> > > 
> > > Changes for v4:
> > >        - split into patchset
> > >        - move ehci.h and ehci-core.h into /include/usb/
> > 
> > Uh,
> > 
> > I have totally no idea which is the last set of patches here now anymore.
> > Anyway, is there any update or is this plain stuck ?
> > 
> > Cheers
> 
> Last set of patches is there:
> [0/4] http://lists.denx.de/pipermail/u-boot/2011-September/102729.html
> [1/4] http://lists.denx.de/pipermail/u-boot/2011-September/102720.html
> [2/4] http://lists.denx.de/pipermail/u-boot/2011-September/102719.html
> [3/4] http://lists.denx.de/pipermail/u-boot/2011-September/102721.html
> [4/4] http://lists.denx.de/pipermail/u-boot/2011-September/102803.html
> 
> I haven't found time to work on this recently, I have some problems in
> school which I absolutely have to solve first.
> Regards,
> Jana Rapava

Remy, bump ?

[U-Boot] [PATCH 1/2 v2] USB cleanup for EfikaMX

[Wolfgang Denk]

Dear Jana Rapava,

In message <1315848040-11962-1-git-send-email-fermata7@gmail.com> you wrote:
> /board/efikamx/efikamx-usb.c: cleanup
> 
> Signed-off-by: Jana Rapava <fermata7@gmail.com>
> ---
>  board/efikamx/efikamx-usb.c |  111 +++++++++++++++++++++++--------------------
>  include/usb/ehci-fsl.h      |   49 +++++++++++++++++++
>  2 files changed, 108 insertions(+), 52 deletions(-)

Checkpatch says:

total: 3 errors, 2 warnings, 239 lines checked

Please clean up and resubmit.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Each kiss is as the first.
	-- Miramanee, Kirk's wife, "The Paradise Syndrome",
	   stardate 4842.6