* [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization
@ 2020-03-13 9:01 ` Dmitry Osipenko
0 siblings, 0 replies; 6+ messages in thread
From: Dmitry Osipenko @ 2020-03-13 9:01 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Nicolas Chauvet
Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
The PL310 Auxiliary Control Register shouldn't have the "Full line of
zero" optimization bit being set before L2 cache is enabled. The L2X0
driver takes care of enabling the optimization by itself.
This patch fixes a noisy error message on Tegra20 and Tegra30 telling
that cache optimization is erroneously enabled without enabling it for
the CPU:
L2C-310: enabling full line of zeros but not enabled in Cortex-A9
Cc: <stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/mach-tegra/tegra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index f1ce2857a251..b620b0651157 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -107,8 +107,8 @@ static const char * const tegra_dt_board_compat[] = {
};
DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
- .l2c_aux_val = 0x3c400001,
- .l2c_aux_mask = 0xc20fc3fe,
+ .l2c_aux_val = 0x3c400000,
+ .l2c_aux_mask = 0xc20fc3ff,
.smp = smp_ops(tegra_smp_ops),
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization
@ 2020-03-13 9:01 ` Dmitry Osipenko
0 siblings, 0 replies; 6+ messages in thread
From: Dmitry Osipenko @ 2020-03-13 9:01 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Nicolas Chauvet
Cc: linux-tegra, Russell King, linux-arm-kernel
The PL310 Auxiliary Control Register shouldn't have the "Full line of
zero" optimization bit being set before L2 cache is enabled. The L2X0
driver takes care of enabling the optimization by itself.
This patch fixes a noisy error message on Tegra20 and Tegra30 telling
that cache optimization is erroneously enabled without enabling it for
the CPU:
L2C-310: enabling full line of zeros but not enabled in Cortex-A9
Cc: <stable@vger.kernel.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/tegra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index f1ce2857a251..b620b0651157 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -107,8 +107,8 @@ static const char * const tegra_dt_board_compat[] = {
};
DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
- .l2c_aux_val = 0x3c400001,
- .l2c_aux_mask = 0xc20fc3fe,
+ .l2c_aux_val = 0x3c400000,
+ .l2c_aux_mask = 0xc20fc3ff,
.smp = smp_ops(tegra_smp_ops),
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread[parent not found: <20200313090104.20750-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization
2020-03-13 9:01 ` Dmitry Osipenko
@ 2020-03-13 10:05 ` Nicolas Chauvet
-1 siblings, 0 replies; 6+ messages in thread
From: Nicolas Chauvet @ 2020-03-13 10:05 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Le ven. 13 mars 2020 à 10:02, Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> a écrit :
>
> The PL310 Auxiliary Control Register shouldn't have the "Full line of
> zero" optimization bit being set before L2 cache is enabled. The L2X0
> driver takes care of enabling the optimization by itself.
>
> This patch fixes a noisy error message on Tegra20 and Tegra30 telling
> that cache optimization is erroneously enabled without enabling it for
> the CPU:
>
> L2C-310: enabling full line of zeros but not enabled in Cortex-A9
>
> Cc: <stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Nicolas Chauvet <kwizart-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This was tested on paz00 (tegra20).
Also tested that suspend still works.
Thanks for fixing this long standing issue!
--
-
Nicolas (kwizart)
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization
@ 2020-03-13 10:05 ` Nicolas Chauvet
0 siblings, 0 replies; 6+ messages in thread
From: Nicolas Chauvet @ 2020-03-13 10:05 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: linux-tegra, Thierry Reding, Russell King, linux-arm-kernel,
Jonathan Hunter
Le ven. 13 mars 2020 à 10:02, Dmitry Osipenko <digetx@gmail.com> a écrit :
>
> The PL310 Auxiliary Control Register shouldn't have the "Full line of
> zero" optimization bit being set before L2 cache is enabled. The L2X0
> driver takes care of enabling the optimization by itself.
>
> This patch fixes a noisy error message on Tegra20 and Tegra30 telling
> that cache optimization is erroneously enabled without enabling it for
> the CPU:
>
> L2C-310: enabling full line of zeros but not enabled in Cortex-A9
>
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
This was tested on paz00 (tegra20).
Also tested that suspend still works.
Thanks for fixing this long standing issue!
--
-
Nicolas (kwizart)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization
2020-03-13 9:01 ` Dmitry Osipenko
@ 2020-05-06 16:44 ` Thierry Reding
-1 siblings, 0 replies; 6+ messages in thread
From: Thierry Reding @ 2020-05-06 16:44 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, Nicolas Chauvet,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
[-- Attachment #1: Type: text/plain, Size: 804 bytes --]
On Fri, Mar 13, 2020 at 12:01:04PM +0300, Dmitry Osipenko wrote:
> The PL310 Auxiliary Control Register shouldn't have the "Full line of
> zero" optimization bit being set before L2 cache is enabled. The L2X0
> driver takes care of enabling the optimization by itself.
>
> This patch fixes a noisy error message on Tegra20 and Tegra30 telling
> that cache optimization is erroneously enabled without enabling it for
> the CPU:
>
> L2C-310: enabling full line of zeros but not enabled in Cortex-A9
>
> Cc: <stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> Signed-off-by: Dmitry Osipenko <digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm/mach-tegra/tegra.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Applied to for-5.8/arm/core, thanks.
Thierry
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization
@ 2020-05-06 16:44 ` Thierry Reding
0 siblings, 0 replies; 6+ messages in thread
From: Thierry Reding @ 2020-05-06 16:44 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Nicolas Chauvet, linux-tegra, Russell King, linux-arm-kernel,
Jonathan Hunter
[-- Attachment #1.1: Type: text/plain, Size: 750 bytes --]
On Fri, Mar 13, 2020 at 12:01:04PM +0300, Dmitry Osipenko wrote:
> The PL310 Auxiliary Control Register shouldn't have the "Full line of
> zero" optimization bit being set before L2 cache is enabled. The L2X0
> driver takes care of enabling the optimization by itself.
>
> This patch fixes a noisy error message on Tegra20 and Tegra30 telling
> that cache optimization is erroneously enabled without enabling it for
> the CPU:
>
> L2C-310: enabling full line of zeros but not enabled in Cortex-A9
>
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> arch/arm/mach-tegra/tegra.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Applied to for-5.8/arm/core, thanks.
Thierry
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
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2020-03-13 9:01 [PATCH v1] ARM: tegra: Correct PL310 Auxiliary Control Register initialization Dmitry Osipenko
2020-03-13 9:01 ` Dmitry Osipenko
[not found] ` <20200313090104.20750-1-digetx-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2020-03-13 10:05 ` Nicolas Chauvet
2020-03-13 10:05 ` Nicolas Chauvet
2020-05-06 16:44 ` Thierry Reding
2020-05-06 16:44 ` Thierry Reding
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