From: Hongbo Zhang <macro.wave.z@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM
Date: Tue, 28 Jun 2016 18:45:18 +0800 [thread overview]
Message-ID: <CABxX_wOdBasuZdysz0g3VFNUK=YCrV+CXGFo3bL==r588vftdA@mail.gmail.com> (raw)
In-Reply-To: <CAGb2v65JvA+Qh1wnPh=2PWGC_L6QciaH_T=8GopJCA-XaEV0qg@mail.gmail.com>
On Tue, Jun 28, 2016 at 12:16 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Tue, Jun 14, 2016 at 3:01 PM, <macro.wave.z@gmail.com> wrote:
>> From: Hongbo Zhang <hongbo.zhang@nxp.com>
>>
>> LS1021 offers two secure OCRAM blocks for trustzone.
>> This patch moves all the secure text sections into the OCRAM.
>>
>> Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
>> ---
>> arch/arm/include/asm/arch-ls102xa/config.h | 2 +-
>> include/configs/ls1021atwr.h | 2 ++
>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
>> index 7a0e4bf..4729044 100644
>> --- a/arch/arm/include/asm/arch-ls102xa/config.h
>> +++ b/arch/arm/include/asm/arch-ls102xa/config.h
>> @@ -10,7 +10,7 @@
>> #define CONFIG_SYS_CACHELINE_SIZE 64
>>
>> #define OCRAM_BASE_ADDR 0x10000000
>> -#define OCRAM_SIZE 0x00020000
>> +#define OCRAM_SIZE 0x00010000
>> #define OCRAM_BASE_S_ADDR 0x10010000
>> #define OCRAM_S_SIZE 0x00010000
>>
>> diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
>> index 9d0c4fe..e6fbd77 100644
>> --- a/include/configs/ls1021atwr.h
>> +++ b/include/configs/ls1021atwr.h
>> @@ -12,6 +12,8 @@
>> #define CONFIG_ARMV7_PSCI
>> #define CONFIG_ARMV7_PSCI_1_0
>>
>> +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
>> +
>> #define CONFIG_SYS_FSL_CLK
>>
>> #define CONFIG_DISPLAY_CPUINFO
>> --
>> 2.1.4
>>
>
> The patch itself looks good. Though I wonder if there's some register
> you need to configure to split access to the 2 SRAM blocks? If they
> are both secure-only, then everything's fine.
>
No other registers needed to be configured, this works fine.
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Thanks for the tag.
next prev parent reply other threads:[~2016-06-28 10:45 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-14 7:01 [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support macro.wave.z at gmail.com
2016-06-14 7:01 ` [U-Boot] [PATCH v5 1/8] ARMv7: PSCI: add PSCI v1.0 functions skeleton macro.wave.z at gmail.com
2016-06-14 7:01 ` [U-Boot] [PATCH v5 2/8] ARMv7: PSCI: factor out reusable psci_cpu_on_common macro.wave.z at gmail.com
2016-06-28 2:49 ` Chen-Yu Tsai
2016-06-28 3:50 ` Hongbo Zhang
2016-06-14 7:01 ` [U-Boot] [PATCH v5 3/8] ARMv7: PSCI: update the place of saving target PC macro.wave.z at gmail.com
2016-06-28 3:24 ` Chen-Yu Tsai
2016-06-28 9:23 ` Hongbo Zhang
2016-06-28 9:48 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 4/8] ARMv7: PSCI: add codes to save context ID for CPU_ON macro.wave.z at gmail.com
2016-06-28 3:15 ` Chen-Yu Tsai
2016-06-28 10:29 ` Hongbo Zhang
2016-06-14 7:01 ` [U-Boot] [PATCH v5 5/8] ARMv7: PSCI: ls102xa: check target CPU ID before further operations macro.wave.z at gmail.com
2016-06-28 4:10 ` Chen-Yu Tsai
2016-06-28 10:39 ` Hongbo Zhang
2016-06-14 7:01 ` [U-Boot] [PATCH v5 6/8] ARMv7: PSCI: ls102xa: check ALREADY_ON or ON_PENDING for CPU_ON macro.wave.z at gmail.com
2016-06-28 4:30 ` Chen-Yu Tsai
2016-06-30 4:24 ` Hongbo Zhang
2016-06-30 14:47 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 7/8] ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention macro.wave.z at gmail.com
2016-06-30 14:45 ` Chen-Yu Tsai
2016-06-14 7:01 ` [U-Boot] [PATCH v5 8/8] ARMv7: PSCI: ls102xa: move secure text section into OCRAM macro.wave.z at gmail.com
2016-06-28 4:16 ` Chen-Yu Tsai
2016-06-28 10:45 ` Hongbo Zhang [this message]
2016-06-15 7:16 ` [U-Boot] [PATCH v5 0/8] ARMv7: PSCI: add PSCI v1.0 support Chen-Yu Tsai
2016-06-15 7:39 ` Marc Zyngier
2016-06-15 8:08 ` Hongbo Zhang
2016-06-24 15:26 ` york sun
2016-06-30 5:28 ` Hongbo Zhang
2016-07-04 7:20 ` Hongbo Zhang
2016-07-04 13:11 ` Hans de Goede
2016-07-05 2:26 ` Hongbo Zhang
2016-07-19 20:34 ` york sun
2016-07-21 4:21 ` Hongbo Zhang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CABxX_wOdBasuZdysz0g3VFNUK=YCrV+CXGFo3bL==r588vftdA@mail.gmail.com' \
--to=macro.wave.z@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.