* [U-Boot] [PATCH] ARM: IGEP0033: Update timing to run DDR at 400MHz.
@ 2013-09-10 9:12 Enric Balletbo i Serra
2013-09-12 10:25 ` Javier Martinez Canillas
0 siblings, 1 reply; 2+ messages in thread
From: Enric Balletbo i Serra @ 2013-09-10 9:12 UTC (permalink / raw)
To: u-boot
From: Enric Balletbo i Serra <eballetbo@iseebcn.com>
We can run the DDR at 400MHz, so update the timings for that purpose.
Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
---
arch/arm/include/asm/arch-am33xx/ddr_defs.h | 24 ++++++++++++------------
board/isee/igep0033/board.c | 4 ++--
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 95f7a9a..fe48b5f 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -110,20 +110,20 @@
#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
/* Samsung K4B2G1646E-BIH9 */
-#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
-#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
-#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
-#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
-#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
-#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
+#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
+#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
+#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
+#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
+#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
-#define K4B2G1646EBIH9_RATIO 0x40
-#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
-#define K4B2G1646EBIH9_RD_DQS 0x3B
-#define K4B2G1646EBIH9_WR_DQS 0x85
-#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
-#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
+#define K4B2G1646EBIH9_RATIO 0x80
+#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
+#define K4B2G1646EBIH9_RD_DQS 0x35
+#define K4B2G1646EBIH9_WR_DQS 0x3A
+#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
+#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
#define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
/**
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 9e91f68..a9c34c6 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -64,7 +64,7 @@ static struct emif_regs ddr3_emif_reg_data = {
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
- 303, OSC-1, 1, -1, -1, -1, -1};
+ 400, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
@@ -83,7 +83,7 @@ void set_mux_conf_regs(void)
void sdram_init(void)
{
- config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
+ config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif
--
1.8.1.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot] [PATCH] ARM: IGEP0033: Update timing to run DDR at 400MHz.
2013-09-10 9:12 [U-Boot] [PATCH] ARM: IGEP0033: Update timing to run DDR at 400MHz Enric Balletbo i Serra
@ 2013-09-12 10:25 ` Javier Martinez Canillas
0 siblings, 0 replies; 2+ messages in thread
From: Javier Martinez Canillas @ 2013-09-12 10:25 UTC (permalink / raw)
To: u-boot
On Tue, Sep 10, 2013 at 11:12 AM, Enric Balletbo i Serra
<eballetbo@gmail.com> wrote:
> From: Enric Balletbo i Serra <eballetbo@iseebcn.com>
>
> We can run the DDR at 400MHz, so update the timings for that purpose.
>
> Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
> ---
> arch/arm/include/asm/arch-am33xx/ddr_defs.h | 24 ++++++++++++------------
> board/isee/igep0033/board.c | 4 ++--
> 2 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> index 95f7a9a..fe48b5f 100644
> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> @@ -110,20 +110,20 @@
> #define MT41J512M8RH125_IOCTRL_VALUE 0x18B
>
> /* Samsung K4B2G1646E-BIH9 */
> -#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
> -#define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
> -#define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
> -#define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
> -#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
> -#define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
> +#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
> +#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
> +#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
> +#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
> +#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
> +#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
> #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
> #define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
> -#define K4B2G1646EBIH9_RATIO 0x40
> -#define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
> -#define K4B2G1646EBIH9_RD_DQS 0x3B
> -#define K4B2G1646EBIH9_WR_DQS 0x85
> -#define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
> -#define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
> +#define K4B2G1646EBIH9_RATIO 0x80
> +#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
> +#define K4B2G1646EBIH9_RD_DQS 0x35
> +#define K4B2G1646EBIH9_WR_DQS 0x3A
> +#define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
> +#define K4B2G1646EBIH9_PHY_WR_DATA 0x76
> #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
>
> /**
> diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
> index 9e91f68..a9c34c6 100644
> --- a/board/isee/igep0033/board.c
> +++ b/board/isee/igep0033/board.c
> @@ -64,7 +64,7 @@ static struct emif_regs ddr3_emif_reg_data = {
>
> #define OSC (V_OSCK/1000000)
> const struct dpll_params dpll_ddr = {
> - 303, OSC-1, 1, -1, -1, -1, -1};
> + 400, OSC-1, 1, -1, -1, -1, -1};
>
> const struct dpll_params *get_dpll_ddr_params(void)
> {
> @@ -83,7 +83,7 @@ void set_mux_conf_regs(void)
>
> void sdram_init(void)
> {
> - config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
> + config_ddr(400, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
> &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
> }
> #endif
> --
> 1.8.1.2
>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2013-09-10 9:12 [U-Boot] [PATCH] ARM: IGEP0033: Update timing to run DDR at 400MHz Enric Balletbo i Serra
2013-09-12 10:25 ` Javier Martinez Canillas
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