* [PATCH] Enable FBC on IVB architecture.
@ 2011-10-20 16:28 Eugeni Dodonov
2011-10-20 16:34 ` Eugeni Dodonov
0 siblings, 1 reply; 8+ messages in thread
From: Eugeni Dodonov @ 2011-10-20 16:28 UTC (permalink / raw)
To: intel-gfx; +Cc: Eugeni Dodonov
This is mostly similar to Ironlake, with some register changes and
additional tricks.
Jesse mentioned that it would make more sense to move those bits into
ivb-specific functions instead of making this work within ironlake ones,
so I added the corresponding functions and setup their pointers
accordingly.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 13 +++++
drivers/gpu/drm/i915/intel_display.c | 85 ++++++++++++++++++++++++++++++++-
3 files changed, 97 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f07e425..66ab204 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -226,6 +226,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
static const struct intel_device_info intel_ivybridge_d_info = {
.is_ivybridge = 1, .gen = 7,
.need_gfx_hws = 1, .has_hotplug = 1,
+ .has_fbc = 1, /* Attempt at enabling FBC on IvyBridge mobile */
.has_bsd_ring = 1,
.has_blt_ring = 1,
};
@@ -233,7 +234,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
static const struct intel_device_info intel_ivybridge_m_info = {
.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
- .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
+ .has_fbc = 1, /* Attempt at enabling FBC on IvyBridge mobile */
.has_bsd_ring = 1,
.has_blt_ring = 1,
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 542453f..c1a97a6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -627,6 +627,8 @@
#define ILK_DISPLAY_CHICKEN1 0x42000
#define ILK_FBCQ_DIS (1<<22)
#define ILK_PABSTRETCH_DIS (1<<21)
+#define IVB_DPR_VS_FBCQ_DIS (1<<22)
+
/*
@@ -638,6 +640,17 @@
#define SNB_CPU_FENCE_ENABLE (1<<29)
#define DPFC_CPU_FENCE_OFFSET 0x100104
+/*
+ * Framebuffer compression for IVB
+ *
+ * Mostly similar to ILK with some changes
+ */
+
+/* Controlled via ILK_DPFC_CONTROL */
+#define IVB_FBC_CTL_PLANEA (0<<29)
+#define IVB_FBC_CTL_PLANEB (1<<29)
+#define IVB_FBC_CTL_PLANEC (2<<29)
+#define IVB_FBC_CPU_FENCE_ENABLE (1<<28)
/*
* GPIO regs
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 04411ad..3fc5156 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1657,6 +1657,79 @@ static bool ironlake_fbc_enabled(struct drm_device *dev)
return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
}
+static void ivb_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_framebuffer *fb = crtc->fb;
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ struct drm_i915_gem_object *obj = intel_fb->obj;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ unsigned long stall_watermark = 200;
+ u32 dpfc_ctl;
+
+ dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
+ dpfc_ctl &= DPFC_RESERVED;
+ dpfc_ctl &= DPFC_RESERVED;
+ /* Workarounds */
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ IVB_DPR_VS_FBCQ_DIS);
+ I915_WRITE(ILK_DSPCLK_GATE,
+ I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPFC_DIS2 |
+ ILK_CLK_FBC);
+ /* IVL has 3 pipes */
+ switch (intel_crtc->plane) {
+ case 0:
+ dpfc_ctl |= IVB_FBC_CTL_PLANEA;
+ break;
+ case 1:
+ dpfc_ctl |= IVB_FBC_CTL_PLANEB;
+ break;
+ case 2:
+ dpfc_ctl |= IVB_FBC_CTL_PLANEC;
+ break;
+ }
+ /* fence enablement */
+ dpfc_ctl |= IVB_FBC_CPU_FENCE_ENABLE | obj->fence_reg;
+ dpfc_ctl |= DPFC_CTL_LIMIT_1X;
+ dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
+ I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
+
+ I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
+ (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
+ (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
+ I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
+ I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
+ /* enable it... */
+ I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
+
+ DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
+}
+
+static void ivb_disable_fbc(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 dpfc_ctl;
+
+ /* Disable compression */
+ dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
+ if (dpfc_ctl & DPFC_CTL_EN) {
+ dpfc_ctl &= ~DPFC_CTL_EN;
+ I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
+
+ DRM_DEBUG_KMS("disabled FBC\n");
+ }
+}
+
+static bool ivb_fbc_enabled(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+}
+
bool intel_fbc_enabled(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8138,9 +8211,15 @@ static void intel_init_display(struct drm_device *dev)
if (I915_HAS_FBC(dev)) {
if (HAS_PCH_SPLIT(dev)) {
- dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
- dev_priv->display.enable_fbc = ironlake_enable_fbc;
- dev_priv->display.disable_fbc = ironlake_disable_fbc;
+ if (IS_GEN7(dev)) {
+ dev_priv->display.fbc_enabled = ivb_fbc_enabled;
+ dev_priv->display.enable_fbc = ivb_enable_fbc;
+ dev_priv->display.disable_fbc = ivb_disable_fbc;
+ } else {
+ dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
+ dev_priv->display.enable_fbc = ironlake_enable_fbc;
+ dev_priv->display.disable_fbc = ironlake_disable_fbc;
+ }
} else if (IS_GM45(dev)) {
dev_priv->display.fbc_enabled = g4x_fbc_enabled;
dev_priv->display.enable_fbc = g4x_enable_fbc;
--
1.7.6.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] Enable FBC on IVB architecture.
2011-10-20 16:28 [PATCH] Enable FBC on IVB architecture Eugeni Dodonov
@ 2011-10-20 16:34 ` Eugeni Dodonov
2011-10-20 17:39 ` Keith Packard
0 siblings, 1 reply; 8+ messages in thread
From: Eugeni Dodonov @ 2011-10-20 16:34 UTC (permalink / raw)
To: Eugeni Dodonov; +Cc: intel-gfx
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On Thu, Oct 20, 2011 at 14:28, Eugeni Dodonov <eugeni.dodonov@intel.com>wrote:
> This is mostly similar to Ironlake, with some register changes and
> additional tricks.
>
> Jesse mentioned that it would make more sense to move those bits into
> ivb-specific functions instead of making this work within ironlake ones,
> so I added the corresponding functions and setup their pointers
> accordingly.
>
Please disregard this, sent too quickly, a cleaner patch is on the way.
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Enable FBC on IVB architecture.
2011-10-20 16:34 ` Eugeni Dodonov
@ 2011-10-20 17:39 ` Keith Packard
2011-10-20 17:41 ` Chris Wilson
0 siblings, 1 reply; 8+ messages in thread
From: Keith Packard @ 2011-10-20 17:39 UTC (permalink / raw)
To: Eugeni Dodonov, Eugeni Dodonov; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 407 bytes --]
On Thu, 20 Oct 2011 14:34:55 -0200, Eugeni Dodonov <eugeni@dodonov.net> wrote:
> > This is mostly similar to Ironlake, with some register changes and
> > additional tricks.
> way.
Have you managed to verify that this actually does anything yet? The
only way we've managed in the past is to stick a watt meter on a machine
and watch it go down when FBC kicks in...
--
keith.packard@intel.com
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Enable FBC on IVB architecture.
2011-10-20 17:39 ` Keith Packard
@ 2011-10-20 17:41 ` Chris Wilson
2011-10-20 17:59 ` Eugeni Dodonov
0 siblings, 1 reply; 8+ messages in thread
From: Chris Wilson @ 2011-10-20 17:41 UTC (permalink / raw)
To: Keith Packard, Eugeni Dodonov, Eugeni Dodonov; +Cc: intel-gfx
On Thu, 20 Oct 2011 10:39:00 -0700, Keith Packard <keithp@keithp.com> wrote:
> Have you managed to verify that this actually does anything yet? The
> only way we've managed in the past is to stick a watt meter on a machine
> and watch it go down when FBC kicks in...
Or up as the case may be. ;-)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Enable FBC on IVB architecture.
2011-10-20 17:41 ` Chris Wilson
@ 2011-10-20 17:59 ` Eugeni Dodonov
0 siblings, 0 replies; 8+ messages in thread
From: Eugeni Dodonov @ 2011-10-20 17:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx, Eugeni Dodonov
[-- Attachment #1.1: Type: text/plain, Size: 827 bytes --]
On Thu, Oct 20, 2011 at 15:41, Chris Wilson <chris@chris-wilson.co.uk>wrote:
> On Thu, 20 Oct 2011 10:39:00 -0700, Keith Packard <keithp@keithp.com>
> wrote:
> > Have you managed to verify that this actually does anything yet? The
> > only way we've managed in the past is to stick a watt meter on a machine
> > and watch it go down when FBC kicks in...
>
> Or up as the case may be. ;-)
>
I am on optimist, I have faith that it will go down :).
Keith - I wasn't able to verify if it actually kicks in, we are out of
powermeters here yet. But it haven't caused any breakage, so if someone with
power-related equipment could give it a try, it would be nice. In the very
worst case, you'll get some dmesg messages which can give some consolation
and maybe a placebo effect :).
--
Eugeni Dodonov
<http://eugeni.dodonov.net/>
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Enable FBC on IVB architecture.
2012-01-17 11:22 ` Daniel Vetter
@ 2012-01-17 17:12 ` Jesse Barnes
0 siblings, 0 replies; 8+ messages in thread
From: Jesse Barnes @ 2012-01-17 17:12 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, Eugeni Dodonov
[-- Attachment #1.1: Type: text/plain, Size: 994 bytes --]
On Tue, 17 Jan 2012 12:22:44 +0100
Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Oct 20, 2011 at 03:15:09PM -0200, Eugeni Dodonov wrote:
> > This is mostly similar to Ironlake, with some register changes and
> > additional tricks.
> >
> > Jesse mentioned that it would make more sense to move those bits into
> > ivb-specific functions instead of making this work within ironlake ones,
> > so I added the corresponding functions and setup their pointers
> > accordingly.
> >
> > v2: Now the correct patch.
> >
> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
>
> Anyone got an opinion on whether this is worth it power-consumption wise?
> fbc has been a bit of a disaster and we have it disabled almost everywhere
> ...
We also need some workarounds on IVB we haven't implemented yet. I'd
say just keep it out of IVB+ unless we can show a real benefit and have
all the workarounds in place.
--
Jesse Barnes, Intel Open Source Technology Center
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] Enable FBC on IVB architecture.
2011-10-20 17:15 Eugeni Dodonov
@ 2012-01-17 11:22 ` Daniel Vetter
2012-01-17 17:12 ` Jesse Barnes
0 siblings, 1 reply; 8+ messages in thread
From: Daniel Vetter @ 2012-01-17 11:22 UTC (permalink / raw)
To: Eugeni Dodonov; +Cc: intel-gfx
On Thu, Oct 20, 2011 at 03:15:09PM -0200, Eugeni Dodonov wrote:
> This is mostly similar to Ironlake, with some register changes and
> additional tricks.
>
> Jesse mentioned that it would make more sense to move those bits into
> ivb-specific functions instead of making this work within ironlake ones,
> so I added the corresponding functions and setup their pointers
> accordingly.
>
> v2: Now the correct patch.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Anyone got an opinion on whether this is worth it power-consumption wise?
fbc has been a bit of a disaster and we have it disabled almost everywhere
...
-Daniel
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 14 ++++++
> drivers/gpu/drm/i915/intel_display.c | 83 ++++++++++++++++++++++++++++++++-
> 3 files changed, 95 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index f07e425..a4300b7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -233,7 +233,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
> static const struct intel_device_info intel_ivybridge_m_info = {
> .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
> .need_gfx_hws = 1, .has_hotplug = 1,
> - .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
> + .has_fbc = 1, /* Attempt at enabling FBC on IvyBridge mobile */
> .has_bsd_ring = 1,
> .has_blt_ring = 1,
> };
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 542453f..4d1ce26 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -627,6 +627,7 @@
> #define ILK_DISPLAY_CHICKEN1 0x42000
> #define ILK_FBCQ_DIS (1<<22)
> #define ILK_PABSTRETCH_DIS (1<<21)
> +#define IVB_DPR_VS_FBCQ_DIS (1<<22)
>
>
> /*
> @@ -638,6 +639,19 @@
> #define SNB_CPU_FENCE_ENABLE (1<<29)
> #define DPFC_CPU_FENCE_OFFSET 0x100104
>
> +/*
> + * Framebuffer compression for IVB
> + *
> + * Mostly similar to ILK with some changes
> + */
> +
> +#define IVB_RESERVED (0x0FFFFF00)
> +
> +/* Controlled via ILK_DPFC_CONTROL */
> +#define IVB_FBC_CTL_PLANEA (0<<29)
> +#define IVB_FBC_CTL_PLANEB (1<<29)
> +#define IVB_FBC_CTL_PLANEC (2<<29)
> +#define IVB_FBC_CPU_FENCE_ENABLE (1<<28)
>
> /*
> * GPIO regs
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 04411ad..de77249 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1657,6 +1657,77 @@ static bool ironlake_fbc_enabled(struct drm_device *dev)
> return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
> }
>
> +static void ivb_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_framebuffer *fb = crtc->fb;
> + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
> + struct drm_i915_gem_object *obj = intel_fb->obj;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> + unsigned long stall_watermark = 200;
> + u32 dpfc_ctl;
> +
> + dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
> + dpfc_ctl &= IVB_RESERVED;
> + /* Workarounds */
> + I915_WRITE(ILK_DISPLAY_CHICKEN1,
> + I915_READ(ILK_DISPLAY_CHICKEN1) |
> + IVB_DPR_VS_FBCQ_DIS);
> + I915_WRITE(ILK_DSPCLK_GATE,
> + I915_READ(ILK_DSPCLK_GATE) |
> + ILK_DPFC_DIS2 |
> + ILK_CLK_FBC);
> + /* IVL has 3 pipes */
> + switch (intel_crtc->plane) {
> + case 0:
> + dpfc_ctl |= IVB_FBC_CTL_PLANEA;
> + break;
> + case 1:
> + dpfc_ctl |= IVB_FBC_CTL_PLANEB;
> + break;
> + case 2:
> + dpfc_ctl |= IVB_FBC_CTL_PLANEC;
> + break;
> + }
> + /* fence enablement */
> + dpfc_ctl |= (IVB_FBC_CPU_FENCE_ENABLE | obj->fence_reg);
> + dpfc_ctl |= DPFC_CTL_LIMIT_1X;
> + I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
> +
> + I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
> + (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
> + (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
> + I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
> + I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
> + /* enable it... */
> + I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
> +
> + DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
> +}
> +
> +static void ivb_disable_fbc(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + u32 dpfc_ctl;
> +
> + /* Disable compression */
> + dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
> + if (dpfc_ctl & DPFC_CTL_EN) {
> + dpfc_ctl &= ~DPFC_CTL_EN;
> + I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
> +
> + DRM_DEBUG_KMS("disabled FBC\n");
> + }
> +}
> +
> +static bool ivb_fbc_enabled(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
> +}
> +
> bool intel_fbc_enabled(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -8138,9 +8209,15 @@ static void intel_init_display(struct drm_device *dev)
>
> if (I915_HAS_FBC(dev)) {
> if (HAS_PCH_SPLIT(dev)) {
> - dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
> - dev_priv->display.enable_fbc = ironlake_enable_fbc;
> - dev_priv->display.disable_fbc = ironlake_disable_fbc;
> + if (IS_GEN7(dev)) {
> + dev_priv->display.fbc_enabled = ivb_fbc_enabled;
> + dev_priv->display.enable_fbc = ivb_enable_fbc;
> + dev_priv->display.disable_fbc = ivb_disable_fbc;
> + } else {
> + dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
> + dev_priv->display.enable_fbc = ironlake_enable_fbc;
> + dev_priv->display.disable_fbc = ironlake_disable_fbc;
> + }
> } else if (IS_GM45(dev)) {
> dev_priv->display.fbc_enabled = g4x_fbc_enabled;
> dev_priv->display.enable_fbc = g4x_enable_fbc;
> --
> 1.7.6.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] Enable FBC on IVB architecture.
@ 2011-10-20 17:15 Eugeni Dodonov
2012-01-17 11:22 ` Daniel Vetter
0 siblings, 1 reply; 8+ messages in thread
From: Eugeni Dodonov @ 2011-10-20 17:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Eugeni Dodonov
This is mostly similar to Ironlake, with some register changes and
additional tricks.
Jesse mentioned that it would make more sense to move those bits into
ivb-specific functions instead of making this work within ironlake ones,
so I added the corresponding functions and setup their pointers
accordingly.
v2: Now the correct patch.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 14 ++++++
drivers/gpu/drm/i915/intel_display.c | 83 ++++++++++++++++++++++++++++++++-
3 files changed, 95 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f07e425..a4300b7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -233,7 +233,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
static const struct intel_device_info intel_ivybridge_m_info = {
.is_ivybridge = 1, .gen = 7, .is_mobile = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
- .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
+ .has_fbc = 1, /* Attempt at enabling FBC on IvyBridge mobile */
.has_bsd_ring = 1,
.has_blt_ring = 1,
};
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 542453f..4d1ce26 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -627,6 +627,7 @@
#define ILK_DISPLAY_CHICKEN1 0x42000
#define ILK_FBCQ_DIS (1<<22)
#define ILK_PABSTRETCH_DIS (1<<21)
+#define IVB_DPR_VS_FBCQ_DIS (1<<22)
/*
@@ -638,6 +639,19 @@
#define SNB_CPU_FENCE_ENABLE (1<<29)
#define DPFC_CPU_FENCE_OFFSET 0x100104
+/*
+ * Framebuffer compression for IVB
+ *
+ * Mostly similar to ILK with some changes
+ */
+
+#define IVB_RESERVED (0x0FFFFF00)
+
+/* Controlled via ILK_DPFC_CONTROL */
+#define IVB_FBC_CTL_PLANEA (0<<29)
+#define IVB_FBC_CTL_PLANEB (1<<29)
+#define IVB_FBC_CTL_PLANEC (2<<29)
+#define IVB_FBC_CPU_FENCE_ENABLE (1<<28)
/*
* GPIO regs
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 04411ad..de77249 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1657,6 +1657,77 @@ static bool ironlake_fbc_enabled(struct drm_device *dev)
return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
}
+static void ivb_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_framebuffer *fb = crtc->fb;
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ struct drm_i915_gem_object *obj = intel_fb->obj;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ unsigned long stall_watermark = 200;
+ u32 dpfc_ctl;
+
+ dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
+ dpfc_ctl &= IVB_RESERVED;
+ /* Workarounds */
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ IVB_DPR_VS_FBCQ_DIS);
+ I915_WRITE(ILK_DSPCLK_GATE,
+ I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPFC_DIS2 |
+ ILK_CLK_FBC);
+ /* IVL has 3 pipes */
+ switch (intel_crtc->plane) {
+ case 0:
+ dpfc_ctl |= IVB_FBC_CTL_PLANEA;
+ break;
+ case 1:
+ dpfc_ctl |= IVB_FBC_CTL_PLANEB;
+ break;
+ case 2:
+ dpfc_ctl |= IVB_FBC_CTL_PLANEC;
+ break;
+ }
+ /* fence enablement */
+ dpfc_ctl |= (IVB_FBC_CPU_FENCE_ENABLE | obj->fence_reg);
+ dpfc_ctl |= DPFC_CTL_LIMIT_1X;
+ I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
+
+ I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
+ (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
+ (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
+ I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
+ I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
+ /* enable it... */
+ I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
+
+ DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
+}
+
+static void ivb_disable_fbc(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 dpfc_ctl;
+
+ /* Disable compression */
+ dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
+ if (dpfc_ctl & DPFC_CTL_EN) {
+ dpfc_ctl &= ~DPFC_CTL_EN;
+ I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
+
+ DRM_DEBUG_KMS("disabled FBC\n");
+ }
+}
+
+static bool ivb_fbc_enabled(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
+}
+
bool intel_fbc_enabled(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8138,9 +8209,15 @@ static void intel_init_display(struct drm_device *dev)
if (I915_HAS_FBC(dev)) {
if (HAS_PCH_SPLIT(dev)) {
- dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
- dev_priv->display.enable_fbc = ironlake_enable_fbc;
- dev_priv->display.disable_fbc = ironlake_disable_fbc;
+ if (IS_GEN7(dev)) {
+ dev_priv->display.fbc_enabled = ivb_fbc_enabled;
+ dev_priv->display.enable_fbc = ivb_enable_fbc;
+ dev_priv->display.disable_fbc = ivb_disable_fbc;
+ } else {
+ dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
+ dev_priv->display.enable_fbc = ironlake_enable_fbc;
+ dev_priv->display.disable_fbc = ironlake_disable_fbc;
+ }
} else if (IS_GM45(dev)) {
dev_priv->display.fbc_enabled = g4x_fbc_enabled;
dev_priv->display.enable_fbc = g4x_enable_fbc;
--
1.7.6.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2012-01-17 17:12 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-10-20 16:28 [PATCH] Enable FBC on IVB architecture Eugeni Dodonov
2011-10-20 16:34 ` Eugeni Dodonov
2011-10-20 17:39 ` Keith Packard
2011-10-20 17:41 ` Chris Wilson
2011-10-20 17:59 ` Eugeni Dodonov
2011-10-20 17:15 Eugeni Dodonov
2012-01-17 11:22 ` Daniel Vetter
2012-01-17 17:12 ` Jesse Barnes
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