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* [dpdk-dev] [PATCH v2 1/2] drivers/raw: remove octeontx2-dma driver
@ 2021-08-12 12:37 Radha Mohan Chintakuntla
  2021-08-13  7:00 ` [dpdk-dev] [PATCH v3 " Radha Mohan Chintakuntla
  2021-08-13  7:01 ` [dpdk-dev] [PATCH v3 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
  0 siblings, 2 replies; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-12 12:37 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-dma driver as the dependent
common/octeontx2 will be soon be going away. Also a new DMA driver will
be coming in this place once the rte_dmadev library is in.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v1:
Fixed compilation issues in documentation


 MAINTAINERS                                 |   6 -
 doc/guides/rawdevs/index.rst                |   1 -
 doc/guides/rawdevs/octeontx2_dma.rst        | 103 -----
 drivers/raw/meson.build                     |   1 -
 drivers/raw/octeontx2_dma/meson.build       |  18 -
 drivers/raw/octeontx2_dma/otx2_dpi_msg.c    | 105 -----
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 441 --------------------
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 197 ---------
 drivers/raw/octeontx2_dma/otx2_dpi_test.c   | 218 ----------
 drivers/raw/octeontx2_dma/version.map       |   3 -
 10 files changed, 1093 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_dma.rst
 delete mode 100644 drivers/raw/octeontx2_dma/meson.build
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_msg.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_test.c
 delete mode 100644 drivers/raw/octeontx2_dma/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 266f5ac1da..9f9aa37c68 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 DMA
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_dma/
-F: doc/guides/rawdevs/octeontx2_dma.rst
-
 Marvell OCTEON TX2 EP
 M: Radha Mohan Chintakuntla <radhac@marvell.com>
 M: Veerasenareddy Burru <vburru@marvell.com>
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 7fbae40ea9..228d4a7743 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,5 +17,4 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_dma
     octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_dma.rst b/doc/guides/rawdevs/octeontx2_dma.rst
deleted file mode 100644
index 6887da5278..0000000000
--- a/doc/guides/rawdevs/octeontx2_dma.rst
+++ /dev/null
@@ -1,103 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-OCTEON TX2 DMA Driver
-=====================
-
-OCTEON TX2 has an internal DMA unit which can be used by applications to initiate
-DMA transaction internally, from/to host when OCTEON TX2 operates in PCIe End
-Point mode. The DMA PF function supports 8 VFs corresponding to 8 DMA queues.
-Each DMA queue was exposed as a VF function when SRIOV enabled.
-
-Features
---------
-
-This DMA PMD supports below 3 modes of memory transfers
-
-#. Internal - OCTEON TX2 DRAM to DRAM without core intervention
-
-#. Inbound  - Host DRAM to OCTEON TX2 DRAM without host/OCTEON TX2 cores involvement
-
-#. Outbound - OCTEON TX2 DRAM to Host DRAM without host/OCTEON TX2 cores involvement
-
-Prerequisites and Compilation procedure
----------------------------------------
-
-   See :doc:`../platform/octeontx2` for setup information.
-
-
-Enabling logs
--------------
-
-For enabling logs, use the following EAL parameter:
-
-.. code-block:: console
-
-   ./your_dma_application <EAL args> --log-level=pmd.raw.octeontx2.dpi,<level>
-
-Using ``pmd.raw.octeontx2.dpi`` as log matching criteria, all Event PMD logs
-can be enabled which are lower than logging ``level``.
-
-Initialization
---------------
-
-The number of DMA VFs (queues) enabled can be controlled by setting sysfs
-entry, `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-dpi/0000\:05\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
--------------
-
-The OCTEON TX2 DPI DMA HW devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring DMA rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to submit DMA
-commands to HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct dpi_rawdev_conf_s conf = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &conf};
-
-   conf.chunk_pool = (void *)rte_mempool_create_empty(...);
-   rte_mempool_set_ops_byname(conf.chunk_pool, rte_mbuf_platform_mempool_ops(), NULL);
-   rte_mempool_populate_default(conf.chunk_pool);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info, sizeof(conf));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using OCTEON TX2 DMA rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, dma devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("DPI:x")`` from the application
-  where x is the VF device's bus id specified in "bus:device.func" format. Use this
-  index for further rawdev function calls.
-
-* This PMD supports driver self test, to test DMA internal mode from test
-  application one can directly calls
-  ``rte_rawdev_selftest(rte_rawdev_get_dev_id("DPI:x"))``
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index b51536f8a7..f25d5f322c 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_dma',
         'octeontx2_ep',
         'skeleton',
 ]
diff --git a/drivers/raw/octeontx2_dma/meson.build b/drivers/raw/octeontx2_dma/meson.build
deleted file mode 100644
index e744fccaae..0000000000
--- a/drivers/raw/octeontx2_dma/meson.build
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files('otx2_dpi_rawdev.c', 'otx2_dpi_msg.c', 'otx2_dpi_test.c')
-
-extra_flags = []
-# This integrated controller runs only on a arm64 machine, remove 32bit warnings
-if not dpdk_conf.get('RTE_ARCH_64')
-    extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
-endif
-
-foreach flag: extra_flags
-    if cc.has_argument(flag)
-        cflags += flag
-    endif
-endforeach
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c b/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
deleted file mode 100644
index 655de216ab..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_MSG_H_
-#define _DPI_MSG_H_
-
-#include <dirent.h>
-#include <fcntl.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "otx2_dpi_rawdev.h"
-
-/* DPI PF DBDF information macro's */
-#define DPI_PF_DBDF_DOMAIN      0
-#define DPI_PF_DBDF_BUS         5
-#define DPI_PF_DBDF_DEVICE      0
-#define DPI_PF_DBDF_FUNCTION    0
-
-#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
-
-union dpi_mbox_message_u {
-	uint64_t u[2];
-	struct dpi_mbox_message_s {
-		/* VF ID to configure */
-		uint64_t vfid           :4;
-		/* Command code */
-		uint64_t cmd            :4;
-		/* Command buffer size in 8-byte words */
-		uint64_t csize          :14;
-		/* aura of the command buffer */
-		uint64_t aura           :20;
-		/* SSO PF function */
-		uint64_t sso_pf_func    :16;
-		/* NPA PF function */
-		uint64_t npa_pf_func    :16;
-	} s;
-};
-
-static inline int
-send_msg_to_pf(struct rte_pci_addr *pci, const char *value, int size)
-{
-	char buff[255] = { 0 };
-	int res, fd;
-
-	res = snprintf(buff, sizeof(buff), "%s/" PCI_PRI_FMT "/%s",
-		       rte_pci_get_sysfs_path(), pci->domain,
-		       pci->bus, DPI_PF_DBDF_DEVICE & 0x7,
-		       DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
-	if ((res < 0) || ((size_t)res > sizeof(buff)))
-		return -ERANGE;
-
-	fd = open(buff, O_WRONLY);
-	if (fd < 0)
-		return -EACCES;
-	res = write(fd, value, size);
-	close(fd);
-	if (res < 0)
-		return -EACCES;
-
-	return 0;
-}
-
-int
-otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_OPEN;
-	mbox_msg.s.csize = size;
-	mbox_msg.s.aura = gaura;
-	mbox_msg.s.sso_pf_func = otx2_sso_pf_func_get();
-	mbox_msg.s.npa_pf_func = otx2_npa_pf_func_get();
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-int
-otx2_dpi_queue_close(struct dpi_vf_s *dpivf)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-#endif /* _DPI_MSG_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
deleted file mode 100644
index 8c01f25ec7..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include <otx2_common.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static const struct rte_pci_id pci_dma_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_DPI_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* Enable/Disable DMA queue */
-static inline int
-dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb)
-{
-	if (enb)
-		otx2_write64(0x1, dpivf->vf_bar0 + DPI_VDMA_EN);
-	else
-		otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Free DMA Queue instruction buffers, and send close notification to PF */
-static inline int
-dma_queue_finish(struct dpi_vf_s *dpivf)
-{
-	uint32_t timeout = 0, sleep = 1;
-	uint64_t reg = 0ULL;
-
-	/* Wait for SADDR to become idle */
-	reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	while (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) {
-		rte_delay_ms(sleep);
-		timeout++;
-		if (timeout >= DPI_QFINISH_TIMEOUT) {
-			otx2_dpi_dbg("Timeout!!! Closing Forcibly");
-			break;
-		}
-		reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	}
-
-	if (otx2_dpi_queue_close(dpivf) < 0)
-		return -EACCES;
-
-	rte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr);
-	dpivf->vf_bar0 = (uintptr_t)NULL;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Write an arbitrary number of command words to a command queue */
-static __rte_always_inline enum dpi_dma_queue_result_e
-dma_queue_write(struct dpi_vf_s *dpi, uint16_t cmd_count, uint64_t *cmds)
-{
-	if ((cmd_count < 1) || (cmd_count > 64))
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	if (cmds == NULL)
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	/* Room available in the current buffer for the command */
-	if (dpi->index + cmd_count < dpi->pool_size_m1) {
-		uint64_t *ptr = dpi->base_ptr;
-
-		ptr += dpi->index;
-		dpi->index += cmd_count;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-	} else {
-		void *new_buffer;
-		uint64_t *ptr;
-		int count;
-
-		/* Allocate new command buffer, return if failed */
-		if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-		    new_buffer == NULL) {
-			return DPI_DMA_QUEUE_NO_MEMORY;
-		}
-		ptr = dpi->base_ptr;
-		/* Figure out how many command words will fit in this buffer.
-		 * One location will be needed for the next buffer pointer.
-		 **/
-		count = dpi->pool_size_m1 - dpi->index;
-		ptr += dpi->index;
-		cmd_count -= count;
-		while (count--)
-			*ptr++ = *cmds++;
-		/* Chunk next ptr is 2DWORDs, second DWORD is reserved. */
-		*ptr++ = (uint64_t)new_buffer;
-		*ptr   = 0;
-		/* The current buffer is full and has a link to the next buffer.
-		 * Time to write the rest of the commands into the new buffer.
-		 **/
-		dpi->base_ptr = new_buffer;
-		dpi->index = cmd_count;
-		ptr = new_buffer;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-		/* queue index may greater than pool size */
-		if (dpi->index >= dpi->pool_size_m1) {
-			if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-			    new_buffer == NULL) {
-				return DPI_DMA_QUEUE_NO_MEMORY;
-			}
-			/* Write next buffer address */
-			*ptr = (uint64_t)new_buffer;
-			dpi->base_ptr = new_buffer;
-			dpi->index = 0;
-		}
-	}
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Submit a DMA command to the DMA queues. */
-static __rte_always_inline int
-dma_queue_submit(struct rte_rawdev *dev, uint16_t cmd_count, uint64_t *cmds)
-{
-	struct dpi_vf_s *dpivf = dev->dev_private;
-	enum dpi_dma_queue_result_e result;
-
-	result = dma_queue_write(dpivf, cmd_count, cmds);
-	rte_wmb();
-	if (likely(result == DPI_DMA_QUEUE_SUCCESS))
-		otx2_write64((uint64_t)cmd_count,
-			     dpivf->vf_bar0 + DPI_VDMA_DBELL);
-
-	return result;
-}
-
-/* Enqueue buffers to DMA queue
- * returns number of buffers enqueued successfully
- */
-static int
-otx2_dpi_rawdev_enqueue_bufs(struct rte_rawdev *dev,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	struct dpi_dma_buf_ptr_s *cmd;
-	uint32_t c = 0;
-
-	for (c = 0; c < count; c++) {
-		uint64_t dpi_cmd[DPI_DMA_CMD_SIZE] = {0};
-		union dpi_dma_instr_hdr_u *hdr;
-		uint16_t index = 0, i;
-
-		hdr = (union dpi_dma_instr_hdr_u *)&dpi_cmd[0];
-		cmd = (struct dpi_dma_buf_ptr_s *)buffers[c]->buf_addr;
-
-		hdr->s.xtype = ctx->xtype & DPI_XTYPE_MASK;
-		hdr->s.pt = ctx->pt & DPI_HDR_PT_MASK;
-		/* Request initiated with byte write completion, but completion
-		 * pointer not provided
-		 */
-		if ((hdr->s.pt == DPI_HDR_PT_ZBW_CA ||
-		     hdr->s.pt == DPI_HDR_PT_ZBW_NC) && cmd->comp_ptr == NULL)
-			return c;
-
-		cmd->comp_ptr->cdata = DPI_REQ_CDATA;
-		hdr->s.ptr = (uint64_t)cmd->comp_ptr;
-		hdr->s.deallocv = ctx->deallocv;
-		hdr->s.tt = ctx->tt & DPI_W0_TT_MASK;
-		hdr->s.grp = ctx->grp & DPI_W0_GRP_MASK;
-
-		/* If caller provides completion ring details, then only queue
-		 * completion address for later polling.
-		 */
-		if (ctx->c_ring) {
-			ctx->c_ring->compl_data[ctx->c_ring->tail] =
-								 cmd->comp_ptr;
-			STRM_INC(ctx->c_ring);
-		}
-
-		if (hdr->s.deallocv)
-			hdr->s.pvfe = 1;
-
-		if (hdr->s.pt == DPI_HDR_PT_WQP)
-			hdr->s.ptr = hdr->s.ptr | DPI_HDR_PT_WQP_STATUSNC;
-
-		index += 4;
-		hdr->s.fport = 0;
-		hdr->s.lport = 0;
-		if (ctx->xtype !=  DPI_XTYPE_INTERNAL_ONLY)
-			hdr->s.lport = ctx->pem_id;
-
-		/* For inbound case, src pointers are last pointers.
-		 * For all other cases, src pointers are first pointers.
-		 */
-		if (ctx->xtype ==  DPI_XTYPE_INBOUND) {
-			hdr->s.nfst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-		} else {
-			hdr->s.nfst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-		}
-		if (dma_queue_submit(dev, index, dpi_cmd))
-			return c;
-	}
-	return c;
-}
-
-/* Check for command completion, returns number of commands completed */
-static int
-otx2_dpi_rawdev_dequeue_bufs(struct rte_rawdev *dev __rte_unused,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	unsigned int i = 0, headp;
-
-	/* No completion ring to poll */
-	if (ctx->c_ring == NULL)
-		return 0;
-
-	headp = ctx->c_ring->head;
-	for (i = 0; i < count && (headp != ctx->c_ring->tail); i++) {
-		struct dpi_dma_req_compl_s *comp_ptr =
-					 ctx->c_ring->compl_data[headp];
-
-		if (comp_ptr->cdata)
-			break;
-
-		/* Request Completed */
-		buffers[i] = (void *)comp_ptr;
-		headp = (headp + 1) % ctx->c_ring->max_cnt;
-	}
-	ctx->c_ring->head = headp;
-
-	return i;
-}
-
-static int
-otx2_dpi_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_START;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static void
-otx2_dpi_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_STOP;
-}
-
-static int
-otx2_dpi_rawdev_close(struct rte_rawdev *dev)
-{
-	dma_engine_enb_dis(dev->dev_private, false);
-	dma_queue_finish(dev->dev_private);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_reset(struct rte_rawdev *dev)
-{
-	return dev ? DPI_QUEUE_STOP : DPI_QUEUE_START;
-}
-
-static int
-otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct dpi_rawdev_conf_s *conf = config;
-	struct dpi_vf_s *dpivf = NULL;
-	void *buf = NULL;
-	uintptr_t pool;
-	uint32_t gaura;
-
-	if (conf == NULL || config_size != sizeof(*conf)) {
-		otx2_dpi_dbg("NULL or invalid configuration");
-		return -EINVAL;
-	}
-	dpivf = (struct dpi_vf_s *)dev->dev_private;
-	dpivf->chunk_pool = conf->chunk_pool;
-	if (rte_mempool_get(conf->chunk_pool, &buf) || (buf == NULL)) {
-		otx2_err("Unable allocate buffer");
-		return -ENODEV;
-	}
-	dpivf->base_ptr = buf;
-	otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-	dpivf->pool_size_m1 = (DPI_CHUNK_SIZE >> 3) - 2;
-	pool = (uintptr_t)((struct rte_mempool *)conf->chunk_pool)->pool_id;
-	gaura = npa_lf_aura_handle_to_aura(pool);
-	otx2_write64(0, dpivf->vf_bar0 + DPI_VDMA_REQQ_CTL);
-	otx2_write64(((uint64_t)buf >> 7) << 7,
-		     dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	if (otx2_dpi_queue_open(dpivf, DPI_CHUNK_SIZE, gaura) < 0) {
-		otx2_err("Unable to open DPI VF %d", dpivf->vf_id);
-		rte_mempool_put(conf->chunk_pool, buf);
-		return -EACCES;
-	}
-	dma_engine_enb_dis(dpivf, true);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static const struct rte_rawdev_ops dpi_rawdev_ops = {
-	.dev_configure = otx2_dpi_rawdev_configure,
-	.dev_start = otx2_dpi_rawdev_start,
-	.dev_stop = otx2_dpi_rawdev_stop,
-	.dev_close = otx2_dpi_rawdev_close,
-	.dev_reset = otx2_dpi_rawdev_reset,
-	.enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs,
-	.dequeue_bufs = otx2_dpi_rawdev_dequeue_bufs,
-	.dev_selftest = test_otx2_dma_rawdev,
-};
-
-static int
-otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct dpi_vf_s *dpivf = NULL;
-	struct rte_rawdev *rawdev;
-	uint16_t vf_id;
-
-	/* For secondary processes, the primary has done all the work */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return DPI_DMA_QUEUE_SUCCESS;
-
-	if (pci_dev->mem_resource[0].addr == NULL) {
-		otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr,
-			     pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate device structure */
-	rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct dpi_vf_s),
-					 rte_socket_id());
-	if (rawdev == NULL) {
-		otx2_err("Rawdev allocation failed");
-		return -EINVAL;
-	}
-
-	rawdev->dev_ops = &dpi_rawdev_ops;
-	rawdev->device = &pci_dev->device;
-	rawdev->driver_name = pci_dev->driver->driver.name;
-
-	dpivf = rawdev->dev_private;
-	if (dpivf->state != DPI_QUEUE_STOP) {
-		otx2_dpi_dbg("Device already started!!!");
-		return -ENODEV;
-	}
-
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-	vf_id -= 1;
-	dpivf->dev = pci_dev;
-	dpivf->state = DPI_QUEUE_START;
-	dpivf->vf_id = vf_id;
-	dpivf->vf_bar0 = (uintptr_t)pci_dev->mem_resource[0].addr;
-	dpivf->vf_bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct dpi_vf_s *dpivf;
-
-	if (pci_dev == NULL) {
-		otx2_dpi_dbg("Invalid pci_dev of the device!");
-		return -EINVAL;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_dpi_dbg("Invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	dpivf = (struct dpi_vf_s *)rawdev->dev_private;
-	dma_engine_enb_dis(dpivf, false);
-	dma_queue_finish(dpivf);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_dpi_rawdev_pmd = {
-	.id_table  = pci_dma_map,
-	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
-	.probe     = otx2_dpi_rawdev_probe,
-	.remove    = otx2_dpi_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(dpi_rawdev_pci_driver, rte_dpi_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(dpi_rawdev_pci_driver, pci_dma_map);
-RTE_PMD_REGISTER_KMOD_DEP(dpi_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
deleted file mode 100644
index 2bc9e3da3c..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_RAWDEV_H_
-#define _DPI_RAWDEV_H_
-
-#include "otx2_common.h"
-#include "otx2_mempool.h"
-
-#define DPI_QUEUE_OPEN	0x1
-#define DPI_QUEUE_CLOSE	0x2
-
-/* DPI VF register offsets from VF_BAR0 */
-#define DPI_VDMA_EN             (0x0)
-#define DPI_VDMA_REQQ_CTL       (0x8)
-#define DPI_VDMA_DBELL          (0x10)
-#define DPI_VDMA_SADDR          (0x18)
-#define DPI_VDMA_COUNTS         (0x20)
-#define DPI_VDMA_NADDR          (0x28)
-#define DPI_VDMA_IWBUSY         (0x30)
-#define DPI_VDMA_CNT            (0x38)
-#define DPI_VF_INT              (0x100)
-#define DPI_VF_INT_W1S          (0x108)
-#define DPI_VF_INT_ENA_W1C      (0x110)
-#define DPI_VF_INT_ENA_W1S      (0x118)
-
-#define DPI_MAX_VFS             8
-#define DPI_DMA_CMD_SIZE        64
-#define DPI_CHUNK_SIZE		1024
-#define DPI_QUEUE_STOP		0x0
-#define DPI_QUEUE_START		0x1
-
-#define DPI_VDMA_SADDR_REQ_IDLE	63
-#define DPI_MAX_POINTER		15
-#define STRM_INC(s)	((s)->tail = ((s)->tail + 1) % (s)->max_cnt)
-#define DPI_QFINISH_TIMEOUT	(10 * 1000)
-
-/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
-#define DPI_XTYPE_OUTBOUND      (0)
-#define DPI_XTYPE_INBOUND       (1)
-#define DPI_XTYPE_INTERNAL_ONLY (2)
-#define DPI_XTYPE_EXTERNAL_ONLY (3)
-#define DPI_XTYPE_MASK		0x3
-#define DPI_HDR_PT_ZBW_CA	0x0
-#define DPI_HDR_PT_ZBW_NC	0x1
-#define DPI_HDR_PT_WQP		0x2
-#define DPI_HDR_PT_WQP_NOSTATUS	0x0
-#define DPI_HDR_PT_WQP_STATUSCA	0x1
-#define DPI_HDR_PT_WQP_STATUSNC	0x3
-#define DPI_HDR_PT_CNT		0x3
-#define DPI_HDR_PT_MASK		0x3
-#define DPI_W0_TT_MASK		0x3
-#define DPI_W0_GRP_MASK		0x3FF
-/* Set Completion data to 0xFF when request submitted,
- * upon successful request completion engine reset to completion status
- */
-#define DPI_REQ_CDATA		0xFF
-
-struct dpi_vf_s {
-	struct rte_pci_device *dev;
-	uint8_t state;
-	uint16_t vf_id;
-	uint8_t domain;
-	uintptr_t vf_bar0;
-	uintptr_t vf_bar2;
-
-	uint16_t pool_size_m1;
-	uint16_t index;
-	uint64_t *base_ptr;
-	void *chunk_pool;
-	struct otx2_mbox *mbox;
-};
-
-struct dpi_rawdev_conf_s {
-	void *chunk_pool;
-};
-
-enum dpi_dma_queue_result_e {
-	DPI_DMA_QUEUE_SUCCESS = 0,
-	DPI_DMA_QUEUE_NO_MEMORY = -1,
-	DPI_DMA_QUEUE_INVALID_PARAM = -2,
-};
-
-struct dpi_dma_req_compl_s {
-	uint64_t cdata;
-	void (*compl_cb)(void *dev, void *arg);
-	void *cb_data;
-};
-
-union dpi_dma_ptr_u {
-	uint64_t u[2];
-	struct dpi_dma_s {
-		uint64_t length:16;
-		uint64_t reserved:44;
-		uint64_t bed:1; /* Big-Endian */
-		uint64_t alloc_l2:1;
-		uint64_t full_write:1;
-		uint64_t invert:1;
-		uint64_t ptr;
-	} s;
-};
-
-struct dpi_dma_buf_ptr_s {
-	union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */
-	union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */
-	uint8_t rptr_cnt;
-	uint8_t wptr_cnt;
-	struct dpi_dma_req_compl_s *comp_ptr;
-};
-
-struct dpi_cring_data_s {
-	struct dpi_dma_req_compl_s **compl_data;
-	uint16_t max_cnt;
-	uint16_t head;
-	uint16_t tail;
-};
-
-struct dpi_dma_queue_ctx_s {
-	uint16_t xtype:2;
-
-	/* Completion pointer type */
-	uint16_t pt:2;
-
-	/* Completion updated using WQE */
-	uint16_t tt:2;
-	uint16_t grp:10;
-	uint32_t tag;
-
-	/* Valid only for Outbound only mode */
-	uint16_t aura:12;
-	uint16_t csel:1;
-	uint16_t ca:1;
-	uint16_t fi:1;
-	uint16_t ii:1;
-	uint16_t fl:1;
-
-	uint16_t pvfe:1;
-	uint16_t dealloce:1;
-	uint16_t req_type:2;
-	uint16_t use_lock:1;
-	uint16_t deallocv;
-	uint16_t  pem_id;
-
-	struct dpi_cring_data_s *c_ring;
-};
-
-/* DPI DMA Instruction Header Format */
-union dpi_dma_instr_hdr_u {
-	uint64_t u[4];
-
-	struct dpi_dma_instr_hdr_s_s {
-		uint64_t tag:32;
-		uint64_t tt:2;
-		uint64_t grp:10;
-		uint64_t reserved_44_47:4;
-		uint64_t nfst:4;
-		uint64_t reserved_52_53:2;
-		uint64_t nlst:4;
-		uint64_t reserved_58_63:6;
-		/* Word 0 - End */
-
-		uint64_t aura:12;
-		uint64_t reserved_76_79:4;
-		uint64_t deallocv:16;
-		uint64_t dealloce:1;
-		uint64_t pvfe:1;
-		uint64_t reserved_98_99:2;
-		uint64_t pt:2;
-		uint64_t reserved_102_103:2;
-		uint64_t fl:1;
-		uint64_t ii:1;
-		uint64_t fi:1;
-		uint64_t ca:1;
-		uint64_t csel:1;
-		uint64_t reserved_109_111:3;
-		uint64_t xtype:2;
-		uint64_t reserved_114_119:6;
-		uint64_t fport:2;
-		uint64_t reserved_122_123:2;
-		uint64_t lport:2;
-		uint64_t reserved_126_127:2;
-		/* Word 1 - End */
-
-		uint64_t ptr:64;
-		/* Word 2 - End */
-
-		uint64_t reserved_192_255:64;
-		/* Word 3 - End */
-	} s;
-};
-
-int otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura);
-int otx2_dpi_queue_close(struct dpi_vf_s *dpivf);
-int test_otx2_dma_rawdev(uint16_t val);
-
-#endif /* _DPI_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_test.c b/drivers/raw/octeontx2_dma/otx2_dpi_test.c
deleted file mode 100644
index cec6ca91b0..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_test.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_debug.h>
-#include <rte_eal.h>
-#include <rte_log.h>
-#include <rte_malloc.h>
-#include <rte_mbuf.h>
-#include <rte_mbuf_pool_ops.h>
-#include <rte_memcpy.h>
-#include <rte_memory.h>
-#include <rte_mempool.h>
-#include <rte_per_lcore.h>
-#include <rte_rawdev.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static struct dpi_cring_data_s cring;
-
-static uint8_t
-buffer_fill(uint8_t *addr, int len, uint8_t val)
-{
-	int j = 0;
-
-	memset(addr, 0, len);
-	for (j = 0; j < len; j++)
-		*(addr + j) = val++;
-
-	return val;
-}
-
-static int
-validate_buffer(uint8_t *saddr, uint8_t *daddr, int len)
-{
-	int j = 0, ret = 0;
-
-	for (j = 0; j < len; j++) {
-		if (*(saddr + j) != *(daddr + j)) {
-			otx2_dpi_dbg("FAIL: Data Integrity failed");
-			otx2_dpi_dbg("index: %d, Expected: 0x%x, Actual: 0x%x",
-				     j, *(saddr + j), *(daddr + j));
-			ret = -1;
-			break;
-		}
-	}
-
-	return ret;
-}
-
-static inline int
-dma_test_internal(int dma_port, int buf_size)
-{
-	struct dpi_dma_req_compl_s *comp_data;
-	struct dpi_dma_queue_ctx_s ctx = {0};
-	struct rte_rawdev_buf buf = {0};
-	struct rte_rawdev_buf *d_buf[1];
-	struct rte_rawdev_buf *bufp[1];
-	struct dpi_dma_buf_ptr_s cmd;
-	union dpi_dma_ptr_u rptr = { {0} };
-	union dpi_dma_ptr_u wptr = { {0} };
-	uint8_t *fptr, *lptr;
-	int ret;
-
-	fptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	lptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	comp_data = rte_malloc("dummy", buf_size, 128);
-	if (fptr == NULL || lptr == NULL || comp_data == NULL) {
-		otx2_dpi_dbg("Unable to allocate internal memory");
-		return -ENOMEM;
-	}
-
-	buffer_fill(fptr, buf_size, 0);
-	memset(&cmd, 0, sizeof(struct dpi_dma_buf_ptr_s));
-	memset(lptr, 0, buf_size);
-	memset(comp_data, 0, buf_size);
-	rptr.s.ptr = (uint64_t)fptr;
-	rptr.s.length = buf_size;
-	wptr.s.ptr = (uint64_t)lptr;
-	wptr.s.length = buf_size;
-	cmd.rptr[0] = &rptr;
-	cmd.wptr[0] = &wptr;
-	cmd.rptr_cnt = 1;
-	cmd.wptr_cnt = 1;
-	cmd.comp_ptr = comp_data;
-	buf.buf_addr = (void *)&cmd;
-	bufp[0] = &buf;
-
-	ctx.xtype = DPI_XTYPE_INTERNAL_ONLY;
-	ctx.pt = 0;
-	ctx.c_ring = &cring;
-
-	ret = rte_rawdev_enqueue_buffers(dma_port,
-					 (struct rte_rawdev_buf **)bufp, 1,
-					 &ctx);
-	if (ret < 0) {
-		otx2_dpi_dbg("Enqueue request failed");
-		return 0;
-	}
-
-	/* Wait and dequeue completion */
-	do {
-		sleep(1);
-		ret = rte_rawdev_dequeue_buffers(dma_port, &d_buf[0], 1, &ctx);
-		if (ret)
-			break;
-
-		otx2_dpi_dbg("Dequeue request not completed");
-	} while (1);
-
-	if (validate_buffer(fptr, lptr, buf_size)) {
-		otx2_dpi_dbg("DMA transfer failed\n");
-		return -EAGAIN;
-	}
-	otx2_dpi_dbg("Internal Only DMA transfer successfully completed");
-
-	if (lptr)
-		rte_free(lptr);
-	if (fptr)
-		rte_free(fptr);
-	if (comp_data)
-		rte_free(comp_data);
-
-	return 0;
-}
-
-static void *
-dpi_create_mempool(void)
-{
-	void *chunk_pool = NULL;
-	char pool_name[25];
-	int ret;
-
-	snprintf(pool_name, sizeof(pool_name), "dpi_chunk_pool");
-
-	chunk_pool = (void *)rte_mempool_create_empty(pool_name, 1024, 1024,
-						      0, 0, rte_socket_id(), 0);
-	if (chunk_pool == NULL) {
-		otx2_dpi_dbg("Unable to create memory pool.");
-		return NULL;
-	}
-
-	ret = rte_mempool_set_ops_byname(chunk_pool,
-					 rte_mbuf_platform_mempool_ops(), NULL);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to set pool ops");
-		rte_mempool_free(chunk_pool);
-		return NULL;
-	}
-
-	ret = rte_mempool_populate_default(chunk_pool);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to populate pool");
-		return NULL;
-	}
-
-	return chunk_pool;
-}
-
-int
-test_otx2_dma_rawdev(uint16_t val)
-{
-	struct rte_rawdev_info rdev_info = {0};
-	struct dpi_rawdev_conf_s conf = {0};
-	int ret, i, size = 1024;
-	int nb_ports;
-
-	RTE_SET_USED(val);
-	nb_ports = rte_rawdev_count();
-	if (nb_ports == 0) {
-		otx2_dpi_dbg("No Rawdev ports - bye");
-		return -ENODEV;
-	}
-
-	i = rte_rawdev_get_dev_id("DPI:5:00.1");
-	/* Configure rawdev ports */
-	conf.chunk_pool = dpi_create_mempool();
-	rdev_info.dev_private = &conf;
-	ret = rte_rawdev_configure(i, (rte_rawdev_obj_t)&rdev_info,
-			sizeof(conf));
-	if (ret) {
-		otx2_dpi_dbg("Unable to configure DPIVF %d", i);
-		return -ENODEV;
-	}
-	otx2_dpi_dbg("rawdev %d configured successfully", i);
-
-	/* Each stream allocate its own completion ring data, store it in
-	 * application context. Each stream needs to use same application
-	 * context for enqueue/dequeue.
-	 */
-	cring.compl_data = rte_malloc("dummy", sizeof(void *) * 1024, 128);
-	if (!cring.compl_data) {
-		otx2_dpi_dbg("Completion allocation failed");
-		return -ENOMEM;
-	}
-
-	cring.max_cnt = 1024;
-	cring.head = 0;
-	cring.tail = 0;
-
-	ret = dma_test_internal(i, size);
-	if (ret)
-		otx2_dpi_dbg("DMA transfer failed for queue %d", i);
-
-	if (rte_rawdev_close(i))
-		otx2_dpi_dbg("Dev close failed for port %d", i);
-
-	if (conf.chunk_pool)
-		rte_mempool_free(conf.chunk_pool);
-
-	return ret;
-}
diff --git a/drivers/raw/octeontx2_dma/version.map b/drivers/raw/octeontx2_dma/version.map
deleted file mode 100644
index 4a76d1d52d..0000000000
--- a/drivers/raw/octeontx2_dma/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_21 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH v3 1/2] drivers/raw: remove octeontx2-dma driver
  2021-08-12 12:37 [dpdk-dev] [PATCH v2 1/2] drivers/raw: remove octeontx2-dma driver Radha Mohan Chintakuntla
@ 2021-08-13  7:00 ` Radha Mohan Chintakuntla
  2021-08-19  7:57   ` [dpdk-dev] [PATCH v4 " Radha Mohan Chintakuntla
  2021-08-13  7:01 ` [dpdk-dev] [PATCH v3 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
  1 sibling, 1 reply; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-13  7:00 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-dma driver as the dependent
common/octeontx2 will be soon be going away. Also a new DMA driver will
be coming in this place once the rte_dmadev library is in.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v2:
Fixed DPDK CI reported issues for more documentation failure.

Changes from v1:
Fixed compilation issues in documentation

 MAINTAINERS                                 |   6 -
 doc/guides/platform/octeontx2.rst           |   3 -
 doc/guides/rawdevs/index.rst                |   1 -
 doc/guides/rawdevs/octeontx2_dma.rst        | 103 -----
 drivers/raw/meson.build                     |   1 -
 drivers/raw/octeontx2_dma/meson.build       |  18 -
 drivers/raw/octeontx2_dma/otx2_dpi_msg.c    | 105 -----
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 441 --------------------
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 197 ---------
 drivers/raw/octeontx2_dma/otx2_dpi_test.c   | 218 ----------
 drivers/raw/octeontx2_dma/version.map       |   3 -
 11 files changed, 1096 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_dma.rst
 delete mode 100644 drivers/raw/octeontx2_dma/meson.build
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_msg.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_test.c
 delete mode 100644 drivers/raw/octeontx2_dma/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 266f5ac1da..9f9aa37c68 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 DMA
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_dma/
-F: doc/guides/rawdevs/octeontx2_dma.rst
-
 Marvell OCTEON TX2 EP
 M: Radha Mohan Chintakuntla <radhac@marvell.com>
 M: Veerasenareddy Burru <vburru@marvell.com>
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 8b5991f03b..3a3d28571c 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -152,9 +152,6 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
 #. **Event Device Driver**
    See :doc:`../eventdevs/octeontx2` for SSO event device driver information.
 
-#. **DMA Rawdev Driver**
-   See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
-
 #. **Crypto Device Driver**
    See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 7fbae40ea9..228d4a7743 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,5 +17,4 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_dma
     octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_dma.rst b/doc/guides/rawdevs/octeontx2_dma.rst
deleted file mode 100644
index 6887da5278..0000000000
--- a/doc/guides/rawdevs/octeontx2_dma.rst
+++ /dev/null
@@ -1,103 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-OCTEON TX2 DMA Driver
-=====================
-
-OCTEON TX2 has an internal DMA unit which can be used by applications to initiate
-DMA transaction internally, from/to host when OCTEON TX2 operates in PCIe End
-Point mode. The DMA PF function supports 8 VFs corresponding to 8 DMA queues.
-Each DMA queue was exposed as a VF function when SRIOV enabled.
-
-Features
---------
-
-This DMA PMD supports below 3 modes of memory transfers
-
-#. Internal - OCTEON TX2 DRAM to DRAM without core intervention
-
-#. Inbound  - Host DRAM to OCTEON TX2 DRAM without host/OCTEON TX2 cores involvement
-
-#. Outbound - OCTEON TX2 DRAM to Host DRAM without host/OCTEON TX2 cores involvement
-
-Prerequisites and Compilation procedure
----------------------------------------
-
-   See :doc:`../platform/octeontx2` for setup information.
-
-
-Enabling logs
--------------
-
-For enabling logs, use the following EAL parameter:
-
-.. code-block:: console
-
-   ./your_dma_application <EAL args> --log-level=pmd.raw.octeontx2.dpi,<level>
-
-Using ``pmd.raw.octeontx2.dpi`` as log matching criteria, all Event PMD logs
-can be enabled which are lower than logging ``level``.
-
-Initialization
---------------
-
-The number of DMA VFs (queues) enabled can be controlled by setting sysfs
-entry, `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-dpi/0000\:05\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
--------------
-
-The OCTEON TX2 DPI DMA HW devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring DMA rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to submit DMA
-commands to HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct dpi_rawdev_conf_s conf = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &conf};
-
-   conf.chunk_pool = (void *)rte_mempool_create_empty(...);
-   rte_mempool_set_ops_byname(conf.chunk_pool, rte_mbuf_platform_mempool_ops(), NULL);
-   rte_mempool_populate_default(conf.chunk_pool);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info, sizeof(conf));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using OCTEON TX2 DMA rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, dma devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("DPI:x")`` from the application
-  where x is the VF device's bus id specified in "bus:device.func" format. Use this
-  index for further rawdev function calls.
-
-* This PMD supports driver self test, to test DMA internal mode from test
-  application one can directly calls
-  ``rte_rawdev_selftest(rte_rawdev_get_dev_id("DPI:x"))``
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index b51536f8a7..f25d5f322c 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_dma',
         'octeontx2_ep',
         'skeleton',
 ]
diff --git a/drivers/raw/octeontx2_dma/meson.build b/drivers/raw/octeontx2_dma/meson.build
deleted file mode 100644
index e744fccaae..0000000000
--- a/drivers/raw/octeontx2_dma/meson.build
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files('otx2_dpi_rawdev.c', 'otx2_dpi_msg.c', 'otx2_dpi_test.c')
-
-extra_flags = []
-# This integrated controller runs only on a arm64 machine, remove 32bit warnings
-if not dpdk_conf.get('RTE_ARCH_64')
-    extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
-endif
-
-foreach flag: extra_flags
-    if cc.has_argument(flag)
-        cflags += flag
-    endif
-endforeach
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c b/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
deleted file mode 100644
index 655de216ab..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_MSG_H_
-#define _DPI_MSG_H_
-
-#include <dirent.h>
-#include <fcntl.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "otx2_dpi_rawdev.h"
-
-/* DPI PF DBDF information macro's */
-#define DPI_PF_DBDF_DOMAIN      0
-#define DPI_PF_DBDF_BUS         5
-#define DPI_PF_DBDF_DEVICE      0
-#define DPI_PF_DBDF_FUNCTION    0
-
-#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
-
-union dpi_mbox_message_u {
-	uint64_t u[2];
-	struct dpi_mbox_message_s {
-		/* VF ID to configure */
-		uint64_t vfid           :4;
-		/* Command code */
-		uint64_t cmd            :4;
-		/* Command buffer size in 8-byte words */
-		uint64_t csize          :14;
-		/* aura of the command buffer */
-		uint64_t aura           :20;
-		/* SSO PF function */
-		uint64_t sso_pf_func    :16;
-		/* NPA PF function */
-		uint64_t npa_pf_func    :16;
-	} s;
-};
-
-static inline int
-send_msg_to_pf(struct rte_pci_addr *pci, const char *value, int size)
-{
-	char buff[255] = { 0 };
-	int res, fd;
-
-	res = snprintf(buff, sizeof(buff), "%s/" PCI_PRI_FMT "/%s",
-		       rte_pci_get_sysfs_path(), pci->domain,
-		       pci->bus, DPI_PF_DBDF_DEVICE & 0x7,
-		       DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
-	if ((res < 0) || ((size_t)res > sizeof(buff)))
-		return -ERANGE;
-
-	fd = open(buff, O_WRONLY);
-	if (fd < 0)
-		return -EACCES;
-	res = write(fd, value, size);
-	close(fd);
-	if (res < 0)
-		return -EACCES;
-
-	return 0;
-}
-
-int
-otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_OPEN;
-	mbox_msg.s.csize = size;
-	mbox_msg.s.aura = gaura;
-	mbox_msg.s.sso_pf_func = otx2_sso_pf_func_get();
-	mbox_msg.s.npa_pf_func = otx2_npa_pf_func_get();
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-int
-otx2_dpi_queue_close(struct dpi_vf_s *dpivf)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-#endif /* _DPI_MSG_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
deleted file mode 100644
index 8c01f25ec7..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include <otx2_common.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static const struct rte_pci_id pci_dma_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_DPI_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* Enable/Disable DMA queue */
-static inline int
-dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb)
-{
-	if (enb)
-		otx2_write64(0x1, dpivf->vf_bar0 + DPI_VDMA_EN);
-	else
-		otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Free DMA Queue instruction buffers, and send close notification to PF */
-static inline int
-dma_queue_finish(struct dpi_vf_s *dpivf)
-{
-	uint32_t timeout = 0, sleep = 1;
-	uint64_t reg = 0ULL;
-
-	/* Wait for SADDR to become idle */
-	reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	while (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) {
-		rte_delay_ms(sleep);
-		timeout++;
-		if (timeout >= DPI_QFINISH_TIMEOUT) {
-			otx2_dpi_dbg("Timeout!!! Closing Forcibly");
-			break;
-		}
-		reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	}
-
-	if (otx2_dpi_queue_close(dpivf) < 0)
-		return -EACCES;
-
-	rte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr);
-	dpivf->vf_bar0 = (uintptr_t)NULL;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Write an arbitrary number of command words to a command queue */
-static __rte_always_inline enum dpi_dma_queue_result_e
-dma_queue_write(struct dpi_vf_s *dpi, uint16_t cmd_count, uint64_t *cmds)
-{
-	if ((cmd_count < 1) || (cmd_count > 64))
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	if (cmds == NULL)
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	/* Room available in the current buffer for the command */
-	if (dpi->index + cmd_count < dpi->pool_size_m1) {
-		uint64_t *ptr = dpi->base_ptr;
-
-		ptr += dpi->index;
-		dpi->index += cmd_count;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-	} else {
-		void *new_buffer;
-		uint64_t *ptr;
-		int count;
-
-		/* Allocate new command buffer, return if failed */
-		if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-		    new_buffer == NULL) {
-			return DPI_DMA_QUEUE_NO_MEMORY;
-		}
-		ptr = dpi->base_ptr;
-		/* Figure out how many command words will fit in this buffer.
-		 * One location will be needed for the next buffer pointer.
-		 **/
-		count = dpi->pool_size_m1 - dpi->index;
-		ptr += dpi->index;
-		cmd_count -= count;
-		while (count--)
-			*ptr++ = *cmds++;
-		/* Chunk next ptr is 2DWORDs, second DWORD is reserved. */
-		*ptr++ = (uint64_t)new_buffer;
-		*ptr   = 0;
-		/* The current buffer is full and has a link to the next buffer.
-		 * Time to write the rest of the commands into the new buffer.
-		 **/
-		dpi->base_ptr = new_buffer;
-		dpi->index = cmd_count;
-		ptr = new_buffer;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-		/* queue index may greater than pool size */
-		if (dpi->index >= dpi->pool_size_m1) {
-			if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-			    new_buffer == NULL) {
-				return DPI_DMA_QUEUE_NO_MEMORY;
-			}
-			/* Write next buffer address */
-			*ptr = (uint64_t)new_buffer;
-			dpi->base_ptr = new_buffer;
-			dpi->index = 0;
-		}
-	}
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Submit a DMA command to the DMA queues. */
-static __rte_always_inline int
-dma_queue_submit(struct rte_rawdev *dev, uint16_t cmd_count, uint64_t *cmds)
-{
-	struct dpi_vf_s *dpivf = dev->dev_private;
-	enum dpi_dma_queue_result_e result;
-
-	result = dma_queue_write(dpivf, cmd_count, cmds);
-	rte_wmb();
-	if (likely(result == DPI_DMA_QUEUE_SUCCESS))
-		otx2_write64((uint64_t)cmd_count,
-			     dpivf->vf_bar0 + DPI_VDMA_DBELL);
-
-	return result;
-}
-
-/* Enqueue buffers to DMA queue
- * returns number of buffers enqueued successfully
- */
-static int
-otx2_dpi_rawdev_enqueue_bufs(struct rte_rawdev *dev,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	struct dpi_dma_buf_ptr_s *cmd;
-	uint32_t c = 0;
-
-	for (c = 0; c < count; c++) {
-		uint64_t dpi_cmd[DPI_DMA_CMD_SIZE] = {0};
-		union dpi_dma_instr_hdr_u *hdr;
-		uint16_t index = 0, i;
-
-		hdr = (union dpi_dma_instr_hdr_u *)&dpi_cmd[0];
-		cmd = (struct dpi_dma_buf_ptr_s *)buffers[c]->buf_addr;
-
-		hdr->s.xtype = ctx->xtype & DPI_XTYPE_MASK;
-		hdr->s.pt = ctx->pt & DPI_HDR_PT_MASK;
-		/* Request initiated with byte write completion, but completion
-		 * pointer not provided
-		 */
-		if ((hdr->s.pt == DPI_HDR_PT_ZBW_CA ||
-		     hdr->s.pt == DPI_HDR_PT_ZBW_NC) && cmd->comp_ptr == NULL)
-			return c;
-
-		cmd->comp_ptr->cdata = DPI_REQ_CDATA;
-		hdr->s.ptr = (uint64_t)cmd->comp_ptr;
-		hdr->s.deallocv = ctx->deallocv;
-		hdr->s.tt = ctx->tt & DPI_W0_TT_MASK;
-		hdr->s.grp = ctx->grp & DPI_W0_GRP_MASK;
-
-		/* If caller provides completion ring details, then only queue
-		 * completion address for later polling.
-		 */
-		if (ctx->c_ring) {
-			ctx->c_ring->compl_data[ctx->c_ring->tail] =
-								 cmd->comp_ptr;
-			STRM_INC(ctx->c_ring);
-		}
-
-		if (hdr->s.deallocv)
-			hdr->s.pvfe = 1;
-
-		if (hdr->s.pt == DPI_HDR_PT_WQP)
-			hdr->s.ptr = hdr->s.ptr | DPI_HDR_PT_WQP_STATUSNC;
-
-		index += 4;
-		hdr->s.fport = 0;
-		hdr->s.lport = 0;
-		if (ctx->xtype !=  DPI_XTYPE_INTERNAL_ONLY)
-			hdr->s.lport = ctx->pem_id;
-
-		/* For inbound case, src pointers are last pointers.
-		 * For all other cases, src pointers are first pointers.
-		 */
-		if (ctx->xtype ==  DPI_XTYPE_INBOUND) {
-			hdr->s.nfst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-		} else {
-			hdr->s.nfst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-		}
-		if (dma_queue_submit(dev, index, dpi_cmd))
-			return c;
-	}
-	return c;
-}
-
-/* Check for command completion, returns number of commands completed */
-static int
-otx2_dpi_rawdev_dequeue_bufs(struct rte_rawdev *dev __rte_unused,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	unsigned int i = 0, headp;
-
-	/* No completion ring to poll */
-	if (ctx->c_ring == NULL)
-		return 0;
-
-	headp = ctx->c_ring->head;
-	for (i = 0; i < count && (headp != ctx->c_ring->tail); i++) {
-		struct dpi_dma_req_compl_s *comp_ptr =
-					 ctx->c_ring->compl_data[headp];
-
-		if (comp_ptr->cdata)
-			break;
-
-		/* Request Completed */
-		buffers[i] = (void *)comp_ptr;
-		headp = (headp + 1) % ctx->c_ring->max_cnt;
-	}
-	ctx->c_ring->head = headp;
-
-	return i;
-}
-
-static int
-otx2_dpi_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_START;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static void
-otx2_dpi_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_STOP;
-}
-
-static int
-otx2_dpi_rawdev_close(struct rte_rawdev *dev)
-{
-	dma_engine_enb_dis(dev->dev_private, false);
-	dma_queue_finish(dev->dev_private);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_reset(struct rte_rawdev *dev)
-{
-	return dev ? DPI_QUEUE_STOP : DPI_QUEUE_START;
-}
-
-static int
-otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct dpi_rawdev_conf_s *conf = config;
-	struct dpi_vf_s *dpivf = NULL;
-	void *buf = NULL;
-	uintptr_t pool;
-	uint32_t gaura;
-
-	if (conf == NULL || config_size != sizeof(*conf)) {
-		otx2_dpi_dbg("NULL or invalid configuration");
-		return -EINVAL;
-	}
-	dpivf = (struct dpi_vf_s *)dev->dev_private;
-	dpivf->chunk_pool = conf->chunk_pool;
-	if (rte_mempool_get(conf->chunk_pool, &buf) || (buf == NULL)) {
-		otx2_err("Unable allocate buffer");
-		return -ENODEV;
-	}
-	dpivf->base_ptr = buf;
-	otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-	dpivf->pool_size_m1 = (DPI_CHUNK_SIZE >> 3) - 2;
-	pool = (uintptr_t)((struct rte_mempool *)conf->chunk_pool)->pool_id;
-	gaura = npa_lf_aura_handle_to_aura(pool);
-	otx2_write64(0, dpivf->vf_bar0 + DPI_VDMA_REQQ_CTL);
-	otx2_write64(((uint64_t)buf >> 7) << 7,
-		     dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	if (otx2_dpi_queue_open(dpivf, DPI_CHUNK_SIZE, gaura) < 0) {
-		otx2_err("Unable to open DPI VF %d", dpivf->vf_id);
-		rte_mempool_put(conf->chunk_pool, buf);
-		return -EACCES;
-	}
-	dma_engine_enb_dis(dpivf, true);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static const struct rte_rawdev_ops dpi_rawdev_ops = {
-	.dev_configure = otx2_dpi_rawdev_configure,
-	.dev_start = otx2_dpi_rawdev_start,
-	.dev_stop = otx2_dpi_rawdev_stop,
-	.dev_close = otx2_dpi_rawdev_close,
-	.dev_reset = otx2_dpi_rawdev_reset,
-	.enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs,
-	.dequeue_bufs = otx2_dpi_rawdev_dequeue_bufs,
-	.dev_selftest = test_otx2_dma_rawdev,
-};
-
-static int
-otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct dpi_vf_s *dpivf = NULL;
-	struct rte_rawdev *rawdev;
-	uint16_t vf_id;
-
-	/* For secondary processes, the primary has done all the work */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return DPI_DMA_QUEUE_SUCCESS;
-
-	if (pci_dev->mem_resource[0].addr == NULL) {
-		otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr,
-			     pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate device structure */
-	rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct dpi_vf_s),
-					 rte_socket_id());
-	if (rawdev == NULL) {
-		otx2_err("Rawdev allocation failed");
-		return -EINVAL;
-	}
-
-	rawdev->dev_ops = &dpi_rawdev_ops;
-	rawdev->device = &pci_dev->device;
-	rawdev->driver_name = pci_dev->driver->driver.name;
-
-	dpivf = rawdev->dev_private;
-	if (dpivf->state != DPI_QUEUE_STOP) {
-		otx2_dpi_dbg("Device already started!!!");
-		return -ENODEV;
-	}
-
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-	vf_id -= 1;
-	dpivf->dev = pci_dev;
-	dpivf->state = DPI_QUEUE_START;
-	dpivf->vf_id = vf_id;
-	dpivf->vf_bar0 = (uintptr_t)pci_dev->mem_resource[0].addr;
-	dpivf->vf_bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct dpi_vf_s *dpivf;
-
-	if (pci_dev == NULL) {
-		otx2_dpi_dbg("Invalid pci_dev of the device!");
-		return -EINVAL;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_dpi_dbg("Invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	dpivf = (struct dpi_vf_s *)rawdev->dev_private;
-	dma_engine_enb_dis(dpivf, false);
-	dma_queue_finish(dpivf);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_dpi_rawdev_pmd = {
-	.id_table  = pci_dma_map,
-	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
-	.probe     = otx2_dpi_rawdev_probe,
-	.remove    = otx2_dpi_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(dpi_rawdev_pci_driver, rte_dpi_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(dpi_rawdev_pci_driver, pci_dma_map);
-RTE_PMD_REGISTER_KMOD_DEP(dpi_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
deleted file mode 100644
index 2bc9e3da3c..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_RAWDEV_H_
-#define _DPI_RAWDEV_H_
-
-#include "otx2_common.h"
-#include "otx2_mempool.h"
-
-#define DPI_QUEUE_OPEN	0x1
-#define DPI_QUEUE_CLOSE	0x2
-
-/* DPI VF register offsets from VF_BAR0 */
-#define DPI_VDMA_EN             (0x0)
-#define DPI_VDMA_REQQ_CTL       (0x8)
-#define DPI_VDMA_DBELL          (0x10)
-#define DPI_VDMA_SADDR          (0x18)
-#define DPI_VDMA_COUNTS         (0x20)
-#define DPI_VDMA_NADDR          (0x28)
-#define DPI_VDMA_IWBUSY         (0x30)
-#define DPI_VDMA_CNT            (0x38)
-#define DPI_VF_INT              (0x100)
-#define DPI_VF_INT_W1S          (0x108)
-#define DPI_VF_INT_ENA_W1C      (0x110)
-#define DPI_VF_INT_ENA_W1S      (0x118)
-
-#define DPI_MAX_VFS             8
-#define DPI_DMA_CMD_SIZE        64
-#define DPI_CHUNK_SIZE		1024
-#define DPI_QUEUE_STOP		0x0
-#define DPI_QUEUE_START		0x1
-
-#define DPI_VDMA_SADDR_REQ_IDLE	63
-#define DPI_MAX_POINTER		15
-#define STRM_INC(s)	((s)->tail = ((s)->tail + 1) % (s)->max_cnt)
-#define DPI_QFINISH_TIMEOUT	(10 * 1000)
-
-/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
-#define DPI_XTYPE_OUTBOUND      (0)
-#define DPI_XTYPE_INBOUND       (1)
-#define DPI_XTYPE_INTERNAL_ONLY (2)
-#define DPI_XTYPE_EXTERNAL_ONLY (3)
-#define DPI_XTYPE_MASK		0x3
-#define DPI_HDR_PT_ZBW_CA	0x0
-#define DPI_HDR_PT_ZBW_NC	0x1
-#define DPI_HDR_PT_WQP		0x2
-#define DPI_HDR_PT_WQP_NOSTATUS	0x0
-#define DPI_HDR_PT_WQP_STATUSCA	0x1
-#define DPI_HDR_PT_WQP_STATUSNC	0x3
-#define DPI_HDR_PT_CNT		0x3
-#define DPI_HDR_PT_MASK		0x3
-#define DPI_W0_TT_MASK		0x3
-#define DPI_W0_GRP_MASK		0x3FF
-/* Set Completion data to 0xFF when request submitted,
- * upon successful request completion engine reset to completion status
- */
-#define DPI_REQ_CDATA		0xFF
-
-struct dpi_vf_s {
-	struct rte_pci_device *dev;
-	uint8_t state;
-	uint16_t vf_id;
-	uint8_t domain;
-	uintptr_t vf_bar0;
-	uintptr_t vf_bar2;
-
-	uint16_t pool_size_m1;
-	uint16_t index;
-	uint64_t *base_ptr;
-	void *chunk_pool;
-	struct otx2_mbox *mbox;
-};
-
-struct dpi_rawdev_conf_s {
-	void *chunk_pool;
-};
-
-enum dpi_dma_queue_result_e {
-	DPI_DMA_QUEUE_SUCCESS = 0,
-	DPI_DMA_QUEUE_NO_MEMORY = -1,
-	DPI_DMA_QUEUE_INVALID_PARAM = -2,
-};
-
-struct dpi_dma_req_compl_s {
-	uint64_t cdata;
-	void (*compl_cb)(void *dev, void *arg);
-	void *cb_data;
-};
-
-union dpi_dma_ptr_u {
-	uint64_t u[2];
-	struct dpi_dma_s {
-		uint64_t length:16;
-		uint64_t reserved:44;
-		uint64_t bed:1; /* Big-Endian */
-		uint64_t alloc_l2:1;
-		uint64_t full_write:1;
-		uint64_t invert:1;
-		uint64_t ptr;
-	} s;
-};
-
-struct dpi_dma_buf_ptr_s {
-	union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */
-	union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */
-	uint8_t rptr_cnt;
-	uint8_t wptr_cnt;
-	struct dpi_dma_req_compl_s *comp_ptr;
-};
-
-struct dpi_cring_data_s {
-	struct dpi_dma_req_compl_s **compl_data;
-	uint16_t max_cnt;
-	uint16_t head;
-	uint16_t tail;
-};
-
-struct dpi_dma_queue_ctx_s {
-	uint16_t xtype:2;
-
-	/* Completion pointer type */
-	uint16_t pt:2;
-
-	/* Completion updated using WQE */
-	uint16_t tt:2;
-	uint16_t grp:10;
-	uint32_t tag;
-
-	/* Valid only for Outbound only mode */
-	uint16_t aura:12;
-	uint16_t csel:1;
-	uint16_t ca:1;
-	uint16_t fi:1;
-	uint16_t ii:1;
-	uint16_t fl:1;
-
-	uint16_t pvfe:1;
-	uint16_t dealloce:1;
-	uint16_t req_type:2;
-	uint16_t use_lock:1;
-	uint16_t deallocv;
-	uint16_t  pem_id;
-
-	struct dpi_cring_data_s *c_ring;
-};
-
-/* DPI DMA Instruction Header Format */
-union dpi_dma_instr_hdr_u {
-	uint64_t u[4];
-
-	struct dpi_dma_instr_hdr_s_s {
-		uint64_t tag:32;
-		uint64_t tt:2;
-		uint64_t grp:10;
-		uint64_t reserved_44_47:4;
-		uint64_t nfst:4;
-		uint64_t reserved_52_53:2;
-		uint64_t nlst:4;
-		uint64_t reserved_58_63:6;
-		/* Word 0 - End */
-
-		uint64_t aura:12;
-		uint64_t reserved_76_79:4;
-		uint64_t deallocv:16;
-		uint64_t dealloce:1;
-		uint64_t pvfe:1;
-		uint64_t reserved_98_99:2;
-		uint64_t pt:2;
-		uint64_t reserved_102_103:2;
-		uint64_t fl:1;
-		uint64_t ii:1;
-		uint64_t fi:1;
-		uint64_t ca:1;
-		uint64_t csel:1;
-		uint64_t reserved_109_111:3;
-		uint64_t xtype:2;
-		uint64_t reserved_114_119:6;
-		uint64_t fport:2;
-		uint64_t reserved_122_123:2;
-		uint64_t lport:2;
-		uint64_t reserved_126_127:2;
-		/* Word 1 - End */
-
-		uint64_t ptr:64;
-		/* Word 2 - End */
-
-		uint64_t reserved_192_255:64;
-		/* Word 3 - End */
-	} s;
-};
-
-int otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura);
-int otx2_dpi_queue_close(struct dpi_vf_s *dpivf);
-int test_otx2_dma_rawdev(uint16_t val);
-
-#endif /* _DPI_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_test.c b/drivers/raw/octeontx2_dma/otx2_dpi_test.c
deleted file mode 100644
index cec6ca91b0..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_test.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_debug.h>
-#include <rte_eal.h>
-#include <rte_log.h>
-#include <rte_malloc.h>
-#include <rte_mbuf.h>
-#include <rte_mbuf_pool_ops.h>
-#include <rte_memcpy.h>
-#include <rte_memory.h>
-#include <rte_mempool.h>
-#include <rte_per_lcore.h>
-#include <rte_rawdev.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static struct dpi_cring_data_s cring;
-
-static uint8_t
-buffer_fill(uint8_t *addr, int len, uint8_t val)
-{
-	int j = 0;
-
-	memset(addr, 0, len);
-	for (j = 0; j < len; j++)
-		*(addr + j) = val++;
-
-	return val;
-}
-
-static int
-validate_buffer(uint8_t *saddr, uint8_t *daddr, int len)
-{
-	int j = 0, ret = 0;
-
-	for (j = 0; j < len; j++) {
-		if (*(saddr + j) != *(daddr + j)) {
-			otx2_dpi_dbg("FAIL: Data Integrity failed");
-			otx2_dpi_dbg("index: %d, Expected: 0x%x, Actual: 0x%x",
-				     j, *(saddr + j), *(daddr + j));
-			ret = -1;
-			break;
-		}
-	}
-
-	return ret;
-}
-
-static inline int
-dma_test_internal(int dma_port, int buf_size)
-{
-	struct dpi_dma_req_compl_s *comp_data;
-	struct dpi_dma_queue_ctx_s ctx = {0};
-	struct rte_rawdev_buf buf = {0};
-	struct rte_rawdev_buf *d_buf[1];
-	struct rte_rawdev_buf *bufp[1];
-	struct dpi_dma_buf_ptr_s cmd;
-	union dpi_dma_ptr_u rptr = { {0} };
-	union dpi_dma_ptr_u wptr = { {0} };
-	uint8_t *fptr, *lptr;
-	int ret;
-
-	fptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	lptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	comp_data = rte_malloc("dummy", buf_size, 128);
-	if (fptr == NULL || lptr == NULL || comp_data == NULL) {
-		otx2_dpi_dbg("Unable to allocate internal memory");
-		return -ENOMEM;
-	}
-
-	buffer_fill(fptr, buf_size, 0);
-	memset(&cmd, 0, sizeof(struct dpi_dma_buf_ptr_s));
-	memset(lptr, 0, buf_size);
-	memset(comp_data, 0, buf_size);
-	rptr.s.ptr = (uint64_t)fptr;
-	rptr.s.length = buf_size;
-	wptr.s.ptr = (uint64_t)lptr;
-	wptr.s.length = buf_size;
-	cmd.rptr[0] = &rptr;
-	cmd.wptr[0] = &wptr;
-	cmd.rptr_cnt = 1;
-	cmd.wptr_cnt = 1;
-	cmd.comp_ptr = comp_data;
-	buf.buf_addr = (void *)&cmd;
-	bufp[0] = &buf;
-
-	ctx.xtype = DPI_XTYPE_INTERNAL_ONLY;
-	ctx.pt = 0;
-	ctx.c_ring = &cring;
-
-	ret = rte_rawdev_enqueue_buffers(dma_port,
-					 (struct rte_rawdev_buf **)bufp, 1,
-					 &ctx);
-	if (ret < 0) {
-		otx2_dpi_dbg("Enqueue request failed");
-		return 0;
-	}
-
-	/* Wait and dequeue completion */
-	do {
-		sleep(1);
-		ret = rte_rawdev_dequeue_buffers(dma_port, &d_buf[0], 1, &ctx);
-		if (ret)
-			break;
-
-		otx2_dpi_dbg("Dequeue request not completed");
-	} while (1);
-
-	if (validate_buffer(fptr, lptr, buf_size)) {
-		otx2_dpi_dbg("DMA transfer failed\n");
-		return -EAGAIN;
-	}
-	otx2_dpi_dbg("Internal Only DMA transfer successfully completed");
-
-	if (lptr)
-		rte_free(lptr);
-	if (fptr)
-		rte_free(fptr);
-	if (comp_data)
-		rte_free(comp_data);
-
-	return 0;
-}
-
-static void *
-dpi_create_mempool(void)
-{
-	void *chunk_pool = NULL;
-	char pool_name[25];
-	int ret;
-
-	snprintf(pool_name, sizeof(pool_name), "dpi_chunk_pool");
-
-	chunk_pool = (void *)rte_mempool_create_empty(pool_name, 1024, 1024,
-						      0, 0, rte_socket_id(), 0);
-	if (chunk_pool == NULL) {
-		otx2_dpi_dbg("Unable to create memory pool.");
-		return NULL;
-	}
-
-	ret = rte_mempool_set_ops_byname(chunk_pool,
-					 rte_mbuf_platform_mempool_ops(), NULL);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to set pool ops");
-		rte_mempool_free(chunk_pool);
-		return NULL;
-	}
-
-	ret = rte_mempool_populate_default(chunk_pool);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to populate pool");
-		return NULL;
-	}
-
-	return chunk_pool;
-}
-
-int
-test_otx2_dma_rawdev(uint16_t val)
-{
-	struct rte_rawdev_info rdev_info = {0};
-	struct dpi_rawdev_conf_s conf = {0};
-	int ret, i, size = 1024;
-	int nb_ports;
-
-	RTE_SET_USED(val);
-	nb_ports = rte_rawdev_count();
-	if (nb_ports == 0) {
-		otx2_dpi_dbg("No Rawdev ports - bye");
-		return -ENODEV;
-	}
-
-	i = rte_rawdev_get_dev_id("DPI:5:00.1");
-	/* Configure rawdev ports */
-	conf.chunk_pool = dpi_create_mempool();
-	rdev_info.dev_private = &conf;
-	ret = rte_rawdev_configure(i, (rte_rawdev_obj_t)&rdev_info,
-			sizeof(conf));
-	if (ret) {
-		otx2_dpi_dbg("Unable to configure DPIVF %d", i);
-		return -ENODEV;
-	}
-	otx2_dpi_dbg("rawdev %d configured successfully", i);
-
-	/* Each stream allocate its own completion ring data, store it in
-	 * application context. Each stream needs to use same application
-	 * context for enqueue/dequeue.
-	 */
-	cring.compl_data = rte_malloc("dummy", sizeof(void *) * 1024, 128);
-	if (!cring.compl_data) {
-		otx2_dpi_dbg("Completion allocation failed");
-		return -ENOMEM;
-	}
-
-	cring.max_cnt = 1024;
-	cring.head = 0;
-	cring.tail = 0;
-
-	ret = dma_test_internal(i, size);
-	if (ret)
-		otx2_dpi_dbg("DMA transfer failed for queue %d", i);
-
-	if (rte_rawdev_close(i))
-		otx2_dpi_dbg("Dev close failed for port %d", i);
-
-	if (conf.chunk_pool)
-		rte_mempool_free(conf.chunk_pool);
-
-	return ret;
-}
diff --git a/drivers/raw/octeontx2_dma/version.map b/drivers/raw/octeontx2_dma/version.map
deleted file mode 100644
index 4a76d1d52d..0000000000
--- a/drivers/raw/octeontx2_dma/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_21 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH v3 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-12 12:37 [dpdk-dev] [PATCH v2 1/2] drivers/raw: remove octeontx2-dma driver Radha Mohan Chintakuntla
  2021-08-13  7:00 ` [dpdk-dev] [PATCH v3 " Radha Mohan Chintakuntla
@ 2021-08-13  7:01 ` Radha Mohan Chintakuntla
  2021-08-19  7:59   ` [dpdk-dev] [PATCH v4 " Radha Mohan Chintakuntla
  1 sibling, 1 reply; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-13  7:01 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-ep driver as the dependent
common/octeontx2 will soon be going away. Moreover this driver is no
longer required as the net/octeontx_ep driver is sufficient.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v2:
Fixed DPDK CI reported issues for more documentation failure.

Changes from v1:
Fixed compilation issues in documentation

 MAINTAINERS                               |   6 -
 doc/guides/rawdevs/index.rst              |   1 -
 doc/guides/rawdevs/octeontx2_ep.rst       |  82 ---
 drivers/raw/meson.build                   |   1 -
 drivers/raw/octeontx2_ep/meson.build      |  11 -
 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------
 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h |  52 --
 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------
 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------
 drivers/raw/octeontx2_ep/otx2_ep_test.c   | 172 -----
 drivers/raw/octeontx2_ep/otx2_ep_vf.c     | 475 ------------
 drivers/raw/octeontx2_ep/otx2_ep_vf.h     |  10 -
 drivers/raw/octeontx2_ep/version.map      |   3 -
 13 files changed, 2520 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_ep.rst
 delete mode 100644 drivers/raw/octeontx2_ep/meson.build
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_test.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.h
 delete mode 100644 drivers/raw/octeontx2_ep/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 9f9aa37c68..1d6a408f49 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 EP
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_ep/
-F: doc/guides/rawdevs/octeontx2_ep.rst
-
 NTB
 M: Xiaoyun Li <xiaoyun.li@intel.com>
 M: Jingjing Wu <jingjing.wu@intel.com>
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 228d4a7743..b6cf917443 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,4 +17,3 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_ep.rst b/doc/guides/rawdevs/octeontx2_ep.rst
deleted file mode 100644
index fb9d346ccf..0000000000
--- a/doc/guides/rawdevs/octeontx2_ep.rst
+++ /dev/null
@@ -1,82 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-Marvell OCTEON TX2 End Point Rawdev Driver
-==========================================
-
-OCTEON TX2 has an internal SDP unit which provides End Point mode of operation
-by exposing its IOQs to Host, IOQs are used for packet I/O between Host and
-OCTEON TX2. Each OCTEON TX2 SDP PF supports a max of 128 VFs and Each VF is
-associated with a set of IOQ pairs.
-
-Features
---------
-
-This OCTEON TX2 End Point mode PMD supports
-
-#. Packet Input - Host to OCTEON TX2 with direct data instruction mode.
-
-#. Packet Output - OCTEON TX2 to Host with info pointer mode.
-
-
-Initialization
---------------
-
-The number of SDP VFs enabled, can be controlled by setting sysfs
-entry `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-ep/0000\:04\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
-------------
-
-The OCTEON TX2 SDP End Point VF devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring SDP EP rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to send/receive
-packets to/from the HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct sdp_rawdev_info config = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &config};
-   config.enqdeq_mpool = (void *)rte_mempool_create(...);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info,
-                        sizeof(config));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using SDP VF EP rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, SDP VF devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("SDPEP:x")`` from the test application
-  where x is the VF device's bus id specified in "bus:device.func"(BDF)
-  format. Use this index for further rawdev function calls.
-
-* The driver's selftest rawdev API can be used to verify the SDP EP mode
-  functional tests which can send/receive the raw data packets to/from the
-  EP device.
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index f25d5f322c..87694a758e 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_ep',
         'skeleton',
 ]
 std_deps = ['rawdev']
diff --git a/drivers/raw/octeontx2_ep/meson.build b/drivers/raw/octeontx2_ep/meson.build
deleted file mode 100644
index 8d7c69aa3c..0000000000
--- a/drivers/raw/octeontx2_ep/meson.build
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files(
-        'otx2_ep_enqdeq.c',
-        'otx2_ep_rawdev.c',
-        'otx2_ep_test.c',
-        'otx2_ep_vf.c',
-)
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
deleted file mode 100644
index d04e957d82..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-#include <dirent.h>
-#include <fcntl.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_enqdeq.h"
-
-static void
-sdp_dmazone_free(const struct rte_memzone *mz)
-{
-	const struct rte_memzone *mz_tmp;
-	int ret = 0;
-
-	if (mz == NULL) {
-		otx2_err("Memzone %s : NULL", mz->name);
-		return;
-	}
-
-	mz_tmp = rte_memzone_lookup(mz->name);
-	if (mz_tmp == NULL) {
-		otx2_err("Memzone %s Not Found", mz->name);
-		return;
-	}
-
-	ret = rte_memzone_free(mz);
-	if (ret)
-		otx2_err("Memzone free failed : ret = %d", ret);
-
-}
-
-/* Free IQ resources */
-int
-sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq;
-
-	iq = sdpvf->instr_queue[iq_no];
-	if (iq == NULL) {
-		otx2_err("Invalid IQ[%d]\n", iq_no);
-		return -ENOMEM;
-	}
-
-	rte_free(iq->req_list);
-	iq->req_list = NULL;
-
-	if (iq->iq_mz) {
-		sdp_dmazone_free(iq->iq_mz);
-		iq->iq_mz = NULL;
-	}
-
-	rte_free(sdpvf->instr_queue[iq_no]);
-	sdpvf->instr_queue[iq_no] = NULL;
-
-	sdpvf->num_iqs--;
-
-	otx2_info("IQ[%d] is deleted", iq_no);
-
-	return 0;
-}
-
-/* IQ initialization */
-static int
-sdp_init_instr_queue(struct sdp_device *sdpvf, int iq_no)
-{
-	const struct sdp_config *conf;
-	struct sdp_instr_queue *iq;
-	uint32_t q_size;
-
-	conf = sdpvf->conf;
-	iq = sdpvf->instr_queue[iq_no];
-	q_size = conf->iq.instr_type * conf->num_iqdef_descs;
-
-	/* IQ memory creation for Instruction submission to OCTEON TX2 */
-	iq->iq_mz = rte_memzone_reserve_aligned("iqmz",
-					q_size,
-					rte_socket_id(),
-					RTE_MEMZONE_IOVA_CONTIG,
-					RTE_CACHE_LINE_SIZE);
-	if (iq->iq_mz == NULL) {
-		otx2_err("IQ[%d] memzone alloc failed", iq_no);
-		goto iq_init_fail;
-	}
-
-	iq->base_addr_dma = iq->iq_mz->iova;
-	iq->base_addr = (uint8_t *)iq->iq_mz->addr;
-
-	if (conf->num_iqdef_descs & (conf->num_iqdef_descs - 1)) {
-		otx2_err("IQ[%d] descs not in power of 2", iq_no);
-		goto iq_init_fail;
-	}
-
-	iq->nb_desc = conf->num_iqdef_descs;
-
-	/* Create a IQ request list to hold requests that have been
-	 * posted to OCTEON TX2. This list will be used for freeing the IQ
-	 * data buffer(s) later once the OCTEON TX2 fetched the requests.
-	 */
-	iq->req_list = rte_zmalloc_socket("request_list",
-			(iq->nb_desc * SDP_IQREQ_LIST_SIZE),
-			RTE_CACHE_LINE_SIZE,
-			rte_socket_id());
-	if (iq->req_list == NULL) {
-		otx2_err("IQ[%d] req_list alloc failed", iq_no);
-		goto iq_init_fail;
-	}
-
-	otx2_info("IQ[%d]: base: %p basedma: %lx count: %d",
-		     iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,
-		     iq->nb_desc);
-
-	iq->sdp_dev = sdpvf;
-	iq->q_no = iq_no;
-	iq->fill_cnt = 0;
-	iq->host_write_index = 0;
-	iq->otx_read_index = 0;
-	iq->flush_index = 0;
-
-	/* Initialize the spinlock for this instruction queue */
-	rte_spinlock_init(&iq->lock);
-	rte_spinlock_init(&iq->post_lock);
-
-	rte_atomic64_clear(&iq->iq_flush_running);
-
-	sdpvf->io_qmask.iq |= (1ull << iq_no);
-
-	/* Set 32B/64B mode for each input queue */
-	if (conf->iq.instr_type == 64)
-		sdpvf->io_qmask.iq64B |= (1ull << iq_no);
-
-	iq->iqcmd_64B = (conf->iq.instr_type == 64);
-
-	/* Set up IQ registers */
-	sdpvf->fn_list.setup_iq_regs(sdpvf, iq_no);
-
-	return 0;
-
-iq_init_fail:
-	return -ENOMEM;
-
-}
-
-int
-sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq;
-
-	iq = (struct sdp_instr_queue *)rte_zmalloc("sdp_IQ", sizeof(*iq),
-						RTE_CACHE_LINE_SIZE);
-	if (iq == NULL)
-		return -ENOMEM;
-
-	sdpvf->instr_queue[iq_no] = iq;
-
-	if (sdp_init_instr_queue(sdpvf, iq_no)) {
-		otx2_err("IQ init is failed");
-		goto delete_IQ;
-	}
-	otx2_info("IQ[%d] is created.", sdpvf->num_iqs);
-
-	sdpvf->num_iqs++;
-
-
-	return 0;
-
-delete_IQ:
-	sdp_delete_iqs(sdpvf, iq_no);
-	return -ENOMEM;
-}
-
-static void
-sdp_droq_reset_indices(struct sdp_droq *droq)
-{
-	droq->read_idx  = 0;
-	droq->write_idx = 0;
-	droq->refill_idx = 0;
-	droq->refill_count = 0;
-	rte_atomic64_set(&droq->pkts_pending, 0);
-}
-
-static void
-sdp_droq_destroy_ring_buffers(struct sdp_device *sdpvf,
-				struct sdp_droq *droq)
-{
-	uint32_t idx;
-
-	for (idx = 0; idx < droq->nb_desc; idx++) {
-		if (droq->recv_buf_list[idx].buffer) {
-			rte_mempool_put(sdpvf->enqdeq_mpool,
-				droq->recv_buf_list[idx].buffer);
-
-			droq->recv_buf_list[idx].buffer = NULL;
-		}
-	}
-
-	sdp_droq_reset_indices(droq);
-}
-
-/* Free OQs resources */
-int
-sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	struct sdp_droq *droq;
-
-	droq = sdpvf->droq[oq_no];
-	if (droq == NULL) {
-		otx2_err("Invalid droq[%d]", oq_no);
-		return -ENOMEM;
-	}
-
-	sdp_droq_destroy_ring_buffers(sdpvf, droq);
-	rte_free(droq->recv_buf_list);
-	droq->recv_buf_list = NULL;
-
-	if (droq->info_mz) {
-		sdp_dmazone_free(droq->info_mz);
-		droq->info_mz = NULL;
-	}
-
-	if (droq->desc_ring_mz) {
-		sdp_dmazone_free(droq->desc_ring_mz);
-		droq->desc_ring_mz = NULL;
-	}
-
-	memset(droq, 0, SDP_DROQ_SIZE);
-
-	rte_free(sdpvf->droq[oq_no]);
-	sdpvf->droq[oq_no] = NULL;
-
-	sdpvf->num_oqs--;
-
-	otx2_info("OQ[%d] is deleted", oq_no);
-	return 0;
-}
-
-static int
-sdp_droq_setup_ring_buffers(struct sdp_device *sdpvf,
-		struct sdp_droq *droq)
-{
-	struct sdp_droq_desc *desc_ring = droq->desc_ring;
-	uint32_t idx;
-	void *buf;
-
-	for (idx = 0; idx < droq->nb_desc; idx++) {
-		if (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||
-		    (buf == NULL)) {
-			otx2_err("OQ buffer alloc failed");
-			droq->stats.rx_alloc_failure++;
-			/* sdp_droq_destroy_ring_buffers(droq);*/
-			return -ENOMEM;
-		}
-
-		droq->recv_buf_list[idx].buffer = buf;
-		droq->info_list[idx].length = 0;
-
-		/* Map ring buffers into memory */
-		desc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma +
-			(idx * SDP_DROQ_INFO_SIZE));
-
-		desc_ring[idx].buffer_ptr = rte_mem_virt2iova(buf);
-	}
-
-	sdp_droq_reset_indices(droq);
-
-	return 0;
-}
-
-static void *
-sdp_alloc_info_buffer(struct sdp_device *sdpvf __rte_unused,
-	struct sdp_droq *droq)
-{
-	droq->info_mz = rte_memzone_reserve_aligned("OQ_info_list",
-				(droq->nb_desc * SDP_DROQ_INFO_SIZE),
-				rte_socket_id(),
-				RTE_MEMZONE_IOVA_CONTIG,
-				RTE_CACHE_LINE_SIZE);
-
-	if (droq->info_mz == NULL)
-		return NULL;
-
-	droq->info_list_dma = droq->info_mz->iova;
-	droq->info_alloc_size = droq->info_mz->len;
-	droq->info_base_addr = (size_t)droq->info_mz->addr;
-
-	return droq->info_mz->addr;
-}
-
-/* OQ initialization */
-static int
-sdp_init_droq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	const struct sdp_config *conf = sdpvf->conf;
-	uint32_t c_refill_threshold;
-	uint32_t desc_ring_size;
-	struct sdp_droq *droq;
-
-	otx2_info("OQ[%d] Init start", q_no);
-
-	droq = sdpvf->droq[q_no];
-	droq->sdp_dev = sdpvf;
-	droq->q_no = q_no;
-
-	c_refill_threshold = conf->oq.refill_threshold;
-	droq->nb_desc      = conf->num_oqdef_descs;
-	droq->buffer_size  = conf->oqdef_buf_size;
-
-	/* OQ desc_ring set up */
-	desc_ring_size = droq->nb_desc * SDP_DROQ_DESC_SIZE;
-	droq->desc_ring_mz = rte_memzone_reserve_aligned("sdp_oqmz",
-						desc_ring_size,
-						rte_socket_id(),
-						RTE_MEMZONE_IOVA_CONTIG,
-						RTE_CACHE_LINE_SIZE);
-
-	if (droq->desc_ring_mz == NULL) {
-		otx2_err("OQ:%d desc_ring allocation failed", q_no);
-		goto init_droq_fail;
-	}
-
-	droq->desc_ring_dma = droq->desc_ring_mz->iova;
-	droq->desc_ring = (struct sdp_droq_desc *)droq->desc_ring_mz->addr;
-
-	otx2_sdp_dbg("OQ[%d]: desc_ring: virt: 0x%p, dma: %lx",
-		    q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);
-	otx2_sdp_dbg("OQ[%d]: num_desc: %d", q_no, droq->nb_desc);
-
-
-	/* OQ info_list set up */
-	droq->info_list = sdp_alloc_info_buffer(sdpvf, droq);
-	if (droq->info_list == NULL) {
-		otx2_err("memory allocation failed for OQ[%d] info_list", q_no);
-		goto init_droq_fail;
-	}
-
-	/* OQ buf_list set up */
-	droq->recv_buf_list = rte_zmalloc_socket("recv_buf_list",
-				(droq->nb_desc * SDP_DROQ_RECVBUF_SIZE),
-				 RTE_CACHE_LINE_SIZE, rte_socket_id());
-	if (droq->recv_buf_list == NULL) {
-		otx2_err("OQ recv_buf_list alloc failed");
-		goto init_droq_fail;
-	}
-
-	if (sdp_droq_setup_ring_buffers(sdpvf, droq))
-		goto init_droq_fail;
-
-	droq->refill_threshold = c_refill_threshold;
-	rte_spinlock_init(&droq->lock);
-
-
-	/* Set up OQ registers */
-	sdpvf->fn_list.setup_oq_regs(sdpvf, q_no);
-
-	sdpvf->io_qmask.oq |= (1ull << q_no);
-
-	return 0;
-
-init_droq_fail:
-	return -ENOMEM;
-}
-
-/* OQ configuration and setup */
-int
-sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	struct sdp_droq *droq;
-
-	/* Allocate new droq. */
-	droq = (struct sdp_droq *)rte_zmalloc("sdp_OQ",
-				sizeof(*droq), RTE_CACHE_LINE_SIZE);
-	if (droq == NULL) {
-		otx2_err("Droq[%d] Creation Failed", oq_no);
-		return -ENOMEM;
-	}
-	sdpvf->droq[oq_no] = droq;
-
-	if (sdp_init_droq(sdpvf, oq_no)) {
-		otx2_err("Droq[%d] Initialization failed", oq_no);
-		goto delete_OQ;
-	}
-	otx2_info("OQ[%d] is created.", oq_no);
-
-	sdpvf->num_oqs++;
-
-	return 0;
-
-delete_OQ:
-	sdp_delete_oqs(sdpvf, oq_no);
-	return -ENOMEM;
-}
-
-static inline void
-sdp_iqreq_delete(struct sdp_device *sdpvf,
-		struct sdp_instr_queue *iq, uint32_t idx)
-{
-	uint32_t reqtype;
-	void *buf;
-
-	buf     = iq->req_list[idx].buf;
-	reqtype = iq->req_list[idx].reqtype;
-
-	switch (reqtype) {
-	case SDP_REQTYPE_NORESP:
-		rte_mempool_put(sdpvf->enqdeq_mpool, buf);
-		otx2_sdp_dbg("IQ buffer freed at idx[%d]", idx);
-		break;
-
-	case SDP_REQTYPE_NORESP_GATHER:
-	case SDP_REQTYPE_NONE:
-	default:
-		otx2_info("This iqreq mode is not supported:%d", reqtype);
-
-	}
-
-	/* Reset the request list at this index */
-	iq->req_list[idx].buf = NULL;
-	iq->req_list[idx].reqtype = 0;
-}
-
-static inline void
-sdp_iqreq_add(struct sdp_instr_queue *iq, void *buf,
-		uint32_t reqtype)
-{
-	iq->req_list[iq->host_write_index].buf = buf;
-	iq->req_list[iq->host_write_index].reqtype = reqtype;
-
-	otx2_sdp_dbg("IQ buffer added at idx[%d]", iq->host_write_index);
-
-}
-
-static void
-sdp_flush_iq(struct sdp_device *sdpvf,
-		struct sdp_instr_queue *iq,
-		uint32_t pending_thresh __rte_unused)
-{
-	uint32_t instr_processed = 0;
-
-	rte_spinlock_lock(&iq->lock);
-
-	iq->otx_read_index = sdpvf->fn_list.update_iq_read_idx(iq);
-	while (iq->flush_index != iq->otx_read_index) {
-		/* Free the IQ data buffer to the pool */
-		sdp_iqreq_delete(sdpvf, iq, iq->flush_index);
-		iq->flush_index =
-			sdp_incr_index(iq->flush_index, 1, iq->nb_desc);
-
-		instr_processed++;
-	}
-
-	iq->stats.instr_processed = instr_processed;
-	rte_atomic64_sub(&iq->instr_pending, instr_processed);
-
-	rte_spinlock_unlock(&iq->lock);
-}
-
-static inline void
-sdp_ring_doorbell(struct sdp_device *sdpvf __rte_unused,
-		struct sdp_instr_queue *iq)
-{
-	otx2_write64(iq->fill_cnt, iq->doorbell_reg);
-
-	/* Make sure doorbell writes observed by HW */
-	rte_io_wmb();
-	iq->fill_cnt = 0;
-
-}
-
-static inline int
-post_iqcmd(struct sdp_instr_queue *iq, uint8_t *iqcmd)
-{
-	uint8_t *iqptr, cmdsize;
-
-	/* This ensures that the read index does not wrap around to
-	 * the same position if queue gets full before OCTEON TX2 could
-	 * fetch any instr.
-	 */
-	if (rte_atomic64_read(&iq->instr_pending) >=
-			      (int32_t)(iq->nb_desc - 1)) {
-		otx2_err("IQ is full, pending:%ld",
-			 (long)rte_atomic64_read(&iq->instr_pending));
-
-		return SDP_IQ_SEND_FAILED;
-	}
-
-	/* Copy cmd into iq */
-	cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
-	iqptr   = iq->base_addr + (cmdsize * iq->host_write_index);
-
-	rte_memcpy(iqptr, iqcmd, cmdsize);
-
-	otx2_sdp_dbg("IQ cmd posted @ index:%d", iq->host_write_index);
-
-	/* Increment the host write index */
-	iq->host_write_index =
-		sdp_incr_index(iq->host_write_index, 1, iq->nb_desc);
-
-	iq->fill_cnt++;
-
-	/* Flush the command into memory. We need to be sure the data
-	 * is in memory before indicating that the instruction is
-	 * pending.
-	 */
-	rte_smp_wmb();
-	rte_atomic64_inc(&iq->instr_pending);
-
-	/* SDP_IQ_SEND_SUCCESS */
-	return 0;
-}
-
-
-static int
-sdp_send_data(struct sdp_device *sdpvf,
-	      struct sdp_instr_queue *iq, void *cmd)
-{
-	uint32_t ret;
-
-	/* Lock this IQ command queue before posting instruction */
-	rte_spinlock_lock(&iq->post_lock);
-
-	/* Submit IQ command */
-	ret = post_iqcmd(iq, cmd);
-
-	if (ret == SDP_IQ_SEND_SUCCESS) {
-		sdp_ring_doorbell(sdpvf, iq);
-
-		iq->stats.instr_posted++;
-		otx2_sdp_dbg("Instr submit success posted: %ld\n",
-			     (long)iq->stats.instr_posted);
-
-	} else {
-		iq->stats.instr_dropped++;
-		otx2_err("Instr submit failed, dropped: %ld\n",
-			 (long)iq->stats.instr_dropped);
-
-	}
-
-	rte_spinlock_unlock(&iq->post_lock);
-
-	return ret;
-}
-
-
-/* Enqueue requests/packets to SDP IQ queue.
- * returns number of requests enqueued successfully
- */
-int
-sdp_rawdev_enqueue(struct rte_rawdev *rawdev,
-		   struct rte_rawdev_buf **buffers __rte_unused,
-		   unsigned int count, rte_rawdev_obj_t context)
-{
-	struct sdp_instr_64B *iqcmd;
-	struct sdp_instr_queue *iq;
-	struct sdp_soft_instr *si;
-	struct sdp_device *sdpvf;
-
-	struct sdp_instr_ih ihx;
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-	si = (struct sdp_soft_instr *)context;
-
-	iq = sdpvf->instr_queue[si->q_no];
-
-	if ((count > 1) || (count < 1)) {
-		otx2_err("This mode not supported: req[%d]", count);
-		goto enq_fail;
-	}
-
-	memset(&ihx, 0, sizeof(struct sdp_instr_ih));
-
-	iqcmd = &si->command;
-	memset(iqcmd, 0, sizeof(struct sdp_instr_64B));
-
-	iqcmd->dptr = (uint64_t)si->dptr;
-
-	/* Populate SDP IH */
-	ihx.pkind  = sdpvf->pkind;
-	ihx.fsz    = si->ih.fsz + 8; /* 8B for NIX IH */
-	ihx.gather = si->ih.gather;
-
-	/* Direct data instruction */
-	ihx.tlen   = si->ih.tlen + ihx.fsz;
-
-	switch (ihx.gather) {
-	case 0: /* Direct data instr */
-		ihx.tlen = si->ih.tlen + ihx.fsz;
-		break;
-
-	default: /* Gather */
-		switch (si->ih.gsz) {
-		case 0: /* Direct gather instr */
-			otx2_err("Direct Gather instr : not supported");
-			goto enq_fail;
-
-		default: /* Indirect gather instr */
-			otx2_err("Indirect Gather instr : not supported");
-			goto enq_fail;
-		}
-	}
-
-	rte_memcpy(&iqcmd->ih, &ihx, sizeof(uint64_t));
-	iqcmd->rptr = (uint64_t)si->rptr;
-	rte_memcpy(&iqcmd->irh, &si->irh, sizeof(uint64_t));
-
-	/* Swap FSZ(front data) here, to avoid swapping on OCTEON TX2 side */
-	sdp_swap_8B_data(&iqcmd->rptr, 1);
-	sdp_swap_8B_data(&iqcmd->irh, 1);
-
-	otx2_sdp_dbg("After swapping");
-	otx2_sdp_dbg("Word0 [dptr]: 0x%016lx", (unsigned long)iqcmd->dptr);
-	otx2_sdp_dbg("Word1 [ihtx]: 0x%016lx", (unsigned long)iqcmd->ih);
-	otx2_sdp_dbg("Word2 [rptr]: 0x%016lx", (unsigned long)iqcmd->rptr);
-	otx2_sdp_dbg("Word3 [irh]: 0x%016lx", (unsigned long)iqcmd->irh);
-	otx2_sdp_dbg("Word4 [exhdr[0]]: 0x%016lx",
-			(unsigned long)iqcmd->exhdr[0]);
-
-	sdp_iqreq_add(iq, si->dptr, si->reqtype);
-
-	if (sdp_send_data(sdpvf, iq, iqcmd)) {
-		otx2_err("Data send failed :");
-		sdp_iqreq_delete(sdpvf, iq, iq->host_write_index);
-		goto enq_fail;
-	}
-
-	if (rte_atomic64_read(&iq->instr_pending) >= 1)
-		sdp_flush_iq(sdpvf, iq, 1 /*(iq->nb_desc / 2)*/);
-
-	/* Return no# of instructions posted successfully. */
-	return count;
-
-enq_fail:
-	return SDP_IQ_SEND_FAILED;
-}
-
-static uint32_t
-sdp_droq_refill(struct sdp_device *sdpvf, struct sdp_droq *droq)
-{
-	struct sdp_droq_desc *desc_ring;
-	uint32_t desc_refilled = 0;
-	void *buf = NULL;
-
-	desc_ring = droq->desc_ring;
-
-	while (droq->refill_count && (desc_refilled < droq->nb_desc)) {
-		/* If a valid buffer exists (happens if there is no dispatch),
-		 * reuse the buffer, else allocate.
-		 */
-		if (droq->recv_buf_list[droq->refill_idx].buffer != NULL)
-			break;
-
-		if (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||
-		    (buf == NULL)) {
-			/* If a buffer could not be allocated, no point in
-			 * continuing
-			 */
-			droq->stats.rx_alloc_failure++;
-			break;
-		}
-
-		droq->recv_buf_list[droq->refill_idx].buffer = buf;
-		desc_ring[droq->refill_idx].buffer_ptr = rte_mem_virt2iova(buf);
-
-		/* Reset any previous values in the length field. */
-		droq->info_list[droq->refill_idx].length = 0;
-
-		droq->refill_idx = sdp_incr_index(droq->refill_idx, 1,
-				droq->nb_desc);
-
-		desc_refilled++;
-		droq->refill_count--;
-
-	}
-
-	return desc_refilled;
-}
-
-static int
-sdp_droq_read_packet(struct sdp_device *sdpvf __rte_unused,
-		     struct sdp_droq *droq,
-		     struct sdp_droq_pkt *droq_pkt)
-{
-	struct sdp_droq_info *info;
-	uint32_t total_len = 0;
-	uint32_t pkt_len = 0;
-
-	info = &droq->info_list[droq->read_idx];
-	sdp_swap_8B_data((uint64_t *)&info->length, 1);
-	if (!info->length) {
-		otx2_err("OQ info_list->length[%ld]", (long)info->length);
-		goto oq_read_fail;
-	}
-
-	/* Deduce the actual data size */
-	info->length -= SDP_RH_SIZE;
-	total_len += (uint32_t)info->length;
-
-	otx2_sdp_dbg("OQ: pkt_len[%ld], buffer_size %d",
-			(long)info->length, droq->buffer_size);
-	if (info->length > droq->buffer_size) {
-		otx2_err("This mode is not supported: pkt_len > buffer_size");
-		goto oq_read_fail;
-	}
-
-	if (info->length <= droq->buffer_size) {
-		pkt_len = (uint32_t)info->length;
-		droq_pkt->data = droq->recv_buf_list[droq->read_idx].buffer;
-		droq_pkt->len  = pkt_len;
-
-		droq->recv_buf_list[droq->read_idx].buffer = NULL;
-		droq->read_idx = sdp_incr_index(droq->read_idx,	1,/* count */
-						droq->nb_desc /* max rd idx */);
-		droq->refill_count++;
-
-	}
-
-	info->length = 0;
-
-	return SDP_OQ_RECV_SUCCESS;
-
-oq_read_fail:
-	return SDP_OQ_RECV_FAILED;
-}
-
-static inline uint32_t
-sdp_check_droq_pkts(struct sdp_droq *droq, uint32_t burst_size)
-{
-	uint32_t min_pkts = 0;
-	uint32_t new_pkts;
-	uint32_t pkt_count;
-
-	/* Latest available OQ packets */
-	pkt_count = rte_read32(droq->pkts_sent_reg);
-
-	/* Newly arrived packets */
-	new_pkts = pkt_count - droq->last_pkt_count;
-	otx2_sdp_dbg("Recvd [%d] new OQ pkts", new_pkts);
-
-	min_pkts = (new_pkts > burst_size) ? burst_size : new_pkts;
-	if (min_pkts) {
-		rte_atomic64_add(&droq->pkts_pending, min_pkts);
-		/* Back up the aggregated packet count so far */
-		droq->last_pkt_count += min_pkts;
-	}
-
-	return min_pkts;
-}
-
-/* Check for response arrival from OCTEON TX2
- * returns number of requests completed
- */
-int
-sdp_rawdev_dequeue(struct rte_rawdev *rawdev,
-		   struct rte_rawdev_buf **buffers, unsigned int count,
-		   rte_rawdev_obj_t context __rte_unused)
-{
-	struct sdp_droq_pkt *oq_pkt;
-	struct sdp_device *sdpvf;
-	struct sdp_droq *droq;
-
-	uint32_t q_no = 0, pkts;
-	uint32_t new_pkts;
-	uint32_t ret;
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-
-	droq = sdpvf->droq[q_no];
-	if (!droq) {
-		otx2_err("Invalid droq[%d]", q_no);
-		goto droq_err;
-	}
-
-	/* Grab the lock */
-	rte_spinlock_lock(&droq->lock);
-
-	new_pkts = sdp_check_droq_pkts(droq, count);
-	if (!new_pkts) {
-		otx2_sdp_dbg("Zero new_pkts:%d", new_pkts);
-		goto deq_fail; /* No pkts at this moment */
-	}
-
-	otx2_sdp_dbg("Received new_pkts = %d", new_pkts);
-
-	for (pkts = 0; pkts < new_pkts; pkts++) {
-
-		/* Push the received pkt to application */
-		oq_pkt = (struct sdp_droq_pkt *)buffers[pkts];
-
-		ret = sdp_droq_read_packet(sdpvf, droq, oq_pkt);
-		if (ret) {
-			otx2_err("DROQ read pakt failed.");
-			goto deq_fail;
-		}
-
-		/* Stats */
-		droq->stats.pkts_received++;
-		droq->stats.bytes_received += oq_pkt->len;
-	}
-
-	/* Ack the h/w with no# of pkts read by Host */
-	rte_write32(pkts, droq->pkts_sent_reg);
-	rte_io_wmb();
-
-	droq->last_pkt_count -= pkts;
-
-	otx2_sdp_dbg("DROQ pkts[%d] pushed to application", pkts);
-
-	/* Refill DROQ buffers */
-	if (droq->refill_count >= 2 /* droq->refill_threshold */) {
-		int desc_refilled = sdp_droq_refill(sdpvf, droq);
-
-		/* Flush the droq descriptor data to memory to be sure
-		 * that when we update the credits the data in memory is
-		 * accurate.
-		 */
-		rte_write32(desc_refilled, droq->pkts_credit_reg);
-
-		/* Ensure mmio write completes */
-		rte_wmb();
-		otx2_sdp_dbg("Refilled count = %d", desc_refilled);
-	}
-
-	/* Release the spin lock */
-	rte_spinlock_unlock(&droq->lock);
-
-	return pkts;
-
-deq_fail:
-	rte_spinlock_unlock(&droq->lock);
-
-droq_err:
-	return SDP_OQ_RECV_FAILED;
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
deleted file mode 100644
index 172fdc5568..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _OTX2_EP_ENQDEQ_H_
-#define _OTX2_EP_ENQDEQ_H_
-
-#include <rte_byteorder.h>
-#include "otx2_ep_rawdev.h"
-
-#define SDP_IQ_SEND_FAILED      (-1)
-#define SDP_IQ_SEND_SUCCESS     (0)
-
-#define SDP_OQ_RECV_FAILED      (-1)
-#define SDP_OQ_RECV_SUCCESS     (0)
-
-static inline uint64_t
-sdp_endian_swap_8B(uint64_t _d)
-{
-	return ((((((uint64_t)(_d)) >>  0) & (uint64_t)0xff) << 56) |
-		(((((uint64_t)(_d)) >>  8) & (uint64_t)0xff) << 48) |
-		(((((uint64_t)(_d)) >> 16) & (uint64_t)0xff) << 40) |
-		(((((uint64_t)(_d)) >> 24) & (uint64_t)0xff) << 32) |
-		(((((uint64_t)(_d)) >> 32) & (uint64_t)0xff) << 24) |
-		(((((uint64_t)(_d)) >> 40) & (uint64_t)0xff) << 16) |
-		(((((uint64_t)(_d)) >> 48) & (uint64_t)0xff) <<  8) |
-		(((((uint64_t)(_d)) >> 56) & (uint64_t)0xff) <<  0));
-}
-
-static inline void
-sdp_swap_8B_data(uint64_t *data, uint32_t blocks)
-{
-	/* Swap 8B blocks */
-	while (blocks) {
-		*data = sdp_endian_swap_8B(*data);
-		blocks--;
-		data++;
-	}
-}
-
-static inline uint32_t
-sdp_incr_index(uint32_t index, uint32_t count, uint32_t max)
-{
-	if ((index + count) >= max)
-		index = index + count - max;
-	else
-		index += count;
-
-	return index;
-}
-
-#endif /* _OTX2_EP_ENQDEQ_H_ */
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
deleted file mode 100644
index b2ccdda83e..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-#include "otx2_ep_vf.h"
-
-static const struct rte_pci_id pci_sdp_vf_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_EP_RAW_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* SDP_VF default configuration */
-const struct sdp_config default_sdp_conf = {
-	/* IQ attributes */
-	.iq                        = {
-		.max_iqs           = SDP_VF_CFG_IO_QUEUES,
-		.instr_type        = SDP_VF_64BYTE_INSTR,
-		.pending_list_size = (SDP_VF_MAX_IQ_DESCRIPTORS *
-				      SDP_VF_CFG_IO_QUEUES),
-	},
-
-	/* OQ attributes */
-	.oq                        = {
-		.max_oqs           = SDP_VF_CFG_IO_QUEUES,
-		.info_ptr          = SDP_VF_OQ_INFOPTR_MODE,
-		.refill_threshold  = SDP_VF_OQ_REFIL_THRESHOLD,
-	},
-
-	.num_iqdef_descs           = SDP_VF_MAX_IQ_DESCRIPTORS,
-	.num_oqdef_descs           = SDP_VF_MAX_OQ_DESCRIPTORS,
-	.oqdef_buf_size            = SDP_VF_OQ_BUF_SIZE,
-
-};
-
-const struct sdp_config*
-sdp_get_defconf(struct sdp_device *sdp_dev __rte_unused)
-{
-	const struct sdp_config *default_conf = NULL;
-
-	default_conf = &default_sdp_conf;
-
-	return default_conf;
-}
-
-static int
-sdp_vfdev_exit(struct rte_rawdev *rawdev)
-{
-	struct sdp_device *sdpvf;
-	uint32_t rawdev_queues, q;
-
-	otx2_info("%s:", __func__);
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-
-	sdpvf->fn_list.disable_io_queues(sdpvf);
-
-	rawdev_queues = sdpvf->num_oqs;
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_delete_oqs(sdpvf, q)) {
-			otx2_err("Failed to delete OQ:%d", q);
-			return -ENOMEM;
-		}
-	}
-	otx2_info("Num OQs:%d freed", sdpvf->num_oqs);
-
-	/* Free the oqbuf_pool */
-	rte_mempool_free(sdpvf->enqdeq_mpool);
-	sdpvf->enqdeq_mpool = NULL;
-
-	otx2_info("Enqdeq_mpool free done");
-
-	rawdev_queues = sdpvf->num_iqs;
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_delete_iqs(sdpvf, q)) {
-			otx2_err("Failed to delete IQ:%d", q);
-			return -ENOMEM;
-		}
-	}
-	otx2_sdp_dbg("Num IQs:%d freed", sdpvf->num_iqs);
-
-	return 0;
-}
-
-static int
-sdp_chip_specific_setup(struct sdp_device *sdpvf)
-{
-	struct rte_pci_device *pdev = sdpvf->pci_dev;
-	uint32_t dev_id = pdev->id.device_id;
-	int ret;
-
-	switch (dev_id) {
-	case PCI_DEVID_OCTEONTX2_EP_RAW_VF:
-		sdpvf->chip_id = PCI_DEVID_OCTEONTX2_EP_RAW_VF;
-		ret = sdp_vf_setup_device(sdpvf);
-
-		break;
-	default:
-		otx2_err("Unsupported device");
-		ret = -EINVAL;
-	}
-
-	if (!ret)
-		otx2_info("SDP dev_id[%d]", dev_id);
-
-	return ret;
-}
-
-/* SDP VF device initialization */
-static int
-sdp_vfdev_init(struct sdp_device *sdpvf)
-{
-	uint32_t rawdev_queues, q;
-
-	if (sdp_chip_specific_setup(sdpvf)) {
-		otx2_err("Chip specific setup failed");
-		goto setup_fail;
-	}
-
-	if (sdpvf->fn_list.setup_device_regs(sdpvf)) {
-		otx2_err("Failed to configure device registers");
-		goto setup_fail;
-	}
-
-	rawdev_queues = (uint32_t)(sdpvf->sriov_info.rings_per_vf);
-
-	/* Rawdev queues setup for enqueue/dequeue */
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_setup_iqs(sdpvf, q)) {
-			otx2_err("Failed to setup IQs");
-			goto iq_fail;
-		}
-	}
-	otx2_info("Total[%d] IQs setup", sdpvf->num_iqs);
-
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_setup_oqs(sdpvf, q)) {
-			otx2_err("Failed to setup OQs");
-			goto oq_fail;
-		}
-	}
-	otx2_info("Total [%d] OQs setup", sdpvf->num_oqs);
-
-	/* Enable IQ/OQ for this device */
-	sdpvf->fn_list.enable_io_queues(sdpvf);
-
-	/* Send OQ desc credits for OQs, credits are always
-	 * sent after the OQs are enabled.
-	 */
-	for (q = 0; q < rawdev_queues; q++) {
-		rte_write32(sdpvf->droq[q]->nb_desc,
-			    sdpvf->droq[q]->pkts_credit_reg);
-
-		rte_io_mb();
-		otx2_info("OQ[%d] dbells [%d]", q,
-		rte_read32(sdpvf->droq[q]->pkts_credit_reg));
-	}
-
-	rte_wmb();
-
-	otx2_info("SDP Device is Ready");
-
-	return 0;
-
-/* Error handling  */
-oq_fail:
-	/* Free the allocated OQs */
-	for (q = 0; q < sdpvf->num_oqs; q++)
-		sdp_delete_oqs(sdpvf, q);
-
-iq_fail:
-	/* Free the allocated IQs */
-	for (q = 0; q < sdpvf->num_iqs; q++)
-		sdp_delete_iqs(sdpvf, q);
-
-setup_fail:
-	return -ENOMEM;
-}
-
-static int
-sdp_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = 1;
-
-	return 0;
-}
-
-static void
-sdp_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = 0;
-}
-
-static int
-sdp_rawdev_close(struct rte_rawdev *dev)
-{
-	int ret;
-	ret = sdp_vfdev_exit(dev);
-	if (ret) {
-		otx2_err(" SDP_EP rawdev exit error");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int
-sdp_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct sdp_rawdev_info *app_info = (struct sdp_rawdev_info *)config;
-	struct sdp_device *sdpvf;
-
-	if (app_info == NULL || config_size != sizeof(*app_info)) {
-		otx2_err("Application config info [NULL] or incorrect size");
-		return -EINVAL;
-	}
-
-	sdpvf = (struct sdp_device *)dev->dev_private;
-
-	sdpvf->conf = app_info->app_conf;
-	sdpvf->enqdeq_mpool = app_info->enqdeq_mpool;
-
-	sdp_vfdev_init(sdpvf);
-
-	return 0;
-
-}
-
-/* SDP VF endpoint rawdev ops */
-static const struct rte_rawdev_ops sdp_rawdev_ops = {
-	.dev_configure  = sdp_rawdev_configure,
-	.dev_start      = sdp_rawdev_start,
-	.dev_stop       = sdp_rawdev_stop,
-	.dev_close      = sdp_rawdev_close,
-	.enqueue_bufs   = sdp_rawdev_enqueue,
-	.dequeue_bufs   = sdp_rawdev_dequeue,
-	.dev_selftest   = sdp_rawdev_selftest,
-};
-
-static int
-otx2_sdp_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct sdp_device *sdpvf = NULL;
-	struct rte_rawdev *sdp_rawdev;
-	uint16_t vf_id;
-
-	/* Single process support */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return 0;
-
-	if (pci_dev->mem_resource[0].addr)
-		otx2_info("SDP_EP BAR0 is mapped:");
-	else {
-		otx2_err("SDP_EP: Failed to map device BARs");
-		otx2_err("BAR0 %p\n BAR2 %p",
-			pci_dev->mem_resource[0].addr,
-			pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "SDPEP:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate rawdev pmd */
-	sdp_rawdev = rte_rawdev_pmd_allocate(name,
-					     sizeof(struct sdp_device),
-					     rte_socket_id());
-
-	if (sdp_rawdev == NULL) {
-		otx2_err("SDP_EP VF rawdev allocation failed");
-		return -ENOMEM;
-	}
-
-	sdp_rawdev->dev_ops = &sdp_rawdev_ops;
-	sdp_rawdev->device = &pci_dev->device;
-	sdp_rawdev->driver_name = pci_dev->driver->driver.name;
-
-	sdpvf = (struct sdp_device *)sdp_rawdev->dev_private;
-	sdpvf->hw_addr = pci_dev->mem_resource[0].addr;
-	sdpvf->pci_dev = pci_dev;
-
-	/* Discover the VF number being probed */
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-
-	vf_id -= 1;
-	sdpvf->vf_num = vf_id;
-
-	otx2_info("SDP_EP VF[%d] probe done", vf_id);
-
-	return 0;
-}
-
-static int
-otx2_sdp_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct sdp_device *sdpvf;
-
-	/* Single process support */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return 0;
-
-	if (pci_dev == NULL) {
-		otx2_err("SDP_EP:invalid pci_dev!");
-		return -EINVAL;
-	}
-
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "SDPEP:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_err("SDP_EP: invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-	otx2_info("Removing SDP_EP VF[%d] ", sdpvf->vf_num);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_sdp_rawdev_pmd = {
-	.id_table  = pci_sdp_vf_map,
-	.drv_flags = (RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA),
-	.probe     = otx2_sdp_rawdev_probe,
-	.remove    = otx2_sdp_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(sdp_rawdev_pci_driver, rte_sdp_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(sdp_rawdev_pci_driver, pci_sdp_vf_map);
-RTE_PMD_REGISTER_KMOD_DEP(sdp_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
deleted file mode 100644
index dab2fb7541..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _OTX2_EP_RAWDEV_H_
-#define _OTX2_EP_RAWDEV_H_
-
-#include <rte_byteorder.h>
-#include <rte_spinlock.h>
-
-/* IQ instruction req types */
-#define SDP_REQTYPE_NONE             (0)
-#define SDP_REQTYPE_NORESP           (1)
-#define SDP_REQTYPE_NORESP_GATHER    (2)
-
-/* Input Request Header format */
-struct sdp_instr_irh {
-	/* Request ID  */
-	uint64_t rid:16;
-
-	/* PCIe port to use for response */
-	uint64_t pcie_port:3;
-
-	/* Scatter indicator  1=scatter */
-	uint64_t scatter:1;
-
-	/* Size of Expected result OR no. of entries in scatter list */
-	uint64_t rlenssz:14;
-
-	/* Desired destination port for result */
-	uint64_t dport:6;
-
-	/* Opcode Specific parameters */
-	uint64_t param:8;
-
-	/* Opcode for the return packet  */
-	uint64_t opcode:16;
-};
-
-/* SDP 32B instruction format */
-struct sdp_instr_32B {
-	/* Pointer where the input data is available. */
-	uint64_t dptr;
-
-	/* SDP Instruction Header.  */
-	uint64_t ih;
-
-	/** Pointer where the response for a RAW mode packet
-	 *  will be written by OCTEON TX2.
-	 */
-	uint64_t rptr;
-
-	/* Input Request Header. Additional info about the input. */
-	uint64_t irh;
-};
-#define SDP_32B_INSTR_SIZE	(sizeof(sdp_instr_32B))
-
-/* SDP 64B instruction format */
-struct sdp_instr_64B {
-	/* Pointer where the input data is available. */
-	uint64_t dptr;
-
-	/* SDP Instruction Header. */
-	uint64_t ih;
-
-	/** Pointer where the response for a RAW mode packet
-	 * will be written by OCTEON TX2.
-	 */
-	uint64_t rptr;
-
-	/* Input Request Header. */
-	uint64_t irh;
-
-	/* Additional headers available in a 64-byte instruction. */
-	uint64_t exhdr[4];
-};
-#define SDP_64B_INSTR_SIZE	(sizeof(sdp_instr_64B))
-
-struct sdp_soft_instr {
-	/** Input data pointer. It is either pointing directly to input data
-	 *  or to a gather list.
-	 */
-	void *dptr;
-
-	/** Response from OCTEON TX2 comes at this address. It is either
-	 *  directlty pointing to output data buffer or to a scatter list.
-	 */
-	void *rptr;
-
-	/* The instruction header. All input commands have this field. */
-	struct sdp_instr_ih ih;
-
-	/* Input request header. */
-	struct sdp_instr_irh irh;
-
-	/** The PCI instruction to be sent to OCTEON TX2. This is stored in the
-	 *  instr to retrieve the physical address of buffers when instr is
-	 *  freed.
-	 */
-	struct sdp_instr_64B command;
-
-	/** If a gather list was allocated, this ptr points to the buffer used
-	 *  for the gather list. The gather list has to be 8B aligned, so this
-	 *  value may be different from dptr.
-	 */
-	void *gather_ptr;
-
-	/* Total data bytes transferred in the gather mode request. */
-	uint64_t gather_bytes;
-
-	/** If a scatter list was allocated, this ptr points to the buffer used
-	 *  for the scatter list. The scatter list has to be 8B aligned, so
-	 *  this value may be different from rptr.
-	 */
-	void *scatter_ptr;
-
-	/* Total data bytes to be received in the scatter mode request. */
-	uint64_t scatter_bytes;
-
-	/* IQ number to which this instruction has to be submitted. */
-	uint32_t q_no;
-
-	/* IQ instruction request type. */
-	uint32_t reqtype;
-};
-#define SDP_SOFT_INSTR_SIZE	(sizeof(sdp_soft_instr))
-
-/* SDP IQ request list */
-struct sdp_instr_list {
-	void *buf;
-	uint32_t reqtype;
-};
-#define SDP_IQREQ_LIST_SIZE	(sizeof(struct sdp_instr_list))
-
-/* Input Queue statistics. Each input queue has four stats fields. */
-struct sdp_iq_stats {
-	uint64_t instr_posted; /* Instructions posted to this queue. */
-	uint64_t instr_processed; /* Instructions processed in this queue. */
-	uint64_t instr_dropped; /* Instructions that could not be processed */
-};
-
-/* Structure to define the configuration attributes for each Input queue. */
-struct sdp_iq_config {
-	/* Max number of IQs available */
-	uint16_t max_iqs;
-
-	/* Command size - 32 or 64 bytes */
-	uint16_t instr_type;
-
-	/* Pending list size, usually set to the sum of the size of all IQs */
-	uint32_t pending_list_size;
-};
-
-/** The instruction (input) queue.
- *  The input queue is used to post raw (instruction) mode data or packet data
- *  to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one
- *  such structure to represent it.
- */
-struct sdp_instr_queue {
-	/* A spinlock to protect access to the input ring.  */
-	rte_spinlock_t lock;
-	rte_spinlock_t post_lock;
-
-	struct sdp_device *sdp_dev;
-	rte_atomic64_t iq_flush_running;
-
-	uint32_t q_no;
-	uint32_t pkt_in_done;
-
-	/* Flag for 64 byte commands. */
-	uint32_t iqcmd_64B:1;
-	uint32_t rsvd:17;
-	uint32_t status:8;
-
-	/* Number of  descriptors in this ring. */
-	uint32_t nb_desc;
-
-	/* Input ring index, where the driver should write the next packet */
-	uint32_t host_write_index;
-
-	/* Input ring index, where the OCTEON TX2 should read the next packet */
-	uint32_t otx_read_index;
-
-	/** This index aids in finding the window in the queue where OCTEON TX2
-	 *  has read the commands.
-	 */
-	uint32_t flush_index;
-
-	/* This keeps track of the instructions pending in this queue. */
-	rte_atomic64_t instr_pending;
-
-	uint32_t reset_instr_cnt;
-
-	/* Pointer to the Virtual Base addr of the input ring. */
-	uint8_t *base_addr;
-
-	/* This IQ request list */
-	struct sdp_instr_list *req_list;
-
-	/* SDP doorbell register for the ring. */
-	void *doorbell_reg;
-
-	/* SDP instruction count register for this ring. */
-	void *inst_cnt_reg;
-
-	/* Number of instructions pending to be posted to OCTEON TX2. */
-	uint32_t fill_cnt;
-
-	/* Statistics for this input queue. */
-	struct sdp_iq_stats stats;
-
-	/* DMA mapped base address of the input descriptor ring. */
-	uint64_t base_addr_dma;
-
-	/* Memory zone */
-	const struct rte_memzone *iq_mz;
-};
-
-/* DROQ packet format for application i/f. */
-struct sdp_droq_pkt {
-	/* DROQ packet data buffer pointer. */
-	uint8_t	 *data;
-
-	/* DROQ packet data length */
-	uint32_t len;
-
-	uint32_t misc;
-};
-
-/** Descriptor format.
- *  The descriptor ring is made of descriptors which have 2 64-bit values:
- *  -# Physical (bus) address of the data buffer.
- *  -# Physical (bus) address of a sdp_droq_info structure.
- *  The device DMA's incoming packets and its information at the address
- *  given by these descriptor fields.
- */
-struct sdp_droq_desc {
-	/* The buffer pointer */
-	uint64_t buffer_ptr;
-
-	/* The Info pointer */
-	uint64_t info_ptr;
-};
-#define SDP_DROQ_DESC_SIZE	(sizeof(struct sdp_droq_desc))
-
-/* Receive Header */
-union sdp_rh {
-	uint64_t rh64;
-};
-#define SDP_RH_SIZE (sizeof(union sdp_rh))
-
-/** Information about packet DMA'ed by OCTEON TX2.
- *  The format of the information available at Info Pointer after OCTEON TX2
- *  has posted a packet. Not all descriptors have valid information. Only
- *  the Info field of the first descriptor for a packet has information
- *  about the packet.
- */
-struct sdp_droq_info {
-	/* The Output Receive Header. */
-	union sdp_rh rh;
-
-	/* The Length of the packet. */
-	uint64_t length;
-};
-#define SDP_DROQ_INFO_SIZE	(sizeof(struct sdp_droq_info))
-
-/** Pointer to data buffer.
- *  Driver keeps a pointer to the data buffer that it made available to
- *  the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)
- *  addresses, this field is required for the driver to keep track of
- *  the virtual address pointers.
- */
-struct sdp_recv_buffer {
-	/* Packet buffer, including meta data. */
-	void *buffer;
-
-	/* Data in the packet buffer. */
-	/* uint8_t *data; */
-};
-#define SDP_DROQ_RECVBUF_SIZE	(sizeof(struct sdp_recv_buffer))
-
-/* DROQ statistics. Each output queue has four stats fields. */
-struct sdp_droq_stats {
-	/* Number of packets received in this queue. */
-	uint64_t pkts_received;
-
-	/* Bytes received by this queue. */
-	uint64_t bytes_received;
-
-	/* Num of failures of rte_pktmbuf_alloc() */
-	uint64_t rx_alloc_failure;
-};
-
-/* Structure to define the configuration attributes for each Output queue. */
-struct sdp_oq_config {
-	/* Max number of OQs available */
-	uint16_t max_oqs;
-
-	/* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
-	uint16_t info_ptr;
-
-	/** The number of buffers that were consumed during packet processing by
-	 *  the driver on this Output queue before the driver attempts to
-	 *  replenish the descriptor ring with new buffers.
-	 */
-	uint32_t refill_threshold;
-};
-
-/* The Descriptor Ring Output Queue(DROQ) structure. */
-struct sdp_droq {
-	/* A spinlock to protect access to this ring. */
-	rte_spinlock_t lock;
-
-	struct sdp_device *sdp_dev;
-	/* The 8B aligned descriptor ring starts at this address. */
-	struct sdp_droq_desc *desc_ring;
-
-	uint32_t q_no;
-	uint32_t last_pkt_count;
-
-	/* Driver should read the next packet at this index */
-	uint32_t read_idx;
-
-	/* OCTEON TX2 will write the next packet at this index */
-	uint32_t write_idx;
-
-	/* At this index, the driver will refill the descriptor's buffer */
-	uint32_t refill_idx;
-
-	/* Packets pending to be processed */
-	rte_atomic64_t pkts_pending;
-
-	/* Number of descriptors in this ring. */
-	uint32_t nb_desc;
-
-	/* The number of descriptors pending to refill. */
-	uint32_t refill_count;
-
-	uint32_t refill_threshold;
-
-	/* The 8B aligned info ptrs begin from this address. */
-	struct sdp_droq_info *info_list;
-
-	/* receive buffer list contains virtual addresses of the buffers. */
-	struct sdp_recv_buffer *recv_buf_list;
-
-	/* The size of each buffer pointed by the buffer pointer. */
-	uint32_t buffer_size;
-
-	/** Pointer to the mapped packet credit register.
-	 *  Host writes number of info/buffer ptrs available to this register
-	 */
-	void *pkts_credit_reg;
-
-	/** Pointer to the mapped packet sent register. OCTEON TX2 writes the
-	 *  number of packets DMA'ed to host memory in this register.
-	 */
-	void *pkts_sent_reg;
-
-	/* Statistics for this DROQ. */
-	struct sdp_droq_stats stats;
-
-	/* DMA mapped address of the DROQ descriptor ring. */
-	size_t desc_ring_dma;
-
-	/* Info_ptr list is allocated at this virtual address. */
-	size_t info_base_addr;
-
-	/* DMA mapped address of the info list */
-	size_t info_list_dma;
-
-	/* Allocated size of info list. */
-	uint32_t info_alloc_size;
-
-	/* Memory zone **/
-	const struct rte_memzone *desc_ring_mz;
-	const struct rte_memzone *info_mz;
-};
-#define SDP_DROQ_SIZE		(sizeof(struct sdp_droq))
-
-/* IQ/OQ mask */
-struct sdp_io_enable {
-	uint64_t iq;
-	uint64_t oq;
-	uint64_t iq64B;
-};
-
-/* Structure to define the configuration. */
-struct sdp_config {
-	/* Input Queue attributes. */
-	struct sdp_iq_config iq;
-
-	/* Output Queue attributes. */
-	struct sdp_oq_config oq;
-
-	/* Num of desc for IQ rings */
-	uint32_t num_iqdef_descs;
-
-	/* Num of desc for OQ rings */
-	uint32_t num_oqdef_descs;
-
-	/* OQ buffer size */
-	uint32_t oqdef_buf_size;
-};
-
-/* Required functions for each VF device */
-struct sdp_fn_list {
-	void (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
-
-	int (*setup_device_regs)(struct sdp_device *sdpvf);
-	uint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq);
-
-	void (*enable_io_queues)(struct sdp_device *sdpvf);
-	void (*disable_io_queues)(struct sdp_device *sdpvf);
-
-	void (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
-
-	void (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
-};
-
-/* SRIOV information */
-struct sdp_sriov_info {
-	/* Number of rings assigned to VF */
-	uint32_t rings_per_vf;
-
-	/* Number of VF devices enabled */
-	uint32_t num_vfs;
-};
-
-
-/* Information to be passed from application */
-struct sdp_rawdev_info {
-	struct rte_mempool *enqdeq_mpool;
-	const struct sdp_config *app_conf;
-};
-
-/* SDP EP VF device */
-struct sdp_device {
-	/* PCI device pointer */
-	struct rte_pci_device *pci_dev;
-	uint16_t chip_id;
-	uint16_t pf_num;
-	uint16_t vf_num;
-
-	/* This device's PCIe port used for traffic. */
-	uint16_t pcie_port;
-	uint32_t pkind;
-
-	/* The state of this device */
-	rte_atomic64_t status;
-
-	/* Memory mapped h/w address */
-	uint8_t *hw_addr;
-
-	struct sdp_fn_list fn_list;
-
-	/* Num IQs */
-	uint32_t num_iqs;
-
-	/* The input instruction queues */
-	struct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];
-
-	/* Num OQs */
-	uint32_t num_oqs;
-
-	/* The DROQ output queues  */
-	struct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];
-
-	/* IOQ data buffer pool */
-	struct rte_mempool *enqdeq_mpool;
-
-	/* IOQ mask */
-	struct sdp_io_enable io_qmask;
-
-	/* SR-IOV info */
-	struct sdp_sriov_info sriov_info;
-
-	/* Device configuration */
-	const struct sdp_config *conf;
-};
-
-const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);
-int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
-int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
-
-int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
-int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
-
-int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
-		       unsigned int count, rte_rawdev_obj_t context);
-int sdp_rawdev_dequeue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
-		       unsigned int count, rte_rawdev_obj_t context);
-
-int sdp_rawdev_selftest(uint16_t dev_id);
-
-#endif /* _OTX2_EP_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_test.c b/drivers/raw/octeontx2_ep/otx2_ep_test.c
deleted file mode 100644
index b876275f7a..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_test.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-
-#define SDP_IOQ_NUM_BUFS   (4 * 1024)
-#define SDP_IOQ_BUF_SIZE   (2 * 1024)
-
-#define SDP_TEST_PKT_FSZ   (0)
-#define SDP_TEST_PKT_SIZE  (1024)
-
-static int
-sdp_validate_data(struct sdp_droq_pkt *oq_pkt, uint8_t *iq_pkt,
-		  uint32_t pkt_len)
-{
-	if (!oq_pkt)
-		return -EINVAL;
-
-	if (pkt_len != oq_pkt->len) {
-		otx2_err("Invalid packet length");
-		return -EINVAL;
-	}
-
-	if (memcmp(oq_pkt->data, iq_pkt, pkt_len) != 0) {
-		otx2_err("Data validation failed");
-		return -EINVAL;
-	}
-	otx2_sdp_dbg("Data validation successful");
-
-	return 0;
-}
-
-static void
-sdp_ioq_buffer_fill(uint8_t *addr, uint32_t len)
-{
-	uint32_t idx;
-
-	memset(addr, 0, len);
-
-	for (idx = 0; idx < len; idx++)
-		addr[idx] = idx;
-}
-
-static struct rte_mempool*
-sdp_ioq_mempool_create(void)
-{
-	struct rte_mempool *mpool;
-
-	mpool = rte_mempool_create("ioqbuf_pool",
-				   SDP_IOQ_NUM_BUFS /*num elt*/,
-				   SDP_IOQ_BUF_SIZE /*elt size*/,
-				   0 /*cache_size*/,
-				   0 /*private_data_size*/,
-				   NULL /*mp_init*/,
-				   NULL /*mp_init arg*/,
-				   NULL /*obj_init*/,
-				   NULL /*obj_init arg*/,
-				   rte_socket_id() /*socket id*/,
-				   (MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET));
-
-	return mpool;
-}
-
-
-int
-sdp_rawdev_selftest(uint16_t dev_id)
-{
-	struct sdp_rawdev_info app_info = {0};
-	struct rte_rawdev_info dev_info = {0};
-
-	struct rte_rawdev_buf *d_buf[1];
-	struct sdp_droq_pkt oq_pkt;
-	struct sdp_soft_instr si;
-	struct sdp_device sdpvf;
-
-	uint32_t buf_size;
-	int ret = 0;
-	void *buf;
-
-	otx2_info("SDP RAWDEV Self Test: Started");
-
-	memset(&oq_pkt, 0x00, sizeof(oq_pkt));
-	d_buf[0] = (struct rte_rawdev_buf *)&oq_pkt;
-
-	struct rte_mempool *ioq_mpool = sdp_ioq_mempool_create();
-	if (!ioq_mpool) {
-		otx2_err("IOQ mpool creation failed");
-		return -ENOMEM;
-	}
-
-	app_info.enqdeq_mpool = ioq_mpool;
-	app_info.app_conf = NULL; /* Use default conf */
-
-	dev_info.dev_private = &app_info;
-
-	ret = rte_rawdev_configure(dev_id, &dev_info, sizeof(app_info));
-	if (ret) {
-		otx2_err("Unable to configure SDP_VF %d", dev_id);
-		rte_mempool_free(ioq_mpool);
-		return -ENOMEM;
-	}
-	otx2_info("SDP VF rawdev[%d] configured successfully", dev_id);
-
-	memset(&si, 0x00, sizeof(si));
-	memset(&sdpvf, 0x00, sizeof(sdpvf));
-
-	buf_size = SDP_TEST_PKT_SIZE;
-
-	si.q_no = 0;
-	si.reqtype = SDP_REQTYPE_NORESP;
-	si.rptr = NULL;
-
-	si.ih.fsz = SDP_TEST_PKT_FSZ;
-	si.ih.tlen = buf_size;
-	si.ih.gather = 0;
-
-	/* Enqueue raw pkt data */
-	rte_mempool_get(ioq_mpool, &buf);
-	if (!buf) {
-		otx2_err("Buffer allocation failed");
-		rte_mempool_free(ioq_mpool);
-		rte_rawdev_close(dev_id);
-		return -ENOMEM;
-	}
-
-	sdp_ioq_buffer_fill(buf, buf_size);
-	si.dptr = (uint8_t *)buf;
-
-	rte_rawdev_enqueue_buffers(dev_id, NULL, 1, &si);
-	usleep(10000);
-
-	/* Dequeue raw pkt data */
-	ret = 0;
-	while (ret < 1) {
-		ret = rte_rawdev_dequeue_buffers(dev_id, &d_buf[0], 1, &si);
-		rte_pause();
-	}
-
-	/* Validate the dequeued raw pkt data */
-	if (sdp_validate_data((struct sdp_droq_pkt *)d_buf[0],
-			      buf, buf_size) != 0) {
-		otx2_err("Data invalid");
-		rte_mempool_put(ioq_mpool,
-				((struct sdp_droq_pkt *)d_buf[0])->data);
-		rte_mempool_free(ioq_mpool);
-		rte_rawdev_close(dev_id);
-		return -EINVAL;
-	}
-
-	rte_mempool_put(ioq_mpool, ((struct sdp_droq_pkt *)d_buf[0])->data);
-	rte_mempool_free(ioq_mpool);
-	rte_rawdev_close(dev_id);
-
-	otx2_info("SDP RAWDEV Self Test: Successful");
-
-	return 0;
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.c b/drivers/raw/octeontx2_ep/otx2_ep_vf.c
deleted file mode 100644
index bf2a19e369..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-#include "otx2_ep_vf.h"
-
-static int
-sdp_vf_reset_iq(struct sdp_device *sdpvf, int q_no)
-{
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-	volatile uint64_t d64 = 0ull;
-
-	/* There is no RST for a ring.
-	 * Clear all registers one by one after disabling the ring
-	 */
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));
-
-	d64 = 0xFFFFFFFF; /* ~0ull */
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr +
-			     SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr +
-				  SDP_VF_R_IN_INSTR_DBELL(q_no));
-	}
-
-	loop = SDP_VF_BUSY_LOOP_COUNT;
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-	}
-
-	d64 = 0ull;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));
-
-	return 0;
-}
-
-static int
-sdp_vf_reset_oq(struct sdp_device *sdpvf, int q_no)
-{
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-	volatile uint64_t d64 = 0ull;
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));
-
-	d64 = 0xFFFFFFFF;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
-
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr +
-			     SDP_VF_R_OUT_SLIST_DBELL(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr +
-				  SDP_VF_R_OUT_SLIST_DBELL(q_no));
-	}
-
-	loop = SDP_VF_BUSY_LOOP_COUNT;
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-	while ((d64 != 0) && (loop--)) {
-		otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-	}
-
-	d64 = 0ull;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_global_iq_reg(struct sdp_device *sdpvf, int q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for IQs
-	 * IS_64B is by default enabled.
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
-
-	reg_val |= SDP_VF_R_IN_CTL_RDSIZE;
-	reg_val |= SDP_VF_R_IN_CTL_IS_64B;
-	reg_val |= SDP_VF_R_IN_CTL_ESR;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
-
-}
-
-static void
-sdp_vf_setup_global_oq_reg(struct sdp_device *sdpvf, int q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
-
-	reg_val |= (SDP_VF_R_OUT_CTL_IMODE);
-
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);
-
-	/* INFO/DATA ptr swap is required  */
-	reg_val |= (SDP_VF_R_OUT_CTL_ES_P);
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
-
-}
-
-static int
-sdp_vf_reset_input_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	otx2_sdp_dbg("%s :", __func__);
-
-	for (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)
-		sdp_vf_reset_iq(sdpvf, q_no);
-
-	return 0;
-}
-
-static int
-sdp_vf_reset_output_queues(struct sdp_device *sdpvf)
-{
-	uint64_t q_no = 0ull;
-
-	otx2_sdp_dbg(" %s :", __func__);
-
-	for (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)
-		sdp_vf_reset_oq(sdpvf, q_no);
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_global_input_regs(struct sdp_device *sdpvf)
-{
-	uint64_t q_no = 0ull;
-
-	sdp_vf_reset_input_queues(sdpvf);
-
-	for (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)
-		sdp_vf_setup_global_iq_reg(sdpvf, q_no);
-}
-
-static void
-sdp_vf_setup_global_output_regs(struct sdp_device *sdpvf)
-{
-	uint32_t q_no;
-
-	sdp_vf_reset_output_queues(sdpvf);
-
-	for (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)
-		sdp_vf_setup_global_oq_reg(sdpvf, q_no);
-
-}
-
-static int
-sdp_vf_setup_device_regs(struct sdp_device *sdpvf)
-{
-	sdp_vf_setup_global_input_regs(sdpvf);
-	sdp_vf_setup_global_output_regs(sdpvf);
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_iq_regs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq = sdpvf->instr_queue[iq_no];
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));
-
-	/* Wait till IDLE to set to 1, not supposed to configure BADDR
-	 * as long as IDLE is 0
-	 */
-	if (!(reg_val & SDP_VF_R_IN_CTL_IDLE)) {
-		do {
-			reg_val = otx2_read64(sdpvf->hw_addr +
-					      SDP_VF_R_IN_CONTROL(iq_no));
-		} while (!(reg_val & SDP_VF_R_IN_CTL_IDLE));
-	}
-
-	/* Write the start of the input queue's ring and its size  */
-	otx2_write64(iq->base_addr_dma, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_BADDR(iq_no));
-	otx2_write64(iq->nb_desc, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_RSIZE(iq_no));
-
-	/* Remember the doorbell & instruction count register addr
-	 * for this queue
-	 */
-	iq->doorbell_reg = (uint8_t *) sdpvf->hw_addr +
-			   SDP_VF_R_IN_INSTR_DBELL(iq_no);
-	iq->inst_cnt_reg = (uint8_t *) sdpvf->hw_addr +
-			   SDP_VF_R_IN_CNTS(iq_no);
-
-	otx2_sdp_dbg("InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p",
-		     iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
-
-	/* Store the current instrn counter(used in flush_iq calculation) */
-	iq->reset_instr_cnt = rte_read32(iq->inst_cnt_reg);
-
-	/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
-	 * to raise
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
-	reg_val = 0xffffffff;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
-
-}
-
-static void
-sdp_vf_setup_oq_regs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	volatile uint64_t reg_val = 0ull;
-	uint64_t oq_ctl = 0ull;
-
-	struct sdp_droq *droq = sdpvf->droq[oq_no];
-
-	/* Wait on IDLE to set to 1, supposed to configure BADDR
-	 * as log as IDLE is 0
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	while (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {
-		reg_val = otx2_read64(sdpvf->hw_addr +
-				      SDP_VF_R_OUT_CONTROL(oq_no));
-	}
-
-	otx2_write64(droq->desc_ring_dma, sdpvf->hw_addr +
-		     SDP_VF_R_OUT_SLIST_BADDR(oq_no));
-	otx2_write64(droq->nb_desc, sdpvf->hw_addr +
-		     SDP_VF_R_OUT_SLIST_RSIZE(oq_no));
-
-	oq_ctl = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	/* Clear the ISIZE and BSIZE (22-0) */
-	oq_ctl &= ~(0x7fffffull);
-
-	/* Populate the BSIZE (15-0) */
-	oq_ctl |= (droq->buffer_size & 0xffff);
-
-	/* Populate ISIZE(22-16) */
-	oq_ctl |= ((SDP_RH_SIZE << 16) & 0x7fffff);
-	otx2_write64(oq_ctl, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	/* Mapped address of the pkt_sent and pkts_credit regs */
-	droq->pkts_sent_reg = (uint8_t *) sdpvf->hw_addr +
-			      SDP_VF_R_OUT_CNTS(oq_no);
-	droq->pkts_credit_reg = (uint8_t *) sdpvf->hw_addr +
-				SDP_VF_R_OUT_SLIST_DBELL(oq_no);
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));
-
-	/* Clear PKT_CNT register */
-	rte_write64(0xFFFFFFFFF, (uint8_t *)sdpvf->hw_addr +
-		    SDP_VF_R_OUT_PKT_CNT(oq_no));
-
-	/* Clear the OQ doorbell  */
-	rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
-	while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
-		rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
-		rte_delay_ms(1);
-	}
-	otx2_sdp_dbg("SDP_R[%d]_credit:%x", oq_no,
-		     rte_read32(droq->pkts_credit_reg));
-
-	/* Clear the OQ_OUT_CNTS doorbell  */
-	reg_val = rte_read32(droq->pkts_sent_reg);
-	rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
-
-	otx2_sdp_dbg("SDP_R[%d]_sent: %x", oq_no,
-		     rte_read32(droq->pkts_sent_reg));
-
-	while (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {
-		reg_val = rte_read32(droq->pkts_sent_reg);
-		rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
-		rte_delay_ms(1);
-	}
-
-}
-
-static void
-sdp_vf_enable_iq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-
-	/* Resetting doorbells during IQ enabling also to handle abrupt
-	 * guest reboot. IQ reset does not clear the doorbells.
-	 */
-	otx2_write64(0xFFFFFFFF, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-	while (((otx2_read64(sdpvf->hw_addr +
-		 SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
-
-		rte_delay_ms(1);
-	}
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	reg_val |= 0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-
-	otx2_info("IQ[%d] enable done", q_no);
-
-}
-
-static void
-sdp_vf_enable_oq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-	reg_val |= 0x1ull;
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-	otx2_info("OQ[%d] enable done", q_no);
-}
-
-static void
-sdp_vf_enable_io_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	for (q_no = 0; q_no < sdpvf->num_iqs; q_no++)
-		sdp_vf_enable_iq(sdpvf, q_no);
-
-	for (q_no = 0; q_no < sdpvf->num_oqs; q_no++)
-		sdp_vf_enable_oq(sdpvf, q_no);
-}
-
-static void
-sdp_vf_disable_iq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	/* Reset the doorbell register for this Input Queue. */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	reg_val &= ~0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-}
-
-static void
-sdp_vf_disable_oq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-	reg_val &= ~0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-}
-
-static void
-sdp_vf_disable_io_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	/* Disable Input Queues. */
-	for (q_no = 0; q_no < sdpvf->num_iqs; q_no++)
-		sdp_vf_disable_iq(sdpvf, q_no);
-
-	/* Disable Output Queues. */
-	for (q_no = 0; q_no < sdpvf->num_oqs; q_no++)
-		sdp_vf_disable_oq(sdpvf, q_no);
-}
-
-static uint32_t
-sdp_vf_update_read_index(struct sdp_instr_queue *iq)
-{
-	uint32_t new_idx = rte_read32(iq->inst_cnt_reg);
-
-	/* The new instr cnt reg is a 32-bit counter that can roll over.
-	 * We have noted the counter's initial value at init time into
-	 * reset_instr_cnt
-	 */
-	if (iq->reset_instr_cnt < new_idx)
-		new_idx -= iq->reset_instr_cnt;
-	else
-		new_idx += (0xffffffff - iq->reset_instr_cnt) + 1;
-
-	/* Modulo of the new index with the IQ size will give us
-	 * the new index.
-	 */
-	new_idx %= iq->nb_desc;
-
-	return new_idx;
-}
-
-int
-sdp_vf_setup_device(struct sdp_device *sdpvf)
-{
-	uint64_t reg_val = 0ull;
-
-	/* If application doesn't provide its conf, use driver default conf */
-	if (sdpvf->conf == NULL) {
-		sdpvf->conf = sdp_get_defconf(sdpvf);
-		if (sdpvf->conf == NULL) {
-			otx2_err("SDP VF default config not found");
-			return -ENOMEM;
-		}
-		otx2_info("Default config is used");
-	}
-
-	/* Get IOQs (RPVF] count */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(0));
-
-	sdpvf->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
-					  & SDP_VF_R_IN_CTL_RPVF_MASK);
-
-	otx2_info("SDP RPVF: %d", sdpvf->sriov_info.rings_per_vf);
-
-	sdpvf->fn_list.setup_iq_regs       = sdp_vf_setup_iq_regs;
-	sdpvf->fn_list.setup_oq_regs       = sdp_vf_setup_oq_regs;
-
-	sdpvf->fn_list.setup_device_regs   = sdp_vf_setup_device_regs;
-	sdpvf->fn_list.update_iq_read_idx  = sdp_vf_update_read_index;
-
-	sdpvf->fn_list.enable_io_queues    = sdp_vf_enable_io_queues;
-	sdpvf->fn_list.disable_io_queues   = sdp_vf_disable_io_queues;
-
-	sdpvf->fn_list.enable_iq           = sdp_vf_enable_iq;
-	sdpvf->fn_list.disable_iq          = sdp_vf_disable_iq;
-
-	sdpvf->fn_list.enable_oq           = sdp_vf_enable_oq;
-	sdpvf->fn_list.disable_oq          = sdp_vf_disable_oq;
-
-
-	return 0;
-
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.h b/drivers/raw/octeontx2_ep/otx2_ep_vf.h
deleted file mode 100644
index 996f2e51eb..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-#ifndef _OTX2_EP_VF_H_
-#define _OTX2_EP_VF_H_
-
-int
-sdp_vf_setup_device(struct sdp_device *sdpvf);
-
-#endif /*_OTX2_EP_VF_H_ */
diff --git a/drivers/raw/octeontx2_ep/version.map b/drivers/raw/octeontx2_ep/version.map
deleted file mode 100644
index 4a76d1d52d..0000000000
--- a/drivers/raw/octeontx2_ep/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_21 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH v4 1/2] drivers/raw: remove octeontx2-dma driver
  2021-08-13  7:00 ` [dpdk-dev] [PATCH v3 " Radha Mohan Chintakuntla
@ 2021-08-19  7:57   ` Radha Mohan Chintakuntla
  2021-08-20  3:38     ` Radha Mohan
  2021-08-23 15:21     ` [dpdk-dev] [PATCH RESEND " Radha Mohan Chintakuntla
  0 siblings, 2 replies; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-19  7:57 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-dma driver as the dependent
common/octeontx2 will be soon be going away. Also a new DMA driver will
be coming in this place once the rte_dmadev library is in.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v3:
Fixed patch application failure on main due to conflict.

Changes from v2:
Fixed DPDK CI reported issues for more documentation failure.

Changes from v1:
Fixed compilation issues in documentation

 MAINTAINERS                                 |   6 -
 doc/guides/platform/octeontx2.rst           |   3 -
 doc/guides/rawdevs/index.rst                |   1 -
 doc/guides/rawdevs/octeontx2_dma.rst        | 103 -----
 drivers/raw/meson.build                     |   1 -
 drivers/raw/octeontx2_dma/meson.build       |  18 -
 drivers/raw/octeontx2_dma/otx2_dpi_msg.c    | 105 -----
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 441 --------------------
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 197 ---------
 drivers/raw/octeontx2_dma/otx2_dpi_test.c   | 218 ----------
 drivers/raw/octeontx2_dma/version.map       |   3 -
 11 files changed, 1096 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_dma.rst
 delete mode 100644 drivers/raw/octeontx2_dma/meson.build
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_msg.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_test.c
 delete mode 100644 drivers/raw/octeontx2_dma/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 266f5ac1da..9f9aa37c68 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 DMA
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_dma/
-F: doc/guides/rawdevs/octeontx2_dma.rst
-
 Marvell OCTEON TX2 EP
 M: Radha Mohan Chintakuntla <radhac@marvell.com>
 M: Veerasenareddy Burru <vburru@marvell.com>
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 8b5991f03b..3a3d28571c 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -152,9 +152,6 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
 #. **Event Device Driver**
    See :doc:`../eventdevs/octeontx2` for SSO event device driver information.
 
-#. **DMA Rawdev Driver**
-   See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
-
 #. **Crypto Device Driver**
    See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 7fbae40ea9..228d4a7743 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,5 +17,4 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_dma
     octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_dma.rst b/doc/guides/rawdevs/octeontx2_dma.rst
deleted file mode 100644
index 6887da5278..0000000000
--- a/doc/guides/rawdevs/octeontx2_dma.rst
+++ /dev/null
@@ -1,103 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-OCTEON TX2 DMA Driver
-=====================
-
-OCTEON TX2 has an internal DMA unit which can be used by applications to initiate
-DMA transaction internally, from/to host when OCTEON TX2 operates in PCIe End
-Point mode. The DMA PF function supports 8 VFs corresponding to 8 DMA queues.
-Each DMA queue was exposed as a VF function when SRIOV enabled.
-
-Features
---------
-
-This DMA PMD supports below 3 modes of memory transfers
-
-#. Internal - OCTEON TX2 DRAM to DRAM without core intervention
-
-#. Inbound  - Host DRAM to OCTEON TX2 DRAM without host/OCTEON TX2 cores involvement
-
-#. Outbound - OCTEON TX2 DRAM to Host DRAM without host/OCTEON TX2 cores involvement
-
-Prerequisites and Compilation procedure
----------------------------------------
-
-   See :doc:`../platform/octeontx2` for setup information.
-
-
-Enabling logs
--------------
-
-For enabling logs, use the following EAL parameter:
-
-.. code-block:: console
-
-   ./your_dma_application <EAL args> --log-level=pmd.raw.octeontx2.dpi,<level>
-
-Using ``pmd.raw.octeontx2.dpi`` as log matching criteria, all Event PMD logs
-can be enabled which are lower than logging ``level``.
-
-Initialization
---------------
-
-The number of DMA VFs (queues) enabled can be controlled by setting sysfs
-entry, `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-dpi/0000\:05\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
--------------
-
-The OCTEON TX2 DPI DMA HW devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring DMA rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to submit DMA
-commands to HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct dpi_rawdev_conf_s conf = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &conf};
-
-   conf.chunk_pool = (void *)rte_mempool_create_empty(...);
-   rte_mempool_set_ops_byname(conf.chunk_pool, rte_mbuf_platform_mempool_ops(), NULL);
-   rte_mempool_populate_default(conf.chunk_pool);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info, sizeof(conf));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using OCTEON TX2 DMA rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, dma devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("DPI:x")`` from the application
-  where x is the VF device's bus id specified in "bus:device.func" format. Use this
-  index for further rawdev function calls.
-
-* This PMD supports driver self test, to test DMA internal mode from test
-  application one can directly calls
-  ``rte_rawdev_selftest(rte_rawdev_get_dev_id("DPI:x"))``
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index b51536f8a7..f25d5f322c 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_dma',
         'octeontx2_ep',
         'skeleton',
 ]
diff --git a/drivers/raw/octeontx2_dma/meson.build b/drivers/raw/octeontx2_dma/meson.build
deleted file mode 100644
index e744fccaae..0000000000
--- a/drivers/raw/octeontx2_dma/meson.build
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files('otx2_dpi_rawdev.c', 'otx2_dpi_msg.c', 'otx2_dpi_test.c')
-
-extra_flags = []
-# This integrated controller runs only on a arm64 machine, remove 32bit warnings
-if not dpdk_conf.get('RTE_ARCH_64')
-    extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
-endif
-
-foreach flag: extra_flags
-    if cc.has_argument(flag)
-        cflags += flag
-    endif
-endforeach
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c b/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
deleted file mode 100644
index 655de216ab..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_MSG_H_
-#define _DPI_MSG_H_
-
-#include <dirent.h>
-#include <fcntl.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "otx2_dpi_rawdev.h"
-
-/* DPI PF DBDF information macro's */
-#define DPI_PF_DBDF_DOMAIN      0
-#define DPI_PF_DBDF_BUS         5
-#define DPI_PF_DBDF_DEVICE      0
-#define DPI_PF_DBDF_FUNCTION    0
-
-#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
-
-union dpi_mbox_message_u {
-	uint64_t u[2];
-	struct dpi_mbox_message_s {
-		/* VF ID to configure */
-		uint64_t vfid           :4;
-		/* Command code */
-		uint64_t cmd            :4;
-		/* Command buffer size in 8-byte words */
-		uint64_t csize          :14;
-		/* aura of the command buffer */
-		uint64_t aura           :20;
-		/* SSO PF function */
-		uint64_t sso_pf_func    :16;
-		/* NPA PF function */
-		uint64_t npa_pf_func    :16;
-	} s;
-};
-
-static inline int
-send_msg_to_pf(struct rte_pci_addr *pci, const char *value, int size)
-{
-	char buff[255] = { 0 };
-	int res, fd;
-
-	res = snprintf(buff, sizeof(buff), "%s/" PCI_PRI_FMT "/%s",
-		       rte_pci_get_sysfs_path(), pci->domain,
-		       pci->bus, DPI_PF_DBDF_DEVICE & 0x7,
-		       DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
-	if ((res < 0) || ((size_t)res > sizeof(buff)))
-		return -ERANGE;
-
-	fd = open(buff, O_WRONLY);
-	if (fd < 0)
-		return -EACCES;
-	res = write(fd, value, size);
-	close(fd);
-	if (res < 0)
-		return -EACCES;
-
-	return 0;
-}
-
-int
-otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_OPEN;
-	mbox_msg.s.csize = size;
-	mbox_msg.s.aura = gaura;
-	mbox_msg.s.sso_pf_func = otx2_sso_pf_func_get();
-	mbox_msg.s.npa_pf_func = otx2_npa_pf_func_get();
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-int
-otx2_dpi_queue_close(struct dpi_vf_s *dpivf)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-#endif /* _DPI_MSG_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
deleted file mode 100644
index 8c01f25ec7..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include <otx2_common.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static const struct rte_pci_id pci_dma_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_DPI_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* Enable/Disable DMA queue */
-static inline int
-dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb)
-{
-	if (enb)
-		otx2_write64(0x1, dpivf->vf_bar0 + DPI_VDMA_EN);
-	else
-		otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Free DMA Queue instruction buffers, and send close notification to PF */
-static inline int
-dma_queue_finish(struct dpi_vf_s *dpivf)
-{
-	uint32_t timeout = 0, sleep = 1;
-	uint64_t reg = 0ULL;
-
-	/* Wait for SADDR to become idle */
-	reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	while (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) {
-		rte_delay_ms(sleep);
-		timeout++;
-		if (timeout >= DPI_QFINISH_TIMEOUT) {
-			otx2_dpi_dbg("Timeout!!! Closing Forcibly");
-			break;
-		}
-		reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	}
-
-	if (otx2_dpi_queue_close(dpivf) < 0)
-		return -EACCES;
-
-	rte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr);
-	dpivf->vf_bar0 = (uintptr_t)NULL;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Write an arbitrary number of command words to a command queue */
-static __rte_always_inline enum dpi_dma_queue_result_e
-dma_queue_write(struct dpi_vf_s *dpi, uint16_t cmd_count, uint64_t *cmds)
-{
-	if ((cmd_count < 1) || (cmd_count > 64))
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	if (cmds == NULL)
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	/* Room available in the current buffer for the command */
-	if (dpi->index + cmd_count < dpi->pool_size_m1) {
-		uint64_t *ptr = dpi->base_ptr;
-
-		ptr += dpi->index;
-		dpi->index += cmd_count;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-	} else {
-		void *new_buffer;
-		uint64_t *ptr;
-		int count;
-
-		/* Allocate new command buffer, return if failed */
-		if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-		    new_buffer == NULL) {
-			return DPI_DMA_QUEUE_NO_MEMORY;
-		}
-		ptr = dpi->base_ptr;
-		/* Figure out how many command words will fit in this buffer.
-		 * One location will be needed for the next buffer pointer.
-		 **/
-		count = dpi->pool_size_m1 - dpi->index;
-		ptr += dpi->index;
-		cmd_count -= count;
-		while (count--)
-			*ptr++ = *cmds++;
-		/* Chunk next ptr is 2DWORDs, second DWORD is reserved. */
-		*ptr++ = (uint64_t)new_buffer;
-		*ptr   = 0;
-		/* The current buffer is full and has a link to the next buffer.
-		 * Time to write the rest of the commands into the new buffer.
-		 **/
-		dpi->base_ptr = new_buffer;
-		dpi->index = cmd_count;
-		ptr = new_buffer;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-		/* queue index may greater than pool size */
-		if (dpi->index >= dpi->pool_size_m1) {
-			if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-			    new_buffer == NULL) {
-				return DPI_DMA_QUEUE_NO_MEMORY;
-			}
-			/* Write next buffer address */
-			*ptr = (uint64_t)new_buffer;
-			dpi->base_ptr = new_buffer;
-			dpi->index = 0;
-		}
-	}
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Submit a DMA command to the DMA queues. */
-static __rte_always_inline int
-dma_queue_submit(struct rte_rawdev *dev, uint16_t cmd_count, uint64_t *cmds)
-{
-	struct dpi_vf_s *dpivf = dev->dev_private;
-	enum dpi_dma_queue_result_e result;
-
-	result = dma_queue_write(dpivf, cmd_count, cmds);
-	rte_wmb();
-	if (likely(result == DPI_DMA_QUEUE_SUCCESS))
-		otx2_write64((uint64_t)cmd_count,
-			     dpivf->vf_bar0 + DPI_VDMA_DBELL);
-
-	return result;
-}
-
-/* Enqueue buffers to DMA queue
- * returns number of buffers enqueued successfully
- */
-static int
-otx2_dpi_rawdev_enqueue_bufs(struct rte_rawdev *dev,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	struct dpi_dma_buf_ptr_s *cmd;
-	uint32_t c = 0;
-
-	for (c = 0; c < count; c++) {
-		uint64_t dpi_cmd[DPI_DMA_CMD_SIZE] = {0};
-		union dpi_dma_instr_hdr_u *hdr;
-		uint16_t index = 0, i;
-
-		hdr = (union dpi_dma_instr_hdr_u *)&dpi_cmd[0];
-		cmd = (struct dpi_dma_buf_ptr_s *)buffers[c]->buf_addr;
-
-		hdr->s.xtype = ctx->xtype & DPI_XTYPE_MASK;
-		hdr->s.pt = ctx->pt & DPI_HDR_PT_MASK;
-		/* Request initiated with byte write completion, but completion
-		 * pointer not provided
-		 */
-		if ((hdr->s.pt == DPI_HDR_PT_ZBW_CA ||
-		     hdr->s.pt == DPI_HDR_PT_ZBW_NC) && cmd->comp_ptr == NULL)
-			return c;
-
-		cmd->comp_ptr->cdata = DPI_REQ_CDATA;
-		hdr->s.ptr = (uint64_t)cmd->comp_ptr;
-		hdr->s.deallocv = ctx->deallocv;
-		hdr->s.tt = ctx->tt & DPI_W0_TT_MASK;
-		hdr->s.grp = ctx->grp & DPI_W0_GRP_MASK;
-
-		/* If caller provides completion ring details, then only queue
-		 * completion address for later polling.
-		 */
-		if (ctx->c_ring) {
-			ctx->c_ring->compl_data[ctx->c_ring->tail] =
-								 cmd->comp_ptr;
-			STRM_INC(ctx->c_ring);
-		}
-
-		if (hdr->s.deallocv)
-			hdr->s.pvfe = 1;
-
-		if (hdr->s.pt == DPI_HDR_PT_WQP)
-			hdr->s.ptr = hdr->s.ptr | DPI_HDR_PT_WQP_STATUSNC;
-
-		index += 4;
-		hdr->s.fport = 0;
-		hdr->s.lport = 0;
-		if (ctx->xtype !=  DPI_XTYPE_INTERNAL_ONLY)
-			hdr->s.lport = ctx->pem_id;
-
-		/* For inbound case, src pointers are last pointers.
-		 * For all other cases, src pointers are first pointers.
-		 */
-		if (ctx->xtype ==  DPI_XTYPE_INBOUND) {
-			hdr->s.nfst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-		} else {
-			hdr->s.nfst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-		}
-		if (dma_queue_submit(dev, index, dpi_cmd))
-			return c;
-	}
-	return c;
-}
-
-/* Check for command completion, returns number of commands completed */
-static int
-otx2_dpi_rawdev_dequeue_bufs(struct rte_rawdev *dev __rte_unused,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	unsigned int i = 0, headp;
-
-	/* No completion ring to poll */
-	if (ctx->c_ring == NULL)
-		return 0;
-
-	headp = ctx->c_ring->head;
-	for (i = 0; i < count && (headp != ctx->c_ring->tail); i++) {
-		struct dpi_dma_req_compl_s *comp_ptr =
-					 ctx->c_ring->compl_data[headp];
-
-		if (comp_ptr->cdata)
-			break;
-
-		/* Request Completed */
-		buffers[i] = (void *)comp_ptr;
-		headp = (headp + 1) % ctx->c_ring->max_cnt;
-	}
-	ctx->c_ring->head = headp;
-
-	return i;
-}
-
-static int
-otx2_dpi_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_START;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static void
-otx2_dpi_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_STOP;
-}
-
-static int
-otx2_dpi_rawdev_close(struct rte_rawdev *dev)
-{
-	dma_engine_enb_dis(dev->dev_private, false);
-	dma_queue_finish(dev->dev_private);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_reset(struct rte_rawdev *dev)
-{
-	return dev ? DPI_QUEUE_STOP : DPI_QUEUE_START;
-}
-
-static int
-otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct dpi_rawdev_conf_s *conf = config;
-	struct dpi_vf_s *dpivf = NULL;
-	void *buf = NULL;
-	uintptr_t pool;
-	uint32_t gaura;
-
-	if (conf == NULL || config_size != sizeof(*conf)) {
-		otx2_dpi_dbg("NULL or invalid configuration");
-		return -EINVAL;
-	}
-	dpivf = (struct dpi_vf_s *)dev->dev_private;
-	dpivf->chunk_pool = conf->chunk_pool;
-	if (rte_mempool_get(conf->chunk_pool, &buf) || (buf == NULL)) {
-		otx2_err("Unable allocate buffer");
-		return -ENODEV;
-	}
-	dpivf->base_ptr = buf;
-	otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-	dpivf->pool_size_m1 = (DPI_CHUNK_SIZE >> 3) - 2;
-	pool = (uintptr_t)((struct rte_mempool *)conf->chunk_pool)->pool_id;
-	gaura = npa_lf_aura_handle_to_aura(pool);
-	otx2_write64(0, dpivf->vf_bar0 + DPI_VDMA_REQQ_CTL);
-	otx2_write64(((uint64_t)buf >> 7) << 7,
-		     dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	if (otx2_dpi_queue_open(dpivf, DPI_CHUNK_SIZE, gaura) < 0) {
-		otx2_err("Unable to open DPI VF %d", dpivf->vf_id);
-		rte_mempool_put(conf->chunk_pool, buf);
-		return -EACCES;
-	}
-	dma_engine_enb_dis(dpivf, true);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static const struct rte_rawdev_ops dpi_rawdev_ops = {
-	.dev_configure = otx2_dpi_rawdev_configure,
-	.dev_start = otx2_dpi_rawdev_start,
-	.dev_stop = otx2_dpi_rawdev_stop,
-	.dev_close = otx2_dpi_rawdev_close,
-	.dev_reset = otx2_dpi_rawdev_reset,
-	.enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs,
-	.dequeue_bufs = otx2_dpi_rawdev_dequeue_bufs,
-	.dev_selftest = test_otx2_dma_rawdev,
-};
-
-static int
-otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct dpi_vf_s *dpivf = NULL;
-	struct rte_rawdev *rawdev;
-	uint16_t vf_id;
-
-	/* For secondary processes, the primary has done all the work */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return DPI_DMA_QUEUE_SUCCESS;
-
-	if (pci_dev->mem_resource[0].addr == NULL) {
-		otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr,
-			     pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate device structure */
-	rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct dpi_vf_s),
-					 rte_socket_id());
-	if (rawdev == NULL) {
-		otx2_err("Rawdev allocation failed");
-		return -EINVAL;
-	}
-
-	rawdev->dev_ops = &dpi_rawdev_ops;
-	rawdev->device = &pci_dev->device;
-	rawdev->driver_name = pci_dev->driver->driver.name;
-
-	dpivf = rawdev->dev_private;
-	if (dpivf->state != DPI_QUEUE_STOP) {
-		otx2_dpi_dbg("Device already started!!!");
-		return -ENODEV;
-	}
-
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-	vf_id -= 1;
-	dpivf->dev = pci_dev;
-	dpivf->state = DPI_QUEUE_START;
-	dpivf->vf_id = vf_id;
-	dpivf->vf_bar0 = (uintptr_t)pci_dev->mem_resource[0].addr;
-	dpivf->vf_bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct dpi_vf_s *dpivf;
-
-	if (pci_dev == NULL) {
-		otx2_dpi_dbg("Invalid pci_dev of the device!");
-		return -EINVAL;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_dpi_dbg("Invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	dpivf = (struct dpi_vf_s *)rawdev->dev_private;
-	dma_engine_enb_dis(dpivf, false);
-	dma_queue_finish(dpivf);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_dpi_rawdev_pmd = {
-	.id_table  = pci_dma_map,
-	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
-	.probe     = otx2_dpi_rawdev_probe,
-	.remove    = otx2_dpi_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(dpi_rawdev_pci_driver, rte_dpi_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(dpi_rawdev_pci_driver, pci_dma_map);
-RTE_PMD_REGISTER_KMOD_DEP(dpi_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
deleted file mode 100644
index 2bc9e3da3c..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_RAWDEV_H_
-#define _DPI_RAWDEV_H_
-
-#include "otx2_common.h"
-#include "otx2_mempool.h"
-
-#define DPI_QUEUE_OPEN	0x1
-#define DPI_QUEUE_CLOSE	0x2
-
-/* DPI VF register offsets from VF_BAR0 */
-#define DPI_VDMA_EN             (0x0)
-#define DPI_VDMA_REQQ_CTL       (0x8)
-#define DPI_VDMA_DBELL          (0x10)
-#define DPI_VDMA_SADDR          (0x18)
-#define DPI_VDMA_COUNTS         (0x20)
-#define DPI_VDMA_NADDR          (0x28)
-#define DPI_VDMA_IWBUSY         (0x30)
-#define DPI_VDMA_CNT            (0x38)
-#define DPI_VF_INT              (0x100)
-#define DPI_VF_INT_W1S          (0x108)
-#define DPI_VF_INT_ENA_W1C      (0x110)
-#define DPI_VF_INT_ENA_W1S      (0x118)
-
-#define DPI_MAX_VFS             8
-#define DPI_DMA_CMD_SIZE        64
-#define DPI_CHUNK_SIZE		1024
-#define DPI_QUEUE_STOP		0x0
-#define DPI_QUEUE_START		0x1
-
-#define DPI_VDMA_SADDR_REQ_IDLE	63
-#define DPI_MAX_POINTER		15
-#define STRM_INC(s)	((s)->tail = ((s)->tail + 1) % (s)->max_cnt)
-#define DPI_QFINISH_TIMEOUT	(10 * 1000)
-
-/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
-#define DPI_XTYPE_OUTBOUND      (0)
-#define DPI_XTYPE_INBOUND       (1)
-#define DPI_XTYPE_INTERNAL_ONLY (2)
-#define DPI_XTYPE_EXTERNAL_ONLY (3)
-#define DPI_XTYPE_MASK		0x3
-#define DPI_HDR_PT_ZBW_CA	0x0
-#define DPI_HDR_PT_ZBW_NC	0x1
-#define DPI_HDR_PT_WQP		0x2
-#define DPI_HDR_PT_WQP_NOSTATUS	0x0
-#define DPI_HDR_PT_WQP_STATUSCA	0x1
-#define DPI_HDR_PT_WQP_STATUSNC	0x3
-#define DPI_HDR_PT_CNT		0x3
-#define DPI_HDR_PT_MASK		0x3
-#define DPI_W0_TT_MASK		0x3
-#define DPI_W0_GRP_MASK		0x3FF
-/* Set Completion data to 0xFF when request submitted,
- * upon successful request completion engine reset to completion status
- */
-#define DPI_REQ_CDATA		0xFF
-
-struct dpi_vf_s {
-	struct rte_pci_device *dev;
-	uint8_t state;
-	uint16_t vf_id;
-	uint8_t domain;
-	uintptr_t vf_bar0;
-	uintptr_t vf_bar2;
-
-	uint16_t pool_size_m1;
-	uint16_t index;
-	uint64_t *base_ptr;
-	void *chunk_pool;
-	struct otx2_mbox *mbox;
-};
-
-struct dpi_rawdev_conf_s {
-	void *chunk_pool;
-};
-
-enum dpi_dma_queue_result_e {
-	DPI_DMA_QUEUE_SUCCESS = 0,
-	DPI_DMA_QUEUE_NO_MEMORY = -1,
-	DPI_DMA_QUEUE_INVALID_PARAM = -2,
-};
-
-struct dpi_dma_req_compl_s {
-	uint64_t cdata;
-	void (*compl_cb)(void *dev, void *arg);
-	void *cb_data;
-};
-
-union dpi_dma_ptr_u {
-	uint64_t u[2];
-	struct dpi_dma_s {
-		uint64_t length:16;
-		uint64_t reserved:44;
-		uint64_t bed:1; /* Big-Endian */
-		uint64_t alloc_l2:1;
-		uint64_t full_write:1;
-		uint64_t invert:1;
-		uint64_t ptr;
-	} s;
-};
-
-struct dpi_dma_buf_ptr_s {
-	union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */
-	union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */
-	uint8_t rptr_cnt;
-	uint8_t wptr_cnt;
-	struct dpi_dma_req_compl_s *comp_ptr;
-};
-
-struct dpi_cring_data_s {
-	struct dpi_dma_req_compl_s **compl_data;
-	uint16_t max_cnt;
-	uint16_t head;
-	uint16_t tail;
-};
-
-struct dpi_dma_queue_ctx_s {
-	uint16_t xtype:2;
-
-	/* Completion pointer type */
-	uint16_t pt:2;
-
-	/* Completion updated using WQE */
-	uint16_t tt:2;
-	uint16_t grp:10;
-	uint32_t tag;
-
-	/* Valid only for Outbound only mode */
-	uint16_t aura:12;
-	uint16_t csel:1;
-	uint16_t ca:1;
-	uint16_t fi:1;
-	uint16_t ii:1;
-	uint16_t fl:1;
-
-	uint16_t pvfe:1;
-	uint16_t dealloce:1;
-	uint16_t req_type:2;
-	uint16_t use_lock:1;
-	uint16_t deallocv;
-	uint16_t  pem_id;
-
-	struct dpi_cring_data_s *c_ring;
-};
-
-/* DPI DMA Instruction Header Format */
-union dpi_dma_instr_hdr_u {
-	uint64_t u[4];
-
-	struct dpi_dma_instr_hdr_s_s {
-		uint64_t tag:32;
-		uint64_t tt:2;
-		uint64_t grp:10;
-		uint64_t reserved_44_47:4;
-		uint64_t nfst:4;
-		uint64_t reserved_52_53:2;
-		uint64_t nlst:4;
-		uint64_t reserved_58_63:6;
-		/* Word 0 - End */
-
-		uint64_t aura:12;
-		uint64_t reserved_76_79:4;
-		uint64_t deallocv:16;
-		uint64_t dealloce:1;
-		uint64_t pvfe:1;
-		uint64_t reserved_98_99:2;
-		uint64_t pt:2;
-		uint64_t reserved_102_103:2;
-		uint64_t fl:1;
-		uint64_t ii:1;
-		uint64_t fi:1;
-		uint64_t ca:1;
-		uint64_t csel:1;
-		uint64_t reserved_109_111:3;
-		uint64_t xtype:2;
-		uint64_t reserved_114_119:6;
-		uint64_t fport:2;
-		uint64_t reserved_122_123:2;
-		uint64_t lport:2;
-		uint64_t reserved_126_127:2;
-		/* Word 1 - End */
-
-		uint64_t ptr:64;
-		/* Word 2 - End */
-
-		uint64_t reserved_192_255:64;
-		/* Word 3 - End */
-	} s;
-};
-
-int otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura);
-int otx2_dpi_queue_close(struct dpi_vf_s *dpivf);
-int test_otx2_dma_rawdev(uint16_t val);
-
-#endif /* _DPI_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_test.c b/drivers/raw/octeontx2_dma/otx2_dpi_test.c
deleted file mode 100644
index cec6ca91b0..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_test.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_debug.h>
-#include <rte_eal.h>
-#include <rte_log.h>
-#include <rte_malloc.h>
-#include <rte_mbuf.h>
-#include <rte_mbuf_pool_ops.h>
-#include <rte_memcpy.h>
-#include <rte_memory.h>
-#include <rte_mempool.h>
-#include <rte_per_lcore.h>
-#include <rte_rawdev.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static struct dpi_cring_data_s cring;
-
-static uint8_t
-buffer_fill(uint8_t *addr, int len, uint8_t val)
-{
-	int j = 0;
-
-	memset(addr, 0, len);
-	for (j = 0; j < len; j++)
-		*(addr + j) = val++;
-
-	return val;
-}
-
-static int
-validate_buffer(uint8_t *saddr, uint8_t *daddr, int len)
-{
-	int j = 0, ret = 0;
-
-	for (j = 0; j < len; j++) {
-		if (*(saddr + j) != *(daddr + j)) {
-			otx2_dpi_dbg("FAIL: Data Integrity failed");
-			otx2_dpi_dbg("index: %d, Expected: 0x%x, Actual: 0x%x",
-				     j, *(saddr + j), *(daddr + j));
-			ret = -1;
-			break;
-		}
-	}
-
-	return ret;
-}
-
-static inline int
-dma_test_internal(int dma_port, int buf_size)
-{
-	struct dpi_dma_req_compl_s *comp_data;
-	struct dpi_dma_queue_ctx_s ctx = {0};
-	struct rte_rawdev_buf buf = {0};
-	struct rte_rawdev_buf *d_buf[1];
-	struct rte_rawdev_buf *bufp[1];
-	struct dpi_dma_buf_ptr_s cmd;
-	union dpi_dma_ptr_u rptr = { {0} };
-	union dpi_dma_ptr_u wptr = { {0} };
-	uint8_t *fptr, *lptr;
-	int ret;
-
-	fptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	lptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	comp_data = rte_malloc("dummy", buf_size, 128);
-	if (fptr == NULL || lptr == NULL || comp_data == NULL) {
-		otx2_dpi_dbg("Unable to allocate internal memory");
-		return -ENOMEM;
-	}
-
-	buffer_fill(fptr, buf_size, 0);
-	memset(&cmd, 0, sizeof(struct dpi_dma_buf_ptr_s));
-	memset(lptr, 0, buf_size);
-	memset(comp_data, 0, buf_size);
-	rptr.s.ptr = (uint64_t)fptr;
-	rptr.s.length = buf_size;
-	wptr.s.ptr = (uint64_t)lptr;
-	wptr.s.length = buf_size;
-	cmd.rptr[0] = &rptr;
-	cmd.wptr[0] = &wptr;
-	cmd.rptr_cnt = 1;
-	cmd.wptr_cnt = 1;
-	cmd.comp_ptr = comp_data;
-	buf.buf_addr = (void *)&cmd;
-	bufp[0] = &buf;
-
-	ctx.xtype = DPI_XTYPE_INTERNAL_ONLY;
-	ctx.pt = 0;
-	ctx.c_ring = &cring;
-
-	ret = rte_rawdev_enqueue_buffers(dma_port,
-					 (struct rte_rawdev_buf **)bufp, 1,
-					 &ctx);
-	if (ret < 0) {
-		otx2_dpi_dbg("Enqueue request failed");
-		return 0;
-	}
-
-	/* Wait and dequeue completion */
-	do {
-		sleep(1);
-		ret = rte_rawdev_dequeue_buffers(dma_port, &d_buf[0], 1, &ctx);
-		if (ret)
-			break;
-
-		otx2_dpi_dbg("Dequeue request not completed");
-	} while (1);
-
-	if (validate_buffer(fptr, lptr, buf_size)) {
-		otx2_dpi_dbg("DMA transfer failed\n");
-		return -EAGAIN;
-	}
-	otx2_dpi_dbg("Internal Only DMA transfer successfully completed");
-
-	if (lptr)
-		rte_free(lptr);
-	if (fptr)
-		rte_free(fptr);
-	if (comp_data)
-		rte_free(comp_data);
-
-	return 0;
-}
-
-static void *
-dpi_create_mempool(void)
-{
-	void *chunk_pool = NULL;
-	char pool_name[25];
-	int ret;
-
-	snprintf(pool_name, sizeof(pool_name), "dpi_chunk_pool");
-
-	chunk_pool = (void *)rte_mempool_create_empty(pool_name, 1024, 1024,
-						      0, 0, rte_socket_id(), 0);
-	if (chunk_pool == NULL) {
-		otx2_dpi_dbg("Unable to create memory pool.");
-		return NULL;
-	}
-
-	ret = rte_mempool_set_ops_byname(chunk_pool,
-					 rte_mbuf_platform_mempool_ops(), NULL);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to set pool ops");
-		rte_mempool_free(chunk_pool);
-		return NULL;
-	}
-
-	ret = rte_mempool_populate_default(chunk_pool);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to populate pool");
-		return NULL;
-	}
-
-	return chunk_pool;
-}
-
-int
-test_otx2_dma_rawdev(uint16_t val)
-{
-	struct rte_rawdev_info rdev_info = {0};
-	struct dpi_rawdev_conf_s conf = {0};
-	int ret, i, size = 1024;
-	int nb_ports;
-
-	RTE_SET_USED(val);
-	nb_ports = rte_rawdev_count();
-	if (nb_ports == 0) {
-		otx2_dpi_dbg("No Rawdev ports - bye");
-		return -ENODEV;
-	}
-
-	i = rte_rawdev_get_dev_id("DPI:5:00.1");
-	/* Configure rawdev ports */
-	conf.chunk_pool = dpi_create_mempool();
-	rdev_info.dev_private = &conf;
-	ret = rte_rawdev_configure(i, (rte_rawdev_obj_t)&rdev_info,
-			sizeof(conf));
-	if (ret) {
-		otx2_dpi_dbg("Unable to configure DPIVF %d", i);
-		return -ENODEV;
-	}
-	otx2_dpi_dbg("rawdev %d configured successfully", i);
-
-	/* Each stream allocate its own completion ring data, store it in
-	 * application context. Each stream needs to use same application
-	 * context for enqueue/dequeue.
-	 */
-	cring.compl_data = rte_malloc("dummy", sizeof(void *) * 1024, 128);
-	if (!cring.compl_data) {
-		otx2_dpi_dbg("Completion allocation failed");
-		return -ENOMEM;
-	}
-
-	cring.max_cnt = 1024;
-	cring.head = 0;
-	cring.tail = 0;
-
-	ret = dma_test_internal(i, size);
-	if (ret)
-		otx2_dpi_dbg("DMA transfer failed for queue %d", i);
-
-	if (rte_rawdev_close(i))
-		otx2_dpi_dbg("Dev close failed for port %d", i);
-
-	if (conf.chunk_pool)
-		rte_mempool_free(conf.chunk_pool);
-
-	return ret;
-}
diff --git a/drivers/raw/octeontx2_dma/version.map b/drivers/raw/octeontx2_dma/version.map
deleted file mode 100644
index c2e0723b4c..0000000000
--- a/drivers/raw/octeontx2_dma/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_22 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH v4 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-13  7:01 ` [dpdk-dev] [PATCH v3 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
@ 2021-08-19  7:59   ` Radha Mohan Chintakuntla
  2021-08-23 12:19     ` Radha Mohan
  0 siblings, 1 reply; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-19  7:59 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-ep driver as the dependent
common/octeontx2 will soon be going away. Moreover this driver is no
longer required as the net/octeontx_ep driver is sufficient.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v3:
Fixed patch application failure due to conflict on main branch.

Changes from v2:
Fixed DPDK CI reported issues for more documentation failure.

Changes from v1:
Fixed compilation issues in documentation

 MAINTAINERS                               |   6 -
 doc/guides/rawdevs/index.rst              |   1 -
 doc/guides/rawdevs/octeontx2_ep.rst       |  82 ---
 drivers/raw/meson.build                   |   1 -
 drivers/raw/octeontx2_ep/meson.build      |  11 -
 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------
 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h |  52 --
 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------
 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------
 drivers/raw/octeontx2_ep/otx2_ep_test.c   | 172 -----
 drivers/raw/octeontx2_ep/otx2_ep_vf.c     | 475 ------------
 drivers/raw/octeontx2_ep/otx2_ep_vf.h     |  10 -
 drivers/raw/octeontx2_ep/version.map      |   3 -
 13 files changed, 2520 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_ep.rst
 delete mode 100644 drivers/raw/octeontx2_ep/meson.build
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_test.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.h
 delete mode 100644 drivers/raw/octeontx2_ep/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 9f9aa37c68..1d6a408f49 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 EP
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_ep/
-F: doc/guides/rawdevs/octeontx2_ep.rst
-
 NTB
 M: Xiaoyun Li <xiaoyun.li@intel.com>
 M: Jingjing Wu <jingjing.wu@intel.com>
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 228d4a7743..b6cf917443 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,4 +17,3 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_ep.rst b/doc/guides/rawdevs/octeontx2_ep.rst
deleted file mode 100644
index fb9d346ccf..0000000000
--- a/doc/guides/rawdevs/octeontx2_ep.rst
+++ /dev/null
@@ -1,82 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-Marvell OCTEON TX2 End Point Rawdev Driver
-==========================================
-
-OCTEON TX2 has an internal SDP unit which provides End Point mode of operation
-by exposing its IOQs to Host, IOQs are used for packet I/O between Host and
-OCTEON TX2. Each OCTEON TX2 SDP PF supports a max of 128 VFs and Each VF is
-associated with a set of IOQ pairs.
-
-Features
---------
-
-This OCTEON TX2 End Point mode PMD supports
-
-#. Packet Input - Host to OCTEON TX2 with direct data instruction mode.
-
-#. Packet Output - OCTEON TX2 to Host with info pointer mode.
-
-
-Initialization
---------------
-
-The number of SDP VFs enabled, can be controlled by setting sysfs
-entry `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-ep/0000\:04\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
-------------
-
-The OCTEON TX2 SDP End Point VF devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring SDP EP rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to send/receive
-packets to/from the HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct sdp_rawdev_info config = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &config};
-   config.enqdeq_mpool = (void *)rte_mempool_create(...);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info,
-                        sizeof(config));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using SDP VF EP rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, SDP VF devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("SDPEP:x")`` from the test application
-  where x is the VF device's bus id specified in "bus:device.func"(BDF)
-  format. Use this index for further rawdev function calls.
-
-* The driver's selftest rawdev API can be used to verify the SDP EP mode
-  functional tests which can send/receive the raw data packets to/from the
-  EP device.
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index f25d5f322c..87694a758e 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_ep',
         'skeleton',
 ]
 std_deps = ['rawdev']
diff --git a/drivers/raw/octeontx2_ep/meson.build b/drivers/raw/octeontx2_ep/meson.build
deleted file mode 100644
index 8d7c69aa3c..0000000000
--- a/drivers/raw/octeontx2_ep/meson.build
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files(
-        'otx2_ep_enqdeq.c',
-        'otx2_ep_rawdev.c',
-        'otx2_ep_test.c',
-        'otx2_ep_vf.c',
-)
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
deleted file mode 100644
index d04e957d82..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-#include <dirent.h>
-#include <fcntl.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_enqdeq.h"
-
-static void
-sdp_dmazone_free(const struct rte_memzone *mz)
-{
-	const struct rte_memzone *mz_tmp;
-	int ret = 0;
-
-	if (mz == NULL) {
-		otx2_err("Memzone %s : NULL", mz->name);
-		return;
-	}
-
-	mz_tmp = rte_memzone_lookup(mz->name);
-	if (mz_tmp == NULL) {
-		otx2_err("Memzone %s Not Found", mz->name);
-		return;
-	}
-
-	ret = rte_memzone_free(mz);
-	if (ret)
-		otx2_err("Memzone free failed : ret = %d", ret);
-
-}
-
-/* Free IQ resources */
-int
-sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq;
-
-	iq = sdpvf->instr_queue[iq_no];
-	if (iq == NULL) {
-		otx2_err("Invalid IQ[%d]\n", iq_no);
-		return -ENOMEM;
-	}
-
-	rte_free(iq->req_list);
-	iq->req_list = NULL;
-
-	if (iq->iq_mz) {
-		sdp_dmazone_free(iq->iq_mz);
-		iq->iq_mz = NULL;
-	}
-
-	rte_free(sdpvf->instr_queue[iq_no]);
-	sdpvf->instr_queue[iq_no] = NULL;
-
-	sdpvf->num_iqs--;
-
-	otx2_info("IQ[%d] is deleted", iq_no);
-
-	return 0;
-}
-
-/* IQ initialization */
-static int
-sdp_init_instr_queue(struct sdp_device *sdpvf, int iq_no)
-{
-	const struct sdp_config *conf;
-	struct sdp_instr_queue *iq;
-	uint32_t q_size;
-
-	conf = sdpvf->conf;
-	iq = sdpvf->instr_queue[iq_no];
-	q_size = conf->iq.instr_type * conf->num_iqdef_descs;
-
-	/* IQ memory creation for Instruction submission to OCTEON TX2 */
-	iq->iq_mz = rte_memzone_reserve_aligned("iqmz",
-					q_size,
-					rte_socket_id(),
-					RTE_MEMZONE_IOVA_CONTIG,
-					RTE_CACHE_LINE_SIZE);
-	if (iq->iq_mz == NULL) {
-		otx2_err("IQ[%d] memzone alloc failed", iq_no);
-		goto iq_init_fail;
-	}
-
-	iq->base_addr_dma = iq->iq_mz->iova;
-	iq->base_addr = (uint8_t *)iq->iq_mz->addr;
-
-	if (conf->num_iqdef_descs & (conf->num_iqdef_descs - 1)) {
-		otx2_err("IQ[%d] descs not in power of 2", iq_no);
-		goto iq_init_fail;
-	}
-
-	iq->nb_desc = conf->num_iqdef_descs;
-
-	/* Create a IQ request list to hold requests that have been
-	 * posted to OCTEON TX2. This list will be used for freeing the IQ
-	 * data buffer(s) later once the OCTEON TX2 fetched the requests.
-	 */
-	iq->req_list = rte_zmalloc_socket("request_list",
-			(iq->nb_desc * SDP_IQREQ_LIST_SIZE),
-			RTE_CACHE_LINE_SIZE,
-			rte_socket_id());
-	if (iq->req_list == NULL) {
-		otx2_err("IQ[%d] req_list alloc failed", iq_no);
-		goto iq_init_fail;
-	}
-
-	otx2_info("IQ[%d]: base: %p basedma: %lx count: %d",
-		     iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,
-		     iq->nb_desc);
-
-	iq->sdp_dev = sdpvf;
-	iq->q_no = iq_no;
-	iq->fill_cnt = 0;
-	iq->host_write_index = 0;
-	iq->otx_read_index = 0;
-	iq->flush_index = 0;
-
-	/* Initialize the spinlock for this instruction queue */
-	rte_spinlock_init(&iq->lock);
-	rte_spinlock_init(&iq->post_lock);
-
-	rte_atomic64_clear(&iq->iq_flush_running);
-
-	sdpvf->io_qmask.iq |= (1ull << iq_no);
-
-	/* Set 32B/64B mode for each input queue */
-	if (conf->iq.instr_type == 64)
-		sdpvf->io_qmask.iq64B |= (1ull << iq_no);
-
-	iq->iqcmd_64B = (conf->iq.instr_type == 64);
-
-	/* Set up IQ registers */
-	sdpvf->fn_list.setup_iq_regs(sdpvf, iq_no);
-
-	return 0;
-
-iq_init_fail:
-	return -ENOMEM;
-
-}
-
-int
-sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq;
-
-	iq = (struct sdp_instr_queue *)rte_zmalloc("sdp_IQ", sizeof(*iq),
-						RTE_CACHE_LINE_SIZE);
-	if (iq == NULL)
-		return -ENOMEM;
-
-	sdpvf->instr_queue[iq_no] = iq;
-
-	if (sdp_init_instr_queue(sdpvf, iq_no)) {
-		otx2_err("IQ init is failed");
-		goto delete_IQ;
-	}
-	otx2_info("IQ[%d] is created.", sdpvf->num_iqs);
-
-	sdpvf->num_iqs++;
-
-
-	return 0;
-
-delete_IQ:
-	sdp_delete_iqs(sdpvf, iq_no);
-	return -ENOMEM;
-}
-
-static void
-sdp_droq_reset_indices(struct sdp_droq *droq)
-{
-	droq->read_idx  = 0;
-	droq->write_idx = 0;
-	droq->refill_idx = 0;
-	droq->refill_count = 0;
-	rte_atomic64_set(&droq->pkts_pending, 0);
-}
-
-static void
-sdp_droq_destroy_ring_buffers(struct sdp_device *sdpvf,
-				struct sdp_droq *droq)
-{
-	uint32_t idx;
-
-	for (idx = 0; idx < droq->nb_desc; idx++) {
-		if (droq->recv_buf_list[idx].buffer) {
-			rte_mempool_put(sdpvf->enqdeq_mpool,
-				droq->recv_buf_list[idx].buffer);
-
-			droq->recv_buf_list[idx].buffer = NULL;
-		}
-	}
-
-	sdp_droq_reset_indices(droq);
-}
-
-/* Free OQs resources */
-int
-sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	struct sdp_droq *droq;
-
-	droq = sdpvf->droq[oq_no];
-	if (droq == NULL) {
-		otx2_err("Invalid droq[%d]", oq_no);
-		return -ENOMEM;
-	}
-
-	sdp_droq_destroy_ring_buffers(sdpvf, droq);
-	rte_free(droq->recv_buf_list);
-	droq->recv_buf_list = NULL;
-
-	if (droq->info_mz) {
-		sdp_dmazone_free(droq->info_mz);
-		droq->info_mz = NULL;
-	}
-
-	if (droq->desc_ring_mz) {
-		sdp_dmazone_free(droq->desc_ring_mz);
-		droq->desc_ring_mz = NULL;
-	}
-
-	memset(droq, 0, SDP_DROQ_SIZE);
-
-	rte_free(sdpvf->droq[oq_no]);
-	sdpvf->droq[oq_no] = NULL;
-
-	sdpvf->num_oqs--;
-
-	otx2_info("OQ[%d] is deleted", oq_no);
-	return 0;
-}
-
-static int
-sdp_droq_setup_ring_buffers(struct sdp_device *sdpvf,
-		struct sdp_droq *droq)
-{
-	struct sdp_droq_desc *desc_ring = droq->desc_ring;
-	uint32_t idx;
-	void *buf;
-
-	for (idx = 0; idx < droq->nb_desc; idx++) {
-		if (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||
-		    (buf == NULL)) {
-			otx2_err("OQ buffer alloc failed");
-			droq->stats.rx_alloc_failure++;
-			/* sdp_droq_destroy_ring_buffers(droq);*/
-			return -ENOMEM;
-		}
-
-		droq->recv_buf_list[idx].buffer = buf;
-		droq->info_list[idx].length = 0;
-
-		/* Map ring buffers into memory */
-		desc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma +
-			(idx * SDP_DROQ_INFO_SIZE));
-
-		desc_ring[idx].buffer_ptr = rte_mem_virt2iova(buf);
-	}
-
-	sdp_droq_reset_indices(droq);
-
-	return 0;
-}
-
-static void *
-sdp_alloc_info_buffer(struct sdp_device *sdpvf __rte_unused,
-	struct sdp_droq *droq)
-{
-	droq->info_mz = rte_memzone_reserve_aligned("OQ_info_list",
-				(droq->nb_desc * SDP_DROQ_INFO_SIZE),
-				rte_socket_id(),
-				RTE_MEMZONE_IOVA_CONTIG,
-				RTE_CACHE_LINE_SIZE);
-
-	if (droq->info_mz == NULL)
-		return NULL;
-
-	droq->info_list_dma = droq->info_mz->iova;
-	droq->info_alloc_size = droq->info_mz->len;
-	droq->info_base_addr = (size_t)droq->info_mz->addr;
-
-	return droq->info_mz->addr;
-}
-
-/* OQ initialization */
-static int
-sdp_init_droq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	const struct sdp_config *conf = sdpvf->conf;
-	uint32_t c_refill_threshold;
-	uint32_t desc_ring_size;
-	struct sdp_droq *droq;
-
-	otx2_info("OQ[%d] Init start", q_no);
-
-	droq = sdpvf->droq[q_no];
-	droq->sdp_dev = sdpvf;
-	droq->q_no = q_no;
-
-	c_refill_threshold = conf->oq.refill_threshold;
-	droq->nb_desc      = conf->num_oqdef_descs;
-	droq->buffer_size  = conf->oqdef_buf_size;
-
-	/* OQ desc_ring set up */
-	desc_ring_size = droq->nb_desc * SDP_DROQ_DESC_SIZE;
-	droq->desc_ring_mz = rte_memzone_reserve_aligned("sdp_oqmz",
-						desc_ring_size,
-						rte_socket_id(),
-						RTE_MEMZONE_IOVA_CONTIG,
-						RTE_CACHE_LINE_SIZE);
-
-	if (droq->desc_ring_mz == NULL) {
-		otx2_err("OQ:%d desc_ring allocation failed", q_no);
-		goto init_droq_fail;
-	}
-
-	droq->desc_ring_dma = droq->desc_ring_mz->iova;
-	droq->desc_ring = (struct sdp_droq_desc *)droq->desc_ring_mz->addr;
-
-	otx2_sdp_dbg("OQ[%d]: desc_ring: virt: 0x%p, dma: %lx",
-		    q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);
-	otx2_sdp_dbg("OQ[%d]: num_desc: %d", q_no, droq->nb_desc);
-
-
-	/* OQ info_list set up */
-	droq->info_list = sdp_alloc_info_buffer(sdpvf, droq);
-	if (droq->info_list == NULL) {
-		otx2_err("memory allocation failed for OQ[%d] info_list", q_no);
-		goto init_droq_fail;
-	}
-
-	/* OQ buf_list set up */
-	droq->recv_buf_list = rte_zmalloc_socket("recv_buf_list",
-				(droq->nb_desc * SDP_DROQ_RECVBUF_SIZE),
-				 RTE_CACHE_LINE_SIZE, rte_socket_id());
-	if (droq->recv_buf_list == NULL) {
-		otx2_err("OQ recv_buf_list alloc failed");
-		goto init_droq_fail;
-	}
-
-	if (sdp_droq_setup_ring_buffers(sdpvf, droq))
-		goto init_droq_fail;
-
-	droq->refill_threshold = c_refill_threshold;
-	rte_spinlock_init(&droq->lock);
-
-
-	/* Set up OQ registers */
-	sdpvf->fn_list.setup_oq_regs(sdpvf, q_no);
-
-	sdpvf->io_qmask.oq |= (1ull << q_no);
-
-	return 0;
-
-init_droq_fail:
-	return -ENOMEM;
-}
-
-/* OQ configuration and setup */
-int
-sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	struct sdp_droq *droq;
-
-	/* Allocate new droq. */
-	droq = (struct sdp_droq *)rte_zmalloc("sdp_OQ",
-				sizeof(*droq), RTE_CACHE_LINE_SIZE);
-	if (droq == NULL) {
-		otx2_err("Droq[%d] Creation Failed", oq_no);
-		return -ENOMEM;
-	}
-	sdpvf->droq[oq_no] = droq;
-
-	if (sdp_init_droq(sdpvf, oq_no)) {
-		otx2_err("Droq[%d] Initialization failed", oq_no);
-		goto delete_OQ;
-	}
-	otx2_info("OQ[%d] is created.", oq_no);
-
-	sdpvf->num_oqs++;
-
-	return 0;
-
-delete_OQ:
-	sdp_delete_oqs(sdpvf, oq_no);
-	return -ENOMEM;
-}
-
-static inline void
-sdp_iqreq_delete(struct sdp_device *sdpvf,
-		struct sdp_instr_queue *iq, uint32_t idx)
-{
-	uint32_t reqtype;
-	void *buf;
-
-	buf     = iq->req_list[idx].buf;
-	reqtype = iq->req_list[idx].reqtype;
-
-	switch (reqtype) {
-	case SDP_REQTYPE_NORESP:
-		rte_mempool_put(sdpvf->enqdeq_mpool, buf);
-		otx2_sdp_dbg("IQ buffer freed at idx[%d]", idx);
-		break;
-
-	case SDP_REQTYPE_NORESP_GATHER:
-	case SDP_REQTYPE_NONE:
-	default:
-		otx2_info("This iqreq mode is not supported:%d", reqtype);
-
-	}
-
-	/* Reset the request list at this index */
-	iq->req_list[idx].buf = NULL;
-	iq->req_list[idx].reqtype = 0;
-}
-
-static inline void
-sdp_iqreq_add(struct sdp_instr_queue *iq, void *buf,
-		uint32_t reqtype)
-{
-	iq->req_list[iq->host_write_index].buf = buf;
-	iq->req_list[iq->host_write_index].reqtype = reqtype;
-
-	otx2_sdp_dbg("IQ buffer added at idx[%d]", iq->host_write_index);
-
-}
-
-static void
-sdp_flush_iq(struct sdp_device *sdpvf,
-		struct sdp_instr_queue *iq,
-		uint32_t pending_thresh __rte_unused)
-{
-	uint32_t instr_processed = 0;
-
-	rte_spinlock_lock(&iq->lock);
-
-	iq->otx_read_index = sdpvf->fn_list.update_iq_read_idx(iq);
-	while (iq->flush_index != iq->otx_read_index) {
-		/* Free the IQ data buffer to the pool */
-		sdp_iqreq_delete(sdpvf, iq, iq->flush_index);
-		iq->flush_index =
-			sdp_incr_index(iq->flush_index, 1, iq->nb_desc);
-
-		instr_processed++;
-	}
-
-	iq->stats.instr_processed = instr_processed;
-	rte_atomic64_sub(&iq->instr_pending, instr_processed);
-
-	rte_spinlock_unlock(&iq->lock);
-}
-
-static inline void
-sdp_ring_doorbell(struct sdp_device *sdpvf __rte_unused,
-		struct sdp_instr_queue *iq)
-{
-	otx2_write64(iq->fill_cnt, iq->doorbell_reg);
-
-	/* Make sure doorbell writes observed by HW */
-	rte_io_wmb();
-	iq->fill_cnt = 0;
-
-}
-
-static inline int
-post_iqcmd(struct sdp_instr_queue *iq, uint8_t *iqcmd)
-{
-	uint8_t *iqptr, cmdsize;
-
-	/* This ensures that the read index does not wrap around to
-	 * the same position if queue gets full before OCTEON TX2 could
-	 * fetch any instr.
-	 */
-	if (rte_atomic64_read(&iq->instr_pending) >=
-			      (int32_t)(iq->nb_desc - 1)) {
-		otx2_err("IQ is full, pending:%ld",
-			 (long)rte_atomic64_read(&iq->instr_pending));
-
-		return SDP_IQ_SEND_FAILED;
-	}
-
-	/* Copy cmd into iq */
-	cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
-	iqptr   = iq->base_addr + (cmdsize * iq->host_write_index);
-
-	rte_memcpy(iqptr, iqcmd, cmdsize);
-
-	otx2_sdp_dbg("IQ cmd posted @ index:%d", iq->host_write_index);
-
-	/* Increment the host write index */
-	iq->host_write_index =
-		sdp_incr_index(iq->host_write_index, 1, iq->nb_desc);
-
-	iq->fill_cnt++;
-
-	/* Flush the command into memory. We need to be sure the data
-	 * is in memory before indicating that the instruction is
-	 * pending.
-	 */
-	rte_smp_wmb();
-	rte_atomic64_inc(&iq->instr_pending);
-
-	/* SDP_IQ_SEND_SUCCESS */
-	return 0;
-}
-
-
-static int
-sdp_send_data(struct sdp_device *sdpvf,
-	      struct sdp_instr_queue *iq, void *cmd)
-{
-	uint32_t ret;
-
-	/* Lock this IQ command queue before posting instruction */
-	rte_spinlock_lock(&iq->post_lock);
-
-	/* Submit IQ command */
-	ret = post_iqcmd(iq, cmd);
-
-	if (ret == SDP_IQ_SEND_SUCCESS) {
-		sdp_ring_doorbell(sdpvf, iq);
-
-		iq->stats.instr_posted++;
-		otx2_sdp_dbg("Instr submit success posted: %ld\n",
-			     (long)iq->stats.instr_posted);
-
-	} else {
-		iq->stats.instr_dropped++;
-		otx2_err("Instr submit failed, dropped: %ld\n",
-			 (long)iq->stats.instr_dropped);
-
-	}
-
-	rte_spinlock_unlock(&iq->post_lock);
-
-	return ret;
-}
-
-
-/* Enqueue requests/packets to SDP IQ queue.
- * returns number of requests enqueued successfully
- */
-int
-sdp_rawdev_enqueue(struct rte_rawdev *rawdev,
-		   struct rte_rawdev_buf **buffers __rte_unused,
-		   unsigned int count, rte_rawdev_obj_t context)
-{
-	struct sdp_instr_64B *iqcmd;
-	struct sdp_instr_queue *iq;
-	struct sdp_soft_instr *si;
-	struct sdp_device *sdpvf;
-
-	struct sdp_instr_ih ihx;
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-	si = (struct sdp_soft_instr *)context;
-
-	iq = sdpvf->instr_queue[si->q_no];
-
-	if ((count > 1) || (count < 1)) {
-		otx2_err("This mode not supported: req[%d]", count);
-		goto enq_fail;
-	}
-
-	memset(&ihx, 0, sizeof(struct sdp_instr_ih));
-
-	iqcmd = &si->command;
-	memset(iqcmd, 0, sizeof(struct sdp_instr_64B));
-
-	iqcmd->dptr = (uint64_t)si->dptr;
-
-	/* Populate SDP IH */
-	ihx.pkind  = sdpvf->pkind;
-	ihx.fsz    = si->ih.fsz + 8; /* 8B for NIX IH */
-	ihx.gather = si->ih.gather;
-
-	/* Direct data instruction */
-	ihx.tlen   = si->ih.tlen + ihx.fsz;
-
-	switch (ihx.gather) {
-	case 0: /* Direct data instr */
-		ihx.tlen = si->ih.tlen + ihx.fsz;
-		break;
-
-	default: /* Gather */
-		switch (si->ih.gsz) {
-		case 0: /* Direct gather instr */
-			otx2_err("Direct Gather instr : not supported");
-			goto enq_fail;
-
-		default: /* Indirect gather instr */
-			otx2_err("Indirect Gather instr : not supported");
-			goto enq_fail;
-		}
-	}
-
-	rte_memcpy(&iqcmd->ih, &ihx, sizeof(uint64_t));
-	iqcmd->rptr = (uint64_t)si->rptr;
-	rte_memcpy(&iqcmd->irh, &si->irh, sizeof(uint64_t));
-
-	/* Swap FSZ(front data) here, to avoid swapping on OCTEON TX2 side */
-	sdp_swap_8B_data(&iqcmd->rptr, 1);
-	sdp_swap_8B_data(&iqcmd->irh, 1);
-
-	otx2_sdp_dbg("After swapping");
-	otx2_sdp_dbg("Word0 [dptr]: 0x%016lx", (unsigned long)iqcmd->dptr);
-	otx2_sdp_dbg("Word1 [ihtx]: 0x%016lx", (unsigned long)iqcmd->ih);
-	otx2_sdp_dbg("Word2 [rptr]: 0x%016lx", (unsigned long)iqcmd->rptr);
-	otx2_sdp_dbg("Word3 [irh]: 0x%016lx", (unsigned long)iqcmd->irh);
-	otx2_sdp_dbg("Word4 [exhdr[0]]: 0x%016lx",
-			(unsigned long)iqcmd->exhdr[0]);
-
-	sdp_iqreq_add(iq, si->dptr, si->reqtype);
-
-	if (sdp_send_data(sdpvf, iq, iqcmd)) {
-		otx2_err("Data send failed :");
-		sdp_iqreq_delete(sdpvf, iq, iq->host_write_index);
-		goto enq_fail;
-	}
-
-	if (rte_atomic64_read(&iq->instr_pending) >= 1)
-		sdp_flush_iq(sdpvf, iq, 1 /*(iq->nb_desc / 2)*/);
-
-	/* Return no# of instructions posted successfully. */
-	return count;
-
-enq_fail:
-	return SDP_IQ_SEND_FAILED;
-}
-
-static uint32_t
-sdp_droq_refill(struct sdp_device *sdpvf, struct sdp_droq *droq)
-{
-	struct sdp_droq_desc *desc_ring;
-	uint32_t desc_refilled = 0;
-	void *buf = NULL;
-
-	desc_ring = droq->desc_ring;
-
-	while (droq->refill_count && (desc_refilled < droq->nb_desc)) {
-		/* If a valid buffer exists (happens if there is no dispatch),
-		 * reuse the buffer, else allocate.
-		 */
-		if (droq->recv_buf_list[droq->refill_idx].buffer != NULL)
-			break;
-
-		if (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||
-		    (buf == NULL)) {
-			/* If a buffer could not be allocated, no point in
-			 * continuing
-			 */
-			droq->stats.rx_alloc_failure++;
-			break;
-		}
-
-		droq->recv_buf_list[droq->refill_idx].buffer = buf;
-		desc_ring[droq->refill_idx].buffer_ptr = rte_mem_virt2iova(buf);
-
-		/* Reset any previous values in the length field. */
-		droq->info_list[droq->refill_idx].length = 0;
-
-		droq->refill_idx = sdp_incr_index(droq->refill_idx, 1,
-				droq->nb_desc);
-
-		desc_refilled++;
-		droq->refill_count--;
-
-	}
-
-	return desc_refilled;
-}
-
-static int
-sdp_droq_read_packet(struct sdp_device *sdpvf __rte_unused,
-		     struct sdp_droq *droq,
-		     struct sdp_droq_pkt *droq_pkt)
-{
-	struct sdp_droq_info *info;
-	uint32_t total_len = 0;
-	uint32_t pkt_len = 0;
-
-	info = &droq->info_list[droq->read_idx];
-	sdp_swap_8B_data((uint64_t *)&info->length, 1);
-	if (!info->length) {
-		otx2_err("OQ info_list->length[%ld]", (long)info->length);
-		goto oq_read_fail;
-	}
-
-	/* Deduce the actual data size */
-	info->length -= SDP_RH_SIZE;
-	total_len += (uint32_t)info->length;
-
-	otx2_sdp_dbg("OQ: pkt_len[%ld], buffer_size %d",
-			(long)info->length, droq->buffer_size);
-	if (info->length > droq->buffer_size) {
-		otx2_err("This mode is not supported: pkt_len > buffer_size");
-		goto oq_read_fail;
-	}
-
-	if (info->length <= droq->buffer_size) {
-		pkt_len = (uint32_t)info->length;
-		droq_pkt->data = droq->recv_buf_list[droq->read_idx].buffer;
-		droq_pkt->len  = pkt_len;
-
-		droq->recv_buf_list[droq->read_idx].buffer = NULL;
-		droq->read_idx = sdp_incr_index(droq->read_idx,	1,/* count */
-						droq->nb_desc /* max rd idx */);
-		droq->refill_count++;
-
-	}
-
-	info->length = 0;
-
-	return SDP_OQ_RECV_SUCCESS;
-
-oq_read_fail:
-	return SDP_OQ_RECV_FAILED;
-}
-
-static inline uint32_t
-sdp_check_droq_pkts(struct sdp_droq *droq, uint32_t burst_size)
-{
-	uint32_t min_pkts = 0;
-	uint32_t new_pkts;
-	uint32_t pkt_count;
-
-	/* Latest available OQ packets */
-	pkt_count = rte_read32(droq->pkts_sent_reg);
-
-	/* Newly arrived packets */
-	new_pkts = pkt_count - droq->last_pkt_count;
-	otx2_sdp_dbg("Recvd [%d] new OQ pkts", new_pkts);
-
-	min_pkts = (new_pkts > burst_size) ? burst_size : new_pkts;
-	if (min_pkts) {
-		rte_atomic64_add(&droq->pkts_pending, min_pkts);
-		/* Back up the aggregated packet count so far */
-		droq->last_pkt_count += min_pkts;
-	}
-
-	return min_pkts;
-}
-
-/* Check for response arrival from OCTEON TX2
- * returns number of requests completed
- */
-int
-sdp_rawdev_dequeue(struct rte_rawdev *rawdev,
-		   struct rte_rawdev_buf **buffers, unsigned int count,
-		   rte_rawdev_obj_t context __rte_unused)
-{
-	struct sdp_droq_pkt *oq_pkt;
-	struct sdp_device *sdpvf;
-	struct sdp_droq *droq;
-
-	uint32_t q_no = 0, pkts;
-	uint32_t new_pkts;
-	uint32_t ret;
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-
-	droq = sdpvf->droq[q_no];
-	if (!droq) {
-		otx2_err("Invalid droq[%d]", q_no);
-		goto droq_err;
-	}
-
-	/* Grab the lock */
-	rte_spinlock_lock(&droq->lock);
-
-	new_pkts = sdp_check_droq_pkts(droq, count);
-	if (!new_pkts) {
-		otx2_sdp_dbg("Zero new_pkts:%d", new_pkts);
-		goto deq_fail; /* No pkts at this moment */
-	}
-
-	otx2_sdp_dbg("Received new_pkts = %d", new_pkts);
-
-	for (pkts = 0; pkts < new_pkts; pkts++) {
-
-		/* Push the received pkt to application */
-		oq_pkt = (struct sdp_droq_pkt *)buffers[pkts];
-
-		ret = sdp_droq_read_packet(sdpvf, droq, oq_pkt);
-		if (ret) {
-			otx2_err("DROQ read pakt failed.");
-			goto deq_fail;
-		}
-
-		/* Stats */
-		droq->stats.pkts_received++;
-		droq->stats.bytes_received += oq_pkt->len;
-	}
-
-	/* Ack the h/w with no# of pkts read by Host */
-	rte_write32(pkts, droq->pkts_sent_reg);
-	rte_io_wmb();
-
-	droq->last_pkt_count -= pkts;
-
-	otx2_sdp_dbg("DROQ pkts[%d] pushed to application", pkts);
-
-	/* Refill DROQ buffers */
-	if (droq->refill_count >= 2 /* droq->refill_threshold */) {
-		int desc_refilled = sdp_droq_refill(sdpvf, droq);
-
-		/* Flush the droq descriptor data to memory to be sure
-		 * that when we update the credits the data in memory is
-		 * accurate.
-		 */
-		rte_write32(desc_refilled, droq->pkts_credit_reg);
-
-		/* Ensure mmio write completes */
-		rte_wmb();
-		otx2_sdp_dbg("Refilled count = %d", desc_refilled);
-	}
-
-	/* Release the spin lock */
-	rte_spinlock_unlock(&droq->lock);
-
-	return pkts;
-
-deq_fail:
-	rte_spinlock_unlock(&droq->lock);
-
-droq_err:
-	return SDP_OQ_RECV_FAILED;
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
deleted file mode 100644
index 172fdc5568..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _OTX2_EP_ENQDEQ_H_
-#define _OTX2_EP_ENQDEQ_H_
-
-#include <rte_byteorder.h>
-#include "otx2_ep_rawdev.h"
-
-#define SDP_IQ_SEND_FAILED      (-1)
-#define SDP_IQ_SEND_SUCCESS     (0)
-
-#define SDP_OQ_RECV_FAILED      (-1)
-#define SDP_OQ_RECV_SUCCESS     (0)
-
-static inline uint64_t
-sdp_endian_swap_8B(uint64_t _d)
-{
-	return ((((((uint64_t)(_d)) >>  0) & (uint64_t)0xff) << 56) |
-		(((((uint64_t)(_d)) >>  8) & (uint64_t)0xff) << 48) |
-		(((((uint64_t)(_d)) >> 16) & (uint64_t)0xff) << 40) |
-		(((((uint64_t)(_d)) >> 24) & (uint64_t)0xff) << 32) |
-		(((((uint64_t)(_d)) >> 32) & (uint64_t)0xff) << 24) |
-		(((((uint64_t)(_d)) >> 40) & (uint64_t)0xff) << 16) |
-		(((((uint64_t)(_d)) >> 48) & (uint64_t)0xff) <<  8) |
-		(((((uint64_t)(_d)) >> 56) & (uint64_t)0xff) <<  0));
-}
-
-static inline void
-sdp_swap_8B_data(uint64_t *data, uint32_t blocks)
-{
-	/* Swap 8B blocks */
-	while (blocks) {
-		*data = sdp_endian_swap_8B(*data);
-		blocks--;
-		data++;
-	}
-}
-
-static inline uint32_t
-sdp_incr_index(uint32_t index, uint32_t count, uint32_t max)
-{
-	if ((index + count) >= max)
-		index = index + count - max;
-	else
-		index += count;
-
-	return index;
-}
-
-#endif /* _OTX2_EP_ENQDEQ_H_ */
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
deleted file mode 100644
index b2ccdda83e..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-#include "otx2_ep_vf.h"
-
-static const struct rte_pci_id pci_sdp_vf_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_EP_RAW_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* SDP_VF default configuration */
-const struct sdp_config default_sdp_conf = {
-	/* IQ attributes */
-	.iq                        = {
-		.max_iqs           = SDP_VF_CFG_IO_QUEUES,
-		.instr_type        = SDP_VF_64BYTE_INSTR,
-		.pending_list_size = (SDP_VF_MAX_IQ_DESCRIPTORS *
-				      SDP_VF_CFG_IO_QUEUES),
-	},
-
-	/* OQ attributes */
-	.oq                        = {
-		.max_oqs           = SDP_VF_CFG_IO_QUEUES,
-		.info_ptr          = SDP_VF_OQ_INFOPTR_MODE,
-		.refill_threshold  = SDP_VF_OQ_REFIL_THRESHOLD,
-	},
-
-	.num_iqdef_descs           = SDP_VF_MAX_IQ_DESCRIPTORS,
-	.num_oqdef_descs           = SDP_VF_MAX_OQ_DESCRIPTORS,
-	.oqdef_buf_size            = SDP_VF_OQ_BUF_SIZE,
-
-};
-
-const struct sdp_config*
-sdp_get_defconf(struct sdp_device *sdp_dev __rte_unused)
-{
-	const struct sdp_config *default_conf = NULL;
-
-	default_conf = &default_sdp_conf;
-
-	return default_conf;
-}
-
-static int
-sdp_vfdev_exit(struct rte_rawdev *rawdev)
-{
-	struct sdp_device *sdpvf;
-	uint32_t rawdev_queues, q;
-
-	otx2_info("%s:", __func__);
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-
-	sdpvf->fn_list.disable_io_queues(sdpvf);
-
-	rawdev_queues = sdpvf->num_oqs;
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_delete_oqs(sdpvf, q)) {
-			otx2_err("Failed to delete OQ:%d", q);
-			return -ENOMEM;
-		}
-	}
-	otx2_info("Num OQs:%d freed", sdpvf->num_oqs);
-
-	/* Free the oqbuf_pool */
-	rte_mempool_free(sdpvf->enqdeq_mpool);
-	sdpvf->enqdeq_mpool = NULL;
-
-	otx2_info("Enqdeq_mpool free done");
-
-	rawdev_queues = sdpvf->num_iqs;
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_delete_iqs(sdpvf, q)) {
-			otx2_err("Failed to delete IQ:%d", q);
-			return -ENOMEM;
-		}
-	}
-	otx2_sdp_dbg("Num IQs:%d freed", sdpvf->num_iqs);
-
-	return 0;
-}
-
-static int
-sdp_chip_specific_setup(struct sdp_device *sdpvf)
-{
-	struct rte_pci_device *pdev = sdpvf->pci_dev;
-	uint32_t dev_id = pdev->id.device_id;
-	int ret;
-
-	switch (dev_id) {
-	case PCI_DEVID_OCTEONTX2_EP_RAW_VF:
-		sdpvf->chip_id = PCI_DEVID_OCTEONTX2_EP_RAW_VF;
-		ret = sdp_vf_setup_device(sdpvf);
-
-		break;
-	default:
-		otx2_err("Unsupported device");
-		ret = -EINVAL;
-	}
-
-	if (!ret)
-		otx2_info("SDP dev_id[%d]", dev_id);
-
-	return ret;
-}
-
-/* SDP VF device initialization */
-static int
-sdp_vfdev_init(struct sdp_device *sdpvf)
-{
-	uint32_t rawdev_queues, q;
-
-	if (sdp_chip_specific_setup(sdpvf)) {
-		otx2_err("Chip specific setup failed");
-		goto setup_fail;
-	}
-
-	if (sdpvf->fn_list.setup_device_regs(sdpvf)) {
-		otx2_err("Failed to configure device registers");
-		goto setup_fail;
-	}
-
-	rawdev_queues = (uint32_t)(sdpvf->sriov_info.rings_per_vf);
-
-	/* Rawdev queues setup for enqueue/dequeue */
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_setup_iqs(sdpvf, q)) {
-			otx2_err("Failed to setup IQs");
-			goto iq_fail;
-		}
-	}
-	otx2_info("Total[%d] IQs setup", sdpvf->num_iqs);
-
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_setup_oqs(sdpvf, q)) {
-			otx2_err("Failed to setup OQs");
-			goto oq_fail;
-		}
-	}
-	otx2_info("Total [%d] OQs setup", sdpvf->num_oqs);
-
-	/* Enable IQ/OQ for this device */
-	sdpvf->fn_list.enable_io_queues(sdpvf);
-
-	/* Send OQ desc credits for OQs, credits are always
-	 * sent after the OQs are enabled.
-	 */
-	for (q = 0; q < rawdev_queues; q++) {
-		rte_write32(sdpvf->droq[q]->nb_desc,
-			    sdpvf->droq[q]->pkts_credit_reg);
-
-		rte_io_mb();
-		otx2_info("OQ[%d] dbells [%d]", q,
-		rte_read32(sdpvf->droq[q]->pkts_credit_reg));
-	}
-
-	rte_wmb();
-
-	otx2_info("SDP Device is Ready");
-
-	return 0;
-
-/* Error handling  */
-oq_fail:
-	/* Free the allocated OQs */
-	for (q = 0; q < sdpvf->num_oqs; q++)
-		sdp_delete_oqs(sdpvf, q);
-
-iq_fail:
-	/* Free the allocated IQs */
-	for (q = 0; q < sdpvf->num_iqs; q++)
-		sdp_delete_iqs(sdpvf, q);
-
-setup_fail:
-	return -ENOMEM;
-}
-
-static int
-sdp_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = 1;
-
-	return 0;
-}
-
-static void
-sdp_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = 0;
-}
-
-static int
-sdp_rawdev_close(struct rte_rawdev *dev)
-{
-	int ret;
-	ret = sdp_vfdev_exit(dev);
-	if (ret) {
-		otx2_err(" SDP_EP rawdev exit error");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int
-sdp_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct sdp_rawdev_info *app_info = (struct sdp_rawdev_info *)config;
-	struct sdp_device *sdpvf;
-
-	if (app_info == NULL || config_size != sizeof(*app_info)) {
-		otx2_err("Application config info [NULL] or incorrect size");
-		return -EINVAL;
-	}
-
-	sdpvf = (struct sdp_device *)dev->dev_private;
-
-	sdpvf->conf = app_info->app_conf;
-	sdpvf->enqdeq_mpool = app_info->enqdeq_mpool;
-
-	sdp_vfdev_init(sdpvf);
-
-	return 0;
-
-}
-
-/* SDP VF endpoint rawdev ops */
-static const struct rte_rawdev_ops sdp_rawdev_ops = {
-	.dev_configure  = sdp_rawdev_configure,
-	.dev_start      = sdp_rawdev_start,
-	.dev_stop       = sdp_rawdev_stop,
-	.dev_close      = sdp_rawdev_close,
-	.enqueue_bufs   = sdp_rawdev_enqueue,
-	.dequeue_bufs   = sdp_rawdev_dequeue,
-	.dev_selftest   = sdp_rawdev_selftest,
-};
-
-static int
-otx2_sdp_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct sdp_device *sdpvf = NULL;
-	struct rte_rawdev *sdp_rawdev;
-	uint16_t vf_id;
-
-	/* Single process support */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return 0;
-
-	if (pci_dev->mem_resource[0].addr)
-		otx2_info("SDP_EP BAR0 is mapped:");
-	else {
-		otx2_err("SDP_EP: Failed to map device BARs");
-		otx2_err("BAR0 %p\n BAR2 %p",
-			pci_dev->mem_resource[0].addr,
-			pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "SDPEP:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate rawdev pmd */
-	sdp_rawdev = rte_rawdev_pmd_allocate(name,
-					     sizeof(struct sdp_device),
-					     rte_socket_id());
-
-	if (sdp_rawdev == NULL) {
-		otx2_err("SDP_EP VF rawdev allocation failed");
-		return -ENOMEM;
-	}
-
-	sdp_rawdev->dev_ops = &sdp_rawdev_ops;
-	sdp_rawdev->device = &pci_dev->device;
-	sdp_rawdev->driver_name = pci_dev->driver->driver.name;
-
-	sdpvf = (struct sdp_device *)sdp_rawdev->dev_private;
-	sdpvf->hw_addr = pci_dev->mem_resource[0].addr;
-	sdpvf->pci_dev = pci_dev;
-
-	/* Discover the VF number being probed */
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-
-	vf_id -= 1;
-	sdpvf->vf_num = vf_id;
-
-	otx2_info("SDP_EP VF[%d] probe done", vf_id);
-
-	return 0;
-}
-
-static int
-otx2_sdp_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct sdp_device *sdpvf;
-
-	/* Single process support */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return 0;
-
-	if (pci_dev == NULL) {
-		otx2_err("SDP_EP:invalid pci_dev!");
-		return -EINVAL;
-	}
-
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "SDPEP:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_err("SDP_EP: invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-	otx2_info("Removing SDP_EP VF[%d] ", sdpvf->vf_num);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_sdp_rawdev_pmd = {
-	.id_table  = pci_sdp_vf_map,
-	.drv_flags = (RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA),
-	.probe     = otx2_sdp_rawdev_probe,
-	.remove    = otx2_sdp_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(sdp_rawdev_pci_driver, rte_sdp_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(sdp_rawdev_pci_driver, pci_sdp_vf_map);
-RTE_PMD_REGISTER_KMOD_DEP(sdp_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
deleted file mode 100644
index dab2fb7541..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _OTX2_EP_RAWDEV_H_
-#define _OTX2_EP_RAWDEV_H_
-
-#include <rte_byteorder.h>
-#include <rte_spinlock.h>
-
-/* IQ instruction req types */
-#define SDP_REQTYPE_NONE             (0)
-#define SDP_REQTYPE_NORESP           (1)
-#define SDP_REQTYPE_NORESP_GATHER    (2)
-
-/* Input Request Header format */
-struct sdp_instr_irh {
-	/* Request ID  */
-	uint64_t rid:16;
-
-	/* PCIe port to use for response */
-	uint64_t pcie_port:3;
-
-	/* Scatter indicator  1=scatter */
-	uint64_t scatter:1;
-
-	/* Size of Expected result OR no. of entries in scatter list */
-	uint64_t rlenssz:14;
-
-	/* Desired destination port for result */
-	uint64_t dport:6;
-
-	/* Opcode Specific parameters */
-	uint64_t param:8;
-
-	/* Opcode for the return packet  */
-	uint64_t opcode:16;
-};
-
-/* SDP 32B instruction format */
-struct sdp_instr_32B {
-	/* Pointer where the input data is available. */
-	uint64_t dptr;
-
-	/* SDP Instruction Header.  */
-	uint64_t ih;
-
-	/** Pointer where the response for a RAW mode packet
-	 *  will be written by OCTEON TX2.
-	 */
-	uint64_t rptr;
-
-	/* Input Request Header. Additional info about the input. */
-	uint64_t irh;
-};
-#define SDP_32B_INSTR_SIZE	(sizeof(sdp_instr_32B))
-
-/* SDP 64B instruction format */
-struct sdp_instr_64B {
-	/* Pointer where the input data is available. */
-	uint64_t dptr;
-
-	/* SDP Instruction Header. */
-	uint64_t ih;
-
-	/** Pointer where the response for a RAW mode packet
-	 * will be written by OCTEON TX2.
-	 */
-	uint64_t rptr;
-
-	/* Input Request Header. */
-	uint64_t irh;
-
-	/* Additional headers available in a 64-byte instruction. */
-	uint64_t exhdr[4];
-};
-#define SDP_64B_INSTR_SIZE	(sizeof(sdp_instr_64B))
-
-struct sdp_soft_instr {
-	/** Input data pointer. It is either pointing directly to input data
-	 *  or to a gather list.
-	 */
-	void *dptr;
-
-	/** Response from OCTEON TX2 comes at this address. It is either
-	 *  directlty pointing to output data buffer or to a scatter list.
-	 */
-	void *rptr;
-
-	/* The instruction header. All input commands have this field. */
-	struct sdp_instr_ih ih;
-
-	/* Input request header. */
-	struct sdp_instr_irh irh;
-
-	/** The PCI instruction to be sent to OCTEON TX2. This is stored in the
-	 *  instr to retrieve the physical address of buffers when instr is
-	 *  freed.
-	 */
-	struct sdp_instr_64B command;
-
-	/** If a gather list was allocated, this ptr points to the buffer used
-	 *  for the gather list. The gather list has to be 8B aligned, so this
-	 *  value may be different from dptr.
-	 */
-	void *gather_ptr;
-
-	/* Total data bytes transferred in the gather mode request. */
-	uint64_t gather_bytes;
-
-	/** If a scatter list was allocated, this ptr points to the buffer used
-	 *  for the scatter list. The scatter list has to be 8B aligned, so
-	 *  this value may be different from rptr.
-	 */
-	void *scatter_ptr;
-
-	/* Total data bytes to be received in the scatter mode request. */
-	uint64_t scatter_bytes;
-
-	/* IQ number to which this instruction has to be submitted. */
-	uint32_t q_no;
-
-	/* IQ instruction request type. */
-	uint32_t reqtype;
-};
-#define SDP_SOFT_INSTR_SIZE	(sizeof(sdp_soft_instr))
-
-/* SDP IQ request list */
-struct sdp_instr_list {
-	void *buf;
-	uint32_t reqtype;
-};
-#define SDP_IQREQ_LIST_SIZE	(sizeof(struct sdp_instr_list))
-
-/* Input Queue statistics. Each input queue has four stats fields. */
-struct sdp_iq_stats {
-	uint64_t instr_posted; /* Instructions posted to this queue. */
-	uint64_t instr_processed; /* Instructions processed in this queue. */
-	uint64_t instr_dropped; /* Instructions that could not be processed */
-};
-
-/* Structure to define the configuration attributes for each Input queue. */
-struct sdp_iq_config {
-	/* Max number of IQs available */
-	uint16_t max_iqs;
-
-	/* Command size - 32 or 64 bytes */
-	uint16_t instr_type;
-
-	/* Pending list size, usually set to the sum of the size of all IQs */
-	uint32_t pending_list_size;
-};
-
-/** The instruction (input) queue.
- *  The input queue is used to post raw (instruction) mode data or packet data
- *  to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one
- *  such structure to represent it.
- */
-struct sdp_instr_queue {
-	/* A spinlock to protect access to the input ring.  */
-	rte_spinlock_t lock;
-	rte_spinlock_t post_lock;
-
-	struct sdp_device *sdp_dev;
-	rte_atomic64_t iq_flush_running;
-
-	uint32_t q_no;
-	uint32_t pkt_in_done;
-
-	/* Flag for 64 byte commands. */
-	uint32_t iqcmd_64B:1;
-	uint32_t rsvd:17;
-	uint32_t status:8;
-
-	/* Number of  descriptors in this ring. */
-	uint32_t nb_desc;
-
-	/* Input ring index, where the driver should write the next packet */
-	uint32_t host_write_index;
-
-	/* Input ring index, where the OCTEON TX2 should read the next packet */
-	uint32_t otx_read_index;
-
-	/** This index aids in finding the window in the queue where OCTEON TX2
-	 *  has read the commands.
-	 */
-	uint32_t flush_index;
-
-	/* This keeps track of the instructions pending in this queue. */
-	rte_atomic64_t instr_pending;
-
-	uint32_t reset_instr_cnt;
-
-	/* Pointer to the Virtual Base addr of the input ring. */
-	uint8_t *base_addr;
-
-	/* This IQ request list */
-	struct sdp_instr_list *req_list;
-
-	/* SDP doorbell register for the ring. */
-	void *doorbell_reg;
-
-	/* SDP instruction count register for this ring. */
-	void *inst_cnt_reg;
-
-	/* Number of instructions pending to be posted to OCTEON TX2. */
-	uint32_t fill_cnt;
-
-	/* Statistics for this input queue. */
-	struct sdp_iq_stats stats;
-
-	/* DMA mapped base address of the input descriptor ring. */
-	uint64_t base_addr_dma;
-
-	/* Memory zone */
-	const struct rte_memzone *iq_mz;
-};
-
-/* DROQ packet format for application i/f. */
-struct sdp_droq_pkt {
-	/* DROQ packet data buffer pointer. */
-	uint8_t	 *data;
-
-	/* DROQ packet data length */
-	uint32_t len;
-
-	uint32_t misc;
-};
-
-/** Descriptor format.
- *  The descriptor ring is made of descriptors which have 2 64-bit values:
- *  -# Physical (bus) address of the data buffer.
- *  -# Physical (bus) address of a sdp_droq_info structure.
- *  The device DMA's incoming packets and its information at the address
- *  given by these descriptor fields.
- */
-struct sdp_droq_desc {
-	/* The buffer pointer */
-	uint64_t buffer_ptr;
-
-	/* The Info pointer */
-	uint64_t info_ptr;
-};
-#define SDP_DROQ_DESC_SIZE	(sizeof(struct sdp_droq_desc))
-
-/* Receive Header */
-union sdp_rh {
-	uint64_t rh64;
-};
-#define SDP_RH_SIZE (sizeof(union sdp_rh))
-
-/** Information about packet DMA'ed by OCTEON TX2.
- *  The format of the information available at Info Pointer after OCTEON TX2
- *  has posted a packet. Not all descriptors have valid information. Only
- *  the Info field of the first descriptor for a packet has information
- *  about the packet.
- */
-struct sdp_droq_info {
-	/* The Output Receive Header. */
-	union sdp_rh rh;
-
-	/* The Length of the packet. */
-	uint64_t length;
-};
-#define SDP_DROQ_INFO_SIZE	(sizeof(struct sdp_droq_info))
-
-/** Pointer to data buffer.
- *  Driver keeps a pointer to the data buffer that it made available to
- *  the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)
- *  addresses, this field is required for the driver to keep track of
- *  the virtual address pointers.
- */
-struct sdp_recv_buffer {
-	/* Packet buffer, including meta data. */
-	void *buffer;
-
-	/* Data in the packet buffer. */
-	/* uint8_t *data; */
-};
-#define SDP_DROQ_RECVBUF_SIZE	(sizeof(struct sdp_recv_buffer))
-
-/* DROQ statistics. Each output queue has four stats fields. */
-struct sdp_droq_stats {
-	/* Number of packets received in this queue. */
-	uint64_t pkts_received;
-
-	/* Bytes received by this queue. */
-	uint64_t bytes_received;
-
-	/* Num of failures of rte_pktmbuf_alloc() */
-	uint64_t rx_alloc_failure;
-};
-
-/* Structure to define the configuration attributes for each Output queue. */
-struct sdp_oq_config {
-	/* Max number of OQs available */
-	uint16_t max_oqs;
-
-	/* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
-	uint16_t info_ptr;
-
-	/** The number of buffers that were consumed during packet processing by
-	 *  the driver on this Output queue before the driver attempts to
-	 *  replenish the descriptor ring with new buffers.
-	 */
-	uint32_t refill_threshold;
-};
-
-/* The Descriptor Ring Output Queue(DROQ) structure. */
-struct sdp_droq {
-	/* A spinlock to protect access to this ring. */
-	rte_spinlock_t lock;
-
-	struct sdp_device *sdp_dev;
-	/* The 8B aligned descriptor ring starts at this address. */
-	struct sdp_droq_desc *desc_ring;
-
-	uint32_t q_no;
-	uint32_t last_pkt_count;
-
-	/* Driver should read the next packet at this index */
-	uint32_t read_idx;
-
-	/* OCTEON TX2 will write the next packet at this index */
-	uint32_t write_idx;
-
-	/* At this index, the driver will refill the descriptor's buffer */
-	uint32_t refill_idx;
-
-	/* Packets pending to be processed */
-	rte_atomic64_t pkts_pending;
-
-	/* Number of descriptors in this ring. */
-	uint32_t nb_desc;
-
-	/* The number of descriptors pending to refill. */
-	uint32_t refill_count;
-
-	uint32_t refill_threshold;
-
-	/* The 8B aligned info ptrs begin from this address. */
-	struct sdp_droq_info *info_list;
-
-	/* receive buffer list contains virtual addresses of the buffers. */
-	struct sdp_recv_buffer *recv_buf_list;
-
-	/* The size of each buffer pointed by the buffer pointer. */
-	uint32_t buffer_size;
-
-	/** Pointer to the mapped packet credit register.
-	 *  Host writes number of info/buffer ptrs available to this register
-	 */
-	void *pkts_credit_reg;
-
-	/** Pointer to the mapped packet sent register. OCTEON TX2 writes the
-	 *  number of packets DMA'ed to host memory in this register.
-	 */
-	void *pkts_sent_reg;
-
-	/* Statistics for this DROQ. */
-	struct sdp_droq_stats stats;
-
-	/* DMA mapped address of the DROQ descriptor ring. */
-	size_t desc_ring_dma;
-
-	/* Info_ptr list is allocated at this virtual address. */
-	size_t info_base_addr;
-
-	/* DMA mapped address of the info list */
-	size_t info_list_dma;
-
-	/* Allocated size of info list. */
-	uint32_t info_alloc_size;
-
-	/* Memory zone **/
-	const struct rte_memzone *desc_ring_mz;
-	const struct rte_memzone *info_mz;
-};
-#define SDP_DROQ_SIZE		(sizeof(struct sdp_droq))
-
-/* IQ/OQ mask */
-struct sdp_io_enable {
-	uint64_t iq;
-	uint64_t oq;
-	uint64_t iq64B;
-};
-
-/* Structure to define the configuration. */
-struct sdp_config {
-	/* Input Queue attributes. */
-	struct sdp_iq_config iq;
-
-	/* Output Queue attributes. */
-	struct sdp_oq_config oq;
-
-	/* Num of desc for IQ rings */
-	uint32_t num_iqdef_descs;
-
-	/* Num of desc for OQ rings */
-	uint32_t num_oqdef_descs;
-
-	/* OQ buffer size */
-	uint32_t oqdef_buf_size;
-};
-
-/* Required functions for each VF device */
-struct sdp_fn_list {
-	void (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
-
-	int (*setup_device_regs)(struct sdp_device *sdpvf);
-	uint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq);
-
-	void (*enable_io_queues)(struct sdp_device *sdpvf);
-	void (*disable_io_queues)(struct sdp_device *sdpvf);
-
-	void (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
-
-	void (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
-};
-
-/* SRIOV information */
-struct sdp_sriov_info {
-	/* Number of rings assigned to VF */
-	uint32_t rings_per_vf;
-
-	/* Number of VF devices enabled */
-	uint32_t num_vfs;
-};
-
-
-/* Information to be passed from application */
-struct sdp_rawdev_info {
-	struct rte_mempool *enqdeq_mpool;
-	const struct sdp_config *app_conf;
-};
-
-/* SDP EP VF device */
-struct sdp_device {
-	/* PCI device pointer */
-	struct rte_pci_device *pci_dev;
-	uint16_t chip_id;
-	uint16_t pf_num;
-	uint16_t vf_num;
-
-	/* This device's PCIe port used for traffic. */
-	uint16_t pcie_port;
-	uint32_t pkind;
-
-	/* The state of this device */
-	rte_atomic64_t status;
-
-	/* Memory mapped h/w address */
-	uint8_t *hw_addr;
-
-	struct sdp_fn_list fn_list;
-
-	/* Num IQs */
-	uint32_t num_iqs;
-
-	/* The input instruction queues */
-	struct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];
-
-	/* Num OQs */
-	uint32_t num_oqs;
-
-	/* The DROQ output queues  */
-	struct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];
-
-	/* IOQ data buffer pool */
-	struct rte_mempool *enqdeq_mpool;
-
-	/* IOQ mask */
-	struct sdp_io_enable io_qmask;
-
-	/* SR-IOV info */
-	struct sdp_sriov_info sriov_info;
-
-	/* Device configuration */
-	const struct sdp_config *conf;
-};
-
-const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);
-int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
-int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
-
-int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
-int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
-
-int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
-		       unsigned int count, rte_rawdev_obj_t context);
-int sdp_rawdev_dequeue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
-		       unsigned int count, rte_rawdev_obj_t context);
-
-int sdp_rawdev_selftest(uint16_t dev_id);
-
-#endif /* _OTX2_EP_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_test.c b/drivers/raw/octeontx2_ep/otx2_ep_test.c
deleted file mode 100644
index b876275f7a..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_test.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-
-#define SDP_IOQ_NUM_BUFS   (4 * 1024)
-#define SDP_IOQ_BUF_SIZE   (2 * 1024)
-
-#define SDP_TEST_PKT_FSZ   (0)
-#define SDP_TEST_PKT_SIZE  (1024)
-
-static int
-sdp_validate_data(struct sdp_droq_pkt *oq_pkt, uint8_t *iq_pkt,
-		  uint32_t pkt_len)
-{
-	if (!oq_pkt)
-		return -EINVAL;
-
-	if (pkt_len != oq_pkt->len) {
-		otx2_err("Invalid packet length");
-		return -EINVAL;
-	}
-
-	if (memcmp(oq_pkt->data, iq_pkt, pkt_len) != 0) {
-		otx2_err("Data validation failed");
-		return -EINVAL;
-	}
-	otx2_sdp_dbg("Data validation successful");
-
-	return 0;
-}
-
-static void
-sdp_ioq_buffer_fill(uint8_t *addr, uint32_t len)
-{
-	uint32_t idx;
-
-	memset(addr, 0, len);
-
-	for (idx = 0; idx < len; idx++)
-		addr[idx] = idx;
-}
-
-static struct rte_mempool*
-sdp_ioq_mempool_create(void)
-{
-	struct rte_mempool *mpool;
-
-	mpool = rte_mempool_create("ioqbuf_pool",
-				   SDP_IOQ_NUM_BUFS /*num elt*/,
-				   SDP_IOQ_BUF_SIZE /*elt size*/,
-				   0 /*cache_size*/,
-				   0 /*private_data_size*/,
-				   NULL /*mp_init*/,
-				   NULL /*mp_init arg*/,
-				   NULL /*obj_init*/,
-				   NULL /*obj_init arg*/,
-				   rte_socket_id() /*socket id*/,
-				   (MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET));
-
-	return mpool;
-}
-
-
-int
-sdp_rawdev_selftest(uint16_t dev_id)
-{
-	struct sdp_rawdev_info app_info = {0};
-	struct rte_rawdev_info dev_info = {0};
-
-	struct rte_rawdev_buf *d_buf[1];
-	struct sdp_droq_pkt oq_pkt;
-	struct sdp_soft_instr si;
-	struct sdp_device sdpvf;
-
-	uint32_t buf_size;
-	int ret = 0;
-	void *buf;
-
-	otx2_info("SDP RAWDEV Self Test: Started");
-
-	memset(&oq_pkt, 0x00, sizeof(oq_pkt));
-	d_buf[0] = (struct rte_rawdev_buf *)&oq_pkt;
-
-	struct rte_mempool *ioq_mpool = sdp_ioq_mempool_create();
-	if (!ioq_mpool) {
-		otx2_err("IOQ mpool creation failed");
-		return -ENOMEM;
-	}
-
-	app_info.enqdeq_mpool = ioq_mpool;
-	app_info.app_conf = NULL; /* Use default conf */
-
-	dev_info.dev_private = &app_info;
-
-	ret = rte_rawdev_configure(dev_id, &dev_info, sizeof(app_info));
-	if (ret) {
-		otx2_err("Unable to configure SDP_VF %d", dev_id);
-		rte_mempool_free(ioq_mpool);
-		return -ENOMEM;
-	}
-	otx2_info("SDP VF rawdev[%d] configured successfully", dev_id);
-
-	memset(&si, 0x00, sizeof(si));
-	memset(&sdpvf, 0x00, sizeof(sdpvf));
-
-	buf_size = SDP_TEST_PKT_SIZE;
-
-	si.q_no = 0;
-	si.reqtype = SDP_REQTYPE_NORESP;
-	si.rptr = NULL;
-
-	si.ih.fsz = SDP_TEST_PKT_FSZ;
-	si.ih.tlen = buf_size;
-	si.ih.gather = 0;
-
-	/* Enqueue raw pkt data */
-	rte_mempool_get(ioq_mpool, &buf);
-	if (!buf) {
-		otx2_err("Buffer allocation failed");
-		rte_mempool_free(ioq_mpool);
-		rte_rawdev_close(dev_id);
-		return -ENOMEM;
-	}
-
-	sdp_ioq_buffer_fill(buf, buf_size);
-	si.dptr = (uint8_t *)buf;
-
-	rte_rawdev_enqueue_buffers(dev_id, NULL, 1, &si);
-	usleep(10000);
-
-	/* Dequeue raw pkt data */
-	ret = 0;
-	while (ret < 1) {
-		ret = rte_rawdev_dequeue_buffers(dev_id, &d_buf[0], 1, &si);
-		rte_pause();
-	}
-
-	/* Validate the dequeued raw pkt data */
-	if (sdp_validate_data((struct sdp_droq_pkt *)d_buf[0],
-			      buf, buf_size) != 0) {
-		otx2_err("Data invalid");
-		rte_mempool_put(ioq_mpool,
-				((struct sdp_droq_pkt *)d_buf[0])->data);
-		rte_mempool_free(ioq_mpool);
-		rte_rawdev_close(dev_id);
-		return -EINVAL;
-	}
-
-	rte_mempool_put(ioq_mpool, ((struct sdp_droq_pkt *)d_buf[0])->data);
-	rte_mempool_free(ioq_mpool);
-	rte_rawdev_close(dev_id);
-
-	otx2_info("SDP RAWDEV Self Test: Successful");
-
-	return 0;
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.c b/drivers/raw/octeontx2_ep/otx2_ep_vf.c
deleted file mode 100644
index bf2a19e369..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-#include "otx2_ep_vf.h"
-
-static int
-sdp_vf_reset_iq(struct sdp_device *sdpvf, int q_no)
-{
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-	volatile uint64_t d64 = 0ull;
-
-	/* There is no RST for a ring.
-	 * Clear all registers one by one after disabling the ring
-	 */
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));
-
-	d64 = 0xFFFFFFFF; /* ~0ull */
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr +
-			     SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr +
-				  SDP_VF_R_IN_INSTR_DBELL(q_no));
-	}
-
-	loop = SDP_VF_BUSY_LOOP_COUNT;
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-	}
-
-	d64 = 0ull;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));
-
-	return 0;
-}
-
-static int
-sdp_vf_reset_oq(struct sdp_device *sdpvf, int q_no)
-{
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-	volatile uint64_t d64 = 0ull;
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));
-
-	d64 = 0xFFFFFFFF;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
-
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr +
-			     SDP_VF_R_OUT_SLIST_DBELL(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr +
-				  SDP_VF_R_OUT_SLIST_DBELL(q_no));
-	}
-
-	loop = SDP_VF_BUSY_LOOP_COUNT;
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-	while ((d64 != 0) && (loop--)) {
-		otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-	}
-
-	d64 = 0ull;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_global_iq_reg(struct sdp_device *sdpvf, int q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for IQs
-	 * IS_64B is by default enabled.
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
-
-	reg_val |= SDP_VF_R_IN_CTL_RDSIZE;
-	reg_val |= SDP_VF_R_IN_CTL_IS_64B;
-	reg_val |= SDP_VF_R_IN_CTL_ESR;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
-
-}
-
-static void
-sdp_vf_setup_global_oq_reg(struct sdp_device *sdpvf, int q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
-
-	reg_val |= (SDP_VF_R_OUT_CTL_IMODE);
-
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);
-
-	/* INFO/DATA ptr swap is required  */
-	reg_val |= (SDP_VF_R_OUT_CTL_ES_P);
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
-
-}
-
-static int
-sdp_vf_reset_input_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	otx2_sdp_dbg("%s :", __func__);
-
-	for (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)
-		sdp_vf_reset_iq(sdpvf, q_no);
-
-	return 0;
-}
-
-static int
-sdp_vf_reset_output_queues(struct sdp_device *sdpvf)
-{
-	uint64_t q_no = 0ull;
-
-	otx2_sdp_dbg(" %s :", __func__);
-
-	for (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)
-		sdp_vf_reset_oq(sdpvf, q_no);
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_global_input_regs(struct sdp_device *sdpvf)
-{
-	uint64_t q_no = 0ull;
-
-	sdp_vf_reset_input_queues(sdpvf);
-
-	for (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)
-		sdp_vf_setup_global_iq_reg(sdpvf, q_no);
-}
-
-static void
-sdp_vf_setup_global_output_regs(struct sdp_device *sdpvf)
-{
-	uint32_t q_no;
-
-	sdp_vf_reset_output_queues(sdpvf);
-
-	for (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)
-		sdp_vf_setup_global_oq_reg(sdpvf, q_no);
-
-}
-
-static int
-sdp_vf_setup_device_regs(struct sdp_device *sdpvf)
-{
-	sdp_vf_setup_global_input_regs(sdpvf);
-	sdp_vf_setup_global_output_regs(sdpvf);
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_iq_regs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq = sdpvf->instr_queue[iq_no];
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));
-
-	/* Wait till IDLE to set to 1, not supposed to configure BADDR
-	 * as long as IDLE is 0
-	 */
-	if (!(reg_val & SDP_VF_R_IN_CTL_IDLE)) {
-		do {
-			reg_val = otx2_read64(sdpvf->hw_addr +
-					      SDP_VF_R_IN_CONTROL(iq_no));
-		} while (!(reg_val & SDP_VF_R_IN_CTL_IDLE));
-	}
-
-	/* Write the start of the input queue's ring and its size  */
-	otx2_write64(iq->base_addr_dma, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_BADDR(iq_no));
-	otx2_write64(iq->nb_desc, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_RSIZE(iq_no));
-
-	/* Remember the doorbell & instruction count register addr
-	 * for this queue
-	 */
-	iq->doorbell_reg = (uint8_t *) sdpvf->hw_addr +
-			   SDP_VF_R_IN_INSTR_DBELL(iq_no);
-	iq->inst_cnt_reg = (uint8_t *) sdpvf->hw_addr +
-			   SDP_VF_R_IN_CNTS(iq_no);
-
-	otx2_sdp_dbg("InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p",
-		     iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
-
-	/* Store the current instrn counter(used in flush_iq calculation) */
-	iq->reset_instr_cnt = rte_read32(iq->inst_cnt_reg);
-
-	/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
-	 * to raise
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
-	reg_val = 0xffffffff;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
-
-}
-
-static void
-sdp_vf_setup_oq_regs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	volatile uint64_t reg_val = 0ull;
-	uint64_t oq_ctl = 0ull;
-
-	struct sdp_droq *droq = sdpvf->droq[oq_no];
-
-	/* Wait on IDLE to set to 1, supposed to configure BADDR
-	 * as log as IDLE is 0
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	while (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {
-		reg_val = otx2_read64(sdpvf->hw_addr +
-				      SDP_VF_R_OUT_CONTROL(oq_no));
-	}
-
-	otx2_write64(droq->desc_ring_dma, sdpvf->hw_addr +
-		     SDP_VF_R_OUT_SLIST_BADDR(oq_no));
-	otx2_write64(droq->nb_desc, sdpvf->hw_addr +
-		     SDP_VF_R_OUT_SLIST_RSIZE(oq_no));
-
-	oq_ctl = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	/* Clear the ISIZE and BSIZE (22-0) */
-	oq_ctl &= ~(0x7fffffull);
-
-	/* Populate the BSIZE (15-0) */
-	oq_ctl |= (droq->buffer_size & 0xffff);
-
-	/* Populate ISIZE(22-16) */
-	oq_ctl |= ((SDP_RH_SIZE << 16) & 0x7fffff);
-	otx2_write64(oq_ctl, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	/* Mapped address of the pkt_sent and pkts_credit regs */
-	droq->pkts_sent_reg = (uint8_t *) sdpvf->hw_addr +
-			      SDP_VF_R_OUT_CNTS(oq_no);
-	droq->pkts_credit_reg = (uint8_t *) sdpvf->hw_addr +
-				SDP_VF_R_OUT_SLIST_DBELL(oq_no);
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));
-
-	/* Clear PKT_CNT register */
-	rte_write64(0xFFFFFFFFF, (uint8_t *)sdpvf->hw_addr +
-		    SDP_VF_R_OUT_PKT_CNT(oq_no));
-
-	/* Clear the OQ doorbell  */
-	rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
-	while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
-		rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
-		rte_delay_ms(1);
-	}
-	otx2_sdp_dbg("SDP_R[%d]_credit:%x", oq_no,
-		     rte_read32(droq->pkts_credit_reg));
-
-	/* Clear the OQ_OUT_CNTS doorbell  */
-	reg_val = rte_read32(droq->pkts_sent_reg);
-	rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
-
-	otx2_sdp_dbg("SDP_R[%d]_sent: %x", oq_no,
-		     rte_read32(droq->pkts_sent_reg));
-
-	while (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {
-		reg_val = rte_read32(droq->pkts_sent_reg);
-		rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
-		rte_delay_ms(1);
-	}
-
-}
-
-static void
-sdp_vf_enable_iq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-
-	/* Resetting doorbells during IQ enabling also to handle abrupt
-	 * guest reboot. IQ reset does not clear the doorbells.
-	 */
-	otx2_write64(0xFFFFFFFF, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-	while (((otx2_read64(sdpvf->hw_addr +
-		 SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
-
-		rte_delay_ms(1);
-	}
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	reg_val |= 0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-
-	otx2_info("IQ[%d] enable done", q_no);
-
-}
-
-static void
-sdp_vf_enable_oq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-	reg_val |= 0x1ull;
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-	otx2_info("OQ[%d] enable done", q_no);
-}
-
-static void
-sdp_vf_enable_io_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	for (q_no = 0; q_no < sdpvf->num_iqs; q_no++)
-		sdp_vf_enable_iq(sdpvf, q_no);
-
-	for (q_no = 0; q_no < sdpvf->num_oqs; q_no++)
-		sdp_vf_enable_oq(sdpvf, q_no);
-}
-
-static void
-sdp_vf_disable_iq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	/* Reset the doorbell register for this Input Queue. */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	reg_val &= ~0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-}
-
-static void
-sdp_vf_disable_oq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-	reg_val &= ~0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-}
-
-static void
-sdp_vf_disable_io_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	/* Disable Input Queues. */
-	for (q_no = 0; q_no < sdpvf->num_iqs; q_no++)
-		sdp_vf_disable_iq(sdpvf, q_no);
-
-	/* Disable Output Queues. */
-	for (q_no = 0; q_no < sdpvf->num_oqs; q_no++)
-		sdp_vf_disable_oq(sdpvf, q_no);
-}
-
-static uint32_t
-sdp_vf_update_read_index(struct sdp_instr_queue *iq)
-{
-	uint32_t new_idx = rte_read32(iq->inst_cnt_reg);
-
-	/* The new instr cnt reg is a 32-bit counter that can roll over.
-	 * We have noted the counter's initial value at init time into
-	 * reset_instr_cnt
-	 */
-	if (iq->reset_instr_cnt < new_idx)
-		new_idx -= iq->reset_instr_cnt;
-	else
-		new_idx += (0xffffffff - iq->reset_instr_cnt) + 1;
-
-	/* Modulo of the new index with the IQ size will give us
-	 * the new index.
-	 */
-	new_idx %= iq->nb_desc;
-
-	return new_idx;
-}
-
-int
-sdp_vf_setup_device(struct sdp_device *sdpvf)
-{
-	uint64_t reg_val = 0ull;
-
-	/* If application doesn't provide its conf, use driver default conf */
-	if (sdpvf->conf == NULL) {
-		sdpvf->conf = sdp_get_defconf(sdpvf);
-		if (sdpvf->conf == NULL) {
-			otx2_err("SDP VF default config not found");
-			return -ENOMEM;
-		}
-		otx2_info("Default config is used");
-	}
-
-	/* Get IOQs (RPVF] count */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(0));
-
-	sdpvf->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
-					  & SDP_VF_R_IN_CTL_RPVF_MASK);
-
-	otx2_info("SDP RPVF: %d", sdpvf->sriov_info.rings_per_vf);
-
-	sdpvf->fn_list.setup_iq_regs       = sdp_vf_setup_iq_regs;
-	sdpvf->fn_list.setup_oq_regs       = sdp_vf_setup_oq_regs;
-
-	sdpvf->fn_list.setup_device_regs   = sdp_vf_setup_device_regs;
-	sdpvf->fn_list.update_iq_read_idx  = sdp_vf_update_read_index;
-
-	sdpvf->fn_list.enable_io_queues    = sdp_vf_enable_io_queues;
-	sdpvf->fn_list.disable_io_queues   = sdp_vf_disable_io_queues;
-
-	sdpvf->fn_list.enable_iq           = sdp_vf_enable_iq;
-	sdpvf->fn_list.disable_iq          = sdp_vf_disable_iq;
-
-	sdpvf->fn_list.enable_oq           = sdp_vf_enable_oq;
-	sdpvf->fn_list.disable_oq          = sdp_vf_disable_oq;
-
-
-	return 0;
-
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.h b/drivers/raw/octeontx2_ep/otx2_ep_vf.h
deleted file mode 100644
index 996f2e51eb..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-#ifndef _OTX2_EP_VF_H_
-#define _OTX2_EP_VF_H_
-
-int
-sdp_vf_setup_device(struct sdp_device *sdpvf);
-
-#endif /*_OTX2_EP_VF_H_ */
diff --git a/drivers/raw/octeontx2_ep/version.map b/drivers/raw/octeontx2_ep/version.map
deleted file mode 100644
index c2e0723b4c..0000000000
--- a/drivers/raw/octeontx2_ep/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_22 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH v4 1/2] drivers/raw: remove octeontx2-dma driver
  2021-08-19  7:57   ` [dpdk-dev] [PATCH v4 " Radha Mohan Chintakuntla
@ 2021-08-20  3:38     ` Radha Mohan
  2021-08-23 15:21     ` [dpdk-dev] [PATCH RESEND " Radha Mohan Chintakuntla
  1 sibling, 0 replies; 17+ messages in thread
From: Radha Mohan @ 2021-08-20  3:38 UTC (permalink / raw)
  To: Radha Mohan Chintakuntla
  Cc: Veerasenareddy Burru, Thomas Monjalon, dpdk-dev, Satananda Burla,
	Jerin Jacob Kollanukkaran

On Thu, Aug 19, 2021 at 1:27 PM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> Removing the rawdev based octeontx2-dma driver as the dependent
> common/octeontx2 will be soon be going away. Also a new DMA driver will
> be coming in this place once the rte_dmadev library is in.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> Changes from v3:
> Fixed patch application failure on main due to conflict.
>
> Changes from v2:
> Fixed DPDK CI reported issues for more documentation failure.
>
> Changes from v1:
> Fixed compilation issues in documentation
>
>  MAINTAINERS                                 |   6 -
>  doc/guides/platform/octeontx2.rst           |   3 -
>  doc/guides/rawdevs/index.rst                |   1 -
>  doc/guides/rawdevs/octeontx2_dma.rst        | 103 -----
>  drivers/raw/meson.build                     |   1 -
>  drivers/raw/octeontx2_dma/meson.build       |  18 -
>  drivers/raw/octeontx2_dma/otx2_dpi_msg.c    | 105 -----
>  drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 441 --------------------
>  drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 197 ---------
>  drivers/raw/octeontx2_dma/otx2_dpi_test.c   | 218 ----------
>  drivers/raw/octeontx2_dma/version.map       |   3 -
>  11 files changed, 1096 deletions(-)
>  delete mode 100644 doc/guides/rawdevs/octeontx2_dma.rst
>  delete mode 100644 drivers/raw/octeontx2_dma/meson.build
>  delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_msg.c
>  delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
>  delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
>  delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_test.c
>  delete mode 100644 drivers/raw/octeontx2_dma/version.map
>
<snip>

Hi Thomas,
The CI is reporting unrelated failures which I think can be ignored.
https://lab.dpdk.org/results/dashboard/patchsets/18263/

regards,
Radha Mohan

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH v4 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-19  7:59   ` [dpdk-dev] [PATCH v4 " Radha Mohan Chintakuntla
@ 2021-08-23 12:19     ` Radha Mohan
  2021-08-23 12:31       ` David Marchand
  0 siblings, 1 reply; 17+ messages in thread
From: Radha Mohan @ 2021-08-23 12:19 UTC (permalink / raw)
  To: Radha Mohan Chintakuntla
  Cc: Veerasenareddy Burru, Thomas Monjalon, dpdk-dev, Satananda Burla,
	Jerin Jacob Kollanukkaran

On Thu, Aug 19, 2021 at 1:29 PM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> Removing the rawdev based octeontx2-ep driver as the dependent
> common/octeontx2 will soon be going away. Moreover this driver is no
> longer required as the net/octeontx_ep driver is sufficient.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> Changes from v3:
> Fixed patch application failure due to conflict on main branch.
>
> Changes from v2:
> Fixed DPDK CI reported issues for more documentation failure.
>
> Changes from v1:
> Fixed compilation issues in documentation
>
>  MAINTAINERS                               |   6 -
>  doc/guides/rawdevs/index.rst              |   1 -
>  doc/guides/rawdevs/octeontx2_ep.rst       |  82 ---
>  drivers/raw/meson.build                   |   1 -
>  drivers/raw/octeontx2_ep/meson.build      |  11 -
>  drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------
>  drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h |  52 --
>  drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------
>  drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------
>  drivers/raw/octeontx2_ep/otx2_ep_test.c   | 172 -----
>  drivers/raw/octeontx2_ep/otx2_ep_vf.c     | 475 ------------
>  drivers/raw/octeontx2_ep/otx2_ep_vf.h     |  10 -
>  drivers/raw/octeontx2_ep/version.map      |   3 -
>  13 files changed, 2520 deletions(-)
>  delete mode 100644 doc/guides/rawdevs/octeontx2_ep.rst
>  delete mode 100644 drivers/raw/octeontx2_ep/meson.build
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_test.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.h
>  delete mode 100644 drivers/raw/octeontx2_ep/version.map
>
<snip>
Hi Thomas,

I received this report that this patch failed to apply
http://mails.dpdk.org/archives/test-report/2021-August/211611.html

But I do not see the issue at my end.
$ git pull --rebase
remote: Counting objects: 17, done
remote: Finding sources: 100% (413/413)
remote: Total 413 (delta 315), reused 413 (delta 315)
Receiving objects: 100% (413/413), 148.64 KiB | 10.62 MiB/s, done.
Resolving deltas: 100% (315/315), completed with 125 local objects.

   7a824dc305..df83c734ef  dpdk-20.11-devel                      ->
origin/dpdk-20.11-devel
   8b59a1248a..34b50fc2d3  dpdk-21.08-devel                      ->
origin/dpdk-21.08-devel
 + 9661f6ac43...fdab8f2e17 next-event                            ->
origin/next-event  (forced update)
   87d9bacc46..5803d86b87  next-net                              ->
origin/next-net
 * [new branch]            user/pbhagavatula/eventdev_abi        ->
origin/user/pbhagavatula/eventdev_abi
   056af3c7e5..55069aef6c  user/skori/cnxk-ingress-policer-devel ->
origin/user/skori/cnxk-ingress-policer-devel


acd23283ff513c4f65290a7c92e9de25b912c0b1 (HEAD -> main) drivers/raw:
remove octeontx2-ep driver
463f4c93c4569fcb8a103d4e9231c4ba6c347b5e drivers/raw: remove
octeontx2-dma driver
fdab8f2e17493192d555cd88cf28b06269174326 (origin/next-event,
origin/main) version: 21.11-rc0
4ac3f3d76e9507a93bcf48d165ffd3a1faba08bb (origin/dpdk-21.08-release)
version: 21.08.0
293e836ea5e93dc923a114272798c5abbee7bae6 doc: announce changes in
IPsec xform structure
132293cb74a341ab05eae526b58c47efe2392b6c doc: announce change in IPsec
SA structure
eed159074e0e17dbd4971a0b9808f164c02acf5c doc: announce hiding crypto
session structures

regards,
Radha Mohan
> 2.24.1
>

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH v4 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-23 12:19     ` Radha Mohan
@ 2021-08-23 12:31       ` David Marchand
  2021-08-23 12:41         ` Radha Mohan
  0 siblings, 1 reply; 17+ messages in thread
From: David Marchand @ 2021-08-23 12:31 UTC (permalink / raw)
  To: Radha Mohan
  Cc: Radha Mohan Chintakuntla, Veerasenareddy Burru, Thomas Monjalon,
	dpdk-dev, Satananda Burla, Jerin Jacob Kollanukkaran

On Mon, Aug 23, 2021 at 2:19 PM Radha Mohan <mohun106@gmail.com> wrote:
> I received this report that this patch failed to apply
> http://mails.dpdk.org/archives/test-report/2021-August/211611.html

The two patches of this series are seen as two separate series.
http://patchwork.dpdk.org/project/dpdk/list/?submitter=2007

I don't have the reason why, but this is likely because of the way
those patches were submitted to the ml.
Please double check.


For the details on the conflict: the CI tries to test each series, so
here, the second patch is tested without the first patch applied, and
it fails.
You can reproduce with:
$ git reset --hard origin/main
$ git describe
v21.08-1-gfdab8f2e17
$ git pw series apply 18350
Applying: drivers/raw: remove octeontx2-ep driver
Using index info to reconstruct a base tree...
M    MAINTAINERS
M    doc/guides/rawdevs/index.rst
M    drivers/raw/meson.build
Falling back to patching base and 3-way merge...
Removing drivers/raw/octeontx2_ep/version.map
Removing drivers/raw/octeontx2_ep/otx2_ep_vf.h
Removing drivers/raw/octeontx2_ep/otx2_ep_vf.c
Removing drivers/raw/octeontx2_ep/otx2_ep_test.c
Removing drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
Removing drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
Removing drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
Removing drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
Removing drivers/raw/octeontx2_ep/meson.build
Auto-merging drivers/raw/meson.build
CONFLICT (content): Merge conflict in drivers/raw/meson.build
Removing doc/guides/rawdevs/octeontx2_ep.rst
Auto-merging doc/guides/rawdevs/index.rst
CONFLICT (content): Merge conflict in doc/guides/rawdevs/index.rst
Auto-merging MAINTAINERS
CONFLICT (content): Merge conflict in MAINTAINERS
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0001 drivers/raw: remove octeontx2-ep driver
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


-- 
David Marchand


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH v4 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-23 12:31       ` David Marchand
@ 2021-08-23 12:41         ` Radha Mohan
  0 siblings, 0 replies; 17+ messages in thread
From: Radha Mohan @ 2021-08-23 12:41 UTC (permalink / raw)
  To: David Marchand
  Cc: Radha Mohan Chintakuntla, Veerasenareddy Burru, Thomas Monjalon,
	dpdk-dev, Satananda Burla, Jerin Jacob Kollanukkaran

On Mon, Aug 23, 2021 at 6:02 PM David Marchand
<david.marchand@redhat.com> wrote:
>
> On Mon, Aug 23, 2021 at 2:19 PM Radha Mohan <mohun106@gmail.com> wrote:
> > I received this report that this patch failed to apply
> > http://mails.dpdk.org/archives/test-report/2021-August/211611.html
>
> The two patches of this series are seen as two separate series.
> http://patchwork.dpdk.org/project/dpdk/list/?submitter=2007
>
> I don't have the reason why, but this is likely because of the way
> those patches were submitted to the ml.
> Please double check.
>
ok let me check and re-submit. thank you.

>
> For the details on the conflict: the CI tries to test each series, so
> here, the second patch is tested without the first patch applied, and
> it fails.
> You can reproduce with:
> $ git reset --hard origin/main
> $ git describe
> v21.08-1-gfdab8f2e17
> $ git pw series apply 18350
> Applying: drivers/raw: remove octeontx2-ep driver
> Using index info to reconstruct a base tree...
> M    MAINTAINERS
> M    doc/guides/rawdevs/index.rst
> M    drivers/raw/meson.build
> Falling back to patching base and 3-way merge...
> Removing drivers/raw/octeontx2_ep/version.map
> Removing drivers/raw/octeontx2_ep/otx2_ep_vf.h
> Removing drivers/raw/octeontx2_ep/otx2_ep_vf.c
> Removing drivers/raw/octeontx2_ep/otx2_ep_test.c
> Removing drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
> Removing drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
> Removing drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
> Removing drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
> Removing drivers/raw/octeontx2_ep/meson.build
> Auto-merging drivers/raw/meson.build
> CONFLICT (content): Merge conflict in drivers/raw/meson.build
> Removing doc/guides/rawdevs/octeontx2_ep.rst
> Auto-merging doc/guides/rawdevs/index.rst
> CONFLICT (content): Merge conflict in doc/guides/rawdevs/index.rst
> Auto-merging MAINTAINERS
> CONFLICT (content): Merge conflict in MAINTAINERS
> error: Failed to merge in the changes.
> hint: Use 'git am --show-current-patch' to see the failed patch
> Patch failed at 0001 drivers/raw: remove octeontx2-ep driver
> When you have resolved this problem, run "git am --continue".
> If you prefer to skip this patch, run "git am --skip" instead.
> To restore the original branch and stop patching, run "git am --abort".
>
>
> --
> David Marchand
>

^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH RESEND v4 1/2] drivers/raw: remove octeontx2-dma driver
  2021-08-19  7:57   ` [dpdk-dev] [PATCH v4 " Radha Mohan Chintakuntla
  2021-08-20  3:38     ` Radha Mohan
@ 2021-08-23 15:21     ` Radha Mohan Chintakuntla
  2021-08-23 15:21       ` [dpdk-dev] [PATCH RESEND v4 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
  2021-08-26 10:50       ` [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver Radha Mohan Chintakuntla
  1 sibling, 2 replies; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-23 15:21 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-dma driver as the dependent
common/octeontx2 will be soon be going away. Also a new DMA driver will
be coming in this place once the rte_dmadev library is in.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v3:
Fixed patch application failure due to conflict on main branch.

Changes from v2:
Fixed DPDK CI reported issues for more documentation failure.

Changes from v1:
Fixed compilation issues in documentation

 MAINTAINERS                                 |   6 -
 doc/guides/platform/octeontx2.rst           |   3 -
 doc/guides/rawdevs/index.rst                |   1 -
 doc/guides/rawdevs/octeontx2_dma.rst        | 103 -----
 drivers/raw/meson.build                     |   1 -
 drivers/raw/octeontx2_dma/meson.build       |  18 -
 drivers/raw/octeontx2_dma/otx2_dpi_msg.c    | 105 -----
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 441 --------------------
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 197 ---------
 drivers/raw/octeontx2_dma/otx2_dpi_test.c   | 218 ----------
 drivers/raw/octeontx2_dma/version.map       |   3 -
 11 files changed, 1096 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_dma.rst
 delete mode 100644 drivers/raw/octeontx2_dma/meson.build
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_msg.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_test.c
 delete mode 100644 drivers/raw/octeontx2_dma/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 266f5ac1da..9f9aa37c68 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 DMA
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_dma/
-F: doc/guides/rawdevs/octeontx2_dma.rst
-
 Marvell OCTEON TX2 EP
 M: Radha Mohan Chintakuntla <radhac@marvell.com>
 M: Veerasenareddy Burru <vburru@marvell.com>
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 8b5991f03b..3a3d28571c 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -152,9 +152,6 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
 #. **Event Device Driver**
    See :doc:`../eventdevs/octeontx2` for SSO event device driver information.
 
-#. **DMA Rawdev Driver**
-   See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
-
 #. **Crypto Device Driver**
    See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 7fbae40ea9..228d4a7743 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,5 +17,4 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_dma
     octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_dma.rst b/doc/guides/rawdevs/octeontx2_dma.rst
deleted file mode 100644
index 6887da5278..0000000000
--- a/doc/guides/rawdevs/octeontx2_dma.rst
+++ /dev/null
@@ -1,103 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-OCTEON TX2 DMA Driver
-=====================
-
-OCTEON TX2 has an internal DMA unit which can be used by applications to initiate
-DMA transaction internally, from/to host when OCTEON TX2 operates in PCIe End
-Point mode. The DMA PF function supports 8 VFs corresponding to 8 DMA queues.
-Each DMA queue was exposed as a VF function when SRIOV enabled.
-
-Features
---------
-
-This DMA PMD supports below 3 modes of memory transfers
-
-#. Internal - OCTEON TX2 DRAM to DRAM without core intervention
-
-#. Inbound  - Host DRAM to OCTEON TX2 DRAM without host/OCTEON TX2 cores involvement
-
-#. Outbound - OCTEON TX2 DRAM to Host DRAM without host/OCTEON TX2 cores involvement
-
-Prerequisites and Compilation procedure
----------------------------------------
-
-   See :doc:`../platform/octeontx2` for setup information.
-
-
-Enabling logs
--------------
-
-For enabling logs, use the following EAL parameter:
-
-.. code-block:: console
-
-   ./your_dma_application <EAL args> --log-level=pmd.raw.octeontx2.dpi,<level>
-
-Using ``pmd.raw.octeontx2.dpi`` as log matching criteria, all Event PMD logs
-can be enabled which are lower than logging ``level``.
-
-Initialization
---------------
-
-The number of DMA VFs (queues) enabled can be controlled by setting sysfs
-entry, `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-dpi/0000\:05\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
--------------
-
-The OCTEON TX2 DPI DMA HW devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring DMA rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to submit DMA
-commands to HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct dpi_rawdev_conf_s conf = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &conf};
-
-   conf.chunk_pool = (void *)rte_mempool_create_empty(...);
-   rte_mempool_set_ops_byname(conf.chunk_pool, rte_mbuf_platform_mempool_ops(), NULL);
-   rte_mempool_populate_default(conf.chunk_pool);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info, sizeof(conf));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using OCTEON TX2 DMA rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, dma devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("DPI:x")`` from the application
-  where x is the VF device's bus id specified in "bus:device.func" format. Use this
-  index for further rawdev function calls.
-
-* This PMD supports driver self test, to test DMA internal mode from test
-  application one can directly calls
-  ``rte_rawdev_selftest(rte_rawdev_get_dev_id("DPI:x"))``
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index b51536f8a7..f25d5f322c 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_dma',
         'octeontx2_ep',
         'skeleton',
 ]
diff --git a/drivers/raw/octeontx2_dma/meson.build b/drivers/raw/octeontx2_dma/meson.build
deleted file mode 100644
index e744fccaae..0000000000
--- a/drivers/raw/octeontx2_dma/meson.build
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files('otx2_dpi_rawdev.c', 'otx2_dpi_msg.c', 'otx2_dpi_test.c')
-
-extra_flags = []
-# This integrated controller runs only on a arm64 machine, remove 32bit warnings
-if not dpdk_conf.get('RTE_ARCH_64')
-    extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
-endif
-
-foreach flag: extra_flags
-    if cc.has_argument(flag)
-        cflags += flag
-    endif
-endforeach
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c b/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
deleted file mode 100644
index 655de216ab..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_MSG_H_
-#define _DPI_MSG_H_
-
-#include <dirent.h>
-#include <fcntl.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "otx2_dpi_rawdev.h"
-
-/* DPI PF DBDF information macro's */
-#define DPI_PF_DBDF_DOMAIN      0
-#define DPI_PF_DBDF_BUS         5
-#define DPI_PF_DBDF_DEVICE      0
-#define DPI_PF_DBDF_FUNCTION    0
-
-#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
-
-union dpi_mbox_message_u {
-	uint64_t u[2];
-	struct dpi_mbox_message_s {
-		/* VF ID to configure */
-		uint64_t vfid           :4;
-		/* Command code */
-		uint64_t cmd            :4;
-		/* Command buffer size in 8-byte words */
-		uint64_t csize          :14;
-		/* aura of the command buffer */
-		uint64_t aura           :20;
-		/* SSO PF function */
-		uint64_t sso_pf_func    :16;
-		/* NPA PF function */
-		uint64_t npa_pf_func    :16;
-	} s;
-};
-
-static inline int
-send_msg_to_pf(struct rte_pci_addr *pci, const char *value, int size)
-{
-	char buff[255] = { 0 };
-	int res, fd;
-
-	res = snprintf(buff, sizeof(buff), "%s/" PCI_PRI_FMT "/%s",
-		       rte_pci_get_sysfs_path(), pci->domain,
-		       pci->bus, DPI_PF_DBDF_DEVICE & 0x7,
-		       DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
-	if ((res < 0) || ((size_t)res > sizeof(buff)))
-		return -ERANGE;
-
-	fd = open(buff, O_WRONLY);
-	if (fd < 0)
-		return -EACCES;
-	res = write(fd, value, size);
-	close(fd);
-	if (res < 0)
-		return -EACCES;
-
-	return 0;
-}
-
-int
-otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_OPEN;
-	mbox_msg.s.csize = size;
-	mbox_msg.s.aura = gaura;
-	mbox_msg.s.sso_pf_func = otx2_sso_pf_func_get();
-	mbox_msg.s.npa_pf_func = otx2_npa_pf_func_get();
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-int
-otx2_dpi_queue_close(struct dpi_vf_s *dpivf)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-#endif /* _DPI_MSG_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
deleted file mode 100644
index 8c01f25ec7..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include <otx2_common.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static const struct rte_pci_id pci_dma_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_DPI_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* Enable/Disable DMA queue */
-static inline int
-dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb)
-{
-	if (enb)
-		otx2_write64(0x1, dpivf->vf_bar0 + DPI_VDMA_EN);
-	else
-		otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Free DMA Queue instruction buffers, and send close notification to PF */
-static inline int
-dma_queue_finish(struct dpi_vf_s *dpivf)
-{
-	uint32_t timeout = 0, sleep = 1;
-	uint64_t reg = 0ULL;
-
-	/* Wait for SADDR to become idle */
-	reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	while (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) {
-		rte_delay_ms(sleep);
-		timeout++;
-		if (timeout >= DPI_QFINISH_TIMEOUT) {
-			otx2_dpi_dbg("Timeout!!! Closing Forcibly");
-			break;
-		}
-		reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	}
-
-	if (otx2_dpi_queue_close(dpivf) < 0)
-		return -EACCES;
-
-	rte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr);
-	dpivf->vf_bar0 = (uintptr_t)NULL;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Write an arbitrary number of command words to a command queue */
-static __rte_always_inline enum dpi_dma_queue_result_e
-dma_queue_write(struct dpi_vf_s *dpi, uint16_t cmd_count, uint64_t *cmds)
-{
-	if ((cmd_count < 1) || (cmd_count > 64))
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	if (cmds == NULL)
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	/* Room available in the current buffer for the command */
-	if (dpi->index + cmd_count < dpi->pool_size_m1) {
-		uint64_t *ptr = dpi->base_ptr;
-
-		ptr += dpi->index;
-		dpi->index += cmd_count;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-	} else {
-		void *new_buffer;
-		uint64_t *ptr;
-		int count;
-
-		/* Allocate new command buffer, return if failed */
-		if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-		    new_buffer == NULL) {
-			return DPI_DMA_QUEUE_NO_MEMORY;
-		}
-		ptr = dpi->base_ptr;
-		/* Figure out how many command words will fit in this buffer.
-		 * One location will be needed for the next buffer pointer.
-		 **/
-		count = dpi->pool_size_m1 - dpi->index;
-		ptr += dpi->index;
-		cmd_count -= count;
-		while (count--)
-			*ptr++ = *cmds++;
-		/* Chunk next ptr is 2DWORDs, second DWORD is reserved. */
-		*ptr++ = (uint64_t)new_buffer;
-		*ptr   = 0;
-		/* The current buffer is full and has a link to the next buffer.
-		 * Time to write the rest of the commands into the new buffer.
-		 **/
-		dpi->base_ptr = new_buffer;
-		dpi->index = cmd_count;
-		ptr = new_buffer;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-		/* queue index may greater than pool size */
-		if (dpi->index >= dpi->pool_size_m1) {
-			if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-			    new_buffer == NULL) {
-				return DPI_DMA_QUEUE_NO_MEMORY;
-			}
-			/* Write next buffer address */
-			*ptr = (uint64_t)new_buffer;
-			dpi->base_ptr = new_buffer;
-			dpi->index = 0;
-		}
-	}
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Submit a DMA command to the DMA queues. */
-static __rte_always_inline int
-dma_queue_submit(struct rte_rawdev *dev, uint16_t cmd_count, uint64_t *cmds)
-{
-	struct dpi_vf_s *dpivf = dev->dev_private;
-	enum dpi_dma_queue_result_e result;
-
-	result = dma_queue_write(dpivf, cmd_count, cmds);
-	rte_wmb();
-	if (likely(result == DPI_DMA_QUEUE_SUCCESS))
-		otx2_write64((uint64_t)cmd_count,
-			     dpivf->vf_bar0 + DPI_VDMA_DBELL);
-
-	return result;
-}
-
-/* Enqueue buffers to DMA queue
- * returns number of buffers enqueued successfully
- */
-static int
-otx2_dpi_rawdev_enqueue_bufs(struct rte_rawdev *dev,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	struct dpi_dma_buf_ptr_s *cmd;
-	uint32_t c = 0;
-
-	for (c = 0; c < count; c++) {
-		uint64_t dpi_cmd[DPI_DMA_CMD_SIZE] = {0};
-		union dpi_dma_instr_hdr_u *hdr;
-		uint16_t index = 0, i;
-
-		hdr = (union dpi_dma_instr_hdr_u *)&dpi_cmd[0];
-		cmd = (struct dpi_dma_buf_ptr_s *)buffers[c]->buf_addr;
-
-		hdr->s.xtype = ctx->xtype & DPI_XTYPE_MASK;
-		hdr->s.pt = ctx->pt & DPI_HDR_PT_MASK;
-		/* Request initiated with byte write completion, but completion
-		 * pointer not provided
-		 */
-		if ((hdr->s.pt == DPI_HDR_PT_ZBW_CA ||
-		     hdr->s.pt == DPI_HDR_PT_ZBW_NC) && cmd->comp_ptr == NULL)
-			return c;
-
-		cmd->comp_ptr->cdata = DPI_REQ_CDATA;
-		hdr->s.ptr = (uint64_t)cmd->comp_ptr;
-		hdr->s.deallocv = ctx->deallocv;
-		hdr->s.tt = ctx->tt & DPI_W0_TT_MASK;
-		hdr->s.grp = ctx->grp & DPI_W0_GRP_MASK;
-
-		/* If caller provides completion ring details, then only queue
-		 * completion address for later polling.
-		 */
-		if (ctx->c_ring) {
-			ctx->c_ring->compl_data[ctx->c_ring->tail] =
-								 cmd->comp_ptr;
-			STRM_INC(ctx->c_ring);
-		}
-
-		if (hdr->s.deallocv)
-			hdr->s.pvfe = 1;
-
-		if (hdr->s.pt == DPI_HDR_PT_WQP)
-			hdr->s.ptr = hdr->s.ptr | DPI_HDR_PT_WQP_STATUSNC;
-
-		index += 4;
-		hdr->s.fport = 0;
-		hdr->s.lport = 0;
-		if (ctx->xtype !=  DPI_XTYPE_INTERNAL_ONLY)
-			hdr->s.lport = ctx->pem_id;
-
-		/* For inbound case, src pointers are last pointers.
-		 * For all other cases, src pointers are first pointers.
-		 */
-		if (ctx->xtype ==  DPI_XTYPE_INBOUND) {
-			hdr->s.nfst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-		} else {
-			hdr->s.nfst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-		}
-		if (dma_queue_submit(dev, index, dpi_cmd))
-			return c;
-	}
-	return c;
-}
-
-/* Check for command completion, returns number of commands completed */
-static int
-otx2_dpi_rawdev_dequeue_bufs(struct rte_rawdev *dev __rte_unused,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	unsigned int i = 0, headp;
-
-	/* No completion ring to poll */
-	if (ctx->c_ring == NULL)
-		return 0;
-
-	headp = ctx->c_ring->head;
-	for (i = 0; i < count && (headp != ctx->c_ring->tail); i++) {
-		struct dpi_dma_req_compl_s *comp_ptr =
-					 ctx->c_ring->compl_data[headp];
-
-		if (comp_ptr->cdata)
-			break;
-
-		/* Request Completed */
-		buffers[i] = (void *)comp_ptr;
-		headp = (headp + 1) % ctx->c_ring->max_cnt;
-	}
-	ctx->c_ring->head = headp;
-
-	return i;
-}
-
-static int
-otx2_dpi_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_START;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static void
-otx2_dpi_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_STOP;
-}
-
-static int
-otx2_dpi_rawdev_close(struct rte_rawdev *dev)
-{
-	dma_engine_enb_dis(dev->dev_private, false);
-	dma_queue_finish(dev->dev_private);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_reset(struct rte_rawdev *dev)
-{
-	return dev ? DPI_QUEUE_STOP : DPI_QUEUE_START;
-}
-
-static int
-otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct dpi_rawdev_conf_s *conf = config;
-	struct dpi_vf_s *dpivf = NULL;
-	void *buf = NULL;
-	uintptr_t pool;
-	uint32_t gaura;
-
-	if (conf == NULL || config_size != sizeof(*conf)) {
-		otx2_dpi_dbg("NULL or invalid configuration");
-		return -EINVAL;
-	}
-	dpivf = (struct dpi_vf_s *)dev->dev_private;
-	dpivf->chunk_pool = conf->chunk_pool;
-	if (rte_mempool_get(conf->chunk_pool, &buf) || (buf == NULL)) {
-		otx2_err("Unable allocate buffer");
-		return -ENODEV;
-	}
-	dpivf->base_ptr = buf;
-	otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-	dpivf->pool_size_m1 = (DPI_CHUNK_SIZE >> 3) - 2;
-	pool = (uintptr_t)((struct rte_mempool *)conf->chunk_pool)->pool_id;
-	gaura = npa_lf_aura_handle_to_aura(pool);
-	otx2_write64(0, dpivf->vf_bar0 + DPI_VDMA_REQQ_CTL);
-	otx2_write64(((uint64_t)buf >> 7) << 7,
-		     dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	if (otx2_dpi_queue_open(dpivf, DPI_CHUNK_SIZE, gaura) < 0) {
-		otx2_err("Unable to open DPI VF %d", dpivf->vf_id);
-		rte_mempool_put(conf->chunk_pool, buf);
-		return -EACCES;
-	}
-	dma_engine_enb_dis(dpivf, true);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static const struct rte_rawdev_ops dpi_rawdev_ops = {
-	.dev_configure = otx2_dpi_rawdev_configure,
-	.dev_start = otx2_dpi_rawdev_start,
-	.dev_stop = otx2_dpi_rawdev_stop,
-	.dev_close = otx2_dpi_rawdev_close,
-	.dev_reset = otx2_dpi_rawdev_reset,
-	.enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs,
-	.dequeue_bufs = otx2_dpi_rawdev_dequeue_bufs,
-	.dev_selftest = test_otx2_dma_rawdev,
-};
-
-static int
-otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct dpi_vf_s *dpivf = NULL;
-	struct rte_rawdev *rawdev;
-	uint16_t vf_id;
-
-	/* For secondary processes, the primary has done all the work */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return DPI_DMA_QUEUE_SUCCESS;
-
-	if (pci_dev->mem_resource[0].addr == NULL) {
-		otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr,
-			     pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate device structure */
-	rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct dpi_vf_s),
-					 rte_socket_id());
-	if (rawdev == NULL) {
-		otx2_err("Rawdev allocation failed");
-		return -EINVAL;
-	}
-
-	rawdev->dev_ops = &dpi_rawdev_ops;
-	rawdev->device = &pci_dev->device;
-	rawdev->driver_name = pci_dev->driver->driver.name;
-
-	dpivf = rawdev->dev_private;
-	if (dpivf->state != DPI_QUEUE_STOP) {
-		otx2_dpi_dbg("Device already started!!!");
-		return -ENODEV;
-	}
-
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-	vf_id -= 1;
-	dpivf->dev = pci_dev;
-	dpivf->state = DPI_QUEUE_START;
-	dpivf->vf_id = vf_id;
-	dpivf->vf_bar0 = (uintptr_t)pci_dev->mem_resource[0].addr;
-	dpivf->vf_bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct dpi_vf_s *dpivf;
-
-	if (pci_dev == NULL) {
-		otx2_dpi_dbg("Invalid pci_dev of the device!");
-		return -EINVAL;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_dpi_dbg("Invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	dpivf = (struct dpi_vf_s *)rawdev->dev_private;
-	dma_engine_enb_dis(dpivf, false);
-	dma_queue_finish(dpivf);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_dpi_rawdev_pmd = {
-	.id_table  = pci_dma_map,
-	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
-	.probe     = otx2_dpi_rawdev_probe,
-	.remove    = otx2_dpi_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(dpi_rawdev_pci_driver, rte_dpi_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(dpi_rawdev_pci_driver, pci_dma_map);
-RTE_PMD_REGISTER_KMOD_DEP(dpi_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
deleted file mode 100644
index 2bc9e3da3c..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_RAWDEV_H_
-#define _DPI_RAWDEV_H_
-
-#include "otx2_common.h"
-#include "otx2_mempool.h"
-
-#define DPI_QUEUE_OPEN	0x1
-#define DPI_QUEUE_CLOSE	0x2
-
-/* DPI VF register offsets from VF_BAR0 */
-#define DPI_VDMA_EN             (0x0)
-#define DPI_VDMA_REQQ_CTL       (0x8)
-#define DPI_VDMA_DBELL          (0x10)
-#define DPI_VDMA_SADDR          (0x18)
-#define DPI_VDMA_COUNTS         (0x20)
-#define DPI_VDMA_NADDR          (0x28)
-#define DPI_VDMA_IWBUSY         (0x30)
-#define DPI_VDMA_CNT            (0x38)
-#define DPI_VF_INT              (0x100)
-#define DPI_VF_INT_W1S          (0x108)
-#define DPI_VF_INT_ENA_W1C      (0x110)
-#define DPI_VF_INT_ENA_W1S      (0x118)
-
-#define DPI_MAX_VFS             8
-#define DPI_DMA_CMD_SIZE        64
-#define DPI_CHUNK_SIZE		1024
-#define DPI_QUEUE_STOP		0x0
-#define DPI_QUEUE_START		0x1
-
-#define DPI_VDMA_SADDR_REQ_IDLE	63
-#define DPI_MAX_POINTER		15
-#define STRM_INC(s)	((s)->tail = ((s)->tail + 1) % (s)->max_cnt)
-#define DPI_QFINISH_TIMEOUT	(10 * 1000)
-
-/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
-#define DPI_XTYPE_OUTBOUND      (0)
-#define DPI_XTYPE_INBOUND       (1)
-#define DPI_XTYPE_INTERNAL_ONLY (2)
-#define DPI_XTYPE_EXTERNAL_ONLY (3)
-#define DPI_XTYPE_MASK		0x3
-#define DPI_HDR_PT_ZBW_CA	0x0
-#define DPI_HDR_PT_ZBW_NC	0x1
-#define DPI_HDR_PT_WQP		0x2
-#define DPI_HDR_PT_WQP_NOSTATUS	0x0
-#define DPI_HDR_PT_WQP_STATUSCA	0x1
-#define DPI_HDR_PT_WQP_STATUSNC	0x3
-#define DPI_HDR_PT_CNT		0x3
-#define DPI_HDR_PT_MASK		0x3
-#define DPI_W0_TT_MASK		0x3
-#define DPI_W0_GRP_MASK		0x3FF
-/* Set Completion data to 0xFF when request submitted,
- * upon successful request completion engine reset to completion status
- */
-#define DPI_REQ_CDATA		0xFF
-
-struct dpi_vf_s {
-	struct rte_pci_device *dev;
-	uint8_t state;
-	uint16_t vf_id;
-	uint8_t domain;
-	uintptr_t vf_bar0;
-	uintptr_t vf_bar2;
-
-	uint16_t pool_size_m1;
-	uint16_t index;
-	uint64_t *base_ptr;
-	void *chunk_pool;
-	struct otx2_mbox *mbox;
-};
-
-struct dpi_rawdev_conf_s {
-	void *chunk_pool;
-};
-
-enum dpi_dma_queue_result_e {
-	DPI_DMA_QUEUE_SUCCESS = 0,
-	DPI_DMA_QUEUE_NO_MEMORY = -1,
-	DPI_DMA_QUEUE_INVALID_PARAM = -2,
-};
-
-struct dpi_dma_req_compl_s {
-	uint64_t cdata;
-	void (*compl_cb)(void *dev, void *arg);
-	void *cb_data;
-};
-
-union dpi_dma_ptr_u {
-	uint64_t u[2];
-	struct dpi_dma_s {
-		uint64_t length:16;
-		uint64_t reserved:44;
-		uint64_t bed:1; /* Big-Endian */
-		uint64_t alloc_l2:1;
-		uint64_t full_write:1;
-		uint64_t invert:1;
-		uint64_t ptr;
-	} s;
-};
-
-struct dpi_dma_buf_ptr_s {
-	union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */
-	union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */
-	uint8_t rptr_cnt;
-	uint8_t wptr_cnt;
-	struct dpi_dma_req_compl_s *comp_ptr;
-};
-
-struct dpi_cring_data_s {
-	struct dpi_dma_req_compl_s **compl_data;
-	uint16_t max_cnt;
-	uint16_t head;
-	uint16_t tail;
-};
-
-struct dpi_dma_queue_ctx_s {
-	uint16_t xtype:2;
-
-	/* Completion pointer type */
-	uint16_t pt:2;
-
-	/* Completion updated using WQE */
-	uint16_t tt:2;
-	uint16_t grp:10;
-	uint32_t tag;
-
-	/* Valid only for Outbound only mode */
-	uint16_t aura:12;
-	uint16_t csel:1;
-	uint16_t ca:1;
-	uint16_t fi:1;
-	uint16_t ii:1;
-	uint16_t fl:1;
-
-	uint16_t pvfe:1;
-	uint16_t dealloce:1;
-	uint16_t req_type:2;
-	uint16_t use_lock:1;
-	uint16_t deallocv;
-	uint16_t  pem_id;
-
-	struct dpi_cring_data_s *c_ring;
-};
-
-/* DPI DMA Instruction Header Format */
-union dpi_dma_instr_hdr_u {
-	uint64_t u[4];
-
-	struct dpi_dma_instr_hdr_s_s {
-		uint64_t tag:32;
-		uint64_t tt:2;
-		uint64_t grp:10;
-		uint64_t reserved_44_47:4;
-		uint64_t nfst:4;
-		uint64_t reserved_52_53:2;
-		uint64_t nlst:4;
-		uint64_t reserved_58_63:6;
-		/* Word 0 - End */
-
-		uint64_t aura:12;
-		uint64_t reserved_76_79:4;
-		uint64_t deallocv:16;
-		uint64_t dealloce:1;
-		uint64_t pvfe:1;
-		uint64_t reserved_98_99:2;
-		uint64_t pt:2;
-		uint64_t reserved_102_103:2;
-		uint64_t fl:1;
-		uint64_t ii:1;
-		uint64_t fi:1;
-		uint64_t ca:1;
-		uint64_t csel:1;
-		uint64_t reserved_109_111:3;
-		uint64_t xtype:2;
-		uint64_t reserved_114_119:6;
-		uint64_t fport:2;
-		uint64_t reserved_122_123:2;
-		uint64_t lport:2;
-		uint64_t reserved_126_127:2;
-		/* Word 1 - End */
-
-		uint64_t ptr:64;
-		/* Word 2 - End */
-
-		uint64_t reserved_192_255:64;
-		/* Word 3 - End */
-	} s;
-};
-
-int otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura);
-int otx2_dpi_queue_close(struct dpi_vf_s *dpivf);
-int test_otx2_dma_rawdev(uint16_t val);
-
-#endif /* _DPI_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_test.c b/drivers/raw/octeontx2_dma/otx2_dpi_test.c
deleted file mode 100644
index cec6ca91b0..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_test.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_debug.h>
-#include <rte_eal.h>
-#include <rte_log.h>
-#include <rte_malloc.h>
-#include <rte_mbuf.h>
-#include <rte_mbuf_pool_ops.h>
-#include <rte_memcpy.h>
-#include <rte_memory.h>
-#include <rte_mempool.h>
-#include <rte_per_lcore.h>
-#include <rte_rawdev.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static struct dpi_cring_data_s cring;
-
-static uint8_t
-buffer_fill(uint8_t *addr, int len, uint8_t val)
-{
-	int j = 0;
-
-	memset(addr, 0, len);
-	for (j = 0; j < len; j++)
-		*(addr + j) = val++;
-
-	return val;
-}
-
-static int
-validate_buffer(uint8_t *saddr, uint8_t *daddr, int len)
-{
-	int j = 0, ret = 0;
-
-	for (j = 0; j < len; j++) {
-		if (*(saddr + j) != *(daddr + j)) {
-			otx2_dpi_dbg("FAIL: Data Integrity failed");
-			otx2_dpi_dbg("index: %d, Expected: 0x%x, Actual: 0x%x",
-				     j, *(saddr + j), *(daddr + j));
-			ret = -1;
-			break;
-		}
-	}
-
-	return ret;
-}
-
-static inline int
-dma_test_internal(int dma_port, int buf_size)
-{
-	struct dpi_dma_req_compl_s *comp_data;
-	struct dpi_dma_queue_ctx_s ctx = {0};
-	struct rte_rawdev_buf buf = {0};
-	struct rte_rawdev_buf *d_buf[1];
-	struct rte_rawdev_buf *bufp[1];
-	struct dpi_dma_buf_ptr_s cmd;
-	union dpi_dma_ptr_u rptr = { {0} };
-	union dpi_dma_ptr_u wptr = { {0} };
-	uint8_t *fptr, *lptr;
-	int ret;
-
-	fptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	lptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	comp_data = rte_malloc("dummy", buf_size, 128);
-	if (fptr == NULL || lptr == NULL || comp_data == NULL) {
-		otx2_dpi_dbg("Unable to allocate internal memory");
-		return -ENOMEM;
-	}
-
-	buffer_fill(fptr, buf_size, 0);
-	memset(&cmd, 0, sizeof(struct dpi_dma_buf_ptr_s));
-	memset(lptr, 0, buf_size);
-	memset(comp_data, 0, buf_size);
-	rptr.s.ptr = (uint64_t)fptr;
-	rptr.s.length = buf_size;
-	wptr.s.ptr = (uint64_t)lptr;
-	wptr.s.length = buf_size;
-	cmd.rptr[0] = &rptr;
-	cmd.wptr[0] = &wptr;
-	cmd.rptr_cnt = 1;
-	cmd.wptr_cnt = 1;
-	cmd.comp_ptr = comp_data;
-	buf.buf_addr = (void *)&cmd;
-	bufp[0] = &buf;
-
-	ctx.xtype = DPI_XTYPE_INTERNAL_ONLY;
-	ctx.pt = 0;
-	ctx.c_ring = &cring;
-
-	ret = rte_rawdev_enqueue_buffers(dma_port,
-					 (struct rte_rawdev_buf **)bufp, 1,
-					 &ctx);
-	if (ret < 0) {
-		otx2_dpi_dbg("Enqueue request failed");
-		return 0;
-	}
-
-	/* Wait and dequeue completion */
-	do {
-		sleep(1);
-		ret = rte_rawdev_dequeue_buffers(dma_port, &d_buf[0], 1, &ctx);
-		if (ret)
-			break;
-
-		otx2_dpi_dbg("Dequeue request not completed");
-	} while (1);
-
-	if (validate_buffer(fptr, lptr, buf_size)) {
-		otx2_dpi_dbg("DMA transfer failed\n");
-		return -EAGAIN;
-	}
-	otx2_dpi_dbg("Internal Only DMA transfer successfully completed");
-
-	if (lptr)
-		rte_free(lptr);
-	if (fptr)
-		rte_free(fptr);
-	if (comp_data)
-		rte_free(comp_data);
-
-	return 0;
-}
-
-static void *
-dpi_create_mempool(void)
-{
-	void *chunk_pool = NULL;
-	char pool_name[25];
-	int ret;
-
-	snprintf(pool_name, sizeof(pool_name), "dpi_chunk_pool");
-
-	chunk_pool = (void *)rte_mempool_create_empty(pool_name, 1024, 1024,
-						      0, 0, rte_socket_id(), 0);
-	if (chunk_pool == NULL) {
-		otx2_dpi_dbg("Unable to create memory pool.");
-		return NULL;
-	}
-
-	ret = rte_mempool_set_ops_byname(chunk_pool,
-					 rte_mbuf_platform_mempool_ops(), NULL);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to set pool ops");
-		rte_mempool_free(chunk_pool);
-		return NULL;
-	}
-
-	ret = rte_mempool_populate_default(chunk_pool);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to populate pool");
-		return NULL;
-	}
-
-	return chunk_pool;
-}
-
-int
-test_otx2_dma_rawdev(uint16_t val)
-{
-	struct rte_rawdev_info rdev_info = {0};
-	struct dpi_rawdev_conf_s conf = {0};
-	int ret, i, size = 1024;
-	int nb_ports;
-
-	RTE_SET_USED(val);
-	nb_ports = rte_rawdev_count();
-	if (nb_ports == 0) {
-		otx2_dpi_dbg("No Rawdev ports - bye");
-		return -ENODEV;
-	}
-
-	i = rte_rawdev_get_dev_id("DPI:5:00.1");
-	/* Configure rawdev ports */
-	conf.chunk_pool = dpi_create_mempool();
-	rdev_info.dev_private = &conf;
-	ret = rte_rawdev_configure(i, (rte_rawdev_obj_t)&rdev_info,
-			sizeof(conf));
-	if (ret) {
-		otx2_dpi_dbg("Unable to configure DPIVF %d", i);
-		return -ENODEV;
-	}
-	otx2_dpi_dbg("rawdev %d configured successfully", i);
-
-	/* Each stream allocate its own completion ring data, store it in
-	 * application context. Each stream needs to use same application
-	 * context for enqueue/dequeue.
-	 */
-	cring.compl_data = rte_malloc("dummy", sizeof(void *) * 1024, 128);
-	if (!cring.compl_data) {
-		otx2_dpi_dbg("Completion allocation failed");
-		return -ENOMEM;
-	}
-
-	cring.max_cnt = 1024;
-	cring.head = 0;
-	cring.tail = 0;
-
-	ret = dma_test_internal(i, size);
-	if (ret)
-		otx2_dpi_dbg("DMA transfer failed for queue %d", i);
-
-	if (rte_rawdev_close(i))
-		otx2_dpi_dbg("Dev close failed for port %d", i);
-
-	if (conf.chunk_pool)
-		rte_mempool_free(conf.chunk_pool);
-
-	return ret;
-}
diff --git a/drivers/raw/octeontx2_dma/version.map b/drivers/raw/octeontx2_dma/version.map
deleted file mode 100644
index c2e0723b4c..0000000000
--- a/drivers/raw/octeontx2_dma/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_22 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH RESEND v4 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-23 15:21     ` [dpdk-dev] [PATCH RESEND " Radha Mohan Chintakuntla
@ 2021-08-23 15:21       ` Radha Mohan Chintakuntla
  2021-08-23 16:27         ` Radha Mohan
  2021-08-26 10:50       ` [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver Radha Mohan Chintakuntla
  1 sibling, 1 reply; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-23 15:21 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-ep driver as the dependent
common/octeontx2 will soon be going away. Moreover this driver is no
longer required as the net/octeontx_ep driver is sufficient.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v3:
Fixed patch application failure due to conflict on main branch.


Changes from v2:
Fixed DPDK CI reported issues for more documentation failure.

Changes from v1:
Fixed compilation issues in documentation

 MAINTAINERS                               |   6 -
 doc/guides/rawdevs/index.rst              |   1 -
 doc/guides/rawdevs/octeontx2_ep.rst       |  82 ---
 drivers/raw/meson.build                   |   1 -
 drivers/raw/octeontx2_ep/meson.build      |  11 -
 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------
 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h |  52 --
 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------
 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------
 drivers/raw/octeontx2_ep/otx2_ep_test.c   | 172 -----
 drivers/raw/octeontx2_ep/otx2_ep_vf.c     | 475 ------------
 drivers/raw/octeontx2_ep/otx2_ep_vf.h     |  10 -
 drivers/raw/octeontx2_ep/version.map      |   3 -
 13 files changed, 2520 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_ep.rst
 delete mode 100644 drivers/raw/octeontx2_ep/meson.build
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_test.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.h
 delete mode 100644 drivers/raw/octeontx2_ep/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 9f9aa37c68..1d6a408f49 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 EP
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_ep/
-F: doc/guides/rawdevs/octeontx2_ep.rst
-
 NTB
 M: Xiaoyun Li <xiaoyun.li@intel.com>
 M: Jingjing Wu <jingjing.wu@intel.com>
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 228d4a7743..b6cf917443 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,4 +17,3 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_ep.rst b/doc/guides/rawdevs/octeontx2_ep.rst
deleted file mode 100644
index fb9d346ccf..0000000000
--- a/doc/guides/rawdevs/octeontx2_ep.rst
+++ /dev/null
@@ -1,82 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-Marvell OCTEON TX2 End Point Rawdev Driver
-==========================================
-
-OCTEON TX2 has an internal SDP unit which provides End Point mode of operation
-by exposing its IOQs to Host, IOQs are used for packet I/O between Host and
-OCTEON TX2. Each OCTEON TX2 SDP PF supports a max of 128 VFs and Each VF is
-associated with a set of IOQ pairs.
-
-Features
---------
-
-This OCTEON TX2 End Point mode PMD supports
-
-#. Packet Input - Host to OCTEON TX2 with direct data instruction mode.
-
-#. Packet Output - OCTEON TX2 to Host with info pointer mode.
-
-
-Initialization
---------------
-
-The number of SDP VFs enabled, can be controlled by setting sysfs
-entry `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-ep/0000\:04\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
-------------
-
-The OCTEON TX2 SDP End Point VF devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring SDP EP rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to send/receive
-packets to/from the HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct sdp_rawdev_info config = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &config};
-   config.enqdeq_mpool = (void *)rte_mempool_create(...);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info,
-                        sizeof(config));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using SDP VF EP rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, SDP VF devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("SDPEP:x")`` from the test application
-  where x is the VF device's bus id specified in "bus:device.func"(BDF)
-  format. Use this index for further rawdev function calls.
-
-* The driver's selftest rawdev API can be used to verify the SDP EP mode
-  functional tests which can send/receive the raw data packets to/from the
-  EP device.
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index f25d5f322c..87694a758e 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_ep',
         'skeleton',
 ]
 std_deps = ['rawdev']
diff --git a/drivers/raw/octeontx2_ep/meson.build b/drivers/raw/octeontx2_ep/meson.build
deleted file mode 100644
index 8d7c69aa3c..0000000000
--- a/drivers/raw/octeontx2_ep/meson.build
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files(
-        'otx2_ep_enqdeq.c',
-        'otx2_ep_rawdev.c',
-        'otx2_ep_test.c',
-        'otx2_ep_vf.c',
-)
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
deleted file mode 100644
index d04e957d82..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-#include <dirent.h>
-#include <fcntl.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_enqdeq.h"
-
-static void
-sdp_dmazone_free(const struct rte_memzone *mz)
-{
-	const struct rte_memzone *mz_tmp;
-	int ret = 0;
-
-	if (mz == NULL) {
-		otx2_err("Memzone %s : NULL", mz->name);
-		return;
-	}
-
-	mz_tmp = rte_memzone_lookup(mz->name);
-	if (mz_tmp == NULL) {
-		otx2_err("Memzone %s Not Found", mz->name);
-		return;
-	}
-
-	ret = rte_memzone_free(mz);
-	if (ret)
-		otx2_err("Memzone free failed : ret = %d", ret);
-
-}
-
-/* Free IQ resources */
-int
-sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq;
-
-	iq = sdpvf->instr_queue[iq_no];
-	if (iq == NULL) {
-		otx2_err("Invalid IQ[%d]\n", iq_no);
-		return -ENOMEM;
-	}
-
-	rte_free(iq->req_list);
-	iq->req_list = NULL;
-
-	if (iq->iq_mz) {
-		sdp_dmazone_free(iq->iq_mz);
-		iq->iq_mz = NULL;
-	}
-
-	rte_free(sdpvf->instr_queue[iq_no]);
-	sdpvf->instr_queue[iq_no] = NULL;
-
-	sdpvf->num_iqs--;
-
-	otx2_info("IQ[%d] is deleted", iq_no);
-
-	return 0;
-}
-
-/* IQ initialization */
-static int
-sdp_init_instr_queue(struct sdp_device *sdpvf, int iq_no)
-{
-	const struct sdp_config *conf;
-	struct sdp_instr_queue *iq;
-	uint32_t q_size;
-
-	conf = sdpvf->conf;
-	iq = sdpvf->instr_queue[iq_no];
-	q_size = conf->iq.instr_type * conf->num_iqdef_descs;
-
-	/* IQ memory creation for Instruction submission to OCTEON TX2 */
-	iq->iq_mz = rte_memzone_reserve_aligned("iqmz",
-					q_size,
-					rte_socket_id(),
-					RTE_MEMZONE_IOVA_CONTIG,
-					RTE_CACHE_LINE_SIZE);
-	if (iq->iq_mz == NULL) {
-		otx2_err("IQ[%d] memzone alloc failed", iq_no);
-		goto iq_init_fail;
-	}
-
-	iq->base_addr_dma = iq->iq_mz->iova;
-	iq->base_addr = (uint8_t *)iq->iq_mz->addr;
-
-	if (conf->num_iqdef_descs & (conf->num_iqdef_descs - 1)) {
-		otx2_err("IQ[%d] descs not in power of 2", iq_no);
-		goto iq_init_fail;
-	}
-
-	iq->nb_desc = conf->num_iqdef_descs;
-
-	/* Create a IQ request list to hold requests that have been
-	 * posted to OCTEON TX2. This list will be used for freeing the IQ
-	 * data buffer(s) later once the OCTEON TX2 fetched the requests.
-	 */
-	iq->req_list = rte_zmalloc_socket("request_list",
-			(iq->nb_desc * SDP_IQREQ_LIST_SIZE),
-			RTE_CACHE_LINE_SIZE,
-			rte_socket_id());
-	if (iq->req_list == NULL) {
-		otx2_err("IQ[%d] req_list alloc failed", iq_no);
-		goto iq_init_fail;
-	}
-
-	otx2_info("IQ[%d]: base: %p basedma: %lx count: %d",
-		     iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,
-		     iq->nb_desc);
-
-	iq->sdp_dev = sdpvf;
-	iq->q_no = iq_no;
-	iq->fill_cnt = 0;
-	iq->host_write_index = 0;
-	iq->otx_read_index = 0;
-	iq->flush_index = 0;
-
-	/* Initialize the spinlock for this instruction queue */
-	rte_spinlock_init(&iq->lock);
-	rte_spinlock_init(&iq->post_lock);
-
-	rte_atomic64_clear(&iq->iq_flush_running);
-
-	sdpvf->io_qmask.iq |= (1ull << iq_no);
-
-	/* Set 32B/64B mode for each input queue */
-	if (conf->iq.instr_type == 64)
-		sdpvf->io_qmask.iq64B |= (1ull << iq_no);
-
-	iq->iqcmd_64B = (conf->iq.instr_type == 64);
-
-	/* Set up IQ registers */
-	sdpvf->fn_list.setup_iq_regs(sdpvf, iq_no);
-
-	return 0;
-
-iq_init_fail:
-	return -ENOMEM;
-
-}
-
-int
-sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq;
-
-	iq = (struct sdp_instr_queue *)rte_zmalloc("sdp_IQ", sizeof(*iq),
-						RTE_CACHE_LINE_SIZE);
-	if (iq == NULL)
-		return -ENOMEM;
-
-	sdpvf->instr_queue[iq_no] = iq;
-
-	if (sdp_init_instr_queue(sdpvf, iq_no)) {
-		otx2_err("IQ init is failed");
-		goto delete_IQ;
-	}
-	otx2_info("IQ[%d] is created.", sdpvf->num_iqs);
-
-	sdpvf->num_iqs++;
-
-
-	return 0;
-
-delete_IQ:
-	sdp_delete_iqs(sdpvf, iq_no);
-	return -ENOMEM;
-}
-
-static void
-sdp_droq_reset_indices(struct sdp_droq *droq)
-{
-	droq->read_idx  = 0;
-	droq->write_idx = 0;
-	droq->refill_idx = 0;
-	droq->refill_count = 0;
-	rte_atomic64_set(&droq->pkts_pending, 0);
-}
-
-static void
-sdp_droq_destroy_ring_buffers(struct sdp_device *sdpvf,
-				struct sdp_droq *droq)
-{
-	uint32_t idx;
-
-	for (idx = 0; idx < droq->nb_desc; idx++) {
-		if (droq->recv_buf_list[idx].buffer) {
-			rte_mempool_put(sdpvf->enqdeq_mpool,
-				droq->recv_buf_list[idx].buffer);
-
-			droq->recv_buf_list[idx].buffer = NULL;
-		}
-	}
-
-	sdp_droq_reset_indices(droq);
-}
-
-/* Free OQs resources */
-int
-sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	struct sdp_droq *droq;
-
-	droq = sdpvf->droq[oq_no];
-	if (droq == NULL) {
-		otx2_err("Invalid droq[%d]", oq_no);
-		return -ENOMEM;
-	}
-
-	sdp_droq_destroy_ring_buffers(sdpvf, droq);
-	rte_free(droq->recv_buf_list);
-	droq->recv_buf_list = NULL;
-
-	if (droq->info_mz) {
-		sdp_dmazone_free(droq->info_mz);
-		droq->info_mz = NULL;
-	}
-
-	if (droq->desc_ring_mz) {
-		sdp_dmazone_free(droq->desc_ring_mz);
-		droq->desc_ring_mz = NULL;
-	}
-
-	memset(droq, 0, SDP_DROQ_SIZE);
-
-	rte_free(sdpvf->droq[oq_no]);
-	sdpvf->droq[oq_no] = NULL;
-
-	sdpvf->num_oqs--;
-
-	otx2_info("OQ[%d] is deleted", oq_no);
-	return 0;
-}
-
-static int
-sdp_droq_setup_ring_buffers(struct sdp_device *sdpvf,
-		struct sdp_droq *droq)
-{
-	struct sdp_droq_desc *desc_ring = droq->desc_ring;
-	uint32_t idx;
-	void *buf;
-
-	for (idx = 0; idx < droq->nb_desc; idx++) {
-		if (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||
-		    (buf == NULL)) {
-			otx2_err("OQ buffer alloc failed");
-			droq->stats.rx_alloc_failure++;
-			/* sdp_droq_destroy_ring_buffers(droq);*/
-			return -ENOMEM;
-		}
-
-		droq->recv_buf_list[idx].buffer = buf;
-		droq->info_list[idx].length = 0;
-
-		/* Map ring buffers into memory */
-		desc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma +
-			(idx * SDP_DROQ_INFO_SIZE));
-
-		desc_ring[idx].buffer_ptr = rte_mem_virt2iova(buf);
-	}
-
-	sdp_droq_reset_indices(droq);
-
-	return 0;
-}
-
-static void *
-sdp_alloc_info_buffer(struct sdp_device *sdpvf __rte_unused,
-	struct sdp_droq *droq)
-{
-	droq->info_mz = rte_memzone_reserve_aligned("OQ_info_list",
-				(droq->nb_desc * SDP_DROQ_INFO_SIZE),
-				rte_socket_id(),
-				RTE_MEMZONE_IOVA_CONTIG,
-				RTE_CACHE_LINE_SIZE);
-
-	if (droq->info_mz == NULL)
-		return NULL;
-
-	droq->info_list_dma = droq->info_mz->iova;
-	droq->info_alloc_size = droq->info_mz->len;
-	droq->info_base_addr = (size_t)droq->info_mz->addr;
-
-	return droq->info_mz->addr;
-}
-
-/* OQ initialization */
-static int
-sdp_init_droq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	const struct sdp_config *conf = sdpvf->conf;
-	uint32_t c_refill_threshold;
-	uint32_t desc_ring_size;
-	struct sdp_droq *droq;
-
-	otx2_info("OQ[%d] Init start", q_no);
-
-	droq = sdpvf->droq[q_no];
-	droq->sdp_dev = sdpvf;
-	droq->q_no = q_no;
-
-	c_refill_threshold = conf->oq.refill_threshold;
-	droq->nb_desc      = conf->num_oqdef_descs;
-	droq->buffer_size  = conf->oqdef_buf_size;
-
-	/* OQ desc_ring set up */
-	desc_ring_size = droq->nb_desc * SDP_DROQ_DESC_SIZE;
-	droq->desc_ring_mz = rte_memzone_reserve_aligned("sdp_oqmz",
-						desc_ring_size,
-						rte_socket_id(),
-						RTE_MEMZONE_IOVA_CONTIG,
-						RTE_CACHE_LINE_SIZE);
-
-	if (droq->desc_ring_mz == NULL) {
-		otx2_err("OQ:%d desc_ring allocation failed", q_no);
-		goto init_droq_fail;
-	}
-
-	droq->desc_ring_dma = droq->desc_ring_mz->iova;
-	droq->desc_ring = (struct sdp_droq_desc *)droq->desc_ring_mz->addr;
-
-	otx2_sdp_dbg("OQ[%d]: desc_ring: virt: 0x%p, dma: %lx",
-		    q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);
-	otx2_sdp_dbg("OQ[%d]: num_desc: %d", q_no, droq->nb_desc);
-
-
-	/* OQ info_list set up */
-	droq->info_list = sdp_alloc_info_buffer(sdpvf, droq);
-	if (droq->info_list == NULL) {
-		otx2_err("memory allocation failed for OQ[%d] info_list", q_no);
-		goto init_droq_fail;
-	}
-
-	/* OQ buf_list set up */
-	droq->recv_buf_list = rte_zmalloc_socket("recv_buf_list",
-				(droq->nb_desc * SDP_DROQ_RECVBUF_SIZE),
-				 RTE_CACHE_LINE_SIZE, rte_socket_id());
-	if (droq->recv_buf_list == NULL) {
-		otx2_err("OQ recv_buf_list alloc failed");
-		goto init_droq_fail;
-	}
-
-	if (sdp_droq_setup_ring_buffers(sdpvf, droq))
-		goto init_droq_fail;
-
-	droq->refill_threshold = c_refill_threshold;
-	rte_spinlock_init(&droq->lock);
-
-
-	/* Set up OQ registers */
-	sdpvf->fn_list.setup_oq_regs(sdpvf, q_no);
-
-	sdpvf->io_qmask.oq |= (1ull << q_no);
-
-	return 0;
-
-init_droq_fail:
-	return -ENOMEM;
-}
-
-/* OQ configuration and setup */
-int
-sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	struct sdp_droq *droq;
-
-	/* Allocate new droq. */
-	droq = (struct sdp_droq *)rte_zmalloc("sdp_OQ",
-				sizeof(*droq), RTE_CACHE_LINE_SIZE);
-	if (droq == NULL) {
-		otx2_err("Droq[%d] Creation Failed", oq_no);
-		return -ENOMEM;
-	}
-	sdpvf->droq[oq_no] = droq;
-
-	if (sdp_init_droq(sdpvf, oq_no)) {
-		otx2_err("Droq[%d] Initialization failed", oq_no);
-		goto delete_OQ;
-	}
-	otx2_info("OQ[%d] is created.", oq_no);
-
-	sdpvf->num_oqs++;
-
-	return 0;
-
-delete_OQ:
-	sdp_delete_oqs(sdpvf, oq_no);
-	return -ENOMEM;
-}
-
-static inline void
-sdp_iqreq_delete(struct sdp_device *sdpvf,
-		struct sdp_instr_queue *iq, uint32_t idx)
-{
-	uint32_t reqtype;
-	void *buf;
-
-	buf     = iq->req_list[idx].buf;
-	reqtype = iq->req_list[idx].reqtype;
-
-	switch (reqtype) {
-	case SDP_REQTYPE_NORESP:
-		rte_mempool_put(sdpvf->enqdeq_mpool, buf);
-		otx2_sdp_dbg("IQ buffer freed at idx[%d]", idx);
-		break;
-
-	case SDP_REQTYPE_NORESP_GATHER:
-	case SDP_REQTYPE_NONE:
-	default:
-		otx2_info("This iqreq mode is not supported:%d", reqtype);
-
-	}
-
-	/* Reset the request list at this index */
-	iq->req_list[idx].buf = NULL;
-	iq->req_list[idx].reqtype = 0;
-}
-
-static inline void
-sdp_iqreq_add(struct sdp_instr_queue *iq, void *buf,
-		uint32_t reqtype)
-{
-	iq->req_list[iq->host_write_index].buf = buf;
-	iq->req_list[iq->host_write_index].reqtype = reqtype;
-
-	otx2_sdp_dbg("IQ buffer added at idx[%d]", iq->host_write_index);
-
-}
-
-static void
-sdp_flush_iq(struct sdp_device *sdpvf,
-		struct sdp_instr_queue *iq,
-		uint32_t pending_thresh __rte_unused)
-{
-	uint32_t instr_processed = 0;
-
-	rte_spinlock_lock(&iq->lock);
-
-	iq->otx_read_index = sdpvf->fn_list.update_iq_read_idx(iq);
-	while (iq->flush_index != iq->otx_read_index) {
-		/* Free the IQ data buffer to the pool */
-		sdp_iqreq_delete(sdpvf, iq, iq->flush_index);
-		iq->flush_index =
-			sdp_incr_index(iq->flush_index, 1, iq->nb_desc);
-
-		instr_processed++;
-	}
-
-	iq->stats.instr_processed = instr_processed;
-	rte_atomic64_sub(&iq->instr_pending, instr_processed);
-
-	rte_spinlock_unlock(&iq->lock);
-}
-
-static inline void
-sdp_ring_doorbell(struct sdp_device *sdpvf __rte_unused,
-		struct sdp_instr_queue *iq)
-{
-	otx2_write64(iq->fill_cnt, iq->doorbell_reg);
-
-	/* Make sure doorbell writes observed by HW */
-	rte_io_wmb();
-	iq->fill_cnt = 0;
-
-}
-
-static inline int
-post_iqcmd(struct sdp_instr_queue *iq, uint8_t *iqcmd)
-{
-	uint8_t *iqptr, cmdsize;
-
-	/* This ensures that the read index does not wrap around to
-	 * the same position if queue gets full before OCTEON TX2 could
-	 * fetch any instr.
-	 */
-	if (rte_atomic64_read(&iq->instr_pending) >=
-			      (int32_t)(iq->nb_desc - 1)) {
-		otx2_err("IQ is full, pending:%ld",
-			 (long)rte_atomic64_read(&iq->instr_pending));
-
-		return SDP_IQ_SEND_FAILED;
-	}
-
-	/* Copy cmd into iq */
-	cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
-	iqptr   = iq->base_addr + (cmdsize * iq->host_write_index);
-
-	rte_memcpy(iqptr, iqcmd, cmdsize);
-
-	otx2_sdp_dbg("IQ cmd posted @ index:%d", iq->host_write_index);
-
-	/* Increment the host write index */
-	iq->host_write_index =
-		sdp_incr_index(iq->host_write_index, 1, iq->nb_desc);
-
-	iq->fill_cnt++;
-
-	/* Flush the command into memory. We need to be sure the data
-	 * is in memory before indicating that the instruction is
-	 * pending.
-	 */
-	rte_smp_wmb();
-	rte_atomic64_inc(&iq->instr_pending);
-
-	/* SDP_IQ_SEND_SUCCESS */
-	return 0;
-}
-
-
-static int
-sdp_send_data(struct sdp_device *sdpvf,
-	      struct sdp_instr_queue *iq, void *cmd)
-{
-	uint32_t ret;
-
-	/* Lock this IQ command queue before posting instruction */
-	rte_spinlock_lock(&iq->post_lock);
-
-	/* Submit IQ command */
-	ret = post_iqcmd(iq, cmd);
-
-	if (ret == SDP_IQ_SEND_SUCCESS) {
-		sdp_ring_doorbell(sdpvf, iq);
-
-		iq->stats.instr_posted++;
-		otx2_sdp_dbg("Instr submit success posted: %ld\n",
-			     (long)iq->stats.instr_posted);
-
-	} else {
-		iq->stats.instr_dropped++;
-		otx2_err("Instr submit failed, dropped: %ld\n",
-			 (long)iq->stats.instr_dropped);
-
-	}
-
-	rte_spinlock_unlock(&iq->post_lock);
-
-	return ret;
-}
-
-
-/* Enqueue requests/packets to SDP IQ queue.
- * returns number of requests enqueued successfully
- */
-int
-sdp_rawdev_enqueue(struct rte_rawdev *rawdev,
-		   struct rte_rawdev_buf **buffers __rte_unused,
-		   unsigned int count, rte_rawdev_obj_t context)
-{
-	struct sdp_instr_64B *iqcmd;
-	struct sdp_instr_queue *iq;
-	struct sdp_soft_instr *si;
-	struct sdp_device *sdpvf;
-
-	struct sdp_instr_ih ihx;
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-	si = (struct sdp_soft_instr *)context;
-
-	iq = sdpvf->instr_queue[si->q_no];
-
-	if ((count > 1) || (count < 1)) {
-		otx2_err("This mode not supported: req[%d]", count);
-		goto enq_fail;
-	}
-
-	memset(&ihx, 0, sizeof(struct sdp_instr_ih));
-
-	iqcmd = &si->command;
-	memset(iqcmd, 0, sizeof(struct sdp_instr_64B));
-
-	iqcmd->dptr = (uint64_t)si->dptr;
-
-	/* Populate SDP IH */
-	ihx.pkind  = sdpvf->pkind;
-	ihx.fsz    = si->ih.fsz + 8; /* 8B for NIX IH */
-	ihx.gather = si->ih.gather;
-
-	/* Direct data instruction */
-	ihx.tlen   = si->ih.tlen + ihx.fsz;
-
-	switch (ihx.gather) {
-	case 0: /* Direct data instr */
-		ihx.tlen = si->ih.tlen + ihx.fsz;
-		break;
-
-	default: /* Gather */
-		switch (si->ih.gsz) {
-		case 0: /* Direct gather instr */
-			otx2_err("Direct Gather instr : not supported");
-			goto enq_fail;
-
-		default: /* Indirect gather instr */
-			otx2_err("Indirect Gather instr : not supported");
-			goto enq_fail;
-		}
-	}
-
-	rte_memcpy(&iqcmd->ih, &ihx, sizeof(uint64_t));
-	iqcmd->rptr = (uint64_t)si->rptr;
-	rte_memcpy(&iqcmd->irh, &si->irh, sizeof(uint64_t));
-
-	/* Swap FSZ(front data) here, to avoid swapping on OCTEON TX2 side */
-	sdp_swap_8B_data(&iqcmd->rptr, 1);
-	sdp_swap_8B_data(&iqcmd->irh, 1);
-
-	otx2_sdp_dbg("After swapping");
-	otx2_sdp_dbg("Word0 [dptr]: 0x%016lx", (unsigned long)iqcmd->dptr);
-	otx2_sdp_dbg("Word1 [ihtx]: 0x%016lx", (unsigned long)iqcmd->ih);
-	otx2_sdp_dbg("Word2 [rptr]: 0x%016lx", (unsigned long)iqcmd->rptr);
-	otx2_sdp_dbg("Word3 [irh]: 0x%016lx", (unsigned long)iqcmd->irh);
-	otx2_sdp_dbg("Word4 [exhdr[0]]: 0x%016lx",
-			(unsigned long)iqcmd->exhdr[0]);
-
-	sdp_iqreq_add(iq, si->dptr, si->reqtype);
-
-	if (sdp_send_data(sdpvf, iq, iqcmd)) {
-		otx2_err("Data send failed :");
-		sdp_iqreq_delete(sdpvf, iq, iq->host_write_index);
-		goto enq_fail;
-	}
-
-	if (rte_atomic64_read(&iq->instr_pending) >= 1)
-		sdp_flush_iq(sdpvf, iq, 1 /*(iq->nb_desc / 2)*/);
-
-	/* Return no# of instructions posted successfully. */
-	return count;
-
-enq_fail:
-	return SDP_IQ_SEND_FAILED;
-}
-
-static uint32_t
-sdp_droq_refill(struct sdp_device *sdpvf, struct sdp_droq *droq)
-{
-	struct sdp_droq_desc *desc_ring;
-	uint32_t desc_refilled = 0;
-	void *buf = NULL;
-
-	desc_ring = droq->desc_ring;
-
-	while (droq->refill_count && (desc_refilled < droq->nb_desc)) {
-		/* If a valid buffer exists (happens if there is no dispatch),
-		 * reuse the buffer, else allocate.
-		 */
-		if (droq->recv_buf_list[droq->refill_idx].buffer != NULL)
-			break;
-
-		if (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||
-		    (buf == NULL)) {
-			/* If a buffer could not be allocated, no point in
-			 * continuing
-			 */
-			droq->stats.rx_alloc_failure++;
-			break;
-		}
-
-		droq->recv_buf_list[droq->refill_idx].buffer = buf;
-		desc_ring[droq->refill_idx].buffer_ptr = rte_mem_virt2iova(buf);
-
-		/* Reset any previous values in the length field. */
-		droq->info_list[droq->refill_idx].length = 0;
-
-		droq->refill_idx = sdp_incr_index(droq->refill_idx, 1,
-				droq->nb_desc);
-
-		desc_refilled++;
-		droq->refill_count--;
-
-	}
-
-	return desc_refilled;
-}
-
-static int
-sdp_droq_read_packet(struct sdp_device *sdpvf __rte_unused,
-		     struct sdp_droq *droq,
-		     struct sdp_droq_pkt *droq_pkt)
-{
-	struct sdp_droq_info *info;
-	uint32_t total_len = 0;
-	uint32_t pkt_len = 0;
-
-	info = &droq->info_list[droq->read_idx];
-	sdp_swap_8B_data((uint64_t *)&info->length, 1);
-	if (!info->length) {
-		otx2_err("OQ info_list->length[%ld]", (long)info->length);
-		goto oq_read_fail;
-	}
-
-	/* Deduce the actual data size */
-	info->length -= SDP_RH_SIZE;
-	total_len += (uint32_t)info->length;
-
-	otx2_sdp_dbg("OQ: pkt_len[%ld], buffer_size %d",
-			(long)info->length, droq->buffer_size);
-	if (info->length > droq->buffer_size) {
-		otx2_err("This mode is not supported: pkt_len > buffer_size");
-		goto oq_read_fail;
-	}
-
-	if (info->length <= droq->buffer_size) {
-		pkt_len = (uint32_t)info->length;
-		droq_pkt->data = droq->recv_buf_list[droq->read_idx].buffer;
-		droq_pkt->len  = pkt_len;
-
-		droq->recv_buf_list[droq->read_idx].buffer = NULL;
-		droq->read_idx = sdp_incr_index(droq->read_idx,	1,/* count */
-						droq->nb_desc /* max rd idx */);
-		droq->refill_count++;
-
-	}
-
-	info->length = 0;
-
-	return SDP_OQ_RECV_SUCCESS;
-
-oq_read_fail:
-	return SDP_OQ_RECV_FAILED;
-}
-
-static inline uint32_t
-sdp_check_droq_pkts(struct sdp_droq *droq, uint32_t burst_size)
-{
-	uint32_t min_pkts = 0;
-	uint32_t new_pkts;
-	uint32_t pkt_count;
-
-	/* Latest available OQ packets */
-	pkt_count = rte_read32(droq->pkts_sent_reg);
-
-	/* Newly arrived packets */
-	new_pkts = pkt_count - droq->last_pkt_count;
-	otx2_sdp_dbg("Recvd [%d] new OQ pkts", new_pkts);
-
-	min_pkts = (new_pkts > burst_size) ? burst_size : new_pkts;
-	if (min_pkts) {
-		rte_atomic64_add(&droq->pkts_pending, min_pkts);
-		/* Back up the aggregated packet count so far */
-		droq->last_pkt_count += min_pkts;
-	}
-
-	return min_pkts;
-}
-
-/* Check for response arrival from OCTEON TX2
- * returns number of requests completed
- */
-int
-sdp_rawdev_dequeue(struct rte_rawdev *rawdev,
-		   struct rte_rawdev_buf **buffers, unsigned int count,
-		   rte_rawdev_obj_t context __rte_unused)
-{
-	struct sdp_droq_pkt *oq_pkt;
-	struct sdp_device *sdpvf;
-	struct sdp_droq *droq;
-
-	uint32_t q_no = 0, pkts;
-	uint32_t new_pkts;
-	uint32_t ret;
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-
-	droq = sdpvf->droq[q_no];
-	if (!droq) {
-		otx2_err("Invalid droq[%d]", q_no);
-		goto droq_err;
-	}
-
-	/* Grab the lock */
-	rte_spinlock_lock(&droq->lock);
-
-	new_pkts = sdp_check_droq_pkts(droq, count);
-	if (!new_pkts) {
-		otx2_sdp_dbg("Zero new_pkts:%d", new_pkts);
-		goto deq_fail; /* No pkts at this moment */
-	}
-
-	otx2_sdp_dbg("Received new_pkts = %d", new_pkts);
-
-	for (pkts = 0; pkts < new_pkts; pkts++) {
-
-		/* Push the received pkt to application */
-		oq_pkt = (struct sdp_droq_pkt *)buffers[pkts];
-
-		ret = sdp_droq_read_packet(sdpvf, droq, oq_pkt);
-		if (ret) {
-			otx2_err("DROQ read pakt failed.");
-			goto deq_fail;
-		}
-
-		/* Stats */
-		droq->stats.pkts_received++;
-		droq->stats.bytes_received += oq_pkt->len;
-	}
-
-	/* Ack the h/w with no# of pkts read by Host */
-	rte_write32(pkts, droq->pkts_sent_reg);
-	rte_io_wmb();
-
-	droq->last_pkt_count -= pkts;
-
-	otx2_sdp_dbg("DROQ pkts[%d] pushed to application", pkts);
-
-	/* Refill DROQ buffers */
-	if (droq->refill_count >= 2 /* droq->refill_threshold */) {
-		int desc_refilled = sdp_droq_refill(sdpvf, droq);
-
-		/* Flush the droq descriptor data to memory to be sure
-		 * that when we update the credits the data in memory is
-		 * accurate.
-		 */
-		rte_write32(desc_refilled, droq->pkts_credit_reg);
-
-		/* Ensure mmio write completes */
-		rte_wmb();
-		otx2_sdp_dbg("Refilled count = %d", desc_refilled);
-	}
-
-	/* Release the spin lock */
-	rte_spinlock_unlock(&droq->lock);
-
-	return pkts;
-
-deq_fail:
-	rte_spinlock_unlock(&droq->lock);
-
-droq_err:
-	return SDP_OQ_RECV_FAILED;
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
deleted file mode 100644
index 172fdc5568..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _OTX2_EP_ENQDEQ_H_
-#define _OTX2_EP_ENQDEQ_H_
-
-#include <rte_byteorder.h>
-#include "otx2_ep_rawdev.h"
-
-#define SDP_IQ_SEND_FAILED      (-1)
-#define SDP_IQ_SEND_SUCCESS     (0)
-
-#define SDP_OQ_RECV_FAILED      (-1)
-#define SDP_OQ_RECV_SUCCESS     (0)
-
-static inline uint64_t
-sdp_endian_swap_8B(uint64_t _d)
-{
-	return ((((((uint64_t)(_d)) >>  0) & (uint64_t)0xff) << 56) |
-		(((((uint64_t)(_d)) >>  8) & (uint64_t)0xff) << 48) |
-		(((((uint64_t)(_d)) >> 16) & (uint64_t)0xff) << 40) |
-		(((((uint64_t)(_d)) >> 24) & (uint64_t)0xff) << 32) |
-		(((((uint64_t)(_d)) >> 32) & (uint64_t)0xff) << 24) |
-		(((((uint64_t)(_d)) >> 40) & (uint64_t)0xff) << 16) |
-		(((((uint64_t)(_d)) >> 48) & (uint64_t)0xff) <<  8) |
-		(((((uint64_t)(_d)) >> 56) & (uint64_t)0xff) <<  0));
-}
-
-static inline void
-sdp_swap_8B_data(uint64_t *data, uint32_t blocks)
-{
-	/* Swap 8B blocks */
-	while (blocks) {
-		*data = sdp_endian_swap_8B(*data);
-		blocks--;
-		data++;
-	}
-}
-
-static inline uint32_t
-sdp_incr_index(uint32_t index, uint32_t count, uint32_t max)
-{
-	if ((index + count) >= max)
-		index = index + count - max;
-	else
-		index += count;
-
-	return index;
-}
-
-#endif /* _OTX2_EP_ENQDEQ_H_ */
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
deleted file mode 100644
index b2ccdda83e..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-#include "otx2_ep_vf.h"
-
-static const struct rte_pci_id pci_sdp_vf_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_EP_RAW_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* SDP_VF default configuration */
-const struct sdp_config default_sdp_conf = {
-	/* IQ attributes */
-	.iq                        = {
-		.max_iqs           = SDP_VF_CFG_IO_QUEUES,
-		.instr_type        = SDP_VF_64BYTE_INSTR,
-		.pending_list_size = (SDP_VF_MAX_IQ_DESCRIPTORS *
-				      SDP_VF_CFG_IO_QUEUES),
-	},
-
-	/* OQ attributes */
-	.oq                        = {
-		.max_oqs           = SDP_VF_CFG_IO_QUEUES,
-		.info_ptr          = SDP_VF_OQ_INFOPTR_MODE,
-		.refill_threshold  = SDP_VF_OQ_REFIL_THRESHOLD,
-	},
-
-	.num_iqdef_descs           = SDP_VF_MAX_IQ_DESCRIPTORS,
-	.num_oqdef_descs           = SDP_VF_MAX_OQ_DESCRIPTORS,
-	.oqdef_buf_size            = SDP_VF_OQ_BUF_SIZE,
-
-};
-
-const struct sdp_config*
-sdp_get_defconf(struct sdp_device *sdp_dev __rte_unused)
-{
-	const struct sdp_config *default_conf = NULL;
-
-	default_conf = &default_sdp_conf;
-
-	return default_conf;
-}
-
-static int
-sdp_vfdev_exit(struct rte_rawdev *rawdev)
-{
-	struct sdp_device *sdpvf;
-	uint32_t rawdev_queues, q;
-
-	otx2_info("%s:", __func__);
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-
-	sdpvf->fn_list.disable_io_queues(sdpvf);
-
-	rawdev_queues = sdpvf->num_oqs;
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_delete_oqs(sdpvf, q)) {
-			otx2_err("Failed to delete OQ:%d", q);
-			return -ENOMEM;
-		}
-	}
-	otx2_info("Num OQs:%d freed", sdpvf->num_oqs);
-
-	/* Free the oqbuf_pool */
-	rte_mempool_free(sdpvf->enqdeq_mpool);
-	sdpvf->enqdeq_mpool = NULL;
-
-	otx2_info("Enqdeq_mpool free done");
-
-	rawdev_queues = sdpvf->num_iqs;
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_delete_iqs(sdpvf, q)) {
-			otx2_err("Failed to delete IQ:%d", q);
-			return -ENOMEM;
-		}
-	}
-	otx2_sdp_dbg("Num IQs:%d freed", sdpvf->num_iqs);
-
-	return 0;
-}
-
-static int
-sdp_chip_specific_setup(struct sdp_device *sdpvf)
-{
-	struct rte_pci_device *pdev = sdpvf->pci_dev;
-	uint32_t dev_id = pdev->id.device_id;
-	int ret;
-
-	switch (dev_id) {
-	case PCI_DEVID_OCTEONTX2_EP_RAW_VF:
-		sdpvf->chip_id = PCI_DEVID_OCTEONTX2_EP_RAW_VF;
-		ret = sdp_vf_setup_device(sdpvf);
-
-		break;
-	default:
-		otx2_err("Unsupported device");
-		ret = -EINVAL;
-	}
-
-	if (!ret)
-		otx2_info("SDP dev_id[%d]", dev_id);
-
-	return ret;
-}
-
-/* SDP VF device initialization */
-static int
-sdp_vfdev_init(struct sdp_device *sdpvf)
-{
-	uint32_t rawdev_queues, q;
-
-	if (sdp_chip_specific_setup(sdpvf)) {
-		otx2_err("Chip specific setup failed");
-		goto setup_fail;
-	}
-
-	if (sdpvf->fn_list.setup_device_regs(sdpvf)) {
-		otx2_err("Failed to configure device registers");
-		goto setup_fail;
-	}
-
-	rawdev_queues = (uint32_t)(sdpvf->sriov_info.rings_per_vf);
-
-	/* Rawdev queues setup for enqueue/dequeue */
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_setup_iqs(sdpvf, q)) {
-			otx2_err("Failed to setup IQs");
-			goto iq_fail;
-		}
-	}
-	otx2_info("Total[%d] IQs setup", sdpvf->num_iqs);
-
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_setup_oqs(sdpvf, q)) {
-			otx2_err("Failed to setup OQs");
-			goto oq_fail;
-		}
-	}
-	otx2_info("Total [%d] OQs setup", sdpvf->num_oqs);
-
-	/* Enable IQ/OQ for this device */
-	sdpvf->fn_list.enable_io_queues(sdpvf);
-
-	/* Send OQ desc credits for OQs, credits are always
-	 * sent after the OQs are enabled.
-	 */
-	for (q = 0; q < rawdev_queues; q++) {
-		rte_write32(sdpvf->droq[q]->nb_desc,
-			    sdpvf->droq[q]->pkts_credit_reg);
-
-		rte_io_mb();
-		otx2_info("OQ[%d] dbells [%d]", q,
-		rte_read32(sdpvf->droq[q]->pkts_credit_reg));
-	}
-
-	rte_wmb();
-
-	otx2_info("SDP Device is Ready");
-
-	return 0;
-
-/* Error handling  */
-oq_fail:
-	/* Free the allocated OQs */
-	for (q = 0; q < sdpvf->num_oqs; q++)
-		sdp_delete_oqs(sdpvf, q);
-
-iq_fail:
-	/* Free the allocated IQs */
-	for (q = 0; q < sdpvf->num_iqs; q++)
-		sdp_delete_iqs(sdpvf, q);
-
-setup_fail:
-	return -ENOMEM;
-}
-
-static int
-sdp_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = 1;
-
-	return 0;
-}
-
-static void
-sdp_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = 0;
-}
-
-static int
-sdp_rawdev_close(struct rte_rawdev *dev)
-{
-	int ret;
-	ret = sdp_vfdev_exit(dev);
-	if (ret) {
-		otx2_err(" SDP_EP rawdev exit error");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int
-sdp_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct sdp_rawdev_info *app_info = (struct sdp_rawdev_info *)config;
-	struct sdp_device *sdpvf;
-
-	if (app_info == NULL || config_size != sizeof(*app_info)) {
-		otx2_err("Application config info [NULL] or incorrect size");
-		return -EINVAL;
-	}
-
-	sdpvf = (struct sdp_device *)dev->dev_private;
-
-	sdpvf->conf = app_info->app_conf;
-	sdpvf->enqdeq_mpool = app_info->enqdeq_mpool;
-
-	sdp_vfdev_init(sdpvf);
-
-	return 0;
-
-}
-
-/* SDP VF endpoint rawdev ops */
-static const struct rte_rawdev_ops sdp_rawdev_ops = {
-	.dev_configure  = sdp_rawdev_configure,
-	.dev_start      = sdp_rawdev_start,
-	.dev_stop       = sdp_rawdev_stop,
-	.dev_close      = sdp_rawdev_close,
-	.enqueue_bufs   = sdp_rawdev_enqueue,
-	.dequeue_bufs   = sdp_rawdev_dequeue,
-	.dev_selftest   = sdp_rawdev_selftest,
-};
-
-static int
-otx2_sdp_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct sdp_device *sdpvf = NULL;
-	struct rte_rawdev *sdp_rawdev;
-	uint16_t vf_id;
-
-	/* Single process support */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return 0;
-
-	if (pci_dev->mem_resource[0].addr)
-		otx2_info("SDP_EP BAR0 is mapped:");
-	else {
-		otx2_err("SDP_EP: Failed to map device BARs");
-		otx2_err("BAR0 %p\n BAR2 %p",
-			pci_dev->mem_resource[0].addr,
-			pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "SDPEP:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate rawdev pmd */
-	sdp_rawdev = rte_rawdev_pmd_allocate(name,
-					     sizeof(struct sdp_device),
-					     rte_socket_id());
-
-	if (sdp_rawdev == NULL) {
-		otx2_err("SDP_EP VF rawdev allocation failed");
-		return -ENOMEM;
-	}
-
-	sdp_rawdev->dev_ops = &sdp_rawdev_ops;
-	sdp_rawdev->device = &pci_dev->device;
-	sdp_rawdev->driver_name = pci_dev->driver->driver.name;
-
-	sdpvf = (struct sdp_device *)sdp_rawdev->dev_private;
-	sdpvf->hw_addr = pci_dev->mem_resource[0].addr;
-	sdpvf->pci_dev = pci_dev;
-
-	/* Discover the VF number being probed */
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-
-	vf_id -= 1;
-	sdpvf->vf_num = vf_id;
-
-	otx2_info("SDP_EP VF[%d] probe done", vf_id);
-
-	return 0;
-}
-
-static int
-otx2_sdp_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct sdp_device *sdpvf;
-
-	/* Single process support */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return 0;
-
-	if (pci_dev == NULL) {
-		otx2_err("SDP_EP:invalid pci_dev!");
-		return -EINVAL;
-	}
-
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "SDPEP:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_err("SDP_EP: invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-	otx2_info("Removing SDP_EP VF[%d] ", sdpvf->vf_num);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_sdp_rawdev_pmd = {
-	.id_table  = pci_sdp_vf_map,
-	.drv_flags = (RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA),
-	.probe     = otx2_sdp_rawdev_probe,
-	.remove    = otx2_sdp_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(sdp_rawdev_pci_driver, rte_sdp_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(sdp_rawdev_pci_driver, pci_sdp_vf_map);
-RTE_PMD_REGISTER_KMOD_DEP(sdp_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
deleted file mode 100644
index dab2fb7541..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _OTX2_EP_RAWDEV_H_
-#define _OTX2_EP_RAWDEV_H_
-
-#include <rte_byteorder.h>
-#include <rte_spinlock.h>
-
-/* IQ instruction req types */
-#define SDP_REQTYPE_NONE             (0)
-#define SDP_REQTYPE_NORESP           (1)
-#define SDP_REQTYPE_NORESP_GATHER    (2)
-
-/* Input Request Header format */
-struct sdp_instr_irh {
-	/* Request ID  */
-	uint64_t rid:16;
-
-	/* PCIe port to use for response */
-	uint64_t pcie_port:3;
-
-	/* Scatter indicator  1=scatter */
-	uint64_t scatter:1;
-
-	/* Size of Expected result OR no. of entries in scatter list */
-	uint64_t rlenssz:14;
-
-	/* Desired destination port for result */
-	uint64_t dport:6;
-
-	/* Opcode Specific parameters */
-	uint64_t param:8;
-
-	/* Opcode for the return packet  */
-	uint64_t opcode:16;
-};
-
-/* SDP 32B instruction format */
-struct sdp_instr_32B {
-	/* Pointer where the input data is available. */
-	uint64_t dptr;
-
-	/* SDP Instruction Header.  */
-	uint64_t ih;
-
-	/** Pointer where the response for a RAW mode packet
-	 *  will be written by OCTEON TX2.
-	 */
-	uint64_t rptr;
-
-	/* Input Request Header. Additional info about the input. */
-	uint64_t irh;
-};
-#define SDP_32B_INSTR_SIZE	(sizeof(sdp_instr_32B))
-
-/* SDP 64B instruction format */
-struct sdp_instr_64B {
-	/* Pointer where the input data is available. */
-	uint64_t dptr;
-
-	/* SDP Instruction Header. */
-	uint64_t ih;
-
-	/** Pointer where the response for a RAW mode packet
-	 * will be written by OCTEON TX2.
-	 */
-	uint64_t rptr;
-
-	/* Input Request Header. */
-	uint64_t irh;
-
-	/* Additional headers available in a 64-byte instruction. */
-	uint64_t exhdr[4];
-};
-#define SDP_64B_INSTR_SIZE	(sizeof(sdp_instr_64B))
-
-struct sdp_soft_instr {
-	/** Input data pointer. It is either pointing directly to input data
-	 *  or to a gather list.
-	 */
-	void *dptr;
-
-	/** Response from OCTEON TX2 comes at this address. It is either
-	 *  directlty pointing to output data buffer or to a scatter list.
-	 */
-	void *rptr;
-
-	/* The instruction header. All input commands have this field. */
-	struct sdp_instr_ih ih;
-
-	/* Input request header. */
-	struct sdp_instr_irh irh;
-
-	/** The PCI instruction to be sent to OCTEON TX2. This is stored in the
-	 *  instr to retrieve the physical address of buffers when instr is
-	 *  freed.
-	 */
-	struct sdp_instr_64B command;
-
-	/** If a gather list was allocated, this ptr points to the buffer used
-	 *  for the gather list. The gather list has to be 8B aligned, so this
-	 *  value may be different from dptr.
-	 */
-	void *gather_ptr;
-
-	/* Total data bytes transferred in the gather mode request. */
-	uint64_t gather_bytes;
-
-	/** If a scatter list was allocated, this ptr points to the buffer used
-	 *  for the scatter list. The scatter list has to be 8B aligned, so
-	 *  this value may be different from rptr.
-	 */
-	void *scatter_ptr;
-
-	/* Total data bytes to be received in the scatter mode request. */
-	uint64_t scatter_bytes;
-
-	/* IQ number to which this instruction has to be submitted. */
-	uint32_t q_no;
-
-	/* IQ instruction request type. */
-	uint32_t reqtype;
-};
-#define SDP_SOFT_INSTR_SIZE	(sizeof(sdp_soft_instr))
-
-/* SDP IQ request list */
-struct sdp_instr_list {
-	void *buf;
-	uint32_t reqtype;
-};
-#define SDP_IQREQ_LIST_SIZE	(sizeof(struct sdp_instr_list))
-
-/* Input Queue statistics. Each input queue has four stats fields. */
-struct sdp_iq_stats {
-	uint64_t instr_posted; /* Instructions posted to this queue. */
-	uint64_t instr_processed; /* Instructions processed in this queue. */
-	uint64_t instr_dropped; /* Instructions that could not be processed */
-};
-
-/* Structure to define the configuration attributes for each Input queue. */
-struct sdp_iq_config {
-	/* Max number of IQs available */
-	uint16_t max_iqs;
-
-	/* Command size - 32 or 64 bytes */
-	uint16_t instr_type;
-
-	/* Pending list size, usually set to the sum of the size of all IQs */
-	uint32_t pending_list_size;
-};
-
-/** The instruction (input) queue.
- *  The input queue is used to post raw (instruction) mode data or packet data
- *  to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one
- *  such structure to represent it.
- */
-struct sdp_instr_queue {
-	/* A spinlock to protect access to the input ring.  */
-	rte_spinlock_t lock;
-	rte_spinlock_t post_lock;
-
-	struct sdp_device *sdp_dev;
-	rte_atomic64_t iq_flush_running;
-
-	uint32_t q_no;
-	uint32_t pkt_in_done;
-
-	/* Flag for 64 byte commands. */
-	uint32_t iqcmd_64B:1;
-	uint32_t rsvd:17;
-	uint32_t status:8;
-
-	/* Number of  descriptors in this ring. */
-	uint32_t nb_desc;
-
-	/* Input ring index, where the driver should write the next packet */
-	uint32_t host_write_index;
-
-	/* Input ring index, where the OCTEON TX2 should read the next packet */
-	uint32_t otx_read_index;
-
-	/** This index aids in finding the window in the queue where OCTEON TX2
-	 *  has read the commands.
-	 */
-	uint32_t flush_index;
-
-	/* This keeps track of the instructions pending in this queue. */
-	rte_atomic64_t instr_pending;
-
-	uint32_t reset_instr_cnt;
-
-	/* Pointer to the Virtual Base addr of the input ring. */
-	uint8_t *base_addr;
-
-	/* This IQ request list */
-	struct sdp_instr_list *req_list;
-
-	/* SDP doorbell register for the ring. */
-	void *doorbell_reg;
-
-	/* SDP instruction count register for this ring. */
-	void *inst_cnt_reg;
-
-	/* Number of instructions pending to be posted to OCTEON TX2. */
-	uint32_t fill_cnt;
-
-	/* Statistics for this input queue. */
-	struct sdp_iq_stats stats;
-
-	/* DMA mapped base address of the input descriptor ring. */
-	uint64_t base_addr_dma;
-
-	/* Memory zone */
-	const struct rte_memzone *iq_mz;
-};
-
-/* DROQ packet format for application i/f. */
-struct sdp_droq_pkt {
-	/* DROQ packet data buffer pointer. */
-	uint8_t	 *data;
-
-	/* DROQ packet data length */
-	uint32_t len;
-
-	uint32_t misc;
-};
-
-/** Descriptor format.
- *  The descriptor ring is made of descriptors which have 2 64-bit values:
- *  -# Physical (bus) address of the data buffer.
- *  -# Physical (bus) address of a sdp_droq_info structure.
- *  The device DMA's incoming packets and its information at the address
- *  given by these descriptor fields.
- */
-struct sdp_droq_desc {
-	/* The buffer pointer */
-	uint64_t buffer_ptr;
-
-	/* The Info pointer */
-	uint64_t info_ptr;
-};
-#define SDP_DROQ_DESC_SIZE	(sizeof(struct sdp_droq_desc))
-
-/* Receive Header */
-union sdp_rh {
-	uint64_t rh64;
-};
-#define SDP_RH_SIZE (sizeof(union sdp_rh))
-
-/** Information about packet DMA'ed by OCTEON TX2.
- *  The format of the information available at Info Pointer after OCTEON TX2
- *  has posted a packet. Not all descriptors have valid information. Only
- *  the Info field of the first descriptor for a packet has information
- *  about the packet.
- */
-struct sdp_droq_info {
-	/* The Output Receive Header. */
-	union sdp_rh rh;
-
-	/* The Length of the packet. */
-	uint64_t length;
-};
-#define SDP_DROQ_INFO_SIZE	(sizeof(struct sdp_droq_info))
-
-/** Pointer to data buffer.
- *  Driver keeps a pointer to the data buffer that it made available to
- *  the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)
- *  addresses, this field is required for the driver to keep track of
- *  the virtual address pointers.
- */
-struct sdp_recv_buffer {
-	/* Packet buffer, including meta data. */
-	void *buffer;
-
-	/* Data in the packet buffer. */
-	/* uint8_t *data; */
-};
-#define SDP_DROQ_RECVBUF_SIZE	(sizeof(struct sdp_recv_buffer))
-
-/* DROQ statistics. Each output queue has four stats fields. */
-struct sdp_droq_stats {
-	/* Number of packets received in this queue. */
-	uint64_t pkts_received;
-
-	/* Bytes received by this queue. */
-	uint64_t bytes_received;
-
-	/* Num of failures of rte_pktmbuf_alloc() */
-	uint64_t rx_alloc_failure;
-};
-
-/* Structure to define the configuration attributes for each Output queue. */
-struct sdp_oq_config {
-	/* Max number of OQs available */
-	uint16_t max_oqs;
-
-	/* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
-	uint16_t info_ptr;
-
-	/** The number of buffers that were consumed during packet processing by
-	 *  the driver on this Output queue before the driver attempts to
-	 *  replenish the descriptor ring with new buffers.
-	 */
-	uint32_t refill_threshold;
-};
-
-/* The Descriptor Ring Output Queue(DROQ) structure. */
-struct sdp_droq {
-	/* A spinlock to protect access to this ring. */
-	rte_spinlock_t lock;
-
-	struct sdp_device *sdp_dev;
-	/* The 8B aligned descriptor ring starts at this address. */
-	struct sdp_droq_desc *desc_ring;
-
-	uint32_t q_no;
-	uint32_t last_pkt_count;
-
-	/* Driver should read the next packet at this index */
-	uint32_t read_idx;
-
-	/* OCTEON TX2 will write the next packet at this index */
-	uint32_t write_idx;
-
-	/* At this index, the driver will refill the descriptor's buffer */
-	uint32_t refill_idx;
-
-	/* Packets pending to be processed */
-	rte_atomic64_t pkts_pending;
-
-	/* Number of descriptors in this ring. */
-	uint32_t nb_desc;
-
-	/* The number of descriptors pending to refill. */
-	uint32_t refill_count;
-
-	uint32_t refill_threshold;
-
-	/* The 8B aligned info ptrs begin from this address. */
-	struct sdp_droq_info *info_list;
-
-	/* receive buffer list contains virtual addresses of the buffers. */
-	struct sdp_recv_buffer *recv_buf_list;
-
-	/* The size of each buffer pointed by the buffer pointer. */
-	uint32_t buffer_size;
-
-	/** Pointer to the mapped packet credit register.
-	 *  Host writes number of info/buffer ptrs available to this register
-	 */
-	void *pkts_credit_reg;
-
-	/** Pointer to the mapped packet sent register. OCTEON TX2 writes the
-	 *  number of packets DMA'ed to host memory in this register.
-	 */
-	void *pkts_sent_reg;
-
-	/* Statistics for this DROQ. */
-	struct sdp_droq_stats stats;
-
-	/* DMA mapped address of the DROQ descriptor ring. */
-	size_t desc_ring_dma;
-
-	/* Info_ptr list is allocated at this virtual address. */
-	size_t info_base_addr;
-
-	/* DMA mapped address of the info list */
-	size_t info_list_dma;
-
-	/* Allocated size of info list. */
-	uint32_t info_alloc_size;
-
-	/* Memory zone **/
-	const struct rte_memzone *desc_ring_mz;
-	const struct rte_memzone *info_mz;
-};
-#define SDP_DROQ_SIZE		(sizeof(struct sdp_droq))
-
-/* IQ/OQ mask */
-struct sdp_io_enable {
-	uint64_t iq;
-	uint64_t oq;
-	uint64_t iq64B;
-};
-
-/* Structure to define the configuration. */
-struct sdp_config {
-	/* Input Queue attributes. */
-	struct sdp_iq_config iq;
-
-	/* Output Queue attributes. */
-	struct sdp_oq_config oq;
-
-	/* Num of desc for IQ rings */
-	uint32_t num_iqdef_descs;
-
-	/* Num of desc for OQ rings */
-	uint32_t num_oqdef_descs;
-
-	/* OQ buffer size */
-	uint32_t oqdef_buf_size;
-};
-
-/* Required functions for each VF device */
-struct sdp_fn_list {
-	void (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
-
-	int (*setup_device_regs)(struct sdp_device *sdpvf);
-	uint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq);
-
-	void (*enable_io_queues)(struct sdp_device *sdpvf);
-	void (*disable_io_queues)(struct sdp_device *sdpvf);
-
-	void (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
-
-	void (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
-};
-
-/* SRIOV information */
-struct sdp_sriov_info {
-	/* Number of rings assigned to VF */
-	uint32_t rings_per_vf;
-
-	/* Number of VF devices enabled */
-	uint32_t num_vfs;
-};
-
-
-/* Information to be passed from application */
-struct sdp_rawdev_info {
-	struct rte_mempool *enqdeq_mpool;
-	const struct sdp_config *app_conf;
-};
-
-/* SDP EP VF device */
-struct sdp_device {
-	/* PCI device pointer */
-	struct rte_pci_device *pci_dev;
-	uint16_t chip_id;
-	uint16_t pf_num;
-	uint16_t vf_num;
-
-	/* This device's PCIe port used for traffic. */
-	uint16_t pcie_port;
-	uint32_t pkind;
-
-	/* The state of this device */
-	rte_atomic64_t status;
-
-	/* Memory mapped h/w address */
-	uint8_t *hw_addr;
-
-	struct sdp_fn_list fn_list;
-
-	/* Num IQs */
-	uint32_t num_iqs;
-
-	/* The input instruction queues */
-	struct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];
-
-	/* Num OQs */
-	uint32_t num_oqs;
-
-	/* The DROQ output queues  */
-	struct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];
-
-	/* IOQ data buffer pool */
-	struct rte_mempool *enqdeq_mpool;
-
-	/* IOQ mask */
-	struct sdp_io_enable io_qmask;
-
-	/* SR-IOV info */
-	struct sdp_sriov_info sriov_info;
-
-	/* Device configuration */
-	const struct sdp_config *conf;
-};
-
-const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);
-int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
-int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
-
-int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
-int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
-
-int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
-		       unsigned int count, rte_rawdev_obj_t context);
-int sdp_rawdev_dequeue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
-		       unsigned int count, rte_rawdev_obj_t context);
-
-int sdp_rawdev_selftest(uint16_t dev_id);
-
-#endif /* _OTX2_EP_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_test.c b/drivers/raw/octeontx2_ep/otx2_ep_test.c
deleted file mode 100644
index b876275f7a..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_test.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-
-#define SDP_IOQ_NUM_BUFS   (4 * 1024)
-#define SDP_IOQ_BUF_SIZE   (2 * 1024)
-
-#define SDP_TEST_PKT_FSZ   (0)
-#define SDP_TEST_PKT_SIZE  (1024)
-
-static int
-sdp_validate_data(struct sdp_droq_pkt *oq_pkt, uint8_t *iq_pkt,
-		  uint32_t pkt_len)
-{
-	if (!oq_pkt)
-		return -EINVAL;
-
-	if (pkt_len != oq_pkt->len) {
-		otx2_err("Invalid packet length");
-		return -EINVAL;
-	}
-
-	if (memcmp(oq_pkt->data, iq_pkt, pkt_len) != 0) {
-		otx2_err("Data validation failed");
-		return -EINVAL;
-	}
-	otx2_sdp_dbg("Data validation successful");
-
-	return 0;
-}
-
-static void
-sdp_ioq_buffer_fill(uint8_t *addr, uint32_t len)
-{
-	uint32_t idx;
-
-	memset(addr, 0, len);
-
-	for (idx = 0; idx < len; idx++)
-		addr[idx] = idx;
-}
-
-static struct rte_mempool*
-sdp_ioq_mempool_create(void)
-{
-	struct rte_mempool *mpool;
-
-	mpool = rte_mempool_create("ioqbuf_pool",
-				   SDP_IOQ_NUM_BUFS /*num elt*/,
-				   SDP_IOQ_BUF_SIZE /*elt size*/,
-				   0 /*cache_size*/,
-				   0 /*private_data_size*/,
-				   NULL /*mp_init*/,
-				   NULL /*mp_init arg*/,
-				   NULL /*obj_init*/,
-				   NULL /*obj_init arg*/,
-				   rte_socket_id() /*socket id*/,
-				   (MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET));
-
-	return mpool;
-}
-
-
-int
-sdp_rawdev_selftest(uint16_t dev_id)
-{
-	struct sdp_rawdev_info app_info = {0};
-	struct rte_rawdev_info dev_info = {0};
-
-	struct rte_rawdev_buf *d_buf[1];
-	struct sdp_droq_pkt oq_pkt;
-	struct sdp_soft_instr si;
-	struct sdp_device sdpvf;
-
-	uint32_t buf_size;
-	int ret = 0;
-	void *buf;
-
-	otx2_info("SDP RAWDEV Self Test: Started");
-
-	memset(&oq_pkt, 0x00, sizeof(oq_pkt));
-	d_buf[0] = (struct rte_rawdev_buf *)&oq_pkt;
-
-	struct rte_mempool *ioq_mpool = sdp_ioq_mempool_create();
-	if (!ioq_mpool) {
-		otx2_err("IOQ mpool creation failed");
-		return -ENOMEM;
-	}
-
-	app_info.enqdeq_mpool = ioq_mpool;
-	app_info.app_conf = NULL; /* Use default conf */
-
-	dev_info.dev_private = &app_info;
-
-	ret = rte_rawdev_configure(dev_id, &dev_info, sizeof(app_info));
-	if (ret) {
-		otx2_err("Unable to configure SDP_VF %d", dev_id);
-		rte_mempool_free(ioq_mpool);
-		return -ENOMEM;
-	}
-	otx2_info("SDP VF rawdev[%d] configured successfully", dev_id);
-
-	memset(&si, 0x00, sizeof(si));
-	memset(&sdpvf, 0x00, sizeof(sdpvf));
-
-	buf_size = SDP_TEST_PKT_SIZE;
-
-	si.q_no = 0;
-	si.reqtype = SDP_REQTYPE_NORESP;
-	si.rptr = NULL;
-
-	si.ih.fsz = SDP_TEST_PKT_FSZ;
-	si.ih.tlen = buf_size;
-	si.ih.gather = 0;
-
-	/* Enqueue raw pkt data */
-	rte_mempool_get(ioq_mpool, &buf);
-	if (!buf) {
-		otx2_err("Buffer allocation failed");
-		rte_mempool_free(ioq_mpool);
-		rte_rawdev_close(dev_id);
-		return -ENOMEM;
-	}
-
-	sdp_ioq_buffer_fill(buf, buf_size);
-	si.dptr = (uint8_t *)buf;
-
-	rte_rawdev_enqueue_buffers(dev_id, NULL, 1, &si);
-	usleep(10000);
-
-	/* Dequeue raw pkt data */
-	ret = 0;
-	while (ret < 1) {
-		ret = rte_rawdev_dequeue_buffers(dev_id, &d_buf[0], 1, &si);
-		rte_pause();
-	}
-
-	/* Validate the dequeued raw pkt data */
-	if (sdp_validate_data((struct sdp_droq_pkt *)d_buf[0],
-			      buf, buf_size) != 0) {
-		otx2_err("Data invalid");
-		rte_mempool_put(ioq_mpool,
-				((struct sdp_droq_pkt *)d_buf[0])->data);
-		rte_mempool_free(ioq_mpool);
-		rte_rawdev_close(dev_id);
-		return -EINVAL;
-	}
-
-	rte_mempool_put(ioq_mpool, ((struct sdp_droq_pkt *)d_buf[0])->data);
-	rte_mempool_free(ioq_mpool);
-	rte_rawdev_close(dev_id);
-
-	otx2_info("SDP RAWDEV Self Test: Successful");
-
-	return 0;
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.c b/drivers/raw/octeontx2_ep/otx2_ep_vf.c
deleted file mode 100644
index bf2a19e369..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-#include "otx2_ep_vf.h"
-
-static int
-sdp_vf_reset_iq(struct sdp_device *sdpvf, int q_no)
-{
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-	volatile uint64_t d64 = 0ull;
-
-	/* There is no RST for a ring.
-	 * Clear all registers one by one after disabling the ring
-	 */
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));
-
-	d64 = 0xFFFFFFFF; /* ~0ull */
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr +
-			     SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr +
-				  SDP_VF_R_IN_INSTR_DBELL(q_no));
-	}
-
-	loop = SDP_VF_BUSY_LOOP_COUNT;
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-	}
-
-	d64 = 0ull;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));
-
-	return 0;
-}
-
-static int
-sdp_vf_reset_oq(struct sdp_device *sdpvf, int q_no)
-{
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-	volatile uint64_t d64 = 0ull;
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));
-
-	d64 = 0xFFFFFFFF;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
-
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr +
-			     SDP_VF_R_OUT_SLIST_DBELL(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr +
-				  SDP_VF_R_OUT_SLIST_DBELL(q_no));
-	}
-
-	loop = SDP_VF_BUSY_LOOP_COUNT;
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-	while ((d64 != 0) && (loop--)) {
-		otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-	}
-
-	d64 = 0ull;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_global_iq_reg(struct sdp_device *sdpvf, int q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for IQs
-	 * IS_64B is by default enabled.
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
-
-	reg_val |= SDP_VF_R_IN_CTL_RDSIZE;
-	reg_val |= SDP_VF_R_IN_CTL_IS_64B;
-	reg_val |= SDP_VF_R_IN_CTL_ESR;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
-
-}
-
-static void
-sdp_vf_setup_global_oq_reg(struct sdp_device *sdpvf, int q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
-
-	reg_val |= (SDP_VF_R_OUT_CTL_IMODE);
-
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);
-
-	/* INFO/DATA ptr swap is required  */
-	reg_val |= (SDP_VF_R_OUT_CTL_ES_P);
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
-
-}
-
-static int
-sdp_vf_reset_input_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	otx2_sdp_dbg("%s :", __func__);
-
-	for (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)
-		sdp_vf_reset_iq(sdpvf, q_no);
-
-	return 0;
-}
-
-static int
-sdp_vf_reset_output_queues(struct sdp_device *sdpvf)
-{
-	uint64_t q_no = 0ull;
-
-	otx2_sdp_dbg(" %s :", __func__);
-
-	for (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)
-		sdp_vf_reset_oq(sdpvf, q_no);
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_global_input_regs(struct sdp_device *sdpvf)
-{
-	uint64_t q_no = 0ull;
-
-	sdp_vf_reset_input_queues(sdpvf);
-
-	for (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)
-		sdp_vf_setup_global_iq_reg(sdpvf, q_no);
-}
-
-static void
-sdp_vf_setup_global_output_regs(struct sdp_device *sdpvf)
-{
-	uint32_t q_no;
-
-	sdp_vf_reset_output_queues(sdpvf);
-
-	for (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)
-		sdp_vf_setup_global_oq_reg(sdpvf, q_no);
-
-}
-
-static int
-sdp_vf_setup_device_regs(struct sdp_device *sdpvf)
-{
-	sdp_vf_setup_global_input_regs(sdpvf);
-	sdp_vf_setup_global_output_regs(sdpvf);
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_iq_regs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq = sdpvf->instr_queue[iq_no];
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));
-
-	/* Wait till IDLE to set to 1, not supposed to configure BADDR
-	 * as long as IDLE is 0
-	 */
-	if (!(reg_val & SDP_VF_R_IN_CTL_IDLE)) {
-		do {
-			reg_val = otx2_read64(sdpvf->hw_addr +
-					      SDP_VF_R_IN_CONTROL(iq_no));
-		} while (!(reg_val & SDP_VF_R_IN_CTL_IDLE));
-	}
-
-	/* Write the start of the input queue's ring and its size  */
-	otx2_write64(iq->base_addr_dma, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_BADDR(iq_no));
-	otx2_write64(iq->nb_desc, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_RSIZE(iq_no));
-
-	/* Remember the doorbell & instruction count register addr
-	 * for this queue
-	 */
-	iq->doorbell_reg = (uint8_t *) sdpvf->hw_addr +
-			   SDP_VF_R_IN_INSTR_DBELL(iq_no);
-	iq->inst_cnt_reg = (uint8_t *) sdpvf->hw_addr +
-			   SDP_VF_R_IN_CNTS(iq_no);
-
-	otx2_sdp_dbg("InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p",
-		     iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
-
-	/* Store the current instrn counter(used in flush_iq calculation) */
-	iq->reset_instr_cnt = rte_read32(iq->inst_cnt_reg);
-
-	/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
-	 * to raise
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
-	reg_val = 0xffffffff;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
-
-}
-
-static void
-sdp_vf_setup_oq_regs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	volatile uint64_t reg_val = 0ull;
-	uint64_t oq_ctl = 0ull;
-
-	struct sdp_droq *droq = sdpvf->droq[oq_no];
-
-	/* Wait on IDLE to set to 1, supposed to configure BADDR
-	 * as log as IDLE is 0
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	while (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {
-		reg_val = otx2_read64(sdpvf->hw_addr +
-				      SDP_VF_R_OUT_CONTROL(oq_no));
-	}
-
-	otx2_write64(droq->desc_ring_dma, sdpvf->hw_addr +
-		     SDP_VF_R_OUT_SLIST_BADDR(oq_no));
-	otx2_write64(droq->nb_desc, sdpvf->hw_addr +
-		     SDP_VF_R_OUT_SLIST_RSIZE(oq_no));
-
-	oq_ctl = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	/* Clear the ISIZE and BSIZE (22-0) */
-	oq_ctl &= ~(0x7fffffull);
-
-	/* Populate the BSIZE (15-0) */
-	oq_ctl |= (droq->buffer_size & 0xffff);
-
-	/* Populate ISIZE(22-16) */
-	oq_ctl |= ((SDP_RH_SIZE << 16) & 0x7fffff);
-	otx2_write64(oq_ctl, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	/* Mapped address of the pkt_sent and pkts_credit regs */
-	droq->pkts_sent_reg = (uint8_t *) sdpvf->hw_addr +
-			      SDP_VF_R_OUT_CNTS(oq_no);
-	droq->pkts_credit_reg = (uint8_t *) sdpvf->hw_addr +
-				SDP_VF_R_OUT_SLIST_DBELL(oq_no);
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));
-
-	/* Clear PKT_CNT register */
-	rte_write64(0xFFFFFFFFF, (uint8_t *)sdpvf->hw_addr +
-		    SDP_VF_R_OUT_PKT_CNT(oq_no));
-
-	/* Clear the OQ doorbell  */
-	rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
-	while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
-		rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
-		rte_delay_ms(1);
-	}
-	otx2_sdp_dbg("SDP_R[%d]_credit:%x", oq_no,
-		     rte_read32(droq->pkts_credit_reg));
-
-	/* Clear the OQ_OUT_CNTS doorbell  */
-	reg_val = rte_read32(droq->pkts_sent_reg);
-	rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
-
-	otx2_sdp_dbg("SDP_R[%d]_sent: %x", oq_no,
-		     rte_read32(droq->pkts_sent_reg));
-
-	while (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {
-		reg_val = rte_read32(droq->pkts_sent_reg);
-		rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
-		rte_delay_ms(1);
-	}
-
-}
-
-static void
-sdp_vf_enable_iq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-
-	/* Resetting doorbells during IQ enabling also to handle abrupt
-	 * guest reboot. IQ reset does not clear the doorbells.
-	 */
-	otx2_write64(0xFFFFFFFF, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-	while (((otx2_read64(sdpvf->hw_addr +
-		 SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
-
-		rte_delay_ms(1);
-	}
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	reg_val |= 0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-
-	otx2_info("IQ[%d] enable done", q_no);
-
-}
-
-static void
-sdp_vf_enable_oq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-	reg_val |= 0x1ull;
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-	otx2_info("OQ[%d] enable done", q_no);
-}
-
-static void
-sdp_vf_enable_io_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	for (q_no = 0; q_no < sdpvf->num_iqs; q_no++)
-		sdp_vf_enable_iq(sdpvf, q_no);
-
-	for (q_no = 0; q_no < sdpvf->num_oqs; q_no++)
-		sdp_vf_enable_oq(sdpvf, q_no);
-}
-
-static void
-sdp_vf_disable_iq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	/* Reset the doorbell register for this Input Queue. */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	reg_val &= ~0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-}
-
-static void
-sdp_vf_disable_oq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-	reg_val &= ~0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-}
-
-static void
-sdp_vf_disable_io_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	/* Disable Input Queues. */
-	for (q_no = 0; q_no < sdpvf->num_iqs; q_no++)
-		sdp_vf_disable_iq(sdpvf, q_no);
-
-	/* Disable Output Queues. */
-	for (q_no = 0; q_no < sdpvf->num_oqs; q_no++)
-		sdp_vf_disable_oq(sdpvf, q_no);
-}
-
-static uint32_t
-sdp_vf_update_read_index(struct sdp_instr_queue *iq)
-{
-	uint32_t new_idx = rte_read32(iq->inst_cnt_reg);
-
-	/* The new instr cnt reg is a 32-bit counter that can roll over.
-	 * We have noted the counter's initial value at init time into
-	 * reset_instr_cnt
-	 */
-	if (iq->reset_instr_cnt < new_idx)
-		new_idx -= iq->reset_instr_cnt;
-	else
-		new_idx += (0xffffffff - iq->reset_instr_cnt) + 1;
-
-	/* Modulo of the new index with the IQ size will give us
-	 * the new index.
-	 */
-	new_idx %= iq->nb_desc;
-
-	return new_idx;
-}
-
-int
-sdp_vf_setup_device(struct sdp_device *sdpvf)
-{
-	uint64_t reg_val = 0ull;
-
-	/* If application doesn't provide its conf, use driver default conf */
-	if (sdpvf->conf == NULL) {
-		sdpvf->conf = sdp_get_defconf(sdpvf);
-		if (sdpvf->conf == NULL) {
-			otx2_err("SDP VF default config not found");
-			return -ENOMEM;
-		}
-		otx2_info("Default config is used");
-	}
-
-	/* Get IOQs (RPVF] count */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(0));
-
-	sdpvf->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
-					  & SDP_VF_R_IN_CTL_RPVF_MASK);
-
-	otx2_info("SDP RPVF: %d", sdpvf->sriov_info.rings_per_vf);
-
-	sdpvf->fn_list.setup_iq_regs       = sdp_vf_setup_iq_regs;
-	sdpvf->fn_list.setup_oq_regs       = sdp_vf_setup_oq_regs;
-
-	sdpvf->fn_list.setup_device_regs   = sdp_vf_setup_device_regs;
-	sdpvf->fn_list.update_iq_read_idx  = sdp_vf_update_read_index;
-
-	sdpvf->fn_list.enable_io_queues    = sdp_vf_enable_io_queues;
-	sdpvf->fn_list.disable_io_queues   = sdp_vf_disable_io_queues;
-
-	sdpvf->fn_list.enable_iq           = sdp_vf_enable_iq;
-	sdpvf->fn_list.disable_iq          = sdp_vf_disable_iq;
-
-	sdpvf->fn_list.enable_oq           = sdp_vf_enable_oq;
-	sdpvf->fn_list.disable_oq          = sdp_vf_disable_oq;
-
-
-	return 0;
-
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.h b/drivers/raw/octeontx2_ep/otx2_ep_vf.h
deleted file mode 100644
index 996f2e51eb..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-#ifndef _OTX2_EP_VF_H_
-#define _OTX2_EP_VF_H_
-
-int
-sdp_vf_setup_device(struct sdp_device *sdpvf);
-
-#endif /*_OTX2_EP_VF_H_ */
diff --git a/drivers/raw/octeontx2_ep/version.map b/drivers/raw/octeontx2_ep/version.map
deleted file mode 100644
index c2e0723b4c..0000000000
--- a/drivers/raw/octeontx2_ep/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_22 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH RESEND v4 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-23 15:21       ` [dpdk-dev] [PATCH RESEND v4 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
@ 2021-08-23 16:27         ` Radha Mohan
  2021-08-25  7:20           ` Thomas Monjalon
  0 siblings, 1 reply; 17+ messages in thread
From: Radha Mohan @ 2021-08-23 16:27 UTC (permalink / raw)
  To: Thomas Monjalon, David Marchand
  Cc: Veerasenareddy Burru, dpdk-dev, Satananda Burla,
	Jerin Jacob Kollanukkaran, Radha Mohan Chintakuntla

On Mon, Aug 23, 2021 at 8:51 PM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> Removing the rawdev based octeontx2-ep driver as the dependent
> common/octeontx2 will soon be going away. Moreover this driver is no
> longer required as the net/octeontx_ep driver is sufficient.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> Changes from v3:
> Fixed patch application failure due to conflict on main branch.
>
>
> Changes from v2:
> Fixed DPDK CI reported issues for more documentation failure.
>
> Changes from v1:
> Fixed compilation issues in documentation
>
>  MAINTAINERS                               |   6 -
>  doc/guides/rawdevs/index.rst              |   1 -
>  doc/guides/rawdevs/octeontx2_ep.rst       |  82 ---
>  drivers/raw/meson.build                   |   1 -
>  drivers/raw/octeontx2_ep/meson.build      |  11 -
>  drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------
>  drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h |  52 --
>  drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------
>  drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------
>  drivers/raw/octeontx2_ep/otx2_ep_test.c   | 172 -----
>  drivers/raw/octeontx2_ep/otx2_ep_vf.c     | 475 ------------
>  drivers/raw/octeontx2_ep/otx2_ep_vf.h     |  10 -
>  drivers/raw/octeontx2_ep/version.map      |   3 -
>  13 files changed, 2520 deletions(-)
>  delete mode 100644 doc/guides/rawdevs/octeontx2_ep.rst
>  delete mode 100644 drivers/raw/octeontx2_ep/meson.build
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_test.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.h
>  delete mode 100644 drivers/raw/octeontx2_ep/version.map
>

hi Thomas,

http://mails.dpdk.org/archives/test-report/2021-August/211681.html

This time it's failing in building release notes guide for 19.08 where
this driver was introduced first. Wouldn't release notes be built for
current ?
It would be odd to remove something from old release notes.

regards,
Radha Mohan

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH RESEND v4 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-23 16:27         ` Radha Mohan
@ 2021-08-25  7:20           ` Thomas Monjalon
  0 siblings, 0 replies; 17+ messages in thread
From: Thomas Monjalon @ 2021-08-25  7:20 UTC (permalink / raw)
  To: Radha Mohan Chintakuntla
  Cc: David Marchand, dev, Veerasenareddy Burru, dpdk-dev,
	Satananda Burla, Jerin Jacob Kollanukkaran, Radha Mohan

23/08/2021 18:27, Radha Mohan:
> >  MAINTAINERS                               |   6 -
> >  doc/guides/rawdevs/index.rst              |   1 -
> >  doc/guides/rawdevs/octeontx2_ep.rst       |  82 ---
> >  drivers/raw/meson.build                   |   1 -
> >  drivers/raw/octeontx2_ep/meson.build      |  11 -
> >  drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------
> >  drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h |  52 --
> >  drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------
> >  drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------
> >  drivers/raw/octeontx2_ep/otx2_ep_test.c   | 172 -----
> >  drivers/raw/octeontx2_ep/otx2_ep_vf.c     | 475 ------------
> >  drivers/raw/octeontx2_ep/otx2_ep_vf.h     |  10 -
> >  drivers/raw/octeontx2_ep/version.map      |   3 -
> >  13 files changed, 2520 deletions(-)

I see you missed updating the section "Removed Items"
of the current release notes.

> hi Thomas,
> 
> http://mails.dpdk.org/archives/test-report/2021-August/211681.html

doc/guides/rel_notes/release_19_08.rst:207:unknown document: ../rawdevs/octeontx2_dma

> This time it's failing in building release notes guide for 19.08 where
> this driver was introduced first.

It is failing on octeontx2_dma but should fail on octeontx2_ep in 20.02.

> Wouldn't release notes be built for current ?

No we have all release notes, and all are generated and published on dpdk.org.

> It would be odd to remove something from old release notes.

I suggest a simple fix in the old 20.02 release notes:
You can simply remove this line:
	See the :doc:`../rawdevs/octeontx2_ep` for more details on this new PMD.

Or if you want to keep it for completeness,
you can replace the link with a raw text ``rawdevs/octeontx2_ep``.




^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver
  2021-08-23 15:21     ` [dpdk-dev] [PATCH RESEND " Radha Mohan Chintakuntla
  2021-08-23 15:21       ` [dpdk-dev] [PATCH RESEND v4 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
@ 2021-08-26 10:50       ` Radha Mohan Chintakuntla
  2021-08-26 10:50         ` [dpdk-dev] [PATCH v5 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
  2021-10-18 16:36         ` [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver Thomas Monjalon
  1 sibling, 2 replies; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-26 10:50 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-dma driver as the dependent
common/octeontx2 will be soon be going away. Also a new DMA driver will
be coming in this place once the rte_dmadev library is in.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v4:
Replaced the reference to documentation in release notes to plain text.

Changes from v3:
Fixed patch application failure due to conflict on main branch.

Changes from v2:
Fixed DPDK CI reported issues for more documentation failure.

Changes from v1:
Fixed compilation issues in documentation

 MAINTAINERS                                 |   6 -
 doc/guides/platform/octeontx2.rst           |   3 -
 doc/guides/rawdevs/index.rst                |   1 -
 doc/guides/rawdevs/octeontx2_dma.rst        | 103 -----
 doc/guides/rel_notes/release_19_08.rst      |   2 +-
 drivers/raw/meson.build                     |   1 -
 drivers/raw/octeontx2_dma/meson.build       |  18 -
 drivers/raw/octeontx2_dma/otx2_dpi_msg.c    | 105 -----
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c | 441 --------------------
 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h | 197 ---------
 drivers/raw/octeontx2_dma/otx2_dpi_test.c   | 218 ----------
 drivers/raw/octeontx2_dma/version.map       |   3 -
 12 files changed, 1 insertion(+), 1097 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_dma.rst
 delete mode 100644 drivers/raw/octeontx2_dma/meson.build
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_msg.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_dma/otx2_dpi_test.c
 delete mode 100644 drivers/raw/octeontx2_dma/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 266f5ac1da..9f9aa37c68 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 DMA
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_dma/
-F: doc/guides/rawdevs/octeontx2_dma.rst
-
 Marvell OCTEON TX2 EP
 M: Radha Mohan Chintakuntla <radhac@marvell.com>
 M: Veerasenareddy Burru <vburru@marvell.com>
diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
index 8b5991f03b..3a3d28571c 100644
--- a/doc/guides/platform/octeontx2.rst
+++ b/doc/guides/platform/octeontx2.rst
@@ -152,9 +152,6 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
 #. **Event Device Driver**
    See :doc:`../eventdevs/octeontx2` for SSO event device driver information.
 
-#. **DMA Rawdev Driver**
-   See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
-
 #. **Crypto Device Driver**
    See :doc:`../cryptodevs/octeontx2` for CPT crypto device driver information.
 
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 7fbae40ea9..228d4a7743 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,5 +17,4 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_dma
     octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_dma.rst b/doc/guides/rawdevs/octeontx2_dma.rst
deleted file mode 100644
index 6887da5278..0000000000
--- a/doc/guides/rawdevs/octeontx2_dma.rst
+++ /dev/null
@@ -1,103 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-OCTEON TX2 DMA Driver
-=====================
-
-OCTEON TX2 has an internal DMA unit which can be used by applications to initiate
-DMA transaction internally, from/to host when OCTEON TX2 operates in PCIe End
-Point mode. The DMA PF function supports 8 VFs corresponding to 8 DMA queues.
-Each DMA queue was exposed as a VF function when SRIOV enabled.
-
-Features
---------
-
-This DMA PMD supports below 3 modes of memory transfers
-
-#. Internal - OCTEON TX2 DRAM to DRAM without core intervention
-
-#. Inbound  - Host DRAM to OCTEON TX2 DRAM without host/OCTEON TX2 cores involvement
-
-#. Outbound - OCTEON TX2 DRAM to Host DRAM without host/OCTEON TX2 cores involvement
-
-Prerequisites and Compilation procedure
----------------------------------------
-
-   See :doc:`../platform/octeontx2` for setup information.
-
-
-Enabling logs
--------------
-
-For enabling logs, use the following EAL parameter:
-
-.. code-block:: console
-
-   ./your_dma_application <EAL args> --log-level=pmd.raw.octeontx2.dpi,<level>
-
-Using ``pmd.raw.octeontx2.dpi`` as log matching criteria, all Event PMD logs
-can be enabled which are lower than logging ``level``.
-
-Initialization
---------------
-
-The number of DMA VFs (queues) enabled can be controlled by setting sysfs
-entry, `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-dpi/0000\:05\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
--------------
-
-The OCTEON TX2 DPI DMA HW devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring DMA rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to submit DMA
-commands to HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct dpi_rawdev_conf_s conf = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &conf};
-
-   conf.chunk_pool = (void *)rte_mempool_create_empty(...);
-   rte_mempool_set_ops_byname(conf.chunk_pool, rte_mbuf_platform_mempool_ops(), NULL);
-   rte_mempool_populate_default(conf.chunk_pool);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info, sizeof(conf));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using OCTEON TX2 DMA rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, dma devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("DPI:x")`` from the application
-  where x is the VF device's bus id specified in "bus:device.func" format. Use this
-  index for further rawdev function calls.
-
-* This PMD supports driver self test, to test DMA internal mode from test
-  application one can directly calls
-  ``rte_rawdev_selftest(rte_rawdev_get_dev_id("DPI:x"))``
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index d2baa828b1..4db7de4096 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -204,7 +204,7 @@ New Features
   * :doc:`../nics/octeontx2`
   * :doc:`../mempool/octeontx2`
   * :doc:`../eventdevs/octeontx2`
-  * :doc:`../rawdevs/octeontx2_dma`
+  * :doc:``../rawdevs/octeontx2_dma``
 
 * **Introduced the Intel NTB PMD.**
 
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index b51536f8a7..f25d5f322c 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_dma',
         'octeontx2_ep',
         'skeleton',
 ]
diff --git a/drivers/raw/octeontx2_dma/meson.build b/drivers/raw/octeontx2_dma/meson.build
deleted file mode 100644
index e744fccaae..0000000000
--- a/drivers/raw/octeontx2_dma/meson.build
+++ /dev/null
@@ -1,18 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files('otx2_dpi_rawdev.c', 'otx2_dpi_msg.c', 'otx2_dpi_test.c')
-
-extra_flags = []
-# This integrated controller runs only on a arm64 machine, remove 32bit warnings
-if not dpdk_conf.get('RTE_ARCH_64')
-    extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
-endif
-
-foreach flag: extra_flags
-    if cc.has_argument(flag)
-        cflags += flag
-    endif
-endforeach
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c b/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
deleted file mode 100644
index 655de216ab..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_msg.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_MSG_H_
-#define _DPI_MSG_H_
-
-#include <dirent.h>
-#include <fcntl.h>
-#include <string.h>
-#include <unistd.h>
-
-#include "otx2_dpi_rawdev.h"
-
-/* DPI PF DBDF information macro's */
-#define DPI_PF_DBDF_DOMAIN      0
-#define DPI_PF_DBDF_BUS         5
-#define DPI_PF_DBDF_DEVICE      0
-#define DPI_PF_DBDF_FUNCTION    0
-
-#define DPI_PF_MBOX_SYSFS_ENTRY "dpi_device_config"
-
-union dpi_mbox_message_u {
-	uint64_t u[2];
-	struct dpi_mbox_message_s {
-		/* VF ID to configure */
-		uint64_t vfid           :4;
-		/* Command code */
-		uint64_t cmd            :4;
-		/* Command buffer size in 8-byte words */
-		uint64_t csize          :14;
-		/* aura of the command buffer */
-		uint64_t aura           :20;
-		/* SSO PF function */
-		uint64_t sso_pf_func    :16;
-		/* NPA PF function */
-		uint64_t npa_pf_func    :16;
-	} s;
-};
-
-static inline int
-send_msg_to_pf(struct rte_pci_addr *pci, const char *value, int size)
-{
-	char buff[255] = { 0 };
-	int res, fd;
-
-	res = snprintf(buff, sizeof(buff), "%s/" PCI_PRI_FMT "/%s",
-		       rte_pci_get_sysfs_path(), pci->domain,
-		       pci->bus, DPI_PF_DBDF_DEVICE & 0x7,
-		       DPI_PF_DBDF_FUNCTION & 0x7, DPI_PF_MBOX_SYSFS_ENTRY);
-	if ((res < 0) || ((size_t)res > sizeof(buff)))
-		return -ERANGE;
-
-	fd = open(buff, O_WRONLY);
-	if (fd < 0)
-		return -EACCES;
-	res = write(fd, value, size);
-	close(fd);
-	if (res < 0)
-		return -EACCES;
-
-	return 0;
-}
-
-int
-otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_OPEN;
-	mbox_msg.s.csize = size;
-	mbox_msg.s.aura = gaura;
-	mbox_msg.s.sso_pf_func = otx2_sso_pf_func_get();
-	mbox_msg.s.npa_pf_func = otx2_npa_pf_func_get();
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-int
-otx2_dpi_queue_close(struct dpi_vf_s *dpivf)
-{
-	union dpi_mbox_message_u mbox_msg;
-	int ret = 0;
-
-	/* DPI PF driver expects vfid starts from index 0 */
-	mbox_msg.s.vfid = dpivf->vf_id;
-	mbox_msg.s.cmd = DPI_QUEUE_CLOSE;
-
-	ret = send_msg_to_pf(&dpivf->dev->addr, (const char *)&mbox_msg,
-				sizeof(mbox_msg));
-	if (ret < 0)
-		otx2_dpi_dbg("Failed to send mbox message to dpi pf");
-
-	return ret;
-}
-
-#endif /* _DPI_MSG_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
deleted file mode 100644
index 8c01f25ec7..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
+++ /dev/null
@@ -1,441 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include <otx2_common.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static const struct rte_pci_id pci_dma_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_DPI_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* Enable/Disable DMA queue */
-static inline int
-dma_engine_enb_dis(struct dpi_vf_s *dpivf, const bool enb)
-{
-	if (enb)
-		otx2_write64(0x1, dpivf->vf_bar0 + DPI_VDMA_EN);
-	else
-		otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Free DMA Queue instruction buffers, and send close notification to PF */
-static inline int
-dma_queue_finish(struct dpi_vf_s *dpivf)
-{
-	uint32_t timeout = 0, sleep = 1;
-	uint64_t reg = 0ULL;
-
-	/* Wait for SADDR to become idle */
-	reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	while (!(reg & BIT_ULL(DPI_VDMA_SADDR_REQ_IDLE))) {
-		rte_delay_ms(sleep);
-		timeout++;
-		if (timeout >= DPI_QFINISH_TIMEOUT) {
-			otx2_dpi_dbg("Timeout!!! Closing Forcibly");
-			break;
-		}
-		reg = otx2_read64(dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	}
-
-	if (otx2_dpi_queue_close(dpivf) < 0)
-		return -EACCES;
-
-	rte_mempool_put(dpivf->chunk_pool, dpivf->base_ptr);
-	dpivf->vf_bar0 = (uintptr_t)NULL;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Write an arbitrary number of command words to a command queue */
-static __rte_always_inline enum dpi_dma_queue_result_e
-dma_queue_write(struct dpi_vf_s *dpi, uint16_t cmd_count, uint64_t *cmds)
-{
-	if ((cmd_count < 1) || (cmd_count > 64))
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	if (cmds == NULL)
-		return DPI_DMA_QUEUE_INVALID_PARAM;
-
-	/* Room available in the current buffer for the command */
-	if (dpi->index + cmd_count < dpi->pool_size_m1) {
-		uint64_t *ptr = dpi->base_ptr;
-
-		ptr += dpi->index;
-		dpi->index += cmd_count;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-	} else {
-		void *new_buffer;
-		uint64_t *ptr;
-		int count;
-
-		/* Allocate new command buffer, return if failed */
-		if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-		    new_buffer == NULL) {
-			return DPI_DMA_QUEUE_NO_MEMORY;
-		}
-		ptr = dpi->base_ptr;
-		/* Figure out how many command words will fit in this buffer.
-		 * One location will be needed for the next buffer pointer.
-		 **/
-		count = dpi->pool_size_m1 - dpi->index;
-		ptr += dpi->index;
-		cmd_count -= count;
-		while (count--)
-			*ptr++ = *cmds++;
-		/* Chunk next ptr is 2DWORDs, second DWORD is reserved. */
-		*ptr++ = (uint64_t)new_buffer;
-		*ptr   = 0;
-		/* The current buffer is full and has a link to the next buffer.
-		 * Time to write the rest of the commands into the new buffer.
-		 **/
-		dpi->base_ptr = new_buffer;
-		dpi->index = cmd_count;
-		ptr = new_buffer;
-		while (cmd_count--)
-			*ptr++ = *cmds++;
-		/* queue index may greater than pool size */
-		if (dpi->index >= dpi->pool_size_m1) {
-			if (rte_mempool_get(dpi->chunk_pool, &new_buffer) ||
-			    new_buffer == NULL) {
-				return DPI_DMA_QUEUE_NO_MEMORY;
-			}
-			/* Write next buffer address */
-			*ptr = (uint64_t)new_buffer;
-			dpi->base_ptr = new_buffer;
-			dpi->index = 0;
-		}
-	}
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-/* Submit a DMA command to the DMA queues. */
-static __rte_always_inline int
-dma_queue_submit(struct rte_rawdev *dev, uint16_t cmd_count, uint64_t *cmds)
-{
-	struct dpi_vf_s *dpivf = dev->dev_private;
-	enum dpi_dma_queue_result_e result;
-
-	result = dma_queue_write(dpivf, cmd_count, cmds);
-	rte_wmb();
-	if (likely(result == DPI_DMA_QUEUE_SUCCESS))
-		otx2_write64((uint64_t)cmd_count,
-			     dpivf->vf_bar0 + DPI_VDMA_DBELL);
-
-	return result;
-}
-
-/* Enqueue buffers to DMA queue
- * returns number of buffers enqueued successfully
- */
-static int
-otx2_dpi_rawdev_enqueue_bufs(struct rte_rawdev *dev,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	struct dpi_dma_buf_ptr_s *cmd;
-	uint32_t c = 0;
-
-	for (c = 0; c < count; c++) {
-		uint64_t dpi_cmd[DPI_DMA_CMD_SIZE] = {0};
-		union dpi_dma_instr_hdr_u *hdr;
-		uint16_t index = 0, i;
-
-		hdr = (union dpi_dma_instr_hdr_u *)&dpi_cmd[0];
-		cmd = (struct dpi_dma_buf_ptr_s *)buffers[c]->buf_addr;
-
-		hdr->s.xtype = ctx->xtype & DPI_XTYPE_MASK;
-		hdr->s.pt = ctx->pt & DPI_HDR_PT_MASK;
-		/* Request initiated with byte write completion, but completion
-		 * pointer not provided
-		 */
-		if ((hdr->s.pt == DPI_HDR_PT_ZBW_CA ||
-		     hdr->s.pt == DPI_HDR_PT_ZBW_NC) && cmd->comp_ptr == NULL)
-			return c;
-
-		cmd->comp_ptr->cdata = DPI_REQ_CDATA;
-		hdr->s.ptr = (uint64_t)cmd->comp_ptr;
-		hdr->s.deallocv = ctx->deallocv;
-		hdr->s.tt = ctx->tt & DPI_W0_TT_MASK;
-		hdr->s.grp = ctx->grp & DPI_W0_GRP_MASK;
-
-		/* If caller provides completion ring details, then only queue
-		 * completion address for later polling.
-		 */
-		if (ctx->c_ring) {
-			ctx->c_ring->compl_data[ctx->c_ring->tail] =
-								 cmd->comp_ptr;
-			STRM_INC(ctx->c_ring);
-		}
-
-		if (hdr->s.deallocv)
-			hdr->s.pvfe = 1;
-
-		if (hdr->s.pt == DPI_HDR_PT_WQP)
-			hdr->s.ptr = hdr->s.ptr | DPI_HDR_PT_WQP_STATUSNC;
-
-		index += 4;
-		hdr->s.fport = 0;
-		hdr->s.lport = 0;
-		if (ctx->xtype !=  DPI_XTYPE_INTERNAL_ONLY)
-			hdr->s.lport = ctx->pem_id;
-
-		/* For inbound case, src pointers are last pointers.
-		 * For all other cases, src pointers are first pointers.
-		 */
-		if (ctx->xtype ==  DPI_XTYPE_INBOUND) {
-			hdr->s.nfst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-		} else {
-			hdr->s.nfst = cmd->rptr_cnt & DPI_MAX_POINTER;
-			hdr->s.nlst = cmd->wptr_cnt & DPI_MAX_POINTER;
-			for (i = 0; i < hdr->s.nfst; i++) {
-				dpi_cmd[index++] = cmd->rptr[i]->u[0];
-				dpi_cmd[index++] = cmd->rptr[i]->u[1];
-			}
-			for (i = 0; i < hdr->s.nlst; i++) {
-				dpi_cmd[index++] = cmd->wptr[i]->u[0];
-				dpi_cmd[index++] = cmd->wptr[i]->u[1];
-			}
-		}
-		if (dma_queue_submit(dev, index, dpi_cmd))
-			return c;
-	}
-	return c;
-}
-
-/* Check for command completion, returns number of commands completed */
-static int
-otx2_dpi_rawdev_dequeue_bufs(struct rte_rawdev *dev __rte_unused,
-			     struct rte_rawdev_buf **buffers,
-			     unsigned int count, rte_rawdev_obj_t context)
-{
-	struct dpi_dma_queue_ctx_s *ctx = (struct dpi_dma_queue_ctx_s *)context;
-	unsigned int i = 0, headp;
-
-	/* No completion ring to poll */
-	if (ctx->c_ring == NULL)
-		return 0;
-
-	headp = ctx->c_ring->head;
-	for (i = 0; i < count && (headp != ctx->c_ring->tail); i++) {
-		struct dpi_dma_req_compl_s *comp_ptr =
-					 ctx->c_ring->compl_data[headp];
-
-		if (comp_ptr->cdata)
-			break;
-
-		/* Request Completed */
-		buffers[i] = (void *)comp_ptr;
-		headp = (headp + 1) % ctx->c_ring->max_cnt;
-	}
-	ctx->c_ring->head = headp;
-
-	return i;
-}
-
-static int
-otx2_dpi_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_START;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static void
-otx2_dpi_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = DPI_QUEUE_STOP;
-}
-
-static int
-otx2_dpi_rawdev_close(struct rte_rawdev *dev)
-{
-	dma_engine_enb_dis(dev->dev_private, false);
-	dma_queue_finish(dev->dev_private);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_reset(struct rte_rawdev *dev)
-{
-	return dev ? DPI_QUEUE_STOP : DPI_QUEUE_START;
-}
-
-static int
-otx2_dpi_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct dpi_rawdev_conf_s *conf = config;
-	struct dpi_vf_s *dpivf = NULL;
-	void *buf = NULL;
-	uintptr_t pool;
-	uint32_t gaura;
-
-	if (conf == NULL || config_size != sizeof(*conf)) {
-		otx2_dpi_dbg("NULL or invalid configuration");
-		return -EINVAL;
-	}
-	dpivf = (struct dpi_vf_s *)dev->dev_private;
-	dpivf->chunk_pool = conf->chunk_pool;
-	if (rte_mempool_get(conf->chunk_pool, &buf) || (buf == NULL)) {
-		otx2_err("Unable allocate buffer");
-		return -ENODEV;
-	}
-	dpivf->base_ptr = buf;
-	otx2_write64(0x0, dpivf->vf_bar0 + DPI_VDMA_EN);
-	dpivf->pool_size_m1 = (DPI_CHUNK_SIZE >> 3) - 2;
-	pool = (uintptr_t)((struct rte_mempool *)conf->chunk_pool)->pool_id;
-	gaura = npa_lf_aura_handle_to_aura(pool);
-	otx2_write64(0, dpivf->vf_bar0 + DPI_VDMA_REQQ_CTL);
-	otx2_write64(((uint64_t)buf >> 7) << 7,
-		     dpivf->vf_bar0 + DPI_VDMA_SADDR);
-	if (otx2_dpi_queue_open(dpivf, DPI_CHUNK_SIZE, gaura) < 0) {
-		otx2_err("Unable to open DPI VF %d", dpivf->vf_id);
-		rte_mempool_put(conf->chunk_pool, buf);
-		return -EACCES;
-	}
-	dma_engine_enb_dis(dpivf, true);
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static const struct rte_rawdev_ops dpi_rawdev_ops = {
-	.dev_configure = otx2_dpi_rawdev_configure,
-	.dev_start = otx2_dpi_rawdev_start,
-	.dev_stop = otx2_dpi_rawdev_stop,
-	.dev_close = otx2_dpi_rawdev_close,
-	.dev_reset = otx2_dpi_rawdev_reset,
-	.enqueue_bufs = otx2_dpi_rawdev_enqueue_bufs,
-	.dequeue_bufs = otx2_dpi_rawdev_dequeue_bufs,
-	.dev_selftest = test_otx2_dma_rawdev,
-};
-
-static int
-otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct dpi_vf_s *dpivf = NULL;
-	struct rte_rawdev *rawdev;
-	uint16_t vf_id;
-
-	/* For secondary processes, the primary has done all the work */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return DPI_DMA_QUEUE_SUCCESS;
-
-	if (pci_dev->mem_resource[0].addr == NULL) {
-		otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr,
-			     pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate device structure */
-	rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct dpi_vf_s),
-					 rte_socket_id());
-	if (rawdev == NULL) {
-		otx2_err("Rawdev allocation failed");
-		return -EINVAL;
-	}
-
-	rawdev->dev_ops = &dpi_rawdev_ops;
-	rawdev->device = &pci_dev->device;
-	rawdev->driver_name = pci_dev->driver->driver.name;
-
-	dpivf = rawdev->dev_private;
-	if (dpivf->state != DPI_QUEUE_STOP) {
-		otx2_dpi_dbg("Device already started!!!");
-		return -ENODEV;
-	}
-
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-	vf_id -= 1;
-	dpivf->dev = pci_dev;
-	dpivf->state = DPI_QUEUE_START;
-	dpivf->vf_id = vf_id;
-	dpivf->vf_bar0 = (uintptr_t)pci_dev->mem_resource[0].addr;
-	dpivf->vf_bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
-
-	return DPI_DMA_QUEUE_SUCCESS;
-}
-
-static int
-otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct dpi_vf_s *dpivf;
-
-	if (pci_dev == NULL) {
-		otx2_dpi_dbg("Invalid pci_dev of the device!");
-		return -EINVAL;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_dpi_dbg("Invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	dpivf = (struct dpi_vf_s *)rawdev->dev_private;
-	dma_engine_enb_dis(dpivf, false);
-	dma_queue_finish(dpivf);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_dpi_rawdev_pmd = {
-	.id_table  = pci_dma_map,
-	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
-	.probe     = otx2_dpi_rawdev_probe,
-	.remove    = otx2_dpi_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(dpi_rawdev_pci_driver, rte_dpi_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(dpi_rawdev_pci_driver, pci_dma_map);
-RTE_PMD_REGISTER_KMOD_DEP(dpi_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h b/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
deleted file mode 100644
index 2bc9e3da3c..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_rawdev.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _DPI_RAWDEV_H_
-#define _DPI_RAWDEV_H_
-
-#include "otx2_common.h"
-#include "otx2_mempool.h"
-
-#define DPI_QUEUE_OPEN	0x1
-#define DPI_QUEUE_CLOSE	0x2
-
-/* DPI VF register offsets from VF_BAR0 */
-#define DPI_VDMA_EN             (0x0)
-#define DPI_VDMA_REQQ_CTL       (0x8)
-#define DPI_VDMA_DBELL          (0x10)
-#define DPI_VDMA_SADDR          (0x18)
-#define DPI_VDMA_COUNTS         (0x20)
-#define DPI_VDMA_NADDR          (0x28)
-#define DPI_VDMA_IWBUSY         (0x30)
-#define DPI_VDMA_CNT            (0x38)
-#define DPI_VF_INT              (0x100)
-#define DPI_VF_INT_W1S          (0x108)
-#define DPI_VF_INT_ENA_W1C      (0x110)
-#define DPI_VF_INT_ENA_W1S      (0x118)
-
-#define DPI_MAX_VFS             8
-#define DPI_DMA_CMD_SIZE        64
-#define DPI_CHUNK_SIZE		1024
-#define DPI_QUEUE_STOP		0x0
-#define DPI_QUEUE_START		0x1
-
-#define DPI_VDMA_SADDR_REQ_IDLE	63
-#define DPI_MAX_POINTER		15
-#define STRM_INC(s)	((s)->tail = ((s)->tail + 1) % (s)->max_cnt)
-#define DPI_QFINISH_TIMEOUT	(10 * 1000)
-
-/* DPI Transfer Type, pointer type in DPI_DMA_INSTR_HDR_S[XTYPE] */
-#define DPI_XTYPE_OUTBOUND      (0)
-#define DPI_XTYPE_INBOUND       (1)
-#define DPI_XTYPE_INTERNAL_ONLY (2)
-#define DPI_XTYPE_EXTERNAL_ONLY (3)
-#define DPI_XTYPE_MASK		0x3
-#define DPI_HDR_PT_ZBW_CA	0x0
-#define DPI_HDR_PT_ZBW_NC	0x1
-#define DPI_HDR_PT_WQP		0x2
-#define DPI_HDR_PT_WQP_NOSTATUS	0x0
-#define DPI_HDR_PT_WQP_STATUSCA	0x1
-#define DPI_HDR_PT_WQP_STATUSNC	0x3
-#define DPI_HDR_PT_CNT		0x3
-#define DPI_HDR_PT_MASK		0x3
-#define DPI_W0_TT_MASK		0x3
-#define DPI_W0_GRP_MASK		0x3FF
-/* Set Completion data to 0xFF when request submitted,
- * upon successful request completion engine reset to completion status
- */
-#define DPI_REQ_CDATA		0xFF
-
-struct dpi_vf_s {
-	struct rte_pci_device *dev;
-	uint8_t state;
-	uint16_t vf_id;
-	uint8_t domain;
-	uintptr_t vf_bar0;
-	uintptr_t vf_bar2;
-
-	uint16_t pool_size_m1;
-	uint16_t index;
-	uint64_t *base_ptr;
-	void *chunk_pool;
-	struct otx2_mbox *mbox;
-};
-
-struct dpi_rawdev_conf_s {
-	void *chunk_pool;
-};
-
-enum dpi_dma_queue_result_e {
-	DPI_DMA_QUEUE_SUCCESS = 0,
-	DPI_DMA_QUEUE_NO_MEMORY = -1,
-	DPI_DMA_QUEUE_INVALID_PARAM = -2,
-};
-
-struct dpi_dma_req_compl_s {
-	uint64_t cdata;
-	void (*compl_cb)(void *dev, void *arg);
-	void *cb_data;
-};
-
-union dpi_dma_ptr_u {
-	uint64_t u[2];
-	struct dpi_dma_s {
-		uint64_t length:16;
-		uint64_t reserved:44;
-		uint64_t bed:1; /* Big-Endian */
-		uint64_t alloc_l2:1;
-		uint64_t full_write:1;
-		uint64_t invert:1;
-		uint64_t ptr;
-	} s;
-};
-
-struct dpi_dma_buf_ptr_s {
-	union dpi_dma_ptr_u *rptr[DPI_MAX_POINTER]; /* Read From pointer list */
-	union dpi_dma_ptr_u *wptr[DPI_MAX_POINTER]; /* Write to pointer list */
-	uint8_t rptr_cnt;
-	uint8_t wptr_cnt;
-	struct dpi_dma_req_compl_s *comp_ptr;
-};
-
-struct dpi_cring_data_s {
-	struct dpi_dma_req_compl_s **compl_data;
-	uint16_t max_cnt;
-	uint16_t head;
-	uint16_t tail;
-};
-
-struct dpi_dma_queue_ctx_s {
-	uint16_t xtype:2;
-
-	/* Completion pointer type */
-	uint16_t pt:2;
-
-	/* Completion updated using WQE */
-	uint16_t tt:2;
-	uint16_t grp:10;
-	uint32_t tag;
-
-	/* Valid only for Outbound only mode */
-	uint16_t aura:12;
-	uint16_t csel:1;
-	uint16_t ca:1;
-	uint16_t fi:1;
-	uint16_t ii:1;
-	uint16_t fl:1;
-
-	uint16_t pvfe:1;
-	uint16_t dealloce:1;
-	uint16_t req_type:2;
-	uint16_t use_lock:1;
-	uint16_t deallocv;
-	uint16_t  pem_id;
-
-	struct dpi_cring_data_s *c_ring;
-};
-
-/* DPI DMA Instruction Header Format */
-union dpi_dma_instr_hdr_u {
-	uint64_t u[4];
-
-	struct dpi_dma_instr_hdr_s_s {
-		uint64_t tag:32;
-		uint64_t tt:2;
-		uint64_t grp:10;
-		uint64_t reserved_44_47:4;
-		uint64_t nfst:4;
-		uint64_t reserved_52_53:2;
-		uint64_t nlst:4;
-		uint64_t reserved_58_63:6;
-		/* Word 0 - End */
-
-		uint64_t aura:12;
-		uint64_t reserved_76_79:4;
-		uint64_t deallocv:16;
-		uint64_t dealloce:1;
-		uint64_t pvfe:1;
-		uint64_t reserved_98_99:2;
-		uint64_t pt:2;
-		uint64_t reserved_102_103:2;
-		uint64_t fl:1;
-		uint64_t ii:1;
-		uint64_t fi:1;
-		uint64_t ca:1;
-		uint64_t csel:1;
-		uint64_t reserved_109_111:3;
-		uint64_t xtype:2;
-		uint64_t reserved_114_119:6;
-		uint64_t fport:2;
-		uint64_t reserved_122_123:2;
-		uint64_t lport:2;
-		uint64_t reserved_126_127:2;
-		/* Word 1 - End */
-
-		uint64_t ptr:64;
-		/* Word 2 - End */
-
-		uint64_t reserved_192_255:64;
-		/* Word 3 - End */
-	} s;
-};
-
-int otx2_dpi_queue_open(struct dpi_vf_s *dpivf, uint32_t size, uint32_t gaura);
-int otx2_dpi_queue_close(struct dpi_vf_s *dpivf);
-int test_otx2_dma_rawdev(uint16_t val);
-
-#endif /* _DPI_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_dma/otx2_dpi_test.c b/drivers/raw/octeontx2_dma/otx2_dpi_test.c
deleted file mode 100644
index cec6ca91b0..0000000000
--- a/drivers/raw/octeontx2_dma/otx2_dpi_test.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_debug.h>
-#include <rte_eal.h>
-#include <rte_log.h>
-#include <rte_malloc.h>
-#include <rte_mbuf.h>
-#include <rte_mbuf_pool_ops.h>
-#include <rte_memcpy.h>
-#include <rte_memory.h>
-#include <rte_mempool.h>
-#include <rte_per_lcore.h>
-#include <rte_rawdev.h>
-
-#include "otx2_dpi_rawdev.h"
-
-static struct dpi_cring_data_s cring;
-
-static uint8_t
-buffer_fill(uint8_t *addr, int len, uint8_t val)
-{
-	int j = 0;
-
-	memset(addr, 0, len);
-	for (j = 0; j < len; j++)
-		*(addr + j) = val++;
-
-	return val;
-}
-
-static int
-validate_buffer(uint8_t *saddr, uint8_t *daddr, int len)
-{
-	int j = 0, ret = 0;
-
-	for (j = 0; j < len; j++) {
-		if (*(saddr + j) != *(daddr + j)) {
-			otx2_dpi_dbg("FAIL: Data Integrity failed");
-			otx2_dpi_dbg("index: %d, Expected: 0x%x, Actual: 0x%x",
-				     j, *(saddr + j), *(daddr + j));
-			ret = -1;
-			break;
-		}
-	}
-
-	return ret;
-}
-
-static inline int
-dma_test_internal(int dma_port, int buf_size)
-{
-	struct dpi_dma_req_compl_s *comp_data;
-	struct dpi_dma_queue_ctx_s ctx = {0};
-	struct rte_rawdev_buf buf = {0};
-	struct rte_rawdev_buf *d_buf[1];
-	struct rte_rawdev_buf *bufp[1];
-	struct dpi_dma_buf_ptr_s cmd;
-	union dpi_dma_ptr_u rptr = { {0} };
-	union dpi_dma_ptr_u wptr = { {0} };
-	uint8_t *fptr, *lptr;
-	int ret;
-
-	fptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	lptr = (uint8_t *)rte_malloc("dummy", buf_size, 128);
-	comp_data = rte_malloc("dummy", buf_size, 128);
-	if (fptr == NULL || lptr == NULL || comp_data == NULL) {
-		otx2_dpi_dbg("Unable to allocate internal memory");
-		return -ENOMEM;
-	}
-
-	buffer_fill(fptr, buf_size, 0);
-	memset(&cmd, 0, sizeof(struct dpi_dma_buf_ptr_s));
-	memset(lptr, 0, buf_size);
-	memset(comp_data, 0, buf_size);
-	rptr.s.ptr = (uint64_t)fptr;
-	rptr.s.length = buf_size;
-	wptr.s.ptr = (uint64_t)lptr;
-	wptr.s.length = buf_size;
-	cmd.rptr[0] = &rptr;
-	cmd.wptr[0] = &wptr;
-	cmd.rptr_cnt = 1;
-	cmd.wptr_cnt = 1;
-	cmd.comp_ptr = comp_data;
-	buf.buf_addr = (void *)&cmd;
-	bufp[0] = &buf;
-
-	ctx.xtype = DPI_XTYPE_INTERNAL_ONLY;
-	ctx.pt = 0;
-	ctx.c_ring = &cring;
-
-	ret = rte_rawdev_enqueue_buffers(dma_port,
-					 (struct rte_rawdev_buf **)bufp, 1,
-					 &ctx);
-	if (ret < 0) {
-		otx2_dpi_dbg("Enqueue request failed");
-		return 0;
-	}
-
-	/* Wait and dequeue completion */
-	do {
-		sleep(1);
-		ret = rte_rawdev_dequeue_buffers(dma_port, &d_buf[0], 1, &ctx);
-		if (ret)
-			break;
-
-		otx2_dpi_dbg("Dequeue request not completed");
-	} while (1);
-
-	if (validate_buffer(fptr, lptr, buf_size)) {
-		otx2_dpi_dbg("DMA transfer failed\n");
-		return -EAGAIN;
-	}
-	otx2_dpi_dbg("Internal Only DMA transfer successfully completed");
-
-	if (lptr)
-		rte_free(lptr);
-	if (fptr)
-		rte_free(fptr);
-	if (comp_data)
-		rte_free(comp_data);
-
-	return 0;
-}
-
-static void *
-dpi_create_mempool(void)
-{
-	void *chunk_pool = NULL;
-	char pool_name[25];
-	int ret;
-
-	snprintf(pool_name, sizeof(pool_name), "dpi_chunk_pool");
-
-	chunk_pool = (void *)rte_mempool_create_empty(pool_name, 1024, 1024,
-						      0, 0, rte_socket_id(), 0);
-	if (chunk_pool == NULL) {
-		otx2_dpi_dbg("Unable to create memory pool.");
-		return NULL;
-	}
-
-	ret = rte_mempool_set_ops_byname(chunk_pool,
-					 rte_mbuf_platform_mempool_ops(), NULL);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to set pool ops");
-		rte_mempool_free(chunk_pool);
-		return NULL;
-	}
-
-	ret = rte_mempool_populate_default(chunk_pool);
-	if (ret < 0) {
-		otx2_dpi_dbg("Unable to populate pool");
-		return NULL;
-	}
-
-	return chunk_pool;
-}
-
-int
-test_otx2_dma_rawdev(uint16_t val)
-{
-	struct rte_rawdev_info rdev_info = {0};
-	struct dpi_rawdev_conf_s conf = {0};
-	int ret, i, size = 1024;
-	int nb_ports;
-
-	RTE_SET_USED(val);
-	nb_ports = rte_rawdev_count();
-	if (nb_ports == 0) {
-		otx2_dpi_dbg("No Rawdev ports - bye");
-		return -ENODEV;
-	}
-
-	i = rte_rawdev_get_dev_id("DPI:5:00.1");
-	/* Configure rawdev ports */
-	conf.chunk_pool = dpi_create_mempool();
-	rdev_info.dev_private = &conf;
-	ret = rte_rawdev_configure(i, (rte_rawdev_obj_t)&rdev_info,
-			sizeof(conf));
-	if (ret) {
-		otx2_dpi_dbg("Unable to configure DPIVF %d", i);
-		return -ENODEV;
-	}
-	otx2_dpi_dbg("rawdev %d configured successfully", i);
-
-	/* Each stream allocate its own completion ring data, store it in
-	 * application context. Each stream needs to use same application
-	 * context for enqueue/dequeue.
-	 */
-	cring.compl_data = rte_malloc("dummy", sizeof(void *) * 1024, 128);
-	if (!cring.compl_data) {
-		otx2_dpi_dbg("Completion allocation failed");
-		return -ENOMEM;
-	}
-
-	cring.max_cnt = 1024;
-	cring.head = 0;
-	cring.tail = 0;
-
-	ret = dma_test_internal(i, size);
-	if (ret)
-		otx2_dpi_dbg("DMA transfer failed for queue %d", i);
-
-	if (rte_rawdev_close(i))
-		otx2_dpi_dbg("Dev close failed for port %d", i);
-
-	if (conf.chunk_pool)
-		rte_mempool_free(conf.chunk_pool);
-
-	return ret;
-}
diff --git a/drivers/raw/octeontx2_dma/version.map b/drivers/raw/octeontx2_dma/version.map
deleted file mode 100644
index c2e0723b4c..0000000000
--- a/drivers/raw/octeontx2_dma/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_22 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* [dpdk-dev] [PATCH v5 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-26 10:50       ` [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver Radha Mohan Chintakuntla
@ 2021-08-26 10:50         ` Radha Mohan Chintakuntla
  2021-08-26 11:10           ` Radha Mohan
  2021-10-18 16:36         ` [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver Thomas Monjalon
  1 sibling, 1 reply; 17+ messages in thread
From: Radha Mohan Chintakuntla @ 2021-08-26 10:50 UTC (permalink / raw)
  To: vburru, thomas; +Cc: dev, sburla, jerinj, Radha Mohan Chintakuntla

Removing the rawdev based octeontx2-ep driver as the dependent
common/octeontx2 will soon be going away. Moreover this driver is no
longer required as the net/octeontx_ep driver is sufficient.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
---
Changes from v4:
Replaced the reference to documentation in release notes to plain text.

Changes from v3:
Fixed patch application failure due to conflict on main branch.

Changes from v2:
Fixed DPDK CI reported issues for more documentation failure.

Changes from v1:
Fixed compilation issues in documentation

 MAINTAINERS                               |   6 -
 doc/guides/rawdevs/index.rst              |   1 -
 doc/guides/rawdevs/octeontx2_ep.rst       |  82 ---
 doc/guides/rel_notes/release_20_02.rst    |   2 +-
 drivers/raw/meson.build                   |   1 -
 drivers/raw/octeontx2_ep/meson.build      |  11 -
 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------
 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h |  52 --
 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------
 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------
 drivers/raw/octeontx2_ep/otx2_ep_test.c   | 172 -----
 drivers/raw/octeontx2_ep/otx2_ep_vf.c     | 475 ------------
 drivers/raw/octeontx2_ep/otx2_ep_vf.h     |  10 -
 drivers/raw/octeontx2_ep/version.map      |   3 -
 14 files changed, 1 insertion(+), 2521 deletions(-)
 delete mode 100644 doc/guides/rawdevs/octeontx2_ep.rst
 delete mode 100644 drivers/raw/octeontx2_ep/meson.build
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_test.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.c
 delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.h
 delete mode 100644 drivers/raw/octeontx2_ep/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 9f9aa37c68..1d6a408f49 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1321,12 +1321,6 @@ M: Tomasz Duszynski <tduszynski@marvell.com>
 F: doc/guides/rawdevs/cnxk_bphy.rst
 F: drivers/raw/cnxk_bphy/
 
-Marvell OCTEON TX2 EP
-M: Radha Mohan Chintakuntla <radhac@marvell.com>
-M: Veerasenareddy Burru <vburru@marvell.com>
-F: drivers/raw/octeontx2_ep/
-F: doc/guides/rawdevs/octeontx2_ep.rst
-
 NTB
 M: Xiaoyun Li <xiaoyun.li@intel.com>
 M: Jingjing Wu <jingjing.wu@intel.com>
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index 228d4a7743..b6cf917443 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -17,4 +17,3 @@ application through rawdev API.
     ifpga
     ioat
     ntb
-    octeontx2_ep
diff --git a/doc/guides/rawdevs/octeontx2_ep.rst b/doc/guides/rawdevs/octeontx2_ep.rst
deleted file mode 100644
index fb9d346ccf..0000000000
--- a/doc/guides/rawdevs/octeontx2_ep.rst
+++ /dev/null
@@ -1,82 +0,0 @@
-..  SPDX-License-Identifier: BSD-3-Clause
-    Copyright(c) 2019 Marvell International Ltd.
-
-Marvell OCTEON TX2 End Point Rawdev Driver
-==========================================
-
-OCTEON TX2 has an internal SDP unit which provides End Point mode of operation
-by exposing its IOQs to Host, IOQs are used for packet I/O between Host and
-OCTEON TX2. Each OCTEON TX2 SDP PF supports a max of 128 VFs and Each VF is
-associated with a set of IOQ pairs.
-
-Features
---------
-
-This OCTEON TX2 End Point mode PMD supports
-
-#. Packet Input - Host to OCTEON TX2 with direct data instruction mode.
-
-#. Packet Output - OCTEON TX2 to Host with info pointer mode.
-
-
-Initialization
---------------
-
-The number of SDP VFs enabled, can be controlled by setting sysfs
-entry `sriov_numvfs` for the corresponding PF driver.
-
-.. code-block:: console
-
- echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-ep/0000\:04\:00.0/sriov_numvfs
-
-Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
-bound to vfio-pci driver.
-
-Device Setup
-------------
-
-The OCTEON TX2 SDP End Point VF devices will need to be bound to a
-user-space IO driver for use. The script ``dpdk-devbind.py`` script
-included with DPDK can be used to view the state of the devices and to bind
-them to a suitable DPDK-supported kernel driver. When querying the status
-of the devices, they will appear under the category of "Misc (rawdev)
-devices", i.e. the command ``dpdk-devbind.py --status-dev misc`` can be
-used to see the state of those devices alone.
-
-Device Configuration
---------------------
-
-Configuring SDP EP rawdev device is done using the ``rte_rawdev_configure()``
-API, which takes the mempool as parameter. PMD uses this pool to send/receive
-packets to/from the HW.
-
-The following code shows how the device is configured
-
-.. code-block:: c
-
-   struct sdp_rawdev_info config = {0};
-   struct rte_rawdev_info rdev_info = {.dev_private = &config};
-   config.enqdeq_mpool = (void *)rte_mempool_create(...);
-
-   rte_rawdev_configure(dev_id, (rte_rawdev_obj_t)&rdev_info,
-                        sizeof(config));
-
-Performing Data Transfer
-------------------------
-
-To perform data transfer using SDP VF EP rawdev devices use standard
-``rte_rawdev_enqueue_buffers()`` and ``rte_rawdev_dequeue_buffers()`` APIs.
-
-Self test
----------
-
-On EAL initialization, SDP VF devices will be probed and populated into the
-raw devices. The rawdev ID of the device can be obtained using
-
-* Invoke ``rte_rawdev_get_dev_id("SDPEP:x")`` from the test application
-  where x is the VF device's bus id specified in "bus:device.func"(BDF)
-  format. Use this index for further rawdev function calls.
-
-* The driver's selftest rawdev API can be used to verify the SDP EP mode
-  functional tests which can send/receive the raw data packets to/from the
-  EP device.
diff --git a/doc/guides/rel_notes/release_20_02.rst b/doc/guides/rel_notes/release_20_02.rst
index 40ebbfac90..83f8f8aa51 100644
--- a/doc/guides/rel_notes/release_20_02.rst
+++ b/doc/guides/rel_notes/release_20_02.rst
@@ -234,7 +234,7 @@ New Features
 * **Added Marvell OCTEON TX2 End Point rawdev PMD.**
 
   Added a new OCTEON TX2 rawdev PMD for End Point mode of operation.
-  See the :doc:`../rawdevs/octeontx2_ep` for more details on this new PMD.
+  See the :doc:``../rawdevs/octeontx2_ep`` for more details on this new PMD.
 
 * **Added event mode to l3fwd sample application.**
 
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index f25d5f322c..87694a758e 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -12,7 +12,6 @@ drivers = [
         'ifpga',
         'ioat',
         'ntb',
-        'octeontx2_ep',
         'skeleton',
 ]
 std_deps = ['rawdev']
diff --git a/drivers/raw/octeontx2_ep/meson.build b/drivers/raw/octeontx2_ep/meson.build
deleted file mode 100644
index 8d7c69aa3c..0000000000
--- a/drivers/raw/octeontx2_ep/meson.build
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-# Copyright(C) 2019 Marvell International Ltd.
-#
-
-deps += ['bus_pci', 'common_octeontx2', 'rawdev']
-sources = files(
-        'otx2_ep_enqdeq.c',
-        'otx2_ep_rawdev.c',
-        'otx2_ep_test.c',
-        'otx2_ep_vf.c',
-)
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
deleted file mode 100644
index d04e957d82..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
+++ /dev/null
@@ -1,846 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <string.h>
-#include <unistd.h>
-#include <dirent.h>
-#include <fcntl.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_enqdeq.h"
-
-static void
-sdp_dmazone_free(const struct rte_memzone *mz)
-{
-	const struct rte_memzone *mz_tmp;
-	int ret = 0;
-
-	if (mz == NULL) {
-		otx2_err("Memzone %s : NULL", mz->name);
-		return;
-	}
-
-	mz_tmp = rte_memzone_lookup(mz->name);
-	if (mz_tmp == NULL) {
-		otx2_err("Memzone %s Not Found", mz->name);
-		return;
-	}
-
-	ret = rte_memzone_free(mz);
-	if (ret)
-		otx2_err("Memzone free failed : ret = %d", ret);
-
-}
-
-/* Free IQ resources */
-int
-sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq;
-
-	iq = sdpvf->instr_queue[iq_no];
-	if (iq == NULL) {
-		otx2_err("Invalid IQ[%d]\n", iq_no);
-		return -ENOMEM;
-	}
-
-	rte_free(iq->req_list);
-	iq->req_list = NULL;
-
-	if (iq->iq_mz) {
-		sdp_dmazone_free(iq->iq_mz);
-		iq->iq_mz = NULL;
-	}
-
-	rte_free(sdpvf->instr_queue[iq_no]);
-	sdpvf->instr_queue[iq_no] = NULL;
-
-	sdpvf->num_iqs--;
-
-	otx2_info("IQ[%d] is deleted", iq_no);
-
-	return 0;
-}
-
-/* IQ initialization */
-static int
-sdp_init_instr_queue(struct sdp_device *sdpvf, int iq_no)
-{
-	const struct sdp_config *conf;
-	struct sdp_instr_queue *iq;
-	uint32_t q_size;
-
-	conf = sdpvf->conf;
-	iq = sdpvf->instr_queue[iq_no];
-	q_size = conf->iq.instr_type * conf->num_iqdef_descs;
-
-	/* IQ memory creation for Instruction submission to OCTEON TX2 */
-	iq->iq_mz = rte_memzone_reserve_aligned("iqmz",
-					q_size,
-					rte_socket_id(),
-					RTE_MEMZONE_IOVA_CONTIG,
-					RTE_CACHE_LINE_SIZE);
-	if (iq->iq_mz == NULL) {
-		otx2_err("IQ[%d] memzone alloc failed", iq_no);
-		goto iq_init_fail;
-	}
-
-	iq->base_addr_dma = iq->iq_mz->iova;
-	iq->base_addr = (uint8_t *)iq->iq_mz->addr;
-
-	if (conf->num_iqdef_descs & (conf->num_iqdef_descs - 1)) {
-		otx2_err("IQ[%d] descs not in power of 2", iq_no);
-		goto iq_init_fail;
-	}
-
-	iq->nb_desc = conf->num_iqdef_descs;
-
-	/* Create a IQ request list to hold requests that have been
-	 * posted to OCTEON TX2. This list will be used for freeing the IQ
-	 * data buffer(s) later once the OCTEON TX2 fetched the requests.
-	 */
-	iq->req_list = rte_zmalloc_socket("request_list",
-			(iq->nb_desc * SDP_IQREQ_LIST_SIZE),
-			RTE_CACHE_LINE_SIZE,
-			rte_socket_id());
-	if (iq->req_list == NULL) {
-		otx2_err("IQ[%d] req_list alloc failed", iq_no);
-		goto iq_init_fail;
-	}
-
-	otx2_info("IQ[%d]: base: %p basedma: %lx count: %d",
-		     iq_no, iq->base_addr, (unsigned long)iq->base_addr_dma,
-		     iq->nb_desc);
-
-	iq->sdp_dev = sdpvf;
-	iq->q_no = iq_no;
-	iq->fill_cnt = 0;
-	iq->host_write_index = 0;
-	iq->otx_read_index = 0;
-	iq->flush_index = 0;
-
-	/* Initialize the spinlock for this instruction queue */
-	rte_spinlock_init(&iq->lock);
-	rte_spinlock_init(&iq->post_lock);
-
-	rte_atomic64_clear(&iq->iq_flush_running);
-
-	sdpvf->io_qmask.iq |= (1ull << iq_no);
-
-	/* Set 32B/64B mode for each input queue */
-	if (conf->iq.instr_type == 64)
-		sdpvf->io_qmask.iq64B |= (1ull << iq_no);
-
-	iq->iqcmd_64B = (conf->iq.instr_type == 64);
-
-	/* Set up IQ registers */
-	sdpvf->fn_list.setup_iq_regs(sdpvf, iq_no);
-
-	return 0;
-
-iq_init_fail:
-	return -ENOMEM;
-
-}
-
-int
-sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq;
-
-	iq = (struct sdp_instr_queue *)rte_zmalloc("sdp_IQ", sizeof(*iq),
-						RTE_CACHE_LINE_SIZE);
-	if (iq == NULL)
-		return -ENOMEM;
-
-	sdpvf->instr_queue[iq_no] = iq;
-
-	if (sdp_init_instr_queue(sdpvf, iq_no)) {
-		otx2_err("IQ init is failed");
-		goto delete_IQ;
-	}
-	otx2_info("IQ[%d] is created.", sdpvf->num_iqs);
-
-	sdpvf->num_iqs++;
-
-
-	return 0;
-
-delete_IQ:
-	sdp_delete_iqs(sdpvf, iq_no);
-	return -ENOMEM;
-}
-
-static void
-sdp_droq_reset_indices(struct sdp_droq *droq)
-{
-	droq->read_idx  = 0;
-	droq->write_idx = 0;
-	droq->refill_idx = 0;
-	droq->refill_count = 0;
-	rte_atomic64_set(&droq->pkts_pending, 0);
-}
-
-static void
-sdp_droq_destroy_ring_buffers(struct sdp_device *sdpvf,
-				struct sdp_droq *droq)
-{
-	uint32_t idx;
-
-	for (idx = 0; idx < droq->nb_desc; idx++) {
-		if (droq->recv_buf_list[idx].buffer) {
-			rte_mempool_put(sdpvf->enqdeq_mpool,
-				droq->recv_buf_list[idx].buffer);
-
-			droq->recv_buf_list[idx].buffer = NULL;
-		}
-	}
-
-	sdp_droq_reset_indices(droq);
-}
-
-/* Free OQs resources */
-int
-sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	struct sdp_droq *droq;
-
-	droq = sdpvf->droq[oq_no];
-	if (droq == NULL) {
-		otx2_err("Invalid droq[%d]", oq_no);
-		return -ENOMEM;
-	}
-
-	sdp_droq_destroy_ring_buffers(sdpvf, droq);
-	rte_free(droq->recv_buf_list);
-	droq->recv_buf_list = NULL;
-
-	if (droq->info_mz) {
-		sdp_dmazone_free(droq->info_mz);
-		droq->info_mz = NULL;
-	}
-
-	if (droq->desc_ring_mz) {
-		sdp_dmazone_free(droq->desc_ring_mz);
-		droq->desc_ring_mz = NULL;
-	}
-
-	memset(droq, 0, SDP_DROQ_SIZE);
-
-	rte_free(sdpvf->droq[oq_no]);
-	sdpvf->droq[oq_no] = NULL;
-
-	sdpvf->num_oqs--;
-
-	otx2_info("OQ[%d] is deleted", oq_no);
-	return 0;
-}
-
-static int
-sdp_droq_setup_ring_buffers(struct sdp_device *sdpvf,
-		struct sdp_droq *droq)
-{
-	struct sdp_droq_desc *desc_ring = droq->desc_ring;
-	uint32_t idx;
-	void *buf;
-
-	for (idx = 0; idx < droq->nb_desc; idx++) {
-		if (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||
-		    (buf == NULL)) {
-			otx2_err("OQ buffer alloc failed");
-			droq->stats.rx_alloc_failure++;
-			/* sdp_droq_destroy_ring_buffers(droq);*/
-			return -ENOMEM;
-		}
-
-		droq->recv_buf_list[idx].buffer = buf;
-		droq->info_list[idx].length = 0;
-
-		/* Map ring buffers into memory */
-		desc_ring[idx].info_ptr = (uint64_t)(droq->info_list_dma +
-			(idx * SDP_DROQ_INFO_SIZE));
-
-		desc_ring[idx].buffer_ptr = rte_mem_virt2iova(buf);
-	}
-
-	sdp_droq_reset_indices(droq);
-
-	return 0;
-}
-
-static void *
-sdp_alloc_info_buffer(struct sdp_device *sdpvf __rte_unused,
-	struct sdp_droq *droq)
-{
-	droq->info_mz = rte_memzone_reserve_aligned("OQ_info_list",
-				(droq->nb_desc * SDP_DROQ_INFO_SIZE),
-				rte_socket_id(),
-				RTE_MEMZONE_IOVA_CONTIG,
-				RTE_CACHE_LINE_SIZE);
-
-	if (droq->info_mz == NULL)
-		return NULL;
-
-	droq->info_list_dma = droq->info_mz->iova;
-	droq->info_alloc_size = droq->info_mz->len;
-	droq->info_base_addr = (size_t)droq->info_mz->addr;
-
-	return droq->info_mz->addr;
-}
-
-/* OQ initialization */
-static int
-sdp_init_droq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	const struct sdp_config *conf = sdpvf->conf;
-	uint32_t c_refill_threshold;
-	uint32_t desc_ring_size;
-	struct sdp_droq *droq;
-
-	otx2_info("OQ[%d] Init start", q_no);
-
-	droq = sdpvf->droq[q_no];
-	droq->sdp_dev = sdpvf;
-	droq->q_no = q_no;
-
-	c_refill_threshold = conf->oq.refill_threshold;
-	droq->nb_desc      = conf->num_oqdef_descs;
-	droq->buffer_size  = conf->oqdef_buf_size;
-
-	/* OQ desc_ring set up */
-	desc_ring_size = droq->nb_desc * SDP_DROQ_DESC_SIZE;
-	droq->desc_ring_mz = rte_memzone_reserve_aligned("sdp_oqmz",
-						desc_ring_size,
-						rte_socket_id(),
-						RTE_MEMZONE_IOVA_CONTIG,
-						RTE_CACHE_LINE_SIZE);
-
-	if (droq->desc_ring_mz == NULL) {
-		otx2_err("OQ:%d desc_ring allocation failed", q_no);
-		goto init_droq_fail;
-	}
-
-	droq->desc_ring_dma = droq->desc_ring_mz->iova;
-	droq->desc_ring = (struct sdp_droq_desc *)droq->desc_ring_mz->addr;
-
-	otx2_sdp_dbg("OQ[%d]: desc_ring: virt: 0x%p, dma: %lx",
-		    q_no, droq->desc_ring, (unsigned long)droq->desc_ring_dma);
-	otx2_sdp_dbg("OQ[%d]: num_desc: %d", q_no, droq->nb_desc);
-
-
-	/* OQ info_list set up */
-	droq->info_list = sdp_alloc_info_buffer(sdpvf, droq);
-	if (droq->info_list == NULL) {
-		otx2_err("memory allocation failed for OQ[%d] info_list", q_no);
-		goto init_droq_fail;
-	}
-
-	/* OQ buf_list set up */
-	droq->recv_buf_list = rte_zmalloc_socket("recv_buf_list",
-				(droq->nb_desc * SDP_DROQ_RECVBUF_SIZE),
-				 RTE_CACHE_LINE_SIZE, rte_socket_id());
-	if (droq->recv_buf_list == NULL) {
-		otx2_err("OQ recv_buf_list alloc failed");
-		goto init_droq_fail;
-	}
-
-	if (sdp_droq_setup_ring_buffers(sdpvf, droq))
-		goto init_droq_fail;
-
-	droq->refill_threshold = c_refill_threshold;
-	rte_spinlock_init(&droq->lock);
-
-
-	/* Set up OQ registers */
-	sdpvf->fn_list.setup_oq_regs(sdpvf, q_no);
-
-	sdpvf->io_qmask.oq |= (1ull << q_no);
-
-	return 0;
-
-init_droq_fail:
-	return -ENOMEM;
-}
-
-/* OQ configuration and setup */
-int
-sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	struct sdp_droq *droq;
-
-	/* Allocate new droq. */
-	droq = (struct sdp_droq *)rte_zmalloc("sdp_OQ",
-				sizeof(*droq), RTE_CACHE_LINE_SIZE);
-	if (droq == NULL) {
-		otx2_err("Droq[%d] Creation Failed", oq_no);
-		return -ENOMEM;
-	}
-	sdpvf->droq[oq_no] = droq;
-
-	if (sdp_init_droq(sdpvf, oq_no)) {
-		otx2_err("Droq[%d] Initialization failed", oq_no);
-		goto delete_OQ;
-	}
-	otx2_info("OQ[%d] is created.", oq_no);
-
-	sdpvf->num_oqs++;
-
-	return 0;
-
-delete_OQ:
-	sdp_delete_oqs(sdpvf, oq_no);
-	return -ENOMEM;
-}
-
-static inline void
-sdp_iqreq_delete(struct sdp_device *sdpvf,
-		struct sdp_instr_queue *iq, uint32_t idx)
-{
-	uint32_t reqtype;
-	void *buf;
-
-	buf     = iq->req_list[idx].buf;
-	reqtype = iq->req_list[idx].reqtype;
-
-	switch (reqtype) {
-	case SDP_REQTYPE_NORESP:
-		rte_mempool_put(sdpvf->enqdeq_mpool, buf);
-		otx2_sdp_dbg("IQ buffer freed at idx[%d]", idx);
-		break;
-
-	case SDP_REQTYPE_NORESP_GATHER:
-	case SDP_REQTYPE_NONE:
-	default:
-		otx2_info("This iqreq mode is not supported:%d", reqtype);
-
-	}
-
-	/* Reset the request list at this index */
-	iq->req_list[idx].buf = NULL;
-	iq->req_list[idx].reqtype = 0;
-}
-
-static inline void
-sdp_iqreq_add(struct sdp_instr_queue *iq, void *buf,
-		uint32_t reqtype)
-{
-	iq->req_list[iq->host_write_index].buf = buf;
-	iq->req_list[iq->host_write_index].reqtype = reqtype;
-
-	otx2_sdp_dbg("IQ buffer added at idx[%d]", iq->host_write_index);
-
-}
-
-static void
-sdp_flush_iq(struct sdp_device *sdpvf,
-		struct sdp_instr_queue *iq,
-		uint32_t pending_thresh __rte_unused)
-{
-	uint32_t instr_processed = 0;
-
-	rte_spinlock_lock(&iq->lock);
-
-	iq->otx_read_index = sdpvf->fn_list.update_iq_read_idx(iq);
-	while (iq->flush_index != iq->otx_read_index) {
-		/* Free the IQ data buffer to the pool */
-		sdp_iqreq_delete(sdpvf, iq, iq->flush_index);
-		iq->flush_index =
-			sdp_incr_index(iq->flush_index, 1, iq->nb_desc);
-
-		instr_processed++;
-	}
-
-	iq->stats.instr_processed = instr_processed;
-	rte_atomic64_sub(&iq->instr_pending, instr_processed);
-
-	rte_spinlock_unlock(&iq->lock);
-}
-
-static inline void
-sdp_ring_doorbell(struct sdp_device *sdpvf __rte_unused,
-		struct sdp_instr_queue *iq)
-{
-	otx2_write64(iq->fill_cnt, iq->doorbell_reg);
-
-	/* Make sure doorbell writes observed by HW */
-	rte_io_wmb();
-	iq->fill_cnt = 0;
-
-}
-
-static inline int
-post_iqcmd(struct sdp_instr_queue *iq, uint8_t *iqcmd)
-{
-	uint8_t *iqptr, cmdsize;
-
-	/* This ensures that the read index does not wrap around to
-	 * the same position if queue gets full before OCTEON TX2 could
-	 * fetch any instr.
-	 */
-	if (rte_atomic64_read(&iq->instr_pending) >=
-			      (int32_t)(iq->nb_desc - 1)) {
-		otx2_err("IQ is full, pending:%ld",
-			 (long)rte_atomic64_read(&iq->instr_pending));
-
-		return SDP_IQ_SEND_FAILED;
-	}
-
-	/* Copy cmd into iq */
-	cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
-	iqptr   = iq->base_addr + (cmdsize * iq->host_write_index);
-
-	rte_memcpy(iqptr, iqcmd, cmdsize);
-
-	otx2_sdp_dbg("IQ cmd posted @ index:%d", iq->host_write_index);
-
-	/* Increment the host write index */
-	iq->host_write_index =
-		sdp_incr_index(iq->host_write_index, 1, iq->nb_desc);
-
-	iq->fill_cnt++;
-
-	/* Flush the command into memory. We need to be sure the data
-	 * is in memory before indicating that the instruction is
-	 * pending.
-	 */
-	rte_smp_wmb();
-	rte_atomic64_inc(&iq->instr_pending);
-
-	/* SDP_IQ_SEND_SUCCESS */
-	return 0;
-}
-
-
-static int
-sdp_send_data(struct sdp_device *sdpvf,
-	      struct sdp_instr_queue *iq, void *cmd)
-{
-	uint32_t ret;
-
-	/* Lock this IQ command queue before posting instruction */
-	rte_spinlock_lock(&iq->post_lock);
-
-	/* Submit IQ command */
-	ret = post_iqcmd(iq, cmd);
-
-	if (ret == SDP_IQ_SEND_SUCCESS) {
-		sdp_ring_doorbell(sdpvf, iq);
-
-		iq->stats.instr_posted++;
-		otx2_sdp_dbg("Instr submit success posted: %ld\n",
-			     (long)iq->stats.instr_posted);
-
-	} else {
-		iq->stats.instr_dropped++;
-		otx2_err("Instr submit failed, dropped: %ld\n",
-			 (long)iq->stats.instr_dropped);
-
-	}
-
-	rte_spinlock_unlock(&iq->post_lock);
-
-	return ret;
-}
-
-
-/* Enqueue requests/packets to SDP IQ queue.
- * returns number of requests enqueued successfully
- */
-int
-sdp_rawdev_enqueue(struct rte_rawdev *rawdev,
-		   struct rte_rawdev_buf **buffers __rte_unused,
-		   unsigned int count, rte_rawdev_obj_t context)
-{
-	struct sdp_instr_64B *iqcmd;
-	struct sdp_instr_queue *iq;
-	struct sdp_soft_instr *si;
-	struct sdp_device *sdpvf;
-
-	struct sdp_instr_ih ihx;
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-	si = (struct sdp_soft_instr *)context;
-
-	iq = sdpvf->instr_queue[si->q_no];
-
-	if ((count > 1) || (count < 1)) {
-		otx2_err("This mode not supported: req[%d]", count);
-		goto enq_fail;
-	}
-
-	memset(&ihx, 0, sizeof(struct sdp_instr_ih));
-
-	iqcmd = &si->command;
-	memset(iqcmd, 0, sizeof(struct sdp_instr_64B));
-
-	iqcmd->dptr = (uint64_t)si->dptr;
-
-	/* Populate SDP IH */
-	ihx.pkind  = sdpvf->pkind;
-	ihx.fsz    = si->ih.fsz + 8; /* 8B for NIX IH */
-	ihx.gather = si->ih.gather;
-
-	/* Direct data instruction */
-	ihx.tlen   = si->ih.tlen + ihx.fsz;
-
-	switch (ihx.gather) {
-	case 0: /* Direct data instr */
-		ihx.tlen = si->ih.tlen + ihx.fsz;
-		break;
-
-	default: /* Gather */
-		switch (si->ih.gsz) {
-		case 0: /* Direct gather instr */
-			otx2_err("Direct Gather instr : not supported");
-			goto enq_fail;
-
-		default: /* Indirect gather instr */
-			otx2_err("Indirect Gather instr : not supported");
-			goto enq_fail;
-		}
-	}
-
-	rte_memcpy(&iqcmd->ih, &ihx, sizeof(uint64_t));
-	iqcmd->rptr = (uint64_t)si->rptr;
-	rte_memcpy(&iqcmd->irh, &si->irh, sizeof(uint64_t));
-
-	/* Swap FSZ(front data) here, to avoid swapping on OCTEON TX2 side */
-	sdp_swap_8B_data(&iqcmd->rptr, 1);
-	sdp_swap_8B_data(&iqcmd->irh, 1);
-
-	otx2_sdp_dbg("After swapping");
-	otx2_sdp_dbg("Word0 [dptr]: 0x%016lx", (unsigned long)iqcmd->dptr);
-	otx2_sdp_dbg("Word1 [ihtx]: 0x%016lx", (unsigned long)iqcmd->ih);
-	otx2_sdp_dbg("Word2 [rptr]: 0x%016lx", (unsigned long)iqcmd->rptr);
-	otx2_sdp_dbg("Word3 [irh]: 0x%016lx", (unsigned long)iqcmd->irh);
-	otx2_sdp_dbg("Word4 [exhdr[0]]: 0x%016lx",
-			(unsigned long)iqcmd->exhdr[0]);
-
-	sdp_iqreq_add(iq, si->dptr, si->reqtype);
-
-	if (sdp_send_data(sdpvf, iq, iqcmd)) {
-		otx2_err("Data send failed :");
-		sdp_iqreq_delete(sdpvf, iq, iq->host_write_index);
-		goto enq_fail;
-	}
-
-	if (rte_atomic64_read(&iq->instr_pending) >= 1)
-		sdp_flush_iq(sdpvf, iq, 1 /*(iq->nb_desc / 2)*/);
-
-	/* Return no# of instructions posted successfully. */
-	return count;
-
-enq_fail:
-	return SDP_IQ_SEND_FAILED;
-}
-
-static uint32_t
-sdp_droq_refill(struct sdp_device *sdpvf, struct sdp_droq *droq)
-{
-	struct sdp_droq_desc *desc_ring;
-	uint32_t desc_refilled = 0;
-	void *buf = NULL;
-
-	desc_ring = droq->desc_ring;
-
-	while (droq->refill_count && (desc_refilled < droq->nb_desc)) {
-		/* If a valid buffer exists (happens if there is no dispatch),
-		 * reuse the buffer, else allocate.
-		 */
-		if (droq->recv_buf_list[droq->refill_idx].buffer != NULL)
-			break;
-
-		if (rte_mempool_get(sdpvf->enqdeq_mpool, &buf) ||
-		    (buf == NULL)) {
-			/* If a buffer could not be allocated, no point in
-			 * continuing
-			 */
-			droq->stats.rx_alloc_failure++;
-			break;
-		}
-
-		droq->recv_buf_list[droq->refill_idx].buffer = buf;
-		desc_ring[droq->refill_idx].buffer_ptr = rte_mem_virt2iova(buf);
-
-		/* Reset any previous values in the length field. */
-		droq->info_list[droq->refill_idx].length = 0;
-
-		droq->refill_idx = sdp_incr_index(droq->refill_idx, 1,
-				droq->nb_desc);
-
-		desc_refilled++;
-		droq->refill_count--;
-
-	}
-
-	return desc_refilled;
-}
-
-static int
-sdp_droq_read_packet(struct sdp_device *sdpvf __rte_unused,
-		     struct sdp_droq *droq,
-		     struct sdp_droq_pkt *droq_pkt)
-{
-	struct sdp_droq_info *info;
-	uint32_t total_len = 0;
-	uint32_t pkt_len = 0;
-
-	info = &droq->info_list[droq->read_idx];
-	sdp_swap_8B_data((uint64_t *)&info->length, 1);
-	if (!info->length) {
-		otx2_err("OQ info_list->length[%ld]", (long)info->length);
-		goto oq_read_fail;
-	}
-
-	/* Deduce the actual data size */
-	info->length -= SDP_RH_SIZE;
-	total_len += (uint32_t)info->length;
-
-	otx2_sdp_dbg("OQ: pkt_len[%ld], buffer_size %d",
-			(long)info->length, droq->buffer_size);
-	if (info->length > droq->buffer_size) {
-		otx2_err("This mode is not supported: pkt_len > buffer_size");
-		goto oq_read_fail;
-	}
-
-	if (info->length <= droq->buffer_size) {
-		pkt_len = (uint32_t)info->length;
-		droq_pkt->data = droq->recv_buf_list[droq->read_idx].buffer;
-		droq_pkt->len  = pkt_len;
-
-		droq->recv_buf_list[droq->read_idx].buffer = NULL;
-		droq->read_idx = sdp_incr_index(droq->read_idx,	1,/* count */
-						droq->nb_desc /* max rd idx */);
-		droq->refill_count++;
-
-	}
-
-	info->length = 0;
-
-	return SDP_OQ_RECV_SUCCESS;
-
-oq_read_fail:
-	return SDP_OQ_RECV_FAILED;
-}
-
-static inline uint32_t
-sdp_check_droq_pkts(struct sdp_droq *droq, uint32_t burst_size)
-{
-	uint32_t min_pkts = 0;
-	uint32_t new_pkts;
-	uint32_t pkt_count;
-
-	/* Latest available OQ packets */
-	pkt_count = rte_read32(droq->pkts_sent_reg);
-
-	/* Newly arrived packets */
-	new_pkts = pkt_count - droq->last_pkt_count;
-	otx2_sdp_dbg("Recvd [%d] new OQ pkts", new_pkts);
-
-	min_pkts = (new_pkts > burst_size) ? burst_size : new_pkts;
-	if (min_pkts) {
-		rte_atomic64_add(&droq->pkts_pending, min_pkts);
-		/* Back up the aggregated packet count so far */
-		droq->last_pkt_count += min_pkts;
-	}
-
-	return min_pkts;
-}
-
-/* Check for response arrival from OCTEON TX2
- * returns number of requests completed
- */
-int
-sdp_rawdev_dequeue(struct rte_rawdev *rawdev,
-		   struct rte_rawdev_buf **buffers, unsigned int count,
-		   rte_rawdev_obj_t context __rte_unused)
-{
-	struct sdp_droq_pkt *oq_pkt;
-	struct sdp_device *sdpvf;
-	struct sdp_droq *droq;
-
-	uint32_t q_no = 0, pkts;
-	uint32_t new_pkts;
-	uint32_t ret;
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-
-	droq = sdpvf->droq[q_no];
-	if (!droq) {
-		otx2_err("Invalid droq[%d]", q_no);
-		goto droq_err;
-	}
-
-	/* Grab the lock */
-	rte_spinlock_lock(&droq->lock);
-
-	new_pkts = sdp_check_droq_pkts(droq, count);
-	if (!new_pkts) {
-		otx2_sdp_dbg("Zero new_pkts:%d", new_pkts);
-		goto deq_fail; /* No pkts at this moment */
-	}
-
-	otx2_sdp_dbg("Received new_pkts = %d", new_pkts);
-
-	for (pkts = 0; pkts < new_pkts; pkts++) {
-
-		/* Push the received pkt to application */
-		oq_pkt = (struct sdp_droq_pkt *)buffers[pkts];
-
-		ret = sdp_droq_read_packet(sdpvf, droq, oq_pkt);
-		if (ret) {
-			otx2_err("DROQ read pakt failed.");
-			goto deq_fail;
-		}
-
-		/* Stats */
-		droq->stats.pkts_received++;
-		droq->stats.bytes_received += oq_pkt->len;
-	}
-
-	/* Ack the h/w with no# of pkts read by Host */
-	rte_write32(pkts, droq->pkts_sent_reg);
-	rte_io_wmb();
-
-	droq->last_pkt_count -= pkts;
-
-	otx2_sdp_dbg("DROQ pkts[%d] pushed to application", pkts);
-
-	/* Refill DROQ buffers */
-	if (droq->refill_count >= 2 /* droq->refill_threshold */) {
-		int desc_refilled = sdp_droq_refill(sdpvf, droq);
-
-		/* Flush the droq descriptor data to memory to be sure
-		 * that when we update the credits the data in memory is
-		 * accurate.
-		 */
-		rte_write32(desc_refilled, droq->pkts_credit_reg);
-
-		/* Ensure mmio write completes */
-		rte_wmb();
-		otx2_sdp_dbg("Refilled count = %d", desc_refilled);
-	}
-
-	/* Release the spin lock */
-	rte_spinlock_unlock(&droq->lock);
-
-	return pkts;
-
-deq_fail:
-	rte_spinlock_unlock(&droq->lock);
-
-droq_err:
-	return SDP_OQ_RECV_FAILED;
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h b/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
deleted file mode 100644
index 172fdc5568..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _OTX2_EP_ENQDEQ_H_
-#define _OTX2_EP_ENQDEQ_H_
-
-#include <rte_byteorder.h>
-#include "otx2_ep_rawdev.h"
-
-#define SDP_IQ_SEND_FAILED      (-1)
-#define SDP_IQ_SEND_SUCCESS     (0)
-
-#define SDP_OQ_RECV_FAILED      (-1)
-#define SDP_OQ_RECV_SUCCESS     (0)
-
-static inline uint64_t
-sdp_endian_swap_8B(uint64_t _d)
-{
-	return ((((((uint64_t)(_d)) >>  0) & (uint64_t)0xff) << 56) |
-		(((((uint64_t)(_d)) >>  8) & (uint64_t)0xff) << 48) |
-		(((((uint64_t)(_d)) >> 16) & (uint64_t)0xff) << 40) |
-		(((((uint64_t)(_d)) >> 24) & (uint64_t)0xff) << 32) |
-		(((((uint64_t)(_d)) >> 32) & (uint64_t)0xff) << 24) |
-		(((((uint64_t)(_d)) >> 40) & (uint64_t)0xff) << 16) |
-		(((((uint64_t)(_d)) >> 48) & (uint64_t)0xff) <<  8) |
-		(((((uint64_t)(_d)) >> 56) & (uint64_t)0xff) <<  0));
-}
-
-static inline void
-sdp_swap_8B_data(uint64_t *data, uint32_t blocks)
-{
-	/* Swap 8B blocks */
-	while (blocks) {
-		*data = sdp_endian_swap_8B(*data);
-		blocks--;
-		data++;
-	}
-}
-
-static inline uint32_t
-sdp_incr_index(uint32_t index, uint32_t count, uint32_t max)
-{
-	if ((index + count) >= max)
-		index = index + count - max;
-	else
-		index += count;
-
-	return index;
-}
-
-#endif /* _OTX2_EP_ENQDEQ_H_ */
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
deleted file mode 100644
index b2ccdda83e..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_bus.h>
-#include <rte_bus_pci.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-#include <rte_pci.h>
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-#include "otx2_ep_vf.h"
-
-static const struct rte_pci_id pci_sdp_vf_map[] = {
-	{
-		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
-			       PCI_DEVID_OCTEONTX2_EP_RAW_VF)
-	},
-	{
-		.vendor_id = 0,
-	},
-};
-
-/* SDP_VF default configuration */
-const struct sdp_config default_sdp_conf = {
-	/* IQ attributes */
-	.iq                        = {
-		.max_iqs           = SDP_VF_CFG_IO_QUEUES,
-		.instr_type        = SDP_VF_64BYTE_INSTR,
-		.pending_list_size = (SDP_VF_MAX_IQ_DESCRIPTORS *
-				      SDP_VF_CFG_IO_QUEUES),
-	},
-
-	/* OQ attributes */
-	.oq                        = {
-		.max_oqs           = SDP_VF_CFG_IO_QUEUES,
-		.info_ptr          = SDP_VF_OQ_INFOPTR_MODE,
-		.refill_threshold  = SDP_VF_OQ_REFIL_THRESHOLD,
-	},
-
-	.num_iqdef_descs           = SDP_VF_MAX_IQ_DESCRIPTORS,
-	.num_oqdef_descs           = SDP_VF_MAX_OQ_DESCRIPTORS,
-	.oqdef_buf_size            = SDP_VF_OQ_BUF_SIZE,
-
-};
-
-const struct sdp_config*
-sdp_get_defconf(struct sdp_device *sdp_dev __rte_unused)
-{
-	const struct sdp_config *default_conf = NULL;
-
-	default_conf = &default_sdp_conf;
-
-	return default_conf;
-}
-
-static int
-sdp_vfdev_exit(struct rte_rawdev *rawdev)
-{
-	struct sdp_device *sdpvf;
-	uint32_t rawdev_queues, q;
-
-	otx2_info("%s:", __func__);
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-
-	sdpvf->fn_list.disable_io_queues(sdpvf);
-
-	rawdev_queues = sdpvf->num_oqs;
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_delete_oqs(sdpvf, q)) {
-			otx2_err("Failed to delete OQ:%d", q);
-			return -ENOMEM;
-		}
-	}
-	otx2_info("Num OQs:%d freed", sdpvf->num_oqs);
-
-	/* Free the oqbuf_pool */
-	rte_mempool_free(sdpvf->enqdeq_mpool);
-	sdpvf->enqdeq_mpool = NULL;
-
-	otx2_info("Enqdeq_mpool free done");
-
-	rawdev_queues = sdpvf->num_iqs;
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_delete_iqs(sdpvf, q)) {
-			otx2_err("Failed to delete IQ:%d", q);
-			return -ENOMEM;
-		}
-	}
-	otx2_sdp_dbg("Num IQs:%d freed", sdpvf->num_iqs);
-
-	return 0;
-}
-
-static int
-sdp_chip_specific_setup(struct sdp_device *sdpvf)
-{
-	struct rte_pci_device *pdev = sdpvf->pci_dev;
-	uint32_t dev_id = pdev->id.device_id;
-	int ret;
-
-	switch (dev_id) {
-	case PCI_DEVID_OCTEONTX2_EP_RAW_VF:
-		sdpvf->chip_id = PCI_DEVID_OCTEONTX2_EP_RAW_VF;
-		ret = sdp_vf_setup_device(sdpvf);
-
-		break;
-	default:
-		otx2_err("Unsupported device");
-		ret = -EINVAL;
-	}
-
-	if (!ret)
-		otx2_info("SDP dev_id[%d]", dev_id);
-
-	return ret;
-}
-
-/* SDP VF device initialization */
-static int
-sdp_vfdev_init(struct sdp_device *sdpvf)
-{
-	uint32_t rawdev_queues, q;
-
-	if (sdp_chip_specific_setup(sdpvf)) {
-		otx2_err("Chip specific setup failed");
-		goto setup_fail;
-	}
-
-	if (sdpvf->fn_list.setup_device_regs(sdpvf)) {
-		otx2_err("Failed to configure device registers");
-		goto setup_fail;
-	}
-
-	rawdev_queues = (uint32_t)(sdpvf->sriov_info.rings_per_vf);
-
-	/* Rawdev queues setup for enqueue/dequeue */
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_setup_iqs(sdpvf, q)) {
-			otx2_err("Failed to setup IQs");
-			goto iq_fail;
-		}
-	}
-	otx2_info("Total[%d] IQs setup", sdpvf->num_iqs);
-
-	for (q = 0; q < rawdev_queues; q++) {
-		if (sdp_setup_oqs(sdpvf, q)) {
-			otx2_err("Failed to setup OQs");
-			goto oq_fail;
-		}
-	}
-	otx2_info("Total [%d] OQs setup", sdpvf->num_oqs);
-
-	/* Enable IQ/OQ for this device */
-	sdpvf->fn_list.enable_io_queues(sdpvf);
-
-	/* Send OQ desc credits for OQs, credits are always
-	 * sent after the OQs are enabled.
-	 */
-	for (q = 0; q < rawdev_queues; q++) {
-		rte_write32(sdpvf->droq[q]->nb_desc,
-			    sdpvf->droq[q]->pkts_credit_reg);
-
-		rte_io_mb();
-		otx2_info("OQ[%d] dbells [%d]", q,
-		rte_read32(sdpvf->droq[q]->pkts_credit_reg));
-	}
-
-	rte_wmb();
-
-	otx2_info("SDP Device is Ready");
-
-	return 0;
-
-/* Error handling  */
-oq_fail:
-	/* Free the allocated OQs */
-	for (q = 0; q < sdpvf->num_oqs; q++)
-		sdp_delete_oqs(sdpvf, q);
-
-iq_fail:
-	/* Free the allocated IQs */
-	for (q = 0; q < sdpvf->num_iqs; q++)
-		sdp_delete_iqs(sdpvf, q);
-
-setup_fail:
-	return -ENOMEM;
-}
-
-static int
-sdp_rawdev_start(struct rte_rawdev *dev)
-{
-	dev->started = 1;
-
-	return 0;
-}
-
-static void
-sdp_rawdev_stop(struct rte_rawdev *dev)
-{
-	dev->started = 0;
-}
-
-static int
-sdp_rawdev_close(struct rte_rawdev *dev)
-{
-	int ret;
-	ret = sdp_vfdev_exit(dev);
-	if (ret) {
-		otx2_err(" SDP_EP rawdev exit error");
-		return ret;
-	}
-
-	return 0;
-}
-
-static int
-sdp_rawdev_configure(const struct rte_rawdev *dev, rte_rawdev_obj_t config,
-		size_t config_size)
-{
-	struct sdp_rawdev_info *app_info = (struct sdp_rawdev_info *)config;
-	struct sdp_device *sdpvf;
-
-	if (app_info == NULL || config_size != sizeof(*app_info)) {
-		otx2_err("Application config info [NULL] or incorrect size");
-		return -EINVAL;
-	}
-
-	sdpvf = (struct sdp_device *)dev->dev_private;
-
-	sdpvf->conf = app_info->app_conf;
-	sdpvf->enqdeq_mpool = app_info->enqdeq_mpool;
-
-	sdp_vfdev_init(sdpvf);
-
-	return 0;
-
-}
-
-/* SDP VF endpoint rawdev ops */
-static const struct rte_rawdev_ops sdp_rawdev_ops = {
-	.dev_configure  = sdp_rawdev_configure,
-	.dev_start      = sdp_rawdev_start,
-	.dev_stop       = sdp_rawdev_stop,
-	.dev_close      = sdp_rawdev_close,
-	.enqueue_bufs   = sdp_rawdev_enqueue,
-	.dequeue_bufs   = sdp_rawdev_dequeue,
-	.dev_selftest   = sdp_rawdev_selftest,
-};
-
-static int
-otx2_sdp_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
-		      struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct sdp_device *sdpvf = NULL;
-	struct rte_rawdev *sdp_rawdev;
-	uint16_t vf_id;
-
-	/* Single process support */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return 0;
-
-	if (pci_dev->mem_resource[0].addr)
-		otx2_info("SDP_EP BAR0 is mapped:");
-	else {
-		otx2_err("SDP_EP: Failed to map device BARs");
-		otx2_err("BAR0 %p\n BAR2 %p",
-			pci_dev->mem_resource[0].addr,
-			pci_dev->mem_resource[2].addr);
-		return -ENODEV;
-	}
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "SDPEP:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	/* Allocate rawdev pmd */
-	sdp_rawdev = rte_rawdev_pmd_allocate(name,
-					     sizeof(struct sdp_device),
-					     rte_socket_id());
-
-	if (sdp_rawdev == NULL) {
-		otx2_err("SDP_EP VF rawdev allocation failed");
-		return -ENOMEM;
-	}
-
-	sdp_rawdev->dev_ops = &sdp_rawdev_ops;
-	sdp_rawdev->device = &pci_dev->device;
-	sdp_rawdev->driver_name = pci_dev->driver->driver.name;
-
-	sdpvf = (struct sdp_device *)sdp_rawdev->dev_private;
-	sdpvf->hw_addr = pci_dev->mem_resource[0].addr;
-	sdpvf->pci_dev = pci_dev;
-
-	/* Discover the VF number being probed */
-	vf_id = ((pci_dev->addr.devid & 0x1F) << 3) |
-		 (pci_dev->addr.function & 0x7);
-
-	vf_id -= 1;
-	sdpvf->vf_num = vf_id;
-
-	otx2_info("SDP_EP VF[%d] probe done", vf_id);
-
-	return 0;
-}
-
-static int
-otx2_sdp_rawdev_remove(struct rte_pci_device *pci_dev)
-{
-	char name[RTE_RAWDEV_NAME_MAX_LEN];
-	struct rte_rawdev *rawdev;
-	struct sdp_device *sdpvf;
-
-	/* Single process support */
-	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
-		return 0;
-
-	if (pci_dev == NULL) {
-		otx2_err("SDP_EP:invalid pci_dev!");
-		return -EINVAL;
-	}
-
-
-	memset(name, 0, sizeof(name));
-	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "SDPEP:%x:%02x.%x",
-		 pci_dev->addr.bus, pci_dev->addr.devid,
-		 pci_dev->addr.function);
-
-	rawdev = rte_rawdev_pmd_get_named_dev(name);
-	if (rawdev == NULL) {
-		otx2_err("SDP_EP: invalid device name (%s)", name);
-		return -EINVAL;
-	}
-
-	sdpvf = (struct sdp_device *)rawdev->dev_private;
-	otx2_info("Removing SDP_EP VF[%d] ", sdpvf->vf_num);
-
-	/* rte_rawdev_close is called by pmd_release */
-	return rte_rawdev_pmd_release(rawdev);
-}
-
-static struct rte_pci_driver rte_sdp_rawdev_pmd = {
-	.id_table  = pci_sdp_vf_map,
-	.drv_flags = (RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA),
-	.probe     = otx2_sdp_rawdev_probe,
-	.remove    = otx2_sdp_rawdev_remove,
-};
-
-RTE_PMD_REGISTER_PCI(sdp_rawdev_pci_driver, rte_sdp_rawdev_pmd);
-RTE_PMD_REGISTER_PCI_TABLE(sdp_rawdev_pci_driver, pci_sdp_vf_map);
-RTE_PMD_REGISTER_KMOD_DEP(sdp_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h b/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
deleted file mode 100644
index dab2fb7541..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
+++ /dev/null
@@ -1,499 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#ifndef _OTX2_EP_RAWDEV_H_
-#define _OTX2_EP_RAWDEV_H_
-
-#include <rte_byteorder.h>
-#include <rte_spinlock.h>
-
-/* IQ instruction req types */
-#define SDP_REQTYPE_NONE             (0)
-#define SDP_REQTYPE_NORESP           (1)
-#define SDP_REQTYPE_NORESP_GATHER    (2)
-
-/* Input Request Header format */
-struct sdp_instr_irh {
-	/* Request ID  */
-	uint64_t rid:16;
-
-	/* PCIe port to use for response */
-	uint64_t pcie_port:3;
-
-	/* Scatter indicator  1=scatter */
-	uint64_t scatter:1;
-
-	/* Size of Expected result OR no. of entries in scatter list */
-	uint64_t rlenssz:14;
-
-	/* Desired destination port for result */
-	uint64_t dport:6;
-
-	/* Opcode Specific parameters */
-	uint64_t param:8;
-
-	/* Opcode for the return packet  */
-	uint64_t opcode:16;
-};
-
-/* SDP 32B instruction format */
-struct sdp_instr_32B {
-	/* Pointer where the input data is available. */
-	uint64_t dptr;
-
-	/* SDP Instruction Header.  */
-	uint64_t ih;
-
-	/** Pointer where the response for a RAW mode packet
-	 *  will be written by OCTEON TX2.
-	 */
-	uint64_t rptr;
-
-	/* Input Request Header. Additional info about the input. */
-	uint64_t irh;
-};
-#define SDP_32B_INSTR_SIZE	(sizeof(sdp_instr_32B))
-
-/* SDP 64B instruction format */
-struct sdp_instr_64B {
-	/* Pointer where the input data is available. */
-	uint64_t dptr;
-
-	/* SDP Instruction Header. */
-	uint64_t ih;
-
-	/** Pointer where the response for a RAW mode packet
-	 * will be written by OCTEON TX2.
-	 */
-	uint64_t rptr;
-
-	/* Input Request Header. */
-	uint64_t irh;
-
-	/* Additional headers available in a 64-byte instruction. */
-	uint64_t exhdr[4];
-};
-#define SDP_64B_INSTR_SIZE	(sizeof(sdp_instr_64B))
-
-struct sdp_soft_instr {
-	/** Input data pointer. It is either pointing directly to input data
-	 *  or to a gather list.
-	 */
-	void *dptr;
-
-	/** Response from OCTEON TX2 comes at this address. It is either
-	 *  directlty pointing to output data buffer or to a scatter list.
-	 */
-	void *rptr;
-
-	/* The instruction header. All input commands have this field. */
-	struct sdp_instr_ih ih;
-
-	/* Input request header. */
-	struct sdp_instr_irh irh;
-
-	/** The PCI instruction to be sent to OCTEON TX2. This is stored in the
-	 *  instr to retrieve the physical address of buffers when instr is
-	 *  freed.
-	 */
-	struct sdp_instr_64B command;
-
-	/** If a gather list was allocated, this ptr points to the buffer used
-	 *  for the gather list. The gather list has to be 8B aligned, so this
-	 *  value may be different from dptr.
-	 */
-	void *gather_ptr;
-
-	/* Total data bytes transferred in the gather mode request. */
-	uint64_t gather_bytes;
-
-	/** If a scatter list was allocated, this ptr points to the buffer used
-	 *  for the scatter list. The scatter list has to be 8B aligned, so
-	 *  this value may be different from rptr.
-	 */
-	void *scatter_ptr;
-
-	/* Total data bytes to be received in the scatter mode request. */
-	uint64_t scatter_bytes;
-
-	/* IQ number to which this instruction has to be submitted. */
-	uint32_t q_no;
-
-	/* IQ instruction request type. */
-	uint32_t reqtype;
-};
-#define SDP_SOFT_INSTR_SIZE	(sizeof(sdp_soft_instr))
-
-/* SDP IQ request list */
-struct sdp_instr_list {
-	void *buf;
-	uint32_t reqtype;
-};
-#define SDP_IQREQ_LIST_SIZE	(sizeof(struct sdp_instr_list))
-
-/* Input Queue statistics. Each input queue has four stats fields. */
-struct sdp_iq_stats {
-	uint64_t instr_posted; /* Instructions posted to this queue. */
-	uint64_t instr_processed; /* Instructions processed in this queue. */
-	uint64_t instr_dropped; /* Instructions that could not be processed */
-};
-
-/* Structure to define the configuration attributes for each Input queue. */
-struct sdp_iq_config {
-	/* Max number of IQs available */
-	uint16_t max_iqs;
-
-	/* Command size - 32 or 64 bytes */
-	uint16_t instr_type;
-
-	/* Pending list size, usually set to the sum of the size of all IQs */
-	uint32_t pending_list_size;
-};
-
-/** The instruction (input) queue.
- *  The input queue is used to post raw (instruction) mode data or packet data
- *  to OCTEON TX2 device from the host. Each IQ of a SDP EP VF device has one
- *  such structure to represent it.
- */
-struct sdp_instr_queue {
-	/* A spinlock to protect access to the input ring.  */
-	rte_spinlock_t lock;
-	rte_spinlock_t post_lock;
-
-	struct sdp_device *sdp_dev;
-	rte_atomic64_t iq_flush_running;
-
-	uint32_t q_no;
-	uint32_t pkt_in_done;
-
-	/* Flag for 64 byte commands. */
-	uint32_t iqcmd_64B:1;
-	uint32_t rsvd:17;
-	uint32_t status:8;
-
-	/* Number of  descriptors in this ring. */
-	uint32_t nb_desc;
-
-	/* Input ring index, where the driver should write the next packet */
-	uint32_t host_write_index;
-
-	/* Input ring index, where the OCTEON TX2 should read the next packet */
-	uint32_t otx_read_index;
-
-	/** This index aids in finding the window in the queue where OCTEON TX2
-	 *  has read the commands.
-	 */
-	uint32_t flush_index;
-
-	/* This keeps track of the instructions pending in this queue. */
-	rte_atomic64_t instr_pending;
-
-	uint32_t reset_instr_cnt;
-
-	/* Pointer to the Virtual Base addr of the input ring. */
-	uint8_t *base_addr;
-
-	/* This IQ request list */
-	struct sdp_instr_list *req_list;
-
-	/* SDP doorbell register for the ring. */
-	void *doorbell_reg;
-
-	/* SDP instruction count register for this ring. */
-	void *inst_cnt_reg;
-
-	/* Number of instructions pending to be posted to OCTEON TX2. */
-	uint32_t fill_cnt;
-
-	/* Statistics for this input queue. */
-	struct sdp_iq_stats stats;
-
-	/* DMA mapped base address of the input descriptor ring. */
-	uint64_t base_addr_dma;
-
-	/* Memory zone */
-	const struct rte_memzone *iq_mz;
-};
-
-/* DROQ packet format for application i/f. */
-struct sdp_droq_pkt {
-	/* DROQ packet data buffer pointer. */
-	uint8_t	 *data;
-
-	/* DROQ packet data length */
-	uint32_t len;
-
-	uint32_t misc;
-};
-
-/** Descriptor format.
- *  The descriptor ring is made of descriptors which have 2 64-bit values:
- *  -# Physical (bus) address of the data buffer.
- *  -# Physical (bus) address of a sdp_droq_info structure.
- *  The device DMA's incoming packets and its information at the address
- *  given by these descriptor fields.
- */
-struct sdp_droq_desc {
-	/* The buffer pointer */
-	uint64_t buffer_ptr;
-
-	/* The Info pointer */
-	uint64_t info_ptr;
-};
-#define SDP_DROQ_DESC_SIZE	(sizeof(struct sdp_droq_desc))
-
-/* Receive Header */
-union sdp_rh {
-	uint64_t rh64;
-};
-#define SDP_RH_SIZE (sizeof(union sdp_rh))
-
-/** Information about packet DMA'ed by OCTEON TX2.
- *  The format of the information available at Info Pointer after OCTEON TX2
- *  has posted a packet. Not all descriptors have valid information. Only
- *  the Info field of the first descriptor for a packet has information
- *  about the packet.
- */
-struct sdp_droq_info {
-	/* The Output Receive Header. */
-	union sdp_rh rh;
-
-	/* The Length of the packet. */
-	uint64_t length;
-};
-#define SDP_DROQ_INFO_SIZE	(sizeof(struct sdp_droq_info))
-
-/** Pointer to data buffer.
- *  Driver keeps a pointer to the data buffer that it made available to
- *  the OCTEON TX2 device. Since the descriptor ring keeps physical (bus)
- *  addresses, this field is required for the driver to keep track of
- *  the virtual address pointers.
- */
-struct sdp_recv_buffer {
-	/* Packet buffer, including meta data. */
-	void *buffer;
-
-	/* Data in the packet buffer. */
-	/* uint8_t *data; */
-};
-#define SDP_DROQ_RECVBUF_SIZE	(sizeof(struct sdp_recv_buffer))
-
-/* DROQ statistics. Each output queue has four stats fields. */
-struct sdp_droq_stats {
-	/* Number of packets received in this queue. */
-	uint64_t pkts_received;
-
-	/* Bytes received by this queue. */
-	uint64_t bytes_received;
-
-	/* Num of failures of rte_pktmbuf_alloc() */
-	uint64_t rx_alloc_failure;
-};
-
-/* Structure to define the configuration attributes for each Output queue. */
-struct sdp_oq_config {
-	/* Max number of OQs available */
-	uint16_t max_oqs;
-
-	/* If set, the Output queue uses info-pointer mode. (Default: 1 ) */
-	uint16_t info_ptr;
-
-	/** The number of buffers that were consumed during packet processing by
-	 *  the driver on this Output queue before the driver attempts to
-	 *  replenish the descriptor ring with new buffers.
-	 */
-	uint32_t refill_threshold;
-};
-
-/* The Descriptor Ring Output Queue(DROQ) structure. */
-struct sdp_droq {
-	/* A spinlock to protect access to this ring. */
-	rte_spinlock_t lock;
-
-	struct sdp_device *sdp_dev;
-	/* The 8B aligned descriptor ring starts at this address. */
-	struct sdp_droq_desc *desc_ring;
-
-	uint32_t q_no;
-	uint32_t last_pkt_count;
-
-	/* Driver should read the next packet at this index */
-	uint32_t read_idx;
-
-	/* OCTEON TX2 will write the next packet at this index */
-	uint32_t write_idx;
-
-	/* At this index, the driver will refill the descriptor's buffer */
-	uint32_t refill_idx;
-
-	/* Packets pending to be processed */
-	rte_atomic64_t pkts_pending;
-
-	/* Number of descriptors in this ring. */
-	uint32_t nb_desc;
-
-	/* The number of descriptors pending to refill. */
-	uint32_t refill_count;
-
-	uint32_t refill_threshold;
-
-	/* The 8B aligned info ptrs begin from this address. */
-	struct sdp_droq_info *info_list;
-
-	/* receive buffer list contains virtual addresses of the buffers. */
-	struct sdp_recv_buffer *recv_buf_list;
-
-	/* The size of each buffer pointed by the buffer pointer. */
-	uint32_t buffer_size;
-
-	/** Pointer to the mapped packet credit register.
-	 *  Host writes number of info/buffer ptrs available to this register
-	 */
-	void *pkts_credit_reg;
-
-	/** Pointer to the mapped packet sent register. OCTEON TX2 writes the
-	 *  number of packets DMA'ed to host memory in this register.
-	 */
-	void *pkts_sent_reg;
-
-	/* Statistics for this DROQ. */
-	struct sdp_droq_stats stats;
-
-	/* DMA mapped address of the DROQ descriptor ring. */
-	size_t desc_ring_dma;
-
-	/* Info_ptr list is allocated at this virtual address. */
-	size_t info_base_addr;
-
-	/* DMA mapped address of the info list */
-	size_t info_list_dma;
-
-	/* Allocated size of info list. */
-	uint32_t info_alloc_size;
-
-	/* Memory zone **/
-	const struct rte_memzone *desc_ring_mz;
-	const struct rte_memzone *info_mz;
-};
-#define SDP_DROQ_SIZE		(sizeof(struct sdp_droq))
-
-/* IQ/OQ mask */
-struct sdp_io_enable {
-	uint64_t iq;
-	uint64_t oq;
-	uint64_t iq64B;
-};
-
-/* Structure to define the configuration. */
-struct sdp_config {
-	/* Input Queue attributes. */
-	struct sdp_iq_config iq;
-
-	/* Output Queue attributes. */
-	struct sdp_oq_config oq;
-
-	/* Num of desc for IQ rings */
-	uint32_t num_iqdef_descs;
-
-	/* Num of desc for OQ rings */
-	uint32_t num_oqdef_descs;
-
-	/* OQ buffer size */
-	uint32_t oqdef_buf_size;
-};
-
-/* Required functions for each VF device */
-struct sdp_fn_list {
-	void (*setup_iq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*setup_oq_regs)(struct sdp_device *sdpvf, uint32_t q_no);
-
-	int (*setup_device_regs)(struct sdp_device *sdpvf);
-	uint32_t (*update_iq_read_idx)(struct sdp_instr_queue *iq);
-
-	void (*enable_io_queues)(struct sdp_device *sdpvf);
-	void (*disable_io_queues)(struct sdp_device *sdpvf);
-
-	void (*enable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*disable_iq)(struct sdp_device *sdpvf, uint32_t q_no);
-
-	void (*enable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
-	void (*disable_oq)(struct sdp_device *sdpvf, uint32_t q_no);
-};
-
-/* SRIOV information */
-struct sdp_sriov_info {
-	/* Number of rings assigned to VF */
-	uint32_t rings_per_vf;
-
-	/* Number of VF devices enabled */
-	uint32_t num_vfs;
-};
-
-
-/* Information to be passed from application */
-struct sdp_rawdev_info {
-	struct rte_mempool *enqdeq_mpool;
-	const struct sdp_config *app_conf;
-};
-
-/* SDP EP VF device */
-struct sdp_device {
-	/* PCI device pointer */
-	struct rte_pci_device *pci_dev;
-	uint16_t chip_id;
-	uint16_t pf_num;
-	uint16_t vf_num;
-
-	/* This device's PCIe port used for traffic. */
-	uint16_t pcie_port;
-	uint32_t pkind;
-
-	/* The state of this device */
-	rte_atomic64_t status;
-
-	/* Memory mapped h/w address */
-	uint8_t *hw_addr;
-
-	struct sdp_fn_list fn_list;
-
-	/* Num IQs */
-	uint32_t num_iqs;
-
-	/* The input instruction queues */
-	struct sdp_instr_queue *instr_queue[SDP_VF_MAX_IOQS_PER_RAWDEV];
-
-	/* Num OQs */
-	uint32_t num_oqs;
-
-	/* The DROQ output queues  */
-	struct sdp_droq *droq[SDP_VF_MAX_IOQS_PER_RAWDEV];
-
-	/* IOQ data buffer pool */
-	struct rte_mempool *enqdeq_mpool;
-
-	/* IOQ mask */
-	struct sdp_io_enable io_qmask;
-
-	/* SR-IOV info */
-	struct sdp_sriov_info sriov_info;
-
-	/* Device configuration */
-	const struct sdp_config *conf;
-};
-
-const struct sdp_config *sdp_get_defconf(struct sdp_device *sdp_dev);
-int sdp_setup_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
-int sdp_delete_iqs(struct sdp_device *sdpvf, uint32_t iq_no);
-
-int sdp_setup_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
-int sdp_delete_oqs(struct sdp_device *sdpvf, uint32_t oq_no);
-
-int sdp_rawdev_enqueue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
-		       unsigned int count, rte_rawdev_obj_t context);
-int sdp_rawdev_dequeue(struct rte_rawdev *dev, struct rte_rawdev_buf **buffers,
-		       unsigned int count, rte_rawdev_obj_t context);
-
-int sdp_rawdev_selftest(uint16_t dev_id);
-
-#endif /* _OTX2_EP_RAWDEV_H_ */
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_test.c b/drivers/raw/octeontx2_ep/otx2_ep_test.c
deleted file mode 100644
index b876275f7a..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_test.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#include <rte_common.h>
-#include <rte_eal.h>
-#include <rte_lcore.h>
-#include <rte_mempool.h>
-
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-
-#define SDP_IOQ_NUM_BUFS   (4 * 1024)
-#define SDP_IOQ_BUF_SIZE   (2 * 1024)
-
-#define SDP_TEST_PKT_FSZ   (0)
-#define SDP_TEST_PKT_SIZE  (1024)
-
-static int
-sdp_validate_data(struct sdp_droq_pkt *oq_pkt, uint8_t *iq_pkt,
-		  uint32_t pkt_len)
-{
-	if (!oq_pkt)
-		return -EINVAL;
-
-	if (pkt_len != oq_pkt->len) {
-		otx2_err("Invalid packet length");
-		return -EINVAL;
-	}
-
-	if (memcmp(oq_pkt->data, iq_pkt, pkt_len) != 0) {
-		otx2_err("Data validation failed");
-		return -EINVAL;
-	}
-	otx2_sdp_dbg("Data validation successful");
-
-	return 0;
-}
-
-static void
-sdp_ioq_buffer_fill(uint8_t *addr, uint32_t len)
-{
-	uint32_t idx;
-
-	memset(addr, 0, len);
-
-	for (idx = 0; idx < len; idx++)
-		addr[idx] = idx;
-}
-
-static struct rte_mempool*
-sdp_ioq_mempool_create(void)
-{
-	struct rte_mempool *mpool;
-
-	mpool = rte_mempool_create("ioqbuf_pool",
-				   SDP_IOQ_NUM_BUFS /*num elt*/,
-				   SDP_IOQ_BUF_SIZE /*elt size*/,
-				   0 /*cache_size*/,
-				   0 /*private_data_size*/,
-				   NULL /*mp_init*/,
-				   NULL /*mp_init arg*/,
-				   NULL /*obj_init*/,
-				   NULL /*obj_init arg*/,
-				   rte_socket_id() /*socket id*/,
-				   (MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET));
-
-	return mpool;
-}
-
-
-int
-sdp_rawdev_selftest(uint16_t dev_id)
-{
-	struct sdp_rawdev_info app_info = {0};
-	struct rte_rawdev_info dev_info = {0};
-
-	struct rte_rawdev_buf *d_buf[1];
-	struct sdp_droq_pkt oq_pkt;
-	struct sdp_soft_instr si;
-	struct sdp_device sdpvf;
-
-	uint32_t buf_size;
-	int ret = 0;
-	void *buf;
-
-	otx2_info("SDP RAWDEV Self Test: Started");
-
-	memset(&oq_pkt, 0x00, sizeof(oq_pkt));
-	d_buf[0] = (struct rte_rawdev_buf *)&oq_pkt;
-
-	struct rte_mempool *ioq_mpool = sdp_ioq_mempool_create();
-	if (!ioq_mpool) {
-		otx2_err("IOQ mpool creation failed");
-		return -ENOMEM;
-	}
-
-	app_info.enqdeq_mpool = ioq_mpool;
-	app_info.app_conf = NULL; /* Use default conf */
-
-	dev_info.dev_private = &app_info;
-
-	ret = rte_rawdev_configure(dev_id, &dev_info, sizeof(app_info));
-	if (ret) {
-		otx2_err("Unable to configure SDP_VF %d", dev_id);
-		rte_mempool_free(ioq_mpool);
-		return -ENOMEM;
-	}
-	otx2_info("SDP VF rawdev[%d] configured successfully", dev_id);
-
-	memset(&si, 0x00, sizeof(si));
-	memset(&sdpvf, 0x00, sizeof(sdpvf));
-
-	buf_size = SDP_TEST_PKT_SIZE;
-
-	si.q_no = 0;
-	si.reqtype = SDP_REQTYPE_NORESP;
-	si.rptr = NULL;
-
-	si.ih.fsz = SDP_TEST_PKT_FSZ;
-	si.ih.tlen = buf_size;
-	si.ih.gather = 0;
-
-	/* Enqueue raw pkt data */
-	rte_mempool_get(ioq_mpool, &buf);
-	if (!buf) {
-		otx2_err("Buffer allocation failed");
-		rte_mempool_free(ioq_mpool);
-		rte_rawdev_close(dev_id);
-		return -ENOMEM;
-	}
-
-	sdp_ioq_buffer_fill(buf, buf_size);
-	si.dptr = (uint8_t *)buf;
-
-	rte_rawdev_enqueue_buffers(dev_id, NULL, 1, &si);
-	usleep(10000);
-
-	/* Dequeue raw pkt data */
-	ret = 0;
-	while (ret < 1) {
-		ret = rte_rawdev_dequeue_buffers(dev_id, &d_buf[0], 1, &si);
-		rte_pause();
-	}
-
-	/* Validate the dequeued raw pkt data */
-	if (sdp_validate_data((struct sdp_droq_pkt *)d_buf[0],
-			      buf, buf_size) != 0) {
-		otx2_err("Data invalid");
-		rte_mempool_put(ioq_mpool,
-				((struct sdp_droq_pkt *)d_buf[0])->data);
-		rte_mempool_free(ioq_mpool);
-		rte_rawdev_close(dev_id);
-		return -EINVAL;
-	}
-
-	rte_mempool_put(ioq_mpool, ((struct sdp_droq_pkt *)d_buf[0])->data);
-	rte_mempool_free(ioq_mpool);
-	rte_rawdev_close(dev_id);
-
-	otx2_info("SDP RAWDEV Self Test: Successful");
-
-	return 0;
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.c b/drivers/raw/octeontx2_ep/otx2_ep_vf.c
deleted file mode 100644
index bf2a19e369..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.c
+++ /dev/null
@@ -1,475 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-
-#include <rte_common.h>
-#include <rte_rawdev.h>
-#include <rte_rawdev_pmd.h>
-
-#include "otx2_common.h"
-#include "otx2_ep_rawdev.h"
-#include "otx2_ep_vf.h"
-
-static int
-sdp_vf_reset_iq(struct sdp_device *sdpvf, int q_no)
-{
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-	volatile uint64_t d64 = 0ull;
-
-	/* There is no RST for a ring.
-	 * Clear all registers one by one after disabling the ring
-	 */
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_BADDR(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(q_no));
-
-	d64 = 0xFFFFFFFF; /* ~0ull */
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr +
-			     SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr +
-				  SDP_VF_R_IN_INSTR_DBELL(q_no));
-	}
-
-	loop = SDP_VF_BUSY_LOOP_COUNT;
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CNTS(q_no));
-	}
-
-	d64 = 0ull;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_PKT_CNT(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_IN_BYTE_CNT(q_no));
-
-	return 0;
-}
-
-static int
-sdp_vf_reset_oq(struct sdp_device *sdpvf, int q_no)
-{
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-	volatile uint64_t d64 = 0ull;
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_BADDR(q_no));
-
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_RSIZE(q_no));
-
-	d64 = 0xFFFFFFFF;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_SLIST_DBELL(q_no));
-
-	while ((d64 != 0) && loop--) {
-		otx2_write64(d64, sdpvf->hw_addr +
-			     SDP_VF_R_OUT_SLIST_DBELL(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr +
-				  SDP_VF_R_OUT_SLIST_DBELL(q_no));
-	}
-
-	loop = SDP_VF_BUSY_LOOP_COUNT;
-	d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-	while ((d64 != 0) && (loop--)) {
-		otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-
-		rte_delay_ms(1);
-
-		d64 = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CNTS(q_no));
-	}
-
-	d64 = 0ull;
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_PKT_CNT(q_no));
-	otx2_write64(d64, sdpvf->hw_addr + SDP_VF_R_OUT_BYTE_CNT(q_no));
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_global_iq_reg(struct sdp_device *sdpvf, int q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	/* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for IQs
-	 * IS_64B is by default enabled.
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
-
-	reg_val |= SDP_VF_R_IN_CTL_RDSIZE;
-	reg_val |= SDP_VF_R_IN_CTL_IS_64B;
-	reg_val |= SDP_VF_R_IN_CTL_ESR;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(q_no));
-
-}
-
-static void
-sdp_vf_setup_global_oq_reg(struct sdp_device *sdpvf, int q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
-
-	reg_val |= (SDP_VF_R_OUT_CTL_IMODE);
-
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_P);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_P);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ES_I);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ROR_D);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_NSR_D);
-	reg_val &= ~(SDP_VF_R_OUT_CTL_ES_D);
-
-	/* INFO/DATA ptr swap is required  */
-	reg_val |= (SDP_VF_R_OUT_CTL_ES_P);
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(q_no));
-
-}
-
-static int
-sdp_vf_reset_input_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	otx2_sdp_dbg("%s :", __func__);
-
-	for (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)
-		sdp_vf_reset_iq(sdpvf, q_no);
-
-	return 0;
-}
-
-static int
-sdp_vf_reset_output_queues(struct sdp_device *sdpvf)
-{
-	uint64_t q_no = 0ull;
-
-	otx2_sdp_dbg(" %s :", __func__);
-
-	for (q_no = 0; q_no < sdpvf->sriov_info.rings_per_vf; q_no++)
-		sdp_vf_reset_oq(sdpvf, q_no);
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_global_input_regs(struct sdp_device *sdpvf)
-{
-	uint64_t q_no = 0ull;
-
-	sdp_vf_reset_input_queues(sdpvf);
-
-	for (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)
-		sdp_vf_setup_global_iq_reg(sdpvf, q_no);
-}
-
-static void
-sdp_vf_setup_global_output_regs(struct sdp_device *sdpvf)
-{
-	uint32_t q_no;
-
-	sdp_vf_reset_output_queues(sdpvf);
-
-	for (q_no = 0; q_no < (sdpvf->sriov_info.rings_per_vf); q_no++)
-		sdp_vf_setup_global_oq_reg(sdpvf, q_no);
-
-}
-
-static int
-sdp_vf_setup_device_regs(struct sdp_device *sdpvf)
-{
-	sdp_vf_setup_global_input_regs(sdpvf);
-	sdp_vf_setup_global_output_regs(sdpvf);
-
-	return 0;
-}
-
-static void
-sdp_vf_setup_iq_regs(struct sdp_device *sdpvf, uint32_t iq_no)
-{
-	struct sdp_instr_queue *iq = sdpvf->instr_queue[iq_no];
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));
-
-	/* Wait till IDLE to set to 1, not supposed to configure BADDR
-	 * as long as IDLE is 0
-	 */
-	if (!(reg_val & SDP_VF_R_IN_CTL_IDLE)) {
-		do {
-			reg_val = otx2_read64(sdpvf->hw_addr +
-					      SDP_VF_R_IN_CONTROL(iq_no));
-		} while (!(reg_val & SDP_VF_R_IN_CTL_IDLE));
-	}
-
-	/* Write the start of the input queue's ring and its size  */
-	otx2_write64(iq->base_addr_dma, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_BADDR(iq_no));
-	otx2_write64(iq->nb_desc, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_RSIZE(iq_no));
-
-	/* Remember the doorbell & instruction count register addr
-	 * for this queue
-	 */
-	iq->doorbell_reg = (uint8_t *) sdpvf->hw_addr +
-			   SDP_VF_R_IN_INSTR_DBELL(iq_no);
-	iq->inst_cnt_reg = (uint8_t *) sdpvf->hw_addr +
-			   SDP_VF_R_IN_CNTS(iq_no);
-
-	otx2_sdp_dbg("InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p",
-		     iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
-
-	/* Store the current instrn counter(used in flush_iq calculation) */
-	iq->reset_instr_cnt = rte_read32(iq->inst_cnt_reg);
-
-	/* IN INTR_THRESHOLD is set to max(FFFFFFFF) which disable the IN INTR
-	 * to raise
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
-	reg_val = 0xffffffff;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_INT_LEVELS(iq_no));
-
-}
-
-static void
-sdp_vf_setup_oq_regs(struct sdp_device *sdpvf, uint32_t oq_no)
-{
-	volatile uint64_t reg_val = 0ull;
-	uint64_t oq_ctl = 0ull;
-
-	struct sdp_droq *droq = sdpvf->droq[oq_no];
-
-	/* Wait on IDLE to set to 1, supposed to configure BADDR
-	 * as log as IDLE is 0
-	 */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	while (!(reg_val & SDP_VF_R_OUT_CTL_IDLE)) {
-		reg_val = otx2_read64(sdpvf->hw_addr +
-				      SDP_VF_R_OUT_CONTROL(oq_no));
-	}
-
-	otx2_write64(droq->desc_ring_dma, sdpvf->hw_addr +
-		     SDP_VF_R_OUT_SLIST_BADDR(oq_no));
-	otx2_write64(droq->nb_desc, sdpvf->hw_addr +
-		     SDP_VF_R_OUT_SLIST_RSIZE(oq_no));
-
-	oq_ctl = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	/* Clear the ISIZE and BSIZE (22-0) */
-	oq_ctl &= ~(0x7fffffull);
-
-	/* Populate the BSIZE (15-0) */
-	oq_ctl |= (droq->buffer_size & 0xffff);
-
-	/* Populate ISIZE(22-16) */
-	oq_ctl |= ((SDP_RH_SIZE << 16) & 0x7fffff);
-	otx2_write64(oq_ctl, sdpvf->hw_addr + SDP_VF_R_OUT_CONTROL(oq_no));
-
-	/* Mapped address of the pkt_sent and pkts_credit regs */
-	droq->pkts_sent_reg = (uint8_t *) sdpvf->hw_addr +
-			      SDP_VF_R_OUT_CNTS(oq_no);
-	droq->pkts_credit_reg = (uint8_t *) sdpvf->hw_addr +
-				SDP_VF_R_OUT_SLIST_DBELL(oq_no);
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_INT_LEVELS(oq_no));
-
-	/* Clear PKT_CNT register */
-	rte_write64(0xFFFFFFFFF, (uint8_t *)sdpvf->hw_addr +
-		    SDP_VF_R_OUT_PKT_CNT(oq_no));
-
-	/* Clear the OQ doorbell  */
-	rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
-	while ((rte_read32(droq->pkts_credit_reg) != 0ull)) {
-		rte_write32(0xFFFFFFFF, droq->pkts_credit_reg);
-		rte_delay_ms(1);
-	}
-	otx2_sdp_dbg("SDP_R[%d]_credit:%x", oq_no,
-		     rte_read32(droq->pkts_credit_reg));
-
-	/* Clear the OQ_OUT_CNTS doorbell  */
-	reg_val = rte_read32(droq->pkts_sent_reg);
-	rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
-
-	otx2_sdp_dbg("SDP_R[%d]_sent: %x", oq_no,
-		     rte_read32(droq->pkts_sent_reg));
-
-	while (((rte_read32(droq->pkts_sent_reg)) != 0ull)) {
-		reg_val = rte_read32(droq->pkts_sent_reg);
-		rte_write32((uint32_t)reg_val, droq->pkts_sent_reg);
-		rte_delay_ms(1);
-	}
-
-}
-
-static void
-sdp_vf_enable_iq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-	uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
-
-	/* Resetting doorbells during IQ enabling also to handle abrupt
-	 * guest reboot. IQ reset does not clear the doorbells.
-	 */
-	otx2_write64(0xFFFFFFFF, sdpvf->hw_addr +
-		     SDP_VF_R_IN_INSTR_DBELL(q_no));
-
-	while (((otx2_read64(sdpvf->hw_addr +
-		 SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
-
-		rte_delay_ms(1);
-	}
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	reg_val |= 0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-
-	otx2_info("IQ[%d] enable done", q_no);
-
-}
-
-static void
-sdp_vf_enable_oq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-	reg_val |= 0x1ull;
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-	otx2_info("OQ[%d] enable done", q_no);
-}
-
-static void
-sdp_vf_enable_io_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	for (q_no = 0; q_no < sdpvf->num_iqs; q_no++)
-		sdp_vf_enable_iq(sdpvf, q_no);
-
-	for (q_no = 0; q_no < sdpvf->num_oqs; q_no++)
-		sdp_vf_enable_oq(sdpvf, q_no);
-}
-
-static void
-sdp_vf_disable_iq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	/* Reset the doorbell register for this Input Queue. */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-	reg_val &= ~0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
-}
-
-static void
-sdp_vf_disable_oq(struct sdp_device *sdpvf, uint32_t q_no)
-{
-	volatile uint64_t reg_val = 0ull;
-
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-	reg_val &= ~0x1ull;
-
-	otx2_write64(reg_val, sdpvf->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
-
-}
-
-static void
-sdp_vf_disable_io_queues(struct sdp_device *sdpvf)
-{
-	uint32_t q_no = 0;
-
-	/* Disable Input Queues. */
-	for (q_no = 0; q_no < sdpvf->num_iqs; q_no++)
-		sdp_vf_disable_iq(sdpvf, q_no);
-
-	/* Disable Output Queues. */
-	for (q_no = 0; q_no < sdpvf->num_oqs; q_no++)
-		sdp_vf_disable_oq(sdpvf, q_no);
-}
-
-static uint32_t
-sdp_vf_update_read_index(struct sdp_instr_queue *iq)
-{
-	uint32_t new_idx = rte_read32(iq->inst_cnt_reg);
-
-	/* The new instr cnt reg is a 32-bit counter that can roll over.
-	 * We have noted the counter's initial value at init time into
-	 * reset_instr_cnt
-	 */
-	if (iq->reset_instr_cnt < new_idx)
-		new_idx -= iq->reset_instr_cnt;
-	else
-		new_idx += (0xffffffff - iq->reset_instr_cnt) + 1;
-
-	/* Modulo of the new index with the IQ size will give us
-	 * the new index.
-	 */
-	new_idx %= iq->nb_desc;
-
-	return new_idx;
-}
-
-int
-sdp_vf_setup_device(struct sdp_device *sdpvf)
-{
-	uint64_t reg_val = 0ull;
-
-	/* If application doesn't provide its conf, use driver default conf */
-	if (sdpvf->conf == NULL) {
-		sdpvf->conf = sdp_get_defconf(sdpvf);
-		if (sdpvf->conf == NULL) {
-			otx2_err("SDP VF default config not found");
-			return -ENOMEM;
-		}
-		otx2_info("Default config is used");
-	}
-
-	/* Get IOQs (RPVF] count */
-	reg_val = otx2_read64(sdpvf->hw_addr + SDP_VF_R_IN_CONTROL(0));
-
-	sdpvf->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
-					  & SDP_VF_R_IN_CTL_RPVF_MASK);
-
-	otx2_info("SDP RPVF: %d", sdpvf->sriov_info.rings_per_vf);
-
-	sdpvf->fn_list.setup_iq_regs       = sdp_vf_setup_iq_regs;
-	sdpvf->fn_list.setup_oq_regs       = sdp_vf_setup_oq_regs;
-
-	sdpvf->fn_list.setup_device_regs   = sdp_vf_setup_device_regs;
-	sdpvf->fn_list.update_iq_read_idx  = sdp_vf_update_read_index;
-
-	sdpvf->fn_list.enable_io_queues    = sdp_vf_enable_io_queues;
-	sdpvf->fn_list.disable_io_queues   = sdp_vf_disable_io_queues;
-
-	sdpvf->fn_list.enable_iq           = sdp_vf_enable_iq;
-	sdpvf->fn_list.disable_iq          = sdp_vf_disable_iq;
-
-	sdpvf->fn_list.enable_oq           = sdp_vf_enable_oq;
-	sdpvf->fn_list.disable_oq          = sdp_vf_disable_oq;
-
-
-	return 0;
-
-}
diff --git a/drivers/raw/octeontx2_ep/otx2_ep_vf.h b/drivers/raw/octeontx2_ep/otx2_ep_vf.h
deleted file mode 100644
index 996f2e51eb..0000000000
--- a/drivers/raw/octeontx2_ep/otx2_ep_vf.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2019 Marvell International Ltd.
- */
-#ifndef _OTX2_EP_VF_H_
-#define _OTX2_EP_VF_H_
-
-int
-sdp_vf_setup_device(struct sdp_device *sdpvf);
-
-#endif /*_OTX2_EP_VF_H_ */
diff --git a/drivers/raw/octeontx2_ep/version.map b/drivers/raw/octeontx2_ep/version.map
deleted file mode 100644
index c2e0723b4c..0000000000
--- a/drivers/raw/octeontx2_ep/version.map
+++ /dev/null
@@ -1,3 +0,0 @@
-DPDK_22 {
-	local: *;
-};
-- 
2.24.1


^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH v5 2/2] drivers/raw: remove octeontx2-ep driver
  2021-08-26 10:50         ` [dpdk-dev] [PATCH v5 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
@ 2021-08-26 11:10           ` Radha Mohan
  0 siblings, 0 replies; 17+ messages in thread
From: Radha Mohan @ 2021-08-26 11:10 UTC (permalink / raw)
  To: Radha Mohan Chintakuntla
  Cc: Veerasenareddy Burru, Thomas Monjalon, dpdk-dev, Satananda Burla,
	Jerin Jacob Kollanukkaran

On Thu, Aug 26, 2021 at 4:20 PM Radha Mohan Chintakuntla
<radhac@marvell.com> wrote:
>
> Removing the rawdev based octeontx2-ep driver as the dependent
> common/octeontx2 will soon be going away. Moreover this driver is no
> longer required as the net/octeontx_ep driver is sufficient.
>
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
> ---
> Changes from v4:
> Replaced the reference to documentation in release notes to plain text.
>
> Changes from v3:
> Fixed patch application failure due to conflict on main branch.
>
> Changes from v2:
> Fixed DPDK CI reported issues for more documentation failure.
>
> Changes from v1:
> Fixed compilation issues in documentation
>
>  MAINTAINERS                               |   6 -
>  doc/guides/rawdevs/index.rst              |   1 -
>  doc/guides/rawdevs/octeontx2_ep.rst       |  82 ---
>  doc/guides/rel_notes/release_20_02.rst    |   2 +-
>  drivers/raw/meson.build                   |   1 -
>  drivers/raw/octeontx2_ep/meson.build      |  11 -
>  drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c | 846 ----------------------
>  drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h |  52 --
>  drivers/raw/octeontx2_ep/otx2_ep_rawdev.c | 362 ---------
>  drivers/raw/octeontx2_ep/otx2_ep_rawdev.h | 499 -------------
>  drivers/raw/octeontx2_ep/otx2_ep_test.c   | 172 -----
>  drivers/raw/octeontx2_ep/otx2_ep_vf.c     | 475 ------------
>  drivers/raw/octeontx2_ep/otx2_ep_vf.h     |  10 -
>  drivers/raw/octeontx2_ep/version.map      |   3 -
>  14 files changed, 1 insertion(+), 2521 deletions(-)
>  delete mode 100644 doc/guides/rawdevs/octeontx2_ep.rst
>  delete mode 100644 drivers/raw/octeontx2_ep/meson.build
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_enqdeq.h
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_rawdev.h
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_test.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.c
>  delete mode 100644 drivers/raw/octeontx2_ep/otx2_ep_vf.h
>  delete mode 100644 drivers/raw/octeontx2_ep/version.map
>
<snip>

hi Thomas,
Now checkpatch doesn't like touching older release notes. There must
be a way of removing irrelevant drivers.

regards,
Radha Mohan

^ permalink raw reply	[flat|nested] 17+ messages in thread

* Re: [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver
  2021-08-26 10:50       ` [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver Radha Mohan Chintakuntla
  2021-08-26 10:50         ` [dpdk-dev] [PATCH v5 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
@ 2021-10-18 16:36         ` Thomas Monjalon
  1 sibling, 0 replies; 17+ messages in thread
From: Thomas Monjalon @ 2021-10-18 16:36 UTC (permalink / raw)
  To: Radha Mohan Chintakuntla; +Cc: vburru, dev, sburla, jerinj

26/08/2021 12:50, Radha Mohan Chintakuntla:
> Removing the rawdev based octeontx2-dma driver as the dependent
> common/octeontx2 will be soon be going away. Also a new DMA driver will
> be coming in this place once the rte_dmadev library is in.
> 
> Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>

This patchset has been forgotten.
I've adjusted the old release notes changes to remove the :doc: part.

Applied, thanks.




^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2021-10-18 16:36 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-12 12:37 [dpdk-dev] [PATCH v2 1/2] drivers/raw: remove octeontx2-dma driver Radha Mohan Chintakuntla
2021-08-13  7:00 ` [dpdk-dev] [PATCH v3 " Radha Mohan Chintakuntla
2021-08-19  7:57   ` [dpdk-dev] [PATCH v4 " Radha Mohan Chintakuntla
2021-08-20  3:38     ` Radha Mohan
2021-08-23 15:21     ` [dpdk-dev] [PATCH RESEND " Radha Mohan Chintakuntla
2021-08-23 15:21       ` [dpdk-dev] [PATCH RESEND v4 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
2021-08-23 16:27         ` Radha Mohan
2021-08-25  7:20           ` Thomas Monjalon
2021-08-26 10:50       ` [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver Radha Mohan Chintakuntla
2021-08-26 10:50         ` [dpdk-dev] [PATCH v5 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
2021-08-26 11:10           ` Radha Mohan
2021-10-18 16:36         ` [dpdk-dev] [PATCH v5 1/2] drivers/raw: remove octeontx2-dma driver Thomas Monjalon
2021-08-13  7:01 ` [dpdk-dev] [PATCH v3 2/2] drivers/raw: remove octeontx2-ep driver Radha Mohan Chintakuntla
2021-08-19  7:59   ` [dpdk-dev] [PATCH v4 " Radha Mohan Chintakuntla
2021-08-23 12:19     ` Radha Mohan
2021-08-23 12:31       ` David Marchand
2021-08-23 12:41         ` Radha Mohan

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