[PATCH 0/4] Add ASPM-L1 Substates support for Tegra

[PATCH 0/4] Add ASPM-L1 Substates support for Tegra

[Vidya Sagar]

Tegra chips T210 and T186 support ASPM-L1 Substates (i.e. L1.1 and L1.2)
This patch series
- adds a generic API for root port controller drivers to
  override the default value of LTR L1.2 Threhold which otherwise comes from
  the same APIs weak implementation in aspm.c file
- applies fixups to reflect correct capability values for
  T_cmrt (Common Mode Restore Time) and
  T_pwr_on (Power On)
  and adjusts counter values for 19.2 MHz of clk_m
- applies fixup specific to T210 to avoid unnecessary wake ups from L1.2 state

PCIe - ASPM L1 Sub States spec
https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf

Testing Done on T210 and T186
- ASPM-L1:
  Verified ASPM-L1 enablement by selecting PCIEASPM_POWERSAVE config
  With the help of Tegra rootport's internal counter registers, confirmed
  link entry in and out of ASPM-L1 state using USB3.0 add-on card, NVMe and NIC
  cards
- ASPM-L1 SubStates:
  Verified ASPM-L1 Substates enablement by selecting PCIEASPM_POWER_SUPERSAVE config
  Confirmed link's entry into L1SS using Westren Digital NVMe card (with Sandisk
  Controller) using Tegra rootport's internal counter registers

Vidya Sagar (4):
  PCI/ASPM: Add API to supply LTR L1.2 threshold
  PCI: tegra: Enable ASPM-L1 capability advertisement
  PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States
  PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2

 drivers/pci/host/pci-tegra.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/pcie/aspm.c      | 11 +++--
 include/linux/pci-aspm.h     |  6 +++
 3 files changed, 113 insertions(+), 3 deletions(-)

-- 
2.7.4

[PATCH 0/4] Add ASPM-L1 Substates support for Tegra

[Vidya Sagar]

Tegra chips T210 and T186 support ASPM-L1 Substates (i.e. L1.1 and L1.2)
This patch series
- adds a generic API for root port controller drivers to
  override the default value of LTR L1.2 Threhold which otherwise comes from
  the same APIs weak implementation in aspm.c file
- applies fixups to reflect correct capability values for
  T_cmrt (Common Mode Restore Time) and
  T_pwr_on (Power On)
  and adjusts counter values for 19.2 MHz of clk_m
- applies fixup specific to T210 to avoid unnecessary wake ups from L1.2 state

PCIe - ASPM L1 Sub States spec
https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf

Testing Done on T210 and T186
- ASPM-L1:
  Verified ASPM-L1 enablement by selecting PCIEASPM_POWERSAVE config
  With the help of Tegra rootport's internal counter registers, confirmed
  link entry in and out of ASPM-L1 state using USB3.0 add-on card, NVMe and NIC
  cards
- ASPM-L1 SubStates:
  Verified ASPM-L1 Substates enablement by selecting PCIEASPM_POWER_SUPERSAVE config
  Confirmed link's entry into L1SS using Westren Digital NVMe card (with Sandisk
  Controller) using Tegra rootport's internal counter registers

Vidya Sagar (4):
  PCI/ASPM: Add API to supply LTR L1.2 threshold
  PCI: tegra: Enable ASPM-L1 capability advertisement
  PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States
  PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2

 drivers/pci/host/pci-tegra.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/pcie/aspm.c      | 11 +++--
 include/linux/pci-aspm.h     |  6 +++
 3 files changed, 113 insertions(+), 3 deletions(-)

-- 
2.7.4

[PATCH 1/4] PCI/ASPM: Add API to supply LTR L1.2 threshold

[Vidya Sagar]

adds API for host controller drivers to specify LTR L1.2
threshold value if it is different from the default value.
weak implementation of the API is added to supply default
value

Signed-off-by: Vidya Sagar <vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/pci/pcie/aspm.c  | 11 ++++++++---
 include/linux/pci-aspm.h |  6 ++++++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 1dfa10cc566b..c6e8604796e5 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -436,6 +436,11 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
 	return NULL;
 }
 
+u32 __weak pcie_aspm_get_ltr_l_1_2_threshold(void)
+{
+	return LTR_L1_2_THRESHOLD_BITS;
+}
+
 /* Calculate L1.2 PM substate timing parameters */
 static void aspm_calc_l1ss_info(struct pcie_link_state *link,
 				struct aspm_register_info *upreg,
@@ -458,10 +463,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
 	else
 		link->l1ss.ctl1 |= val2 << 8;
 	/*
-	 * We currently use LTR L1.2 threshold to be fixed constant picked from
-	 * Intel's coreboot.
+	 * Get LTR L1.2 threshold value specific to a platform if present
+	 * Otherwise, get a constant value picked from Intel's coreboot.
 	 */
-	link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
+	link->l1ss.ctl1 |= pcie_aspm_get_ltr_l_1_2_threshold();
 
 	/* Choose the greater of the two T_pwr_on */
 	val1 = (upreg->l1ss_cap >> 19) & 0x1F;
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
index 207c561fb40e..7ffde0f57688 100644
--- a/include/linux/pci-aspm.h
+++ b/include/linux/pci-aspm.h
@@ -30,6 +30,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 void pci_disable_link_state(struct pci_dev *pdev, int state);
 void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
 void pcie_no_aspm(void);
+u32 pcie_aspm_get_ltr_l_1_2_threshold(void);
 #else
 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
 {
@@ -49,6 +50,11 @@ static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
 static inline void pcie_no_aspm(void)
 {
 }
+
+static inline u32 pcie_aspm_get_ltr_l_1_2_threshold(void)
+{
+	return 0;
+}
 #endif
 
 #ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
-- 
2.7.4

[PATCH 1/4] PCI/ASPM: Add API to supply LTR L1.2 threshold

[Vidya Sagar]

adds API for host controller drivers to specify LTR L1.2
threshold value if it is different from the default value.
weak implementation of the API is added to supply default
value

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/pci/pcie/aspm.c  | 11 ++++++++---
 include/linux/pci-aspm.h |  6 ++++++
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 1dfa10cc566b..c6e8604796e5 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -436,6 +436,11 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
 	return NULL;
 }
 
+u32 __weak pcie_aspm_get_ltr_l_1_2_threshold(void)
+{
+	return LTR_L1_2_THRESHOLD_BITS;
+}
+
 /* Calculate L1.2 PM substate timing parameters */
 static void aspm_calc_l1ss_info(struct pcie_link_state *link,
 				struct aspm_register_info *upreg,
@@ -458,10 +463,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
 	else
 		link->l1ss.ctl1 |= val2 << 8;
 	/*
-	 * We currently use LTR L1.2 threshold to be fixed constant picked from
-	 * Intel's coreboot.
+	 * Get LTR L1.2 threshold value specific to a platform if present
+	 * Otherwise, get a constant value picked from Intel's coreboot.
 	 */
-	link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
+	link->l1ss.ctl1 |= pcie_aspm_get_ltr_l_1_2_threshold();
 
 	/* Choose the greater of the two T_pwr_on */
 	val1 = (upreg->l1ss_cap >> 19) & 0x1F;
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
index 207c561fb40e..7ffde0f57688 100644
--- a/include/linux/pci-aspm.h
+++ b/include/linux/pci-aspm.h
@@ -30,6 +30,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 void pci_disable_link_state(struct pci_dev *pdev, int state);
 void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
 void pcie_no_aspm(void);
+u32 pcie_aspm_get_ltr_l_1_2_threshold(void);
 #else
 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
 {
@@ -49,6 +50,11 @@ static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
 static inline void pcie_no_aspm(void)
 {
 }
+
+static inline u32 pcie_aspm_get_ltr_l_1_2_threshold(void)
+{
+	return 0;
+}
 #endif
 
 #ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
-- 
2.7.4

[PATCH 2/4] PCI: tegra: Enable ASPM-L1 capability advertisement

[Vidya Sagar]

Enables advertisement of ASPM-L1 support in capability
registers of applicable Tegra chips

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index adae03d671ab..e1526cc5d381 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -226,6 +226,9 @@
 #define  RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK	(0xff << 18)
 #define  RP_VEND_XP_UPDATE_FC_THRESHOLD_T210	(0x60 << 18)
 
+#define RP_VEND_XP1	0xf04
+#define RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT	BIT(21)
+
 #define RP_VEND_CTL0	0xf44
 #define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK	(0xf << 12)
 #define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH	(0x9 << 12)
@@ -327,6 +330,7 @@ struct tegra_pcie_soc {
 	bool RAW_violation_fixup;
 	bool program_deskew_time;
 	bool updateFC_threshold;
+	bool has_aspm_l1;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2188,6 +2192,13 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
 	value = readl(port->base + RP_VEND_CTL1);
 	value |= RP_VEND_CTL1_ERPT;
 	writel(value, port->base + RP_VEND_CTL1);
+
+	if (port->pcie->soc->has_aspm_l1) {
+		/* Advertise ASPM-L1 state capability*/
+		value = readl(port->base + RP_VEND_XP1);
+		value |= RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT;
+		writel(value, port->base + RP_VEND_XP1);
+	}
 }
 
 static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
@@ -2391,6 +2402,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
+	.has_aspm_l1 = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2412,6 +2424,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
+	.has_aspm_l1 = true,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2432,6 +2445,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.RAW_violation_fixup = true,
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
+	.has_aspm_l1 = true,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2460,6 +2474,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.RAW_violation_fixup = false,
 	.program_deskew_time = true,
 	.updateFC_threshold = true,
+	.has_aspm_l1 = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2481,6 +2496,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
+	.has_aspm_l1 = true,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.7.4

[PATCH 2/4] PCI: tegra: Enable ASPM-L1 capability advertisement

[Vidya Sagar]

Enables advertisement of ASPM-L1 support in capability
registers of applicable Tegra chips

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index adae03d671ab..e1526cc5d381 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -226,6 +226,9 @@
 #define  RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK	(0xff << 18)
 #define  RP_VEND_XP_UPDATE_FC_THRESHOLD_T210	(0x60 << 18)
 
+#define RP_VEND_XP1	0xf04
+#define RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT	BIT(21)
+
 #define RP_VEND_CTL0	0xf44
 #define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK	(0xf << 12)
 #define  RP_VEND_CTL0_DSK_RST_PULSE_WIDTH	(0x9 << 12)
@@ -327,6 +330,7 @@ struct tegra_pcie_soc {
 	bool RAW_violation_fixup;
 	bool program_deskew_time;
 	bool updateFC_threshold;
+	bool has_aspm_l1;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2188,6 +2192,13 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
 	value = readl(port->base + RP_VEND_CTL1);
 	value |= RP_VEND_CTL1_ERPT;
 	writel(value, port->base + RP_VEND_CTL1);
+
+	if (port->pcie->soc->has_aspm_l1) {
+		/* Advertise ASPM-L1 state capability*/
+		value = readl(port->base + RP_VEND_XP1);
+		value |= RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT;
+		writel(value, port->base + RP_VEND_XP1);
+	}
 }
 
 static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
@@ -2391,6 +2402,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
+	.has_aspm_l1 = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2412,6 +2424,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
+	.has_aspm_l1 = true,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2432,6 +2445,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.RAW_violation_fixup = true,
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
+	.has_aspm_l1 = true,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2460,6 +2474,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.RAW_violation_fixup = false,
 	.program_deskew_time = true,
 	.updateFC_threshold = true,
+	.has_aspm_l1 = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2481,6 +2496,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.RAW_violation_fixup = false,
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
+	.has_aspm_l1 = true,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.7.4

[PATCH 3/4] PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States

[Vidya Sagar]

Programs T_cmrt (Commmon Mode Restore Time) and T_pwr_on (Power On)
values to get them reflected in ASPM-L1 Sub-States capability registers
Also adjusts internal counter values according to 19.2 MHz clk_m value

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 65 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index e1526cc5d381..08da67a82a2d 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -40,6 +40,7 @@
 #include <linux/of_pci.h>
 #include <linux/of_platform.h>
 #include <linux/pci.h>
+#include <linux/pci-aspm.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/reset.h>
@@ -191,6 +192,27 @@
 #define RP_PRIV_XP_DL	0x494
 #define  RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD	(0x1ff << 1)
 
+#define RP_L1_PM_SUBSTATES_CTL				0xC00
+#define RP_L1_PM_SUBSTATES_CTL_CM_RTIME_MASK		(0xFF << 8)
+#define RP_L1_PM_SUBSTATES_CTL_CM_RTIME_SHIFT		8
+#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_MASK		(0x3 << 16)
+#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_SHIFT		16
+#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_MASK		(0x1F << 19)
+#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT		19
+#define RP_L1_PM_SUBSTATES_CTL_HIDE_CAP			(0x1 << 24)
+
+#define RP_L1_PM_SUBSTATES_1_CTL			0xC04
+#define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK	0x1FFF
+#define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY		0x26
+
+#define RP_L1_PM_SUBSTATES_2_CTL			0xC08
+#define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK	0x1FFF
+#define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY		0x4D
+#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_MASK	(0xFF << 13)
+#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND		(0x13 << 13)
+#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP_MASK	(0xF << 21)
+#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP	(0x2 << 21)
+
 #define RP_RX_HDR_LIMIT	0xe00
 #define  RP_RX_HDR_LIMIT_PW_MASK	(0xff << 8)
 #define  RP_RX_HDR_LIMIT_PW		(0x0e << 8)
@@ -331,6 +353,7 @@ struct tegra_pcie_soc {
 	bool program_deskew_time;
 	bool updateFC_threshold;
 	bool has_aspm_l1;
+	bool has_aspm_l1ss;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -423,6 +446,12 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
 	return readl(pcie->pads + offset);
 }
 
+u32 pcie_aspm_get_ltr_l_1_2_threshold(void)
+{
+	/* LTR L1.2 Threshold = 55us for all ports */
+	return ((0x37 << 16) | (0x02 << 29));
+}
+
 /*
  * The configuration space mapping on Tegra is somewhat similar to the ECAM
  * defined by PCIe. However it deviates a bit in how the 4 bits for extended
@@ -2262,6 +2291,37 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 		value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210;
 		writel(value, port->base + RP_VEND_XP);
 	}
+
+	if (soc->has_aspm_l1ss) {
+		/* Set Common Mode Restore Time to 30us */
+		value = readl(port->base + RP_L1_PM_SUBSTATES_CTL);
+		value &= ~RP_L1_PM_SUBSTATES_CTL_CM_RTIME_MASK;
+		value |= (0x1E << RP_L1_PM_SUBSTATES_CTL_CM_RTIME_SHIFT);
+		writel(value, port->base + RP_L1_PM_SUBSTATES_CTL);
+
+		/* set T_Power_On to 70us */
+		value = readl(port->base + RP_L1_PM_SUBSTATES_CTL);
+		value &= ~(RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_MASK |
+			RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_MASK);
+		value |= (1 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_SHIFT) |
+			(7 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT);
+		writel(value, port->base + RP_L1_PM_SUBSTATES_CTL);
+
+		/* Following is based on clk_m being 19.2 MHz */
+		value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL);
+		value &= ~RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK;
+		value |= RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY;
+		writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL);
+
+		value = readl(port->base + RP_L1_PM_SUBSTATES_2_CTL);
+		value &= ~RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK;
+		value |= RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY;
+		value &= ~RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_MASK;
+		value |= RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND;
+		value &= ~RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP_MASK;
+		value |= RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP;
+		writel(value, port->base + RP_L1_PM_SUBSTATES_2_CTL);
+	}
 }
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
@@ -2403,6 +2463,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
 	.has_aspm_l1 = false,
+	.has_aspm_l1ss = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2425,6 +2486,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
+	.has_aspm_l1ss = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2446,6 +2508,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
+	.has_aspm_l1ss = false,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2475,6 +2538,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.program_deskew_time = true,
 	.updateFC_threshold = true,
 	.has_aspm_l1 = true,
+	.has_aspm_l1ss = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2497,6 +2561,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
+	.has_aspm_l1ss = true,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.7.4

[PATCH 3/4] PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States

[Vidya Sagar]

Programs T_cmrt (Commmon Mode Restore Time) and T_pwr_on (Power On)
values to get them reflected in ASPM-L1 Sub-States capability registers
Also adjusts internal counter values according to 19.2 MHz clk_m value

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 65 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index e1526cc5d381..08da67a82a2d 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -40,6 +40,7 @@
 #include <linux/of_pci.h>
 #include <linux/of_platform.h>
 #include <linux/pci.h>
+#include <linux/pci-aspm.h>
 #include <linux/phy/phy.h>
 #include <linux/platform_device.h>
 #include <linux/reset.h>
@@ -191,6 +192,27 @@
 #define RP_PRIV_XP_DL	0x494
 #define  RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD	(0x1ff << 1)
 
+#define RP_L1_PM_SUBSTATES_CTL				0xC00
+#define RP_L1_PM_SUBSTATES_CTL_CM_RTIME_MASK		(0xFF << 8)
+#define RP_L1_PM_SUBSTATES_CTL_CM_RTIME_SHIFT		8
+#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_MASK		(0x3 << 16)
+#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_SHIFT		16
+#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_MASK		(0x1F << 19)
+#define RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT		19
+#define RP_L1_PM_SUBSTATES_CTL_HIDE_CAP			(0x1 << 24)
+
+#define RP_L1_PM_SUBSTATES_1_CTL			0xC04
+#define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK	0x1FFF
+#define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY		0x26
+
+#define RP_L1_PM_SUBSTATES_2_CTL			0xC08
+#define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK	0x1FFF
+#define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY		0x4D
+#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_MASK	(0xFF << 13)
+#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND		(0x13 << 13)
+#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP_MASK	(0xF << 21)
+#define RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP	(0x2 << 21)
+
 #define RP_RX_HDR_LIMIT	0xe00
 #define  RP_RX_HDR_LIMIT_PW_MASK	(0xff << 8)
 #define  RP_RX_HDR_LIMIT_PW		(0x0e << 8)
@@ -331,6 +353,7 @@ struct tegra_pcie_soc {
 	bool program_deskew_time;
 	bool updateFC_threshold;
 	bool has_aspm_l1;
+	bool has_aspm_l1ss;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -423,6 +446,12 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
 	return readl(pcie->pads + offset);
 }
 
+u32 pcie_aspm_get_ltr_l_1_2_threshold(void)
+{
+	/* LTR L1.2 Threshold = 55us for all ports */
+	return ((0x37 << 16) | (0x02 << 29));
+}
+
 /*
  * The configuration space mapping on Tegra is somewhat similar to the ECAM
  * defined by PCIe. However it deviates a bit in how the 4 bits for extended
@@ -2262,6 +2291,37 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 		value |= RP_VEND_XP_UPDATE_FC_THRESHOLD_T210;
 		writel(value, port->base + RP_VEND_XP);
 	}
+
+	if (soc->has_aspm_l1ss) {
+		/* Set Common Mode Restore Time to 30us */
+		value = readl(port->base + RP_L1_PM_SUBSTATES_CTL);
+		value &= ~RP_L1_PM_SUBSTATES_CTL_CM_RTIME_MASK;
+		value |= (0x1E << RP_L1_PM_SUBSTATES_CTL_CM_RTIME_SHIFT);
+		writel(value, port->base + RP_L1_PM_SUBSTATES_CTL);
+
+		/* set T_Power_On to 70us */
+		value = readl(port->base + RP_L1_PM_SUBSTATES_CTL);
+		value &= ~(RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_MASK |
+			RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_MASK);
+		value |= (1 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_SCL_SHIFT) |
+			(7 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT);
+		writel(value, port->base + RP_L1_PM_SUBSTATES_CTL);
+
+		/* Following is based on clk_m being 19.2 MHz */
+		value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL);
+		value &= ~RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK;
+		value |= RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY;
+		writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL);
+
+		value = readl(port->base + RP_L1_PM_SUBSTATES_2_CTL);
+		value &= ~RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK;
+		value |= RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY;
+		value &= ~RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_MASK;
+		value |= RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND;
+		value &= ~RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP_MASK;
+		value |= RP_L1_PM_SUBSTATES_2_CTL_MICROSECOND_COMP;
+		writel(value, port->base + RP_L1_PM_SUBSTATES_2_CTL);
+	}
 }
 /*
  * FIXME: If there are no PCIe cards attached, then calling this function
@@ -2403,6 +2463,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
 	.has_aspm_l1 = false,
+	.has_aspm_l1ss = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2425,6 +2486,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
+	.has_aspm_l1ss = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2446,6 +2508,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
+	.has_aspm_l1ss = false,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2475,6 +2538,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.program_deskew_time = true,
 	.updateFC_threshold = true,
 	.has_aspm_l1 = true,
+	.has_aspm_l1ss = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2497,6 +2561,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.program_deskew_time = false,
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
+	.has_aspm_l1ss = true,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.7.4

[PATCH 4/4] PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2

[Vidya Sagar]

sets CLKREQ asserted delay to a higher value to avoid
unnecessary wake up from L1.2_ENTRY state for Tegra210

Signed-off-by: Vidya Sagar <vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 drivers/pci/host/pci-tegra.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 08da67a82a2d..811209dedde2 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -204,6 +204,8 @@
 #define RP_L1_PM_SUBSTATES_1_CTL			0xC04
 #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK	0x1FFF
 #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY		0x26
+#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK		(0x1FF << 13)
+#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY		(0x27 << 13)
 
 #define RP_L1_PM_SUBSTATES_2_CTL			0xC08
 #define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK	0x1FFF
@@ -354,6 +356,7 @@ struct tegra_pcie_soc {
 	bool updateFC_threshold;
 	bool has_aspm_l1;
 	bool has_aspm_l1ss;
+	bool l1ss_rp_wake_fixup;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2307,6 +2310,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 			(7 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT);
 		writel(value, port->base + RP_L1_PM_SUBSTATES_CTL);
 
+		if (soc->l1ss_rp_wake_fixup) {
+			/* Set CLKREQ asserted delay greater than Power_Off
+			 * time (2us) to avoid RP wakeup in L1.2_ENTRY
+			 */
+			value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL);
+			value &= ~RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK;
+			value |= RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY;
+			writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL);
+		}
+
 		/* Following is based on clk_m being 19.2 MHz */
 		value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL);
 		value &= ~RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK;
@@ -2464,6 +2477,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.updateFC_threshold = false,
 	.has_aspm_l1 = false,
 	.has_aspm_l1ss = false,
+	.l1ss_rp_wake_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2487,6 +2501,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
 	.has_aspm_l1ss = false,
+	.l1ss_rp_wake_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2509,6 +2524,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
 	.has_aspm_l1ss = false,
+	.l1ss_rp_wake_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2539,6 +2555,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.updateFC_threshold = true,
 	.has_aspm_l1 = true,
 	.has_aspm_l1ss = true,
+	.l1ss_rp_wake_fixup = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2562,6 +2579,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
 	.has_aspm_l1ss = true,
+	.l1ss_rp_wake_fixup = false,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.7.4

[PATCH 4/4] PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2

[Vidya Sagar]

sets CLKREQ asserted delay to a higher value to avoid
unnecessary wake up from L1.2_ENTRY state for Tegra210

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 drivers/pci/host/pci-tegra.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 08da67a82a2d..811209dedde2 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -204,6 +204,8 @@
 #define RP_L1_PM_SUBSTATES_1_CTL			0xC04
 #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK	0x1FFF
 #define RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY		0x26
+#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK		(0x1FF << 13)
+#define RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY		(0x27 << 13)
 
 #define RP_L1_PM_SUBSTATES_2_CTL			0xC08
 #define RP_L1_PM_SUBSTATES_2_CTL_T_L1_2_DLY_MASK	0x1FFF
@@ -354,6 +356,7 @@ struct tegra_pcie_soc {
 	bool updateFC_threshold;
 	bool has_aspm_l1;
 	bool has_aspm_l1ss;
+	bool l1ss_rp_wake_fixup;
 };
 
 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
@@ -2307,6 +2310,16 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
 			(7 << RP_L1_PM_SUBSTATES_CTL_T_PWRN_VAL_SHIFT);
 		writel(value, port->base + RP_L1_PM_SUBSTATES_CTL);
 
+		if (soc->l1ss_rp_wake_fixup) {
+			/* Set CLKREQ asserted delay greater than Power_Off
+			 * time (2us) to avoid RP wakeup in L1.2_ENTRY
+			 */
+			value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL);
+			value &= ~RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY_MASK;
+			value |= RP_L1SS_1_CTL_CLKREQ_ASSERTED_DLY;
+			writel(value, port->base + RP_L1_PM_SUBSTATES_1_CTL);
+		}
+
 		/* Following is based on clk_m being 19.2 MHz */
 		value = readl(port->base + RP_L1_PM_SUBSTATES_1_CTL);
 		value &= ~RP_L1_PM_SUBSTATES_1_CTL_PWR_OFF_DLY_MASK;
@@ -2464,6 +2477,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
 	.updateFC_threshold = false,
 	.has_aspm_l1 = false,
 	.has_aspm_l1ss = false,
+	.l1ss_rp_wake_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra30_pcie = {
@@ -2487,6 +2501,7 @@ static const struct tegra_pcie_soc tegra30_pcie = {
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
 	.has_aspm_l1ss = false,
+	.l1ss_rp_wake_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra124_pcie = {
@@ -2509,6 +2524,7 @@ static const struct tegra_pcie_soc tegra124_pcie = {
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
 	.has_aspm_l1ss = false,
+	.l1ss_rp_wake_fixup = false,
 };
 
 static const struct tegra_pcie_soc tegra210_pcie = {
@@ -2539,6 +2555,7 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	.updateFC_threshold = true,
 	.has_aspm_l1 = true,
 	.has_aspm_l1ss = true,
+	.l1ss_rp_wake_fixup = true,
 };
 
 static const struct tegra_pcie_soc tegra186_pcie = {
@@ -2562,6 +2579,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 	.updateFC_threshold = false,
 	.has_aspm_l1 = true,
 	.has_aspm_l1ss = true,
+	.l1ss_rp_wake_fixup = false,
 };
 
 static const struct of_device_id tegra_pcie_of_match[] = {
-- 
2.7.4

Re: [PATCH 1/4] PCI/ASPM: Add API to supply LTR L1.2 threshold

[Rajat Jain]

On Mon, Oct 30, 2017 at 4:03 AM, Vidya Sagar <vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> adds API for host controller drivers to specify LTR L1.2
> threshold value if it is different from the default value.
> weak implementation of the API is added to supply default
> value
>
> Signed-off-by: Vidya Sagar <vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
>  drivers/pci/pcie/aspm.c  | 11 ++++++++---
>  include/linux/pci-aspm.h |  6 ++++++
>  2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 1dfa10cc566b..c6e8604796e5 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -436,6 +436,11 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
>         return NULL;
>  }
>
> +u32 __weak pcie_aspm_get_ltr_l_1_2_threshold(void)
> +{
> +       return LTR_L1_2_THRESHOLD_BITS;
> +}
> +
>  /* Calculate L1.2 PM substate timing parameters */
>  static void aspm_calc_l1ss_info(struct pcie_link_state *link,
>                                 struct aspm_register_info *upreg,
> @@ -458,10 +463,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
>         else
>                 link->l1ss.ctl1 |= val2 << 8;
>         /*
> -        * We currently use LTR L1.2 threshold to be fixed constant picked from
> -        * Intel's coreboot.
> +        * Get LTR L1.2 threshold value specific to a platform if present
> +        * Otherwise, get a constant value picked from Intel's coreboot.
>          */
> -       link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
> +       link->l1ss.ctl1 |= pcie_aspm_get_ltr_l_1_2_threshold();
>
>         /* Choose the greater of the two T_pwr_on */
>         val1 = (upreg->l1ss_cap >> 19) & 0x1F;
> diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
> index 207c561fb40e..7ffde0f57688 100644
> --- a/include/linux/pci-aspm.h
> +++ b/include/linux/pci-aspm.h
> @@ -30,6 +30,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
>  void pci_disable_link_state(struct pci_dev *pdev, int state);
>  void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
>  void pcie_no_aspm(void);
> +u32 pcie_aspm_get_ltr_l_1_2_threshold(void);
>  #else
>  static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
>  {
> @@ -49,6 +50,11 @@ static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
>  static inline void pcie_no_aspm(void)
>  {
>  }
> +
> +static inline u32 pcie_aspm_get_ltr_l_1_2_threshold(void)
> +{
> +       return 0;
> +}

Do we really need this (bogus) function definition in
!defined(CONFIG_PCIEASPM) case? I believe the other bogus definitions
in that section are needed because functions outside of
CONFIG_PCIEASPM call it.

>  #endif
>
>  #ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
> --
> 2.7.4
>

Re: [PATCH 1/4] PCI/ASPM: Add API to supply LTR L1.2 threshold

[Rajat Jain]

On Mon, Oct 30, 2017 at 4:03 AM, Vidya Sagar <vidyas@nvidia.com> wrote:
> adds API for host controller drivers to specify LTR L1.2
> threshold value if it is different from the default value.
> weak implementation of the API is added to supply default
> value
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  drivers/pci/pcie/aspm.c  | 11 ++++++++---
>  include/linux/pci-aspm.h |  6 ++++++
>  2 files changed, 14 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 1dfa10cc566b..c6e8604796e5 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -436,6 +436,11 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
>         return NULL;
>  }
>
> +u32 __weak pcie_aspm_get_ltr_l_1_2_threshold(void)
> +{
> +       return LTR_L1_2_THRESHOLD_BITS;
> +}
> +
>  /* Calculate L1.2 PM substate timing parameters */
>  static void aspm_calc_l1ss_info(struct pcie_link_state *link,
>                                 struct aspm_register_info *upreg,
> @@ -458,10 +463,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
>         else
>                 link->l1ss.ctl1 |= val2 << 8;
>         /*
> -        * We currently use LTR L1.2 threshold to be fixed constant picked from
> -        * Intel's coreboot.
> +        * Get LTR L1.2 threshold value specific to a platform if present
> +        * Otherwise, get a constant value picked from Intel's coreboot.
>          */
> -       link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
> +       link->l1ss.ctl1 |= pcie_aspm_get_ltr_l_1_2_threshold();
>
>         /* Choose the greater of the two T_pwr_on */
>         val1 = (upreg->l1ss_cap >> 19) & 0x1F;
> diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
> index 207c561fb40e..7ffde0f57688 100644
> --- a/include/linux/pci-aspm.h
> +++ b/include/linux/pci-aspm.h
> @@ -30,6 +30,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
>  void pci_disable_link_state(struct pci_dev *pdev, int state);
>  void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
>  void pcie_no_aspm(void);
> +u32 pcie_aspm_get_ltr_l_1_2_threshold(void);
>  #else
>  static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
>  {
> @@ -49,6 +50,11 @@ static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
>  static inline void pcie_no_aspm(void)
>  {
>  }
> +
> +static inline u32 pcie_aspm_get_ltr_l_1_2_threshold(void)
> +{
> +       return 0;
> +}

Do we really need this (bogus) function definition in
!defined(CONFIG_PCIEASPM) case? I believe the other bogus definitions
in that section are needed because functions outside of
CONFIG_PCIEASPM call it.

>  #endif
>
>  #ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
> --
> 2.7.4
>

Re: [PATCH 0/4] Add ASPM-L1 Substates support for Tegra

[Rajat Jain]

On Mon, Oct 30, 2017 at 4:03 AM, Vidya Sagar <vidyas-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> Tegra chips T210 and T186 support ASPM-L1 Substates (i.e. L1.1 and L1.2)
> This patch series
> - adds a generic API for root port controller drivers to
>   override the default value of LTR L1.2 Threhold which otherwise comes from
>   the same APIs weak implementation in aspm.c file

May be I'm imagining things, (and may be this is a question for
Bjorn), but is it possible to ever have a system that could have more
than 1 *type* of root port? If so, the current proposal only allows
for 1 value of LTR threshold (system wide) which may not be ideal.

> - applies fixups to reflect correct capability values for
>   T_cmrt (Common Mode Restore Time) and
>   T_pwr_on (Power On)
>   and adjusts counter values for 19.2 MHz of clk_m
> - applies fixup specific to T210 to avoid unnecessary wake ups from L1.2 state
>
> PCIe - ASPM L1 Sub States spec
> https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf
>
> Testing Done on T210 and T186
> - ASPM-L1:
>   Verified ASPM-L1 enablement by selecting PCIEASPM_POWERSAVE config
>   With the help of Tegra rootport's internal counter registers, confirmed
>   link entry in and out of ASPM-L1 state using USB3.0 add-on card, NVMe and NIC
>   cards
> - ASPM-L1 SubStates:
>   Verified ASPM-L1 Substates enablement by selecting PCIEASPM_POWER_SUPERSAVE config
>   Confirmed link's entry into L1SS using Westren Digital NVMe card (with Sandisk
>   Controller) using Tegra rootport's internal counter registers
>
> Vidya Sagar (4):
>   PCI/ASPM: Add API to supply LTR L1.2 threshold
>   PCI: tegra: Enable ASPM-L1 capability advertisement
>   PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States
>   PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2
>
>  drivers/pci/host/pci-tegra.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
>  drivers/pci/pcie/aspm.c      | 11 +++--
>  include/linux/pci-aspm.h     |  6 +++
>  3 files changed, 113 insertions(+), 3 deletions(-)
>
> --
> 2.7.4
>

Re: [PATCH 0/4] Add ASPM-L1 Substates support for Tegra

[Rajat Jain]

On Mon, Oct 30, 2017 at 4:03 AM, Vidya Sagar <vidyas@nvidia.com> wrote:
> Tegra chips T210 and T186 support ASPM-L1 Substates (i.e. L1.1 and L1.2)
> This patch series
> - adds a generic API for root port controller drivers to
>   override the default value of LTR L1.2 Threhold which otherwise comes from
>   the same APIs weak implementation in aspm.c file

May be I'm imagining things, (and may be this is a question for
Bjorn), but is it possible to ever have a system that could have more
than 1 *type* of root port? If so, the current proposal only allows
for 1 value of LTR threshold (system wide) which may not be ideal.

> - applies fixups to reflect correct capability values for
>   T_cmrt (Common Mode Restore Time) and
>   T_pwr_on (Power On)
>   and adjusts counter values for 19.2 MHz of clk_m
> - applies fixup specific to T210 to avoid unnecessary wake ups from L1.2 state
>
> PCIe - ASPM L1 Sub States spec
> https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf
>
> Testing Done on T210 and T186
> - ASPM-L1:
>   Verified ASPM-L1 enablement by selecting PCIEASPM_POWERSAVE config
>   With the help of Tegra rootport's internal counter registers, confirmed
>   link entry in and out of ASPM-L1 state using USB3.0 add-on card, NVMe and NIC
>   cards
> - ASPM-L1 SubStates:
>   Verified ASPM-L1 Substates enablement by selecting PCIEASPM_POWER_SUPERSAVE config
>   Confirmed link's entry into L1SS using Westren Digital NVMe card (with Sandisk
>   Controller) using Tegra rootport's internal counter registers
>
> Vidya Sagar (4):
>   PCI/ASPM: Add API to supply LTR L1.2 threshold
>   PCI: tegra: Enable ASPM-L1 capability advertisement
>   PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States
>   PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2
>
>  drivers/pci/host/pci-tegra.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
>  drivers/pci/pcie/aspm.c      | 11 +++--
>  include/linux/pci-aspm.h     |  6 +++
>  3 files changed, 113 insertions(+), 3 deletions(-)
>
> --
> 2.7.4
>

Re: [PATCH 1/4] PCI/ASPM: Add API to supply LTR L1.2 threshold

[Vidya Sagar]

On Monday 30 October 2017 10:25 PM, Rajat Jain wrote:
> On Mon, Oct 30, 2017 at 4:03 AM, Vidya Sagar <vidyas@nvidia.com> wrote:
>> adds API for host controller drivers to specify LTR L1.2
>> threshold value if it is different from the default value.
>> weak implementation of the API is added to supply default
>> value
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>>   drivers/pci/pcie/aspm.c  | 11 ++++++++---
>>   include/linux/pci-aspm.h |  6 ++++++
>>   2 files changed, 14 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
>> index 1dfa10cc566b..c6e8604796e5 100644
>> --- a/drivers/pci/pcie/aspm.c
>> +++ b/drivers/pci/pcie/aspm.c
>> @@ -436,6 +436,11 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
>>          return NULL;
>>   }
>>
>> +u32 __weak pcie_aspm_get_ltr_l_1_2_threshold(void)
>> +{
>> +       return LTR_L1_2_THRESHOLD_BITS;
>> +}
>> +
>>   /* Calculate L1.2 PM substate timing parameters */
>>   static void aspm_calc_l1ss_info(struct pcie_link_state *link,
>>                                  struct aspm_register_info *upreg,
>> @@ -458,10 +463,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
>>          else
>>                  link->l1ss.ctl1 |= val2 << 8;
>>          /*
>> -        * We currently use LTR L1.2 threshold to be fixed constant picked from
>> -        * Intel's coreboot.
>> +        * Get LTR L1.2 threshold value specific to a platform if present
>> +        * Otherwise, get a constant value picked from Intel's coreboot.
>>           */
>> -       link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
>> +       link->l1ss.ctl1 |= pcie_aspm_get_ltr_l_1_2_threshold();
>>
>>          /* Choose the greater of the two T_pwr_on */
>>          val1 = (upreg->l1ss_cap >> 19) & 0x1F;
>> diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
>> index 207c561fb40e..7ffde0f57688 100644
>> --- a/include/linux/pci-aspm.h
>> +++ b/include/linux/pci-aspm.h
>> @@ -30,6 +30,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
>>   void pci_disable_link_state(struct pci_dev *pdev, int state);
>>   void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
>>   void pcie_no_aspm(void);
>> +u32 pcie_aspm_get_ltr_l_1_2_threshold(void);
>>   #else
>>   static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
>>   {
>> @@ -49,6 +50,11 @@ static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
>>   static inline void pcie_no_aspm(void)
>>   {
>>   }
>> +
>> +static inline u32 pcie_aspm_get_ltr_l_1_2_threshold(void)
>> +{
>> +       return 0;
>> +}
> Do we really need this (bogus) function definition in
> !defined(CONFIG_PCIEASPM) case? I believe the other bogus definitions
> in that section are needed because functions outside of
> CONFIG_PCIEASPM call it.
I'll remove it in my next patch.
>>   #endif
>>
>>   #ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
>> --
>> 2.7.4
>>

Re: [PATCH 1/4] PCI/ASPM: Add API to supply LTR L1.2 threshold

[Vidya Sagar]

On Monday 30 October 2017 10:25 PM, Rajat Jain wrote:
> On Mon, Oct 30, 2017 at 4:03 AM, Vidya Sagar <vidyas@nvidia.com> wrote:
>> adds API for host controller drivers to specify LTR L1.2
>> threshold value if it is different from the default value.
>> weak implementation of the API is added to supply default
>> value
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>>   drivers/pci/pcie/aspm.c  | 11 ++++++++---
>>   include/linux/pci-aspm.h |  6 ++++++
>>   2 files changed, 14 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
>> index 1dfa10cc566b..c6e8604796e5 100644
>> --- a/drivers/pci/pcie/aspm.c
>> +++ b/drivers/pci/pcie/aspm.c
>> @@ -436,6 +436,11 @@ static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
>>          return NULL;
>>   }
>>
>> +u32 __weak pcie_aspm_get_ltr_l_1_2_threshold(void)
>> +{
>> +       return LTR_L1_2_THRESHOLD_BITS;
>> +}
>> +
>>   /* Calculate L1.2 PM substate timing parameters */
>>   static void aspm_calc_l1ss_info(struct pcie_link_state *link,
>>                                  struct aspm_register_info *upreg,
>> @@ -458,10 +463,10 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
>>          else
>>                  link->l1ss.ctl1 |= val2 << 8;
>>          /*
>> -        * We currently use LTR L1.2 threshold to be fixed constant picked from
>> -        * Intel's coreboot.
>> +        * Get LTR L1.2 threshold value specific to a platform if present
>> +        * Otherwise, get a constant value picked from Intel's coreboot.
>>           */
>> -       link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
>> +       link->l1ss.ctl1 |= pcie_aspm_get_ltr_l_1_2_threshold();
>>
>>          /* Choose the greater of the two T_pwr_on */
>>          val1 = (upreg->l1ss_cap >> 19) & 0x1F;
>> diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
>> index 207c561fb40e..7ffde0f57688 100644
>> --- a/include/linux/pci-aspm.h
>> +++ b/include/linux/pci-aspm.h
>> @@ -30,6 +30,7 @@ void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
>>   void pci_disable_link_state(struct pci_dev *pdev, int state);
>>   void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
>>   void pcie_no_aspm(void);
>> +u32 pcie_aspm_get_ltr_l_1_2_threshold(void);
>>   #else
>>   static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
>>   {
>> @@ -49,6 +50,11 @@ static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
>>   static inline void pcie_no_aspm(void)
>>   {
>>   }
>> +
>> +static inline u32 pcie_aspm_get_ltr_l_1_2_threshold(void)
>> +{
>> +       return 0;
>> +}
> Do we really need this (bogus) function definition in
> !defined(CONFIG_PCIEASPM) case? I believe the other bogus definitions
> in that section are needed because functions outside of
> CONFIG_PCIEASPM call it.
I'll remove it in my next patch.
>>   #endif
>>
>>   #ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
>> --
>> 2.7.4
>>