* [PATCH linux dev-4.10 v2] arm: dts: aspeed: Add missing clock sources for barreleye
@ 2017-05-25 21:13 Eddie James
2017-05-26 4:33 ` Joel Stanley
0 siblings, 1 reply; 4+ messages in thread
From: Eddie James @ 2017-05-25 21:13 UTC (permalink / raw)
To: openbmc; +Cc: joel, Edward A. James
From: "Edward A. James" <eajames@us.ibm.com>
Reorganize flash controllers into the ast2400 config. Barreleye wasn't
booting with the new aspeed-smc driver.
Signed-off-by: Edward A. James <eajames@us.ibm.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++--------------
arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 52 ++++++++------------------
arch/arm/boot/dts/aspeed-g4.dtsi | 34 +++++++++++++++++
3 files changed, 66 insertions(+), 64 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts b/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
index be1f2d1..7a616bb 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
@@ -31,34 +31,6 @@
};
};
- ahb {
- bmc_pnor: fmc@1e620000 {
- reg = < 0x1e620000 0x94
- 0x20000000 0x02000000 >;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "aspeed,ast2400-fmc";
- flash@0 {
- reg = < 0 >;
- compatible = "jedec,spi-nor" ;
-#include "aspeed-bmc-opp-flash-layout.dtsi"
- };
- };
-
- host_pnor: spi@1e630000 {
- reg = < 0x1e630000 0x18
- 0x30000000 0x02000000 >;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "aspeed,ast2400-spi";
- flash@0 {
- reg = < 0 >;
- compatible = "jedec,spi-nor" ;
- label = "pnor";
- };
- };
- };
-
leds {
compatible = "gpio-leds";
@@ -76,6 +48,22 @@
};
};
+&bmc_pnor {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+ };
+};
+
+&host_pnor {
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ };
+};
+
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
index b4faa1d..e55abe6 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
@@ -47,42 +47,6 @@
};
};
- ahb {
- bmc_pnor: fmc@1e620000 {
- reg = < 0x1e620000 0x94
- 0x20000000 0x02000000 >;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "aspeed,ast2400-fmc";
- aspeed,fmc-has-dma;
- interrupts = <19>;
- clocks = <&clk_ahb>;
- clock-names = "ahb";
- flash@0 {
- reg = < 0 >;
- compatible = "jedec,spi-nor" ;
- m25p,fast-read;
-#include "aspeed-bmc-opp-flash-layout.dtsi"
- };
- };
-
- host_pnor: spi@1e630000 {
- reg = < 0x1e630000 0x18
- 0x30000000 0x02000000 >;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "aspeed,ast2400-spi";
- clocks = <&clk_ahb>;
- clock-names = "ahb";
- flash {
- reg = < 0 >;
- compatible = "jedec,spi-nor" ;
- label = "pnor";
- m25p,fast-read;
- };
- };
- };
-
gpio-fsi {
compatible = "fsi-master-gpio", "fsi-master";
@@ -94,6 +58,22 @@
};
};
+&bmc_pnor {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+#include "aspeed-bmc-opp-flash-layout.dtsi"
+ };
+};
+
+&host_pnor {
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ };
+};
+
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index d8827d5..9fb7889 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -44,6 +44,40 @@
#size-cells = <1>;
ranges;
+ bmc_pnor: fmc@1e620000 {
+ reg = < 0x1e620000 0x94
+ 0x20000000 0x02000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2400-fmc";
+ status = "disabled";
+ aspeed,fmc-has-dma;
+ interrupts = <19>;
+ clocks = <&clk_ahb>;
+ clock-names = "ahb";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+ status = "disabled";
+ };
+ };
+
+ host_pnor: spi@1e630000 {
+ reg = < 0x1e630000 0x18
+ 0x30000000 0x02000000 >;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "aspeed,ast2400-spi";
+ status = "disabled";
+ clocks = <&clk_ahb>;
+ clock-names = "ahb";
+ flash@0 {
+ reg = < 0 >;
+ compatible = "jedec,spi-nor" ;
+ status = "disabled";
+ };
+ };
+
vic: interrupt-controller@1e6c0080 {
compatible = "aspeed,ast2400-vic";
interrupt-controller;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH linux dev-4.10 v2] arm: dts: aspeed: Add missing clock sources for barreleye
2017-05-25 21:13 [PATCH linux dev-4.10 v2] arm: dts: aspeed: Add missing clock sources for barreleye Eddie James
@ 2017-05-26 4:33 ` Joel Stanley
2017-05-26 6:17 ` Cédric Le Goater
0 siblings, 1 reply; 4+ messages in thread
From: Joel Stanley @ 2017-05-26 4:33 UTC (permalink / raw)
To: Eddie James; +Cc: OpenBMC Maillist, Edward A. James, Cédric Le Goater
On Fri, May 26, 2017 at 7:13 AM, Eddie James <eajames@linux.vnet.ibm.com> wrote:
> From: "Edward A. James" <eajames@us.ibm.com>
>
> Reorganize flash controllers into the ast2400 config. Barreleye wasn't
> booting with the new aspeed-smc driver.
Your commit message mentions Barreleye, but you're also updating Palmetto.
Can you please update all of the ast2400 platforms?
Also cc Cedric on your next version so he can check that we're doing
the correct thing.
>
> Signed-off-by: Edward A. James <eajames@us.ibm.com>
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++--------------
> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 52 ++++++++------------------
> arch/arm/boot/dts/aspeed-g4.dtsi | 34 +++++++++++++++++
> 3 files changed, 66 insertions(+), 64 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts b/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
> index be1f2d1..7a616bb 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
> @@ -31,34 +31,6 @@
> };
> };
>
> - ahb {
> - bmc_pnor: fmc@1e620000 {
> - reg = < 0x1e620000 0x94
> - 0x20000000 0x02000000 >;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "aspeed,ast2400-fmc";
> - flash@0 {
> - reg = < 0 >;
> - compatible = "jedec,spi-nor" ;
> -#include "aspeed-bmc-opp-flash-layout.dtsi"
> - };
> - };
> -
> - host_pnor: spi@1e630000 {
> - reg = < 0x1e630000 0x18
> - 0x30000000 0x02000000 >;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "aspeed,ast2400-spi";
> - flash@0 {
> - reg = < 0 >;
> - compatible = "jedec,spi-nor" ;
> - label = "pnor";
> - };
> - };
> - };
> -
> leds {
> compatible = "gpio-leds";
>
> @@ -76,6 +48,22 @@
> };
> };
>
> +&bmc_pnor {
> + status = "okay";
> + flash@0 {
> + status = "okay";
> + m25p,fast-read;
> +#include "aspeed-bmc-opp-flash-layout.dtsi"
> + };
> +};
> +
> +&host_pnor {
> + flash@0 {
> + status = "okay";
> + m25p,fast-read;
> + };
> +};
> +
> &pinctrl {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> index b4faa1d..e55abe6 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
> @@ -47,42 +47,6 @@
> };
> };
>
> - ahb {
> - bmc_pnor: fmc@1e620000 {
> - reg = < 0x1e620000 0x94
> - 0x20000000 0x02000000 >;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "aspeed,ast2400-fmc";
> - aspeed,fmc-has-dma;
> - interrupts = <19>;
> - clocks = <&clk_ahb>;
> - clock-names = "ahb";
> - flash@0 {
> - reg = < 0 >;
> - compatible = "jedec,spi-nor" ;
> - m25p,fast-read;
> -#include "aspeed-bmc-opp-flash-layout.dtsi"
> - };
> - };
> -
> - host_pnor: spi@1e630000 {
> - reg = < 0x1e630000 0x18
> - 0x30000000 0x02000000 >;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "aspeed,ast2400-spi";
> - clocks = <&clk_ahb>;
> - clock-names = "ahb";
> - flash {
> - reg = < 0 >;
> - compatible = "jedec,spi-nor" ;
> - label = "pnor";
> - m25p,fast-read;
> - };
> - };
> - };
> -
> gpio-fsi {
> compatible = "fsi-master-gpio", "fsi-master";
>
> @@ -94,6 +58,22 @@
> };
> };
>
> +&bmc_pnor {
> + status = "okay";
> + flash@0 {
> + status = "okay";
> + m25p,fast-read;
> +#include "aspeed-bmc-opp-flash-layout.dtsi"
> + };
> +};
> +
> +&host_pnor {
> + flash@0 {
> + status = "okay";
> + m25p,fast-read;
> + };
> +};
> +
> &pinctrl {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
> index d8827d5..9fb7889 100644
> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
> @@ -44,6 +44,40 @@
> #size-cells = <1>;
> ranges;
>
> + bmc_pnor: fmc@1e620000 {
> + reg = < 0x1e620000 0x94
> + 0x20000000 0x02000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2400-fmc";
> + status = "disabled";
> + aspeed,fmc-has-dma;
> + interrupts = <19>;
> + clocks = <&clk_ahb>;
> + clock-names = "ahb";
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor" ;
> + status = "disabled";
> + };
> + };
> +
> + host_pnor: spi@1e630000 {
> + reg = < 0x1e630000 0x18
> + 0x30000000 0x02000000 >;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "aspeed,ast2400-spi";
> + status = "disabled";
> + clocks = <&clk_ahb>;
> + clock-names = "ahb";
> + flash@0 {
> + reg = < 0 >;
> + compatible = "jedec,spi-nor" ;
> + status = "disabled";
> + };
> + };
> +
> vic: interrupt-controller@1e6c0080 {
> compatible = "aspeed,ast2400-vic";
> interrupt-controller;
> --
> 1.8.3.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH linux dev-4.10 v2] arm: dts: aspeed: Add missing clock sources for barreleye
2017-05-26 4:33 ` Joel Stanley
@ 2017-05-26 6:17 ` Cédric Le Goater
2017-05-31 12:47 ` Joel Stanley
0 siblings, 1 reply; 4+ messages in thread
From: Cédric Le Goater @ 2017-05-26 6:17 UTC (permalink / raw)
To: Joel Stanley, Eddie James; +Cc: OpenBMC Maillist, Edward A. James
On 05/26/2017 06:33 AM, Joel Stanley wrote:
> On Fri, May 26, 2017 at 7:13 AM, Eddie James <eajames@linux.vnet.ibm.com> wrote:
>> From: "Edward A. James" <eajames@us.ibm.com>
>>
>> Reorganize flash controllers into the ast2400 config. Barreleye wasn't
>> booting with the new aspeed-smc driver.
>
> Your commit message mentions Barreleye, but you're also updating Palmetto.
>
> Can you please update all of the ast2400 platforms?
>
> Also cc Cedric on your next version so he can check that we're doing
> the correct thing.
Joel,
I would also like to add CONFIG_VMSPLIT_2G on the G4 to define
correctly the SMC controller flash mapping window on the AHB Bus.
It is limited to 32MB currently
Do you think we can take these ?
http://patchwork.ozlabs.org/patch/752285/
http://patchwork.ozlabs.org/patch/752287/
C.
>> Signed-off-by: Edward A. James <eajames@us.ibm.com>
>> ---
>> arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts | 44 ++++++++--------------
>> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 52 ++++++++------------------
>> arch/arm/boot/dts/aspeed-g4.dtsi | 34 +++++++++++++++++
>> 3 files changed, 66 insertions(+), 64 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts b/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
>> index be1f2d1..7a616bb 100644
>> --- a/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
>> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-barreleye.dts
>> @@ -31,34 +31,6 @@
>> };
>> };
>>
>> - ahb {
>> - bmc_pnor: fmc@1e620000 {
>> - reg = < 0x1e620000 0x94
>> - 0x20000000 0x02000000 >;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "aspeed,ast2400-fmc";
>> - flash@0 {
>> - reg = < 0 >;
>> - compatible = "jedec,spi-nor" ;
>> -#include "aspeed-bmc-opp-flash-layout.dtsi"
>> - };
>> - };
>> -
>> - host_pnor: spi@1e630000 {
>> - reg = < 0x1e630000 0x18
>> - 0x30000000 0x02000000 >;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "aspeed,ast2400-spi";
>> - flash@0 {
>> - reg = < 0 >;
>> - compatible = "jedec,spi-nor" ;
>> - label = "pnor";
>> - };
>> - };
>> - };
>> -
>> leds {
>> compatible = "gpio-leds";
>>
>> @@ -76,6 +48,22 @@
>> };
>> };
>>
>> +&bmc_pnor {
>> + status = "okay";
>> + flash@0 {
>> + status = "okay";
>> + m25p,fast-read;
>> +#include "aspeed-bmc-opp-flash-layout.dtsi"
>> + };
>> +};
>> +
>> +&host_pnor {
>> + flash@0 {
>> + status = "okay";
>> + m25p,fast-read;
>> + };
>> +};
>> +
>> &pinctrl {
>> pinctrl-names = "default";
>> pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
>> diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
>> index b4faa1d..e55abe6 100644
>> --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
>> +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts
>> @@ -47,42 +47,6 @@
>> };
>> };
>>
>> - ahb {
>> - bmc_pnor: fmc@1e620000 {
>> - reg = < 0x1e620000 0x94
>> - 0x20000000 0x02000000 >;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "aspeed,ast2400-fmc";
>> - aspeed,fmc-has-dma;
>> - interrupts = <19>;
>> - clocks = <&clk_ahb>;
>> - clock-names = "ahb";
>> - flash@0 {
>> - reg = < 0 >;
>> - compatible = "jedec,spi-nor" ;
>> - m25p,fast-read;
>> -#include "aspeed-bmc-opp-flash-layout.dtsi"
>> - };
>> - };
>> -
>> - host_pnor: spi@1e630000 {
>> - reg = < 0x1e630000 0x18
>> - 0x30000000 0x02000000 >;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - compatible = "aspeed,ast2400-spi";
>> - clocks = <&clk_ahb>;
>> - clock-names = "ahb";
>> - flash {
>> - reg = < 0 >;
>> - compatible = "jedec,spi-nor" ;
>> - label = "pnor";
>> - m25p,fast-read;
>> - };
>> - };
>> - };
>> -
>> gpio-fsi {
>> compatible = "fsi-master-gpio", "fsi-master";
>>
>> @@ -94,6 +58,22 @@
>> };
>> };
>>
>> +&bmc_pnor {
>> + status = "okay";
>> + flash@0 {
>> + status = "okay";
>> + m25p,fast-read;
>> +#include "aspeed-bmc-opp-flash-layout.dtsi"
>> + };
>> +};
>> +
>> +&host_pnor {
>> + flash@0 {
>> + status = "okay";
>> + m25p,fast-read;
>> + };
>> +};
>> +
>> &pinctrl {
>> pinctrl-names = "default";
>> pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
>> diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
>> index d8827d5..9fb7889 100644
>> --- a/arch/arm/boot/dts/aspeed-g4.dtsi
>> +++ b/arch/arm/boot/dts/aspeed-g4.dtsi
>> @@ -44,6 +44,40 @@
>> #size-cells = <1>;
>> ranges;
>>
>> + bmc_pnor: fmc@1e620000 {
>> + reg = < 0x1e620000 0x94
>> + 0x20000000 0x02000000 >;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "aspeed,ast2400-fmc";
>> + status = "disabled";
>> + aspeed,fmc-has-dma;
>> + interrupts = <19>;
>> + clocks = <&clk_ahb>;
>> + clock-names = "ahb";
>> + flash@0 {
>> + reg = < 0 >;
>> + compatible = "jedec,spi-nor" ;
>> + status = "disabled";
>> + };
>> + };
>> +
>> + host_pnor: spi@1e630000 {
>> + reg = < 0x1e630000 0x18
>> + 0x30000000 0x02000000 >;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "aspeed,ast2400-spi";
>> + status = "disabled";
>> + clocks = <&clk_ahb>;
>> + clock-names = "ahb";
>> + flash@0 {
>> + reg = < 0 >;
>> + compatible = "jedec,spi-nor" ;
>> + status = "disabled";
>> + };
>> + };
>> +
>> vic: interrupt-controller@1e6c0080 {
>> compatible = "aspeed,ast2400-vic";
>> interrupt-controller;
>> --
>> 1.8.3.1
>>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH linux dev-4.10 v2] arm: dts: aspeed: Add missing clock sources for barreleye
2017-05-26 6:17 ` Cédric Le Goater
@ 2017-05-31 12:47 ` Joel Stanley
0 siblings, 0 replies; 4+ messages in thread
From: Joel Stanley @ 2017-05-31 12:47 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: Eddie James, OpenBMC Maillist, Edward A. James
On Fri, May 26, 2017 at 3:47 PM, Cédric Le Goater <clg@kaod.org> wrote:
> On 05/26/2017 06:33 AM, Joel Stanley wrote:
>> On Fri, May 26, 2017 at 7:13 AM, Eddie James <eajames@linux.vnet.ibm.com> wrote:
>>> From: "Edward A. James" <eajames@us.ibm.com>
>>>
>>> Reorganize flash controllers into the ast2400 config. Barreleye wasn't
>>> booting with the new aspeed-smc driver.
>>
>> Your commit message mentions Barreleye, but you're also updating Palmetto.
>>
>> Can you please update all of the ast2400 platforms?
>>
>> Also cc Cedric on your next version so he can check that we're doing
>> the correct thing.
>
> Joel,
>
> I would also like to add CONFIG_VMSPLIT_2G on the G4 to define
> correctly the SMC controller flash mapping window on the AHB Bus.
> It is limited to 32MB currently
Yes, we should do that, I agree.
>
> Do you think we can take these ?
>
> http://patchwork.ozlabs.org/patch/752285/
"ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers"
This one did not apply, as the device tree we have in dev-4.10 is
ancient compared to upstream. I think Eddie's series that converts the
machines over to match the ast2500 should help.
I will apply it once I have applied Eddie's v5 (as v4 needs some fixes
for missing fast-read properties).
> http://patchwork.ozlabs.org/patch/752287/
I applied this one.
Apologies for not applying them earlier. I had assumed they were
intended for the upstream tree. I have applied both of them to my
staging tree for upstream as well.
Cheers,
Joel
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-05-31 12:48 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2017-05-25 21:13 [PATCH linux dev-4.10 v2] arm: dts: aspeed: Add missing clock sources for barreleye Eddie James
2017-05-26 4:33 ` Joel Stanley
2017-05-26 6:17 ` Cédric Le Goater
2017-05-31 12:47 ` Joel Stanley
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