[PATCH v3 0/8] Renesas RZ PFC and GPIO driver

[PATCH v3 0/8] Renesas RZ PFC and GPIO driver

[Jacopo Mondi]

Hello
   here it is v3 of PFC and GPIO driver for Renesas RZ SoC Series.

I'll premit that this series goes in the "pin-based PFC HW in group-based PFC
software" direction, and that, after some discussions on v1, it is
not clear yet if this is desirable for RZ series or we may want to explore
other solutions.

Compared to v2 I have fixed Linus' remarks on GPIO driver, and made it to use
a "more standard" set of registers among other RZ SoC to drive gpio pins
(thanks Chris for pointing this out).
Other bits in the driver changed, but that's mostly cosmetic stuff.

I have applied on top of PFC patch one of the patches I sent as RFC
(pinctrl: sh-pfc: r7s72100: Add IO mode selection) to set previously ignored
PIPC, PIBC and PBDC register to let the alternate function decide the pin's
I/O mode.

Other minor fixes applied to dts and dtsi.
Changes to the GPIO driver have required dtsi to change accordingly, in order
to provide memory regions for the newly used registers.

As per the previous submission, I can only test accessing an i2c-gpio eeprom,
so everyone interested (and with an actual test board on the desk) may want to
test and possibly provide feedbacks.

Thanks
   j

---

v1 -> v2:
    - split node addition in r7s72100.dtsi and r7s72100-genami.dts in 2 patches
    - break down addition of peripheral nodes in  r7s72100-genami.dts in 4
      patches
    - drop GPIO aliases in .dtsi file

v2 -> v3:
    - Add IO mode selection patch on top of PFC driver
    - Reworked commit messages that looked ugly in PFC and GPIO driver
    - Reworked GPIO driver to include Linus review comments and change the
      set of registers used to set pin's direction/value
    - Changed dtsi to make PFC and GPIO iomem regions not overlap
    - Drop "renesas" prefix from "groups" and "function" attributes as
      suggested by Geert.
---

Geert Uytterhoeven (1):
  arm: dts: r7s72100-genmai: Add pinctrl for RSPI

Jacopo Mondi (1):
  pinctrl: sh-pfc: r7s72100: Configure I/O mode

Magnus Damm (5):
  pinctrl: sh-pfc: Add r7s72100 PFC driver
  gpio: gpio-rz: GPIO driver for Renesas RZ series
  arm: dts: r7s72100: GPIO and PFC device nodes
  arm: dts: r7s72100-genmai: SCIF2 PINCTRL configuration
  arm: dts: r7s72100-genmai: LED1 and LED2 support

Simon Horman (1):
  arm: dts: r7s72100-genmai:Add ethernet PFC node

 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       |   1 +
 arch/arm/boot/dts/r7s72100-genmai.dts              |  50 ++
 arch/arm/boot/dts/r7s72100.dtsi                    | 136 ++++++
 drivers/gpio/Kconfig                               |   6 +
 drivers/gpio/Makefile                              |   1 +
 drivers/gpio/gpio-rz.c                             | 211 ++++++++
 drivers/pinctrl/sh-pfc/Kconfig                     |   5 +
 drivers/pinctrl/sh-pfc/Makefile                    |   1 +
 drivers/pinctrl/sh-pfc/core.c                      |   6 +
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c              | 532 +++++++++++++++++++++
 drivers/pinctrl/sh-pfc/sh_pfc.h                    |   9 +-
 11 files changed, 955 insertions(+), 3 deletions(-)
 create mode 100644 drivers/gpio/gpio-rz.c
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r7s72100.c

-- 
2.7.4

[PATCH v3 1/8] pinctrl: sh-pfc: Add r7s72100 PFC driver

[Jacopo Mondi]

From: Magnus Damm <damm@opensource.se>

Squash commits in Geert's renesas-driver/genmai-gpio-and-pfc branch that
add support for r7s72100 PFC.
This squash combines commits for Magnus' original driver, several
"groups" definitions and minor fixes on top to forward-port it to a more
recent kernel (v4.10)

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 .../bindings/pinctrl/renesas,pfc-pinctrl.txt       |   1 +
 drivers/pinctrl/sh-pfc/Kconfig                     |   5 +
 drivers/pinctrl/sh-pfc/Makefile                    |   1 +
 drivers/pinctrl/sh-pfc/core.c                      |   6 +
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c              | 529 +++++++++++++++++++++
 drivers/pinctrl/sh-pfc/sh_pfc.h                    |   9 +-
 6 files changed, 548 insertions(+), 3 deletions(-)
 create mode 100644 drivers/pinctrl/sh-pfc/pfc-r7s72100.c

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 13df949..bd6629b 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -11,6 +11,7 @@ Required Properties:
 
   - compatible: should be one of the following.
     - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
+    - "renesas,pfc-r7s72100": for R7S72100 (RZ/A1H) compatible pin-controller.
     - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
     - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
     - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller.
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 07eca54..e4ccae2 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -24,6 +24,11 @@ config PINCTRL_PFC_EMEV2
 	depends on ARCH_EMEV2
 	select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R7S72100
+	def_bool y
+	depends on ARCH_R7S72100
+	select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A73A4
 	def_bool y
 	depends on ARCH_R8A73A4
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 2dda8c6..b953392 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -1,6 +1,7 @@
 obj-$(CONFIG_PINCTRL_SH_PFC)	+= core.o pinctrl.o
 obj-$(CONFIG_PINCTRL_SH_PFC_GPIO)	+= gpio.o
 obj-$(CONFIG_PINCTRL_PFC_EMEV2)	+= pfc-emev2.o
+obj-$(CONFIG_PINCTRL_PFC_R7S72100)	+= pfc-r7s72100.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)	+= pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)	+= pfc-r8a7740.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7778)	+= pfc-r8a7778.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index cf80ce1..c0d74e1 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -473,6 +473,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
 		.data = &emev2_pinmux_info,
 	},
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R7S72100
+	{
+		.compatible = "renesas,pfc-r7s72100",
+		.data = &r7s72100_pinmux_info,
+	},
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
 	{
 		.compatible = "renesas,pfc-r8a73a4",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r7s72100.c b/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
new file mode 100644
index 0000000..72e1dff
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
@@ -0,0 +1,529 @@
+/*
+ * R7S72100 processor support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ */
+
+#include <linux/kernel.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, sfx)						\
+	PORT_GP_16(0, fn, sfx), PORT_GP_16(1, fn, sfx),			\
+	PORT_GP_16(2, fn, sfx), PORT_GP_16(3, fn, sfx),			\
+	PORT_GP_16(4, fn, sfx), PORT_GP_16(5, fn, sfx),			\
+	PORT_GP_16(6, fn, sfx), PORT_GP_16(7, fn, sfx),			\
+	PORT_GP_16(8, fn, sfx), PORT_GP_16(9, fn, sfx),			\
+	PORT_GP_16(10, fn, sfx), PORT_GP_16(11, fn, sfx),			\
+	PORT_GP_16(12, fn, sfx)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(PMC_0), GP_ALL(PMC_1),
+	GP_ALL(PFC_0), GP_ALL(PFC_1),
+	GP_ALL(PFCE_0), GP_ALL(PFCE_1),
+	GP_ALL(PFCAE_0), GP_ALL(PFCAE_1),
+	GP_ALL(PIBC_0), GP_ALL(PIBC_1),
+	GP_ALL(PBDC_0), GP_ALL(PBDC_1),
+	GP_ALL(PIPC_0), GP_ALL(PIPC_1),
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+	GP_ALL(MARK_FN1), GP_ALL(MARK_FN2), GP_ALL(MARK_FN3), GP_ALL(MARK_FN4),
+	GP_ALL(MARK_FN5), GP_ALL(MARK_FN6), GP_ALL(MARK_FN7), GP_ALL(MARK_FN8),
+	PINMUX_MARK_END,
+};
+
+#define _P_ALL(n) CPU_ALL_PORT(n, unused)
+
+#define _P_GPIO(bank, _pin, _name, sfx, cfg) \
+	_GP_GPIO(16, bank, _pin, _name, sfx, cfg)
+
+#define _P_DATA(bank, pin, name, sfx, cfg)					\
+	PINMUX_DATA(name##_DATA, name##_PMC_0,		\
+		    name##_PIBC_1, name##_PBDC_1)
+
+#define _P_FN(n, fn, pfcae, pfce, pfc)					\
+	PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1,		\
+		    n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)
+
+#define _P_MARK_FN1(bank, pin, name, sfx, cfg) _P_FN(name, 1, 0, 0, 0)
+#define _P_MARK_FN2(bank, pin, name, sfx, cfg) _P_FN(name, 2, 0, 0, 1)
+#define _P_MARK_FN3(bank, pin, name, sfx, cfg) _P_FN(name, 3, 0, 1, 0)
+#define _P_MARK_FN4(bank, pin, name, sfx, cfg) _P_FN(name, 4, 0, 1, 1)
+#define _P_MARK_FN5(bank, pin, name, sfx, cfg) _P_FN(name, 5, 1, 0, 0)
+#define _P_MARK_FN6(bank, pin, name, sfx, cfg) _P_FN(name, 6, 1, 0, 1)
+#define _P_MARK_FN7(bank, pin, name, sfx, cfg) _P_FN(name, 7, 1, 1, 0)
+#define _P_MARK_FN8(bank, pin, name, sfx, cfg) _P_FN(name, 8, 1, 1, 1)
+
+static const u16 pinmux_data[] = {
+	_P_ALL(_P_DATA), /* PINMUX_DATA(P_M_N_DATA, P_M_N_PMC_0)... */
+	_P_ALL(_P_MARK_FN1), _P_ALL(_P_MARK_FN2),
+	_P_ALL(_P_MARK_FN3), _P_ALL(_P_MARK_FN4),
+	_P_ALL(_P_MARK_FN5), _P_ALL(_P_MARK_FN6),
+	_P_ALL(_P_MARK_FN7), _P_ALL(_P_MARK_FN8),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+	_P_ALL(_P_GPIO),
+};
+
+#define RZ_PORT_PIN(bank, pin) (((bank) * 16) + (pin))
+
+#define __RZ_STR(pfx, hw, bank, pin, sfx)		\
+	pfx##_##hw##_p##bank##_##pin####sfx
+
+#define RZ_PIN_AND_MUX(pfx, hw, bank, pin, fn)				\
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _pins)[] = {	\
+	RZ_PORT_PIN(bank, pin),						\
+};									\
+static const unsigned int __RZ_STR(pfx, hw, bank, pin, _mux)[] = {	\
+	GP_##bank##_##pin##_MARK_FN##fn,					\
+};
+
+#define RZ_PMX_GROUP(pfx, hw, bank, pin, fn) \
+	SH_PFC_PIN_GROUP(pfx##_##hw##_p##bank##_##pin),
+
+#define __RZ_GROUPS(x) #x
+
+#define RZ_GROUPS(pfx, hw, bank, pin, fn) \
+	__RZ_GROUPS(pfx##_##hw##_p##bank##_##pin),
+
+#define RIIC0(fn)			\
+	fn(riic0, scl, 1, 0, 1)		\
+	fn(riic0, sda, 1, 1, 1)
+
+#define RIIC1(fn)			\
+	fn(riic1, scl, 1, 2, 1)		\
+	fn(riic1, sda, 1, 3, 1)
+
+#define RIIC2(fn)			\
+	fn(riic2, scl, 1, 4, 1)		\
+	fn(riic2, sda, 1, 5, 1)
+
+#define RIIC3(fn)			\
+	fn(riic3, scl, 1, 6, 1)		\
+	fn(riic3, sda, 1, 7, 1)
+
+RIIC0(RZ_PIN_AND_MUX)
+RIIC1(RZ_PIN_AND_MUX)
+RIIC2(RZ_PIN_AND_MUX)
+RIIC3(RZ_PIN_AND_MUX)
+
+#define RSPI0(fn)			\
+	fn(rspi0, rspck,  2, 12, 2)	\
+	fn(rspi0, ssl0,   2, 13, 2)	\
+	fn(rspi0, mosi,   2, 14, 2)	\
+	fn(rspi0, miso,   2, 15, 2)	\
+	fn(rspi0, rspck,  7, 15, 2)	\
+	fn(rspi0, ssl0,   8,  0, 2)	\
+	fn(rspi0, mosi,   8,  1, 2)	\
+	fn(rspi0, miso,   8,  2, 2)	\
+	fn(rspi0, rspck, 10, 12, 4)	\
+	fn(rspi0, ssl0,  10, 13, 4)	\
+	fn(rspi0, mosi,  10, 14, 4)	\
+	fn(rspi0, miso,  10, 15, 4)	\
+
+#define RSPI1(fn)			\
+	fn(rspi1, rspck,  4,  4, 2)	\
+	fn(rspi1, ssl0,   4,  5, 2)	\
+	fn(rspi1, mosi,   4,  6, 2)	\
+	fn(rspi1, miso,   4,  7, 2)	\
+	fn(rspi1, rspck,  6,  4, 7)	\
+	fn(rspi1, ssl0,   6,  5, 7)	\
+	fn(rspi1, mosi,   6,  6, 7)	\
+	fn(rspi1, miso,   6,  7, 7)	\
+	fn(rspi1, rspck, 11, 12, 2)	\
+	fn(rspi1, ssl0,  11, 13, 2)	\
+	fn(rspi1, mosi,  11, 14, 2)	\
+	fn(rspi1, miso,  11, 15, 2)	\
+
+#define RSPI2(fn)			\
+	fn(rspi2, rspck,  8,  3, 3)	\
+	fn(rspi2, ssl0,   8,  4, 3)	\
+	fn(rspi2, mosi,   8,  5, 3)	\
+	fn(rspi2, miso,   8,  6, 3)	\
+	fn(rspi2, rspck,  8, 14, 5)	\
+	fn(rspi2, ssl0,   8, 15, 5)	\
+	fn(rspi2, mosi,   9,  0, 5)	\
+	fn(rspi2, miso,   9,  1, 5)	\
+
+#define RSPI3(fn)			\
+	fn(rspi3, rspck,  3,  0, 8)	\
+	fn(rspi3, ssl0,   3,  1, 8)	\
+	fn(rspi3, mosi,   3,  2, 8)	\
+	fn(rspi3, miso,   3,  3, 8)	\
+	fn(rspi3, rspck,  5,  0, 8)	\
+	fn(rspi3, ssl0,   5,  1, 8)	\
+	fn(rspi3, mosi,   5,  2, 8)	\
+	fn(rspi3, miso,   5,  3, 8)	\
+
+#define RSPI4(fn)			\
+	fn(rspi4, rspck,  2,  8, 8)	\
+	fn(rspi4, ssl0,   2,  9, 8)	\
+	fn(rspi4, mosi,   2, 10, 8)	\
+	fn(rspi4, miso,   2, 11, 8)	\
+	fn(rspi4, rspck,  4,  0, 7)	\
+	fn(rspi4, ssl0,   4,  1, 7)	\
+	fn(rspi4, mosi,   4,  2, 7)	\
+	fn(rspi4, miso,   4,  3, 7)	\
+
+RSPI0(RZ_PIN_AND_MUX)
+RSPI1(RZ_PIN_AND_MUX)
+RSPI2(RZ_PIN_AND_MUX)
+RSPI3(RZ_PIN_AND_MUX)
+RSPI4(RZ_PIN_AND_MUX)
+
+#define SCIF0(fn)			\
+	fn(scif0, clk, 2, 13, 6)	\
+	fn(scif0, txd, 2, 14, 6)	\
+	fn(scif0, rxd, 2, 15, 6)	\
+	fn(scif0, clk, 4, 8, 7)		\
+	fn(scif0, txd, 4, 9, 7)		\
+	fn(scif0, rxd, 4, 10, 7)	\
+	fn(scif0, clk, 6, 8, 5)		\
+	fn(scif0, txd, 6, 9, 5)		\
+	fn(scif0, rxd, 6, 10, 5)
+
+#define SCIF1(fn)			\
+	fn(scif1, cts, 2, 3, 6)		\
+	fn(scif1, clk, 2, 4, 6)		\
+	fn(scif1, txd, 2, 5, 6)		\
+	fn(scif1, rxd, 2, 6, 6)		\
+	fn(scif1, rts, 2, 7, 6)		\
+	fn(scif1, clk, 4, 11, 7)	\
+	fn(scif1, txd, 4, 12, 7)	\
+	fn(scif1, rxd, 4, 13, 7)	\
+	fn(scif1, clk, 6, 11, 5)	\
+	fn(scif1, txd, 6, 12, 5)	\
+	fn(scif1, rxd, 6, 13, 5)	\
+	fn(scif1, clk, 9, 2, 4)		\
+	fn(scif1, txd, 9, 3, 4)		\
+	fn(scif1, rxd, 9, 4, 4)		\
+	fn(scif1, cts, 9, 5, 4)		\
+	fn(scif1, rts, 9, 6, 4)
+
+#define SCIF2(fn)			\
+	fn(scif2, clk, 3, 0, 4)		\
+	fn(scif2, txd, 3, 1, 4)		\
+	fn(scif2, rxd, 3, 2, 4)		\
+	fn(scif2, txd, 3, 0, 6)		\
+	fn(scif2, clk, 4, 1, 5)		\
+	fn(scif2, txd, 4, 2, 5)		\
+	fn(scif2, rxd, 4, 3, 5)		\
+	fn(scif2, txd, 4, 14, 7)	\
+	fn(scif2, rxd, 4, 15, 7)	\
+	fn(scif2, txd, 6, 2, 7)		\
+	fn(scif2, rxd, 6, 3, 7)		\
+	fn(scif2, clk, 8, 3, 7)		\
+	fn(scif2, rxd, 8, 4, 7)		\
+	fn(scif2, txd, 8, 6, 7)
+
+#define SCIF3(fn)			\
+	fn(scif3, clk, 3, 4, 7)		\
+	fn(scif3, txd, 3, 5, 7)		\
+	fn(scif3, rxd, 3, 6, 7)		\
+	fn(scif3, clk, 5, 2, 5)		\
+	fn(scif3, txd, 5, 3, 5)		\
+	fn(scif3, rxd, 5, 4, 5)		\
+	fn(scif3, rxd, 6, 0, 7)		\
+	fn(scif3, txd, 6, 1, 7)		\
+	fn(scif3, txd, 8, 8, 7)		\
+	fn(scif3, rxd, 8, 9, 7)
+
+#define SCIF4(fn)			\
+	fn(scif4, txd, 5, 0, 5)		\
+	fn(scif4, rxd, 5, 1, 5)		\
+	fn(scif4, clk, 7, 0, 4)		\
+	fn(scif4, txd, 7, 1, 4)		\
+	fn(scif4, rxd, 7, 2, 4)		\
+	fn(scif4, txd, 8, 14, 7)	\
+	fn(scif4, rxd, 8, 15, 7)
+
+#define SCIF5(fn)			\
+	fn(scif5, cts, 6, 3, 5)		\
+	fn(scif5, rts, 6, 4, 5)		\
+	fn(scif5, clk, 6, 5, 5)		\
+	fn(scif5, txd, 6, 6, 5)		\
+	fn(scif5, rxd, 6, 7, 5)		\
+	fn(scif5, cts, 7, 15, 4)	\
+	fn(scif5, clk, 8, 0, 4)		\
+	fn(scif5, txd, 8, 1, 4)		\
+	fn(scif5, rxd, 8, 2, 4)		\
+	fn(scif5, rts, 8, 3, 4)		\
+	fn(scif5, rxd, 8, 11, 5)	\
+	fn(scif5, clk, 8, 12, 5)	\
+	fn(scif5, txd, 8, 13, 5)	\
+	fn(scif5, cts, 11, 7, 3)	\
+	fn(scif5, rts, 11, 8, 3)	\
+	fn(scif5, clk, 11, 9, 3)	\
+	fn(scif5, txd, 11, 10, 3)	\
+	fn(scif5, rxd, 11, 11, 3)
+
+#define SCIF6(fn)			\
+	fn(scif6, txd, 5, 6, 5)		\
+	fn(scif6, rxd, 5, 7, 5)		\
+	fn(scif6, clk, 6, 13, 4)	\
+	fn(scif6, txd, 6, 14, 4)	\
+	fn(scif6, rxd, 6, 15, 4)	\
+	fn(scif6, clk, 11, 0, 4)	\
+	fn(scif6, txd, 11, 1, 4)	\
+	fn(scif6, rxd, 11, 2, 4)
+
+#define SCIF7(fn)			\
+	fn(scif7, clk, 7, 3, 4)		\
+	fn(scif7, txd, 7, 4, 4)		\
+	fn(scif7, rxd, 7, 5, 4)		\
+	fn(scif7, cts, 7, 6, 4)		\
+	fn(scif7, rts, 7, 7, 4)
+
+SCIF0(RZ_PIN_AND_MUX)
+SCIF1(RZ_PIN_AND_MUX)
+SCIF2(RZ_PIN_AND_MUX)
+SCIF3(RZ_PIN_AND_MUX)
+SCIF4(RZ_PIN_AND_MUX)
+SCIF5(RZ_PIN_AND_MUX)
+SCIF6(RZ_PIN_AND_MUX)
+SCIF7(RZ_PIN_AND_MUX)
+
+#define ETHERNET(fn)			\
+	fn(ethernet, col,    1,  3, 3)		\
+	fn(ethernet, col,    1, 14, 4)		\
+	fn(ethernet, int,    1, 15, 1)		\
+	fn(ethernet, txclk,  2,  0, 2)		\
+	fn(ethernet, txer,   2,  1, 2)		\
+	fn(ethernet, txen,   2,  2, 2)		\
+	fn(ethernet, txcrs,  2,  3, 2)		\
+	fn(ethernet, txd0,   2,  4, 2)		\
+	fn(ethernet, txd1,   2,  5, 2)		\
+	fn(ethernet, txd2,   2,  6, 2)		\
+	fn(ethernet, txd3,   2,  7, 2)		\
+	fn(ethernet, rxd0,   2,  8, 2)		\
+	fn(ethernet, rxd1,   2,  9, 2)		\
+	fn(ethernet, rxd2,   2, 10, 2)		\
+	fn(ethernet, rxd3,   2, 11, 2)		\
+	fn(ethernet, txclk,  3,  0, 2)		\
+	fn(ethernet, txer,   3,  1, 2)		\
+	fn(ethernet, txen,   3,  2, 2)		\
+	fn(ethernet, mdio,   3,  3, 2)		\
+	fn(ethernet, rxclk,  3,  4, 2)		\
+	fn(ethernet, rxer,   3,  5, 2)		\
+	fn(ethernet, rxdv,   3,  6, 2)		\
+	fn(ethernet, mdc,    5,  9, 2)		\
+	fn(ethernet, mdc,    7,  0, 3)		\
+	fn(ethernet, txclk,  7,  1, 3)		\
+	fn(ethernet, txer,   7,  2, 3)		\
+	fn(ethernet, txen,   7,  3, 3)		\
+	fn(ethernet, txd0,   7,  4, 3)		\
+	fn(ethernet, txd1,   7,  5, 3)		\
+	fn(ethernet, txd2,   7,  6, 3)		\
+	fn(ethernet, txd3,   7,  7, 3)		\
+	fn(ethernet, rxd0,   7,  9, 3)		\
+	fn(ethernet, rxd1,   7, 10, 3)		\
+	fn(ethernet, rxd2,   7, 11, 2)		\
+	fn(ethernet, rxd3,   7, 12, 3)		\
+	fn(ethernet, mdio,   7, 13, 3)		\
+	fn(ethernet, crs,    7, 14, 3)		\
+	fn(ethernet, rxclk,  7, 15, 3)		\
+	fn(ethernet, rxer,   8,  0, 3)		\
+	fn(ethernet, rxd,    8,  1, 3)		\
+	fn(ethernet, col,    8,  7, 5)		\
+	fn(ethernet, txclk, 10,  0, 4)		\
+	fn(ethernet, txer,  10,  1, 4)		\
+	fn(ethernet, txen,  10,  2, 4)		\
+	fn(ethernet, crs,   10,  3, 4)		\
+	fn(ethernet, txd0,  10,  4, 4)		\
+	fn(ethernet, txd1,  10,  5, 4)		\
+	fn(ethernet, txd2,  10,  6, 4)		\
+	fn(ethernet, txd3,  10,  7, 4)		\
+	fn(ethernet, txd0,  10,  8, 4)		\
+	fn(ethernet, txd1,  10,  9, 4)		\
+	fn(ethernet, txd2,  10, 10, 4)		\
+	fn(ethernet, txd3,  10, 11, 4)		\
+
+ETHERNET(RZ_PIN_AND_MUX)
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+	RIIC0(RZ_PMX_GROUP)
+	RIIC1(RZ_PMX_GROUP)
+	RIIC2(RZ_PMX_GROUP)
+	RIIC3(RZ_PMX_GROUP)
+	RSPI0(RZ_PMX_GROUP)
+	RSPI1(RZ_PMX_GROUP)
+	RSPI2(RZ_PMX_GROUP)
+	RSPI3(RZ_PMX_GROUP)
+	RSPI4(RZ_PMX_GROUP)
+	SCIF0(RZ_PMX_GROUP)
+	SCIF1(RZ_PMX_GROUP)
+	SCIF2(RZ_PMX_GROUP)
+	SCIF3(RZ_PMX_GROUP)
+	SCIF4(RZ_PMX_GROUP)
+	SCIF5(RZ_PMX_GROUP)
+	SCIF6(RZ_PMX_GROUP)
+	SCIF7(RZ_PMX_GROUP)
+	ETHERNET(RZ_PMX_GROUP)
+};
+
+static const char * const riic0_groups[] = {
+	RIIC0(RZ_GROUPS)
+};
+
+static const char * const riic1_groups[] = {
+	RIIC1(RZ_GROUPS)
+};
+
+static const char * const riic2_groups[] = {
+	RIIC2(RZ_GROUPS)
+};
+
+static const char * const riic3_groups[] = {
+	RIIC3(RZ_GROUPS)
+};
+
+static const char * const rspi0_groups[] = {
+	RSPI0(RZ_GROUPS)
+};
+
+static const char * const rspi1_groups[] = {
+	RSPI1(RZ_GROUPS)
+};
+
+static const char * const rspi2_groups[] = {
+	RSPI2(RZ_GROUPS)
+};
+
+static const char * const rspi3_groups[] = {
+	RSPI3(RZ_GROUPS)
+};
+
+static const char * const rspi4_groups[] = {
+	RSPI4(RZ_GROUPS)
+};
+
+static const char * const scif0_groups[] = {
+	SCIF0(RZ_GROUPS)
+};
+
+static const char * const scif1_groups[] = {
+	SCIF1(RZ_GROUPS)
+};
+
+static const char * const scif2_groups[] = {
+	SCIF2(RZ_GROUPS)
+};
+
+static const char * const scif3_groups[] = {
+	SCIF3(RZ_GROUPS)
+};
+
+static const char * const scif4_groups[] = {
+	SCIF4(RZ_GROUPS)
+};
+
+static const char * const scif5_groups[] = {
+	SCIF5(RZ_GROUPS)
+};
+
+static const char * const scif6_groups[] = {
+	SCIF6(RZ_GROUPS)
+};
+
+static const char * const scif7_groups[] = {
+	SCIF7(RZ_GROUPS)
+};
+
+static const char * const ethernet_groups[] = {
+	ETHERNET(RZ_GROUPS)
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(riic0),
+	SH_PFC_FUNCTION(riic1),
+	SH_PFC_FUNCTION(riic2),
+	SH_PFC_FUNCTION(riic3),
+	SH_PFC_FUNCTION(rspi0),
+	SH_PFC_FUNCTION(rspi1),
+	SH_PFC_FUNCTION(rspi2),
+	SH_PFC_FUNCTION(rspi3),
+	SH_PFC_FUNCTION(rspi4),
+	SH_PFC_FUNCTION(scif0),
+	SH_PFC_FUNCTION(scif1),
+	SH_PFC_FUNCTION(scif2),
+	SH_PFC_FUNCTION(scif3),
+	SH_PFC_FUNCTION(scif4),
+	SH_PFC_FUNCTION(scif5),
+	SH_PFC_FUNCTION(scif6),
+	SH_PFC_FUNCTION(scif7),
+	SH_PFC_FUNCTION(ethernet),
+};
+
+#define PFC_REG(idx, name, reg)						\
+	{ PINMUX_CFG_REG(__stringify(name), reg, 16, 1) {		\
+		GP_##idx##_15_##name##_0, GP_##idx##_15_##name##_1,	\
+		GP_##idx##_14_##name##_0, GP_##idx##_14_##name##_1,	\
+		GP_##idx##_13_##name##_0, GP_##idx##_13_##name##_1,	\
+		GP_##idx##_12_##name##_0, GP_##idx##_12_##name##_1,	\
+		GP_##idx##_11_##name##_0, GP_##idx##_11_##name##_1,	\
+		GP_##idx##_10_##name##_0, GP_##idx##_10_##name##_1,	\
+		GP_##idx##_9_##name##_0, GP_##idx##_9_##name##_1,		\
+		GP_##idx##_8_##name##_0, GP_##idx##_8_##name##_1,		\
+		GP_##idx##_7_##name##_0, GP_##idx##_7_##name##_1,		\
+		GP_##idx##_6_##name##_0, GP_##idx##_6_##name##_1,		\
+		GP_##idx##_5_##name##_0, GP_##idx##_5_##name##_1,		\
+		GP_##idx##_4_##name##_0, GP_##idx##_4_##name##_1,		\
+		GP_##idx##_3_##name##_0, GP_##idx##_3_##name##_1,		\
+		GP_##idx##_2_##name##_0, GP_##idx##_2_##name##_1,		\
+		GP_##idx##_1_##name##_0, GP_##idx##_1_##name##_1,		\
+		GP_##idx##_0_##name##_0, GP_##idx##_0_##name##_1 }	\
+	}
+
+#define PFC_REGS(idx)						\
+	PFC_REG(idx, PMC, (0xfcfe3400 + (idx * 4))),		\
+	PFC_REG(idx, PFC, (0xfcfe3500 + (idx * 4))),		\
+	PFC_REG(idx, PFCE, (0xfcfe3600 + (idx * 4))),		\
+	PFC_REG(idx, PFCAE, (0xfcfe3a00 + (idx * 4))),		\
+	PFC_REG(idx, PIBC, (0xfcfe7000 + (idx * 4))),		\
+	PFC_REG(idx, PBDC, (0xfcfe7100 + (idx * 4))),		\
+	PFC_REG(idx, PIPC, (0xfcfe7200 + (idx * 4)))
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	PFC_REGS(0), PFC_REGS(1), PFC_REGS(2), PFC_REGS(3),
+	PFC_REGS(4), PFC_REGS(5), PFC_REGS(6), PFC_REGS(7),
+	PFC_REGS(8), PFC_REGS(9), PFC_REGS(10), PFC_REGS(11),
+	PFC_REG(12, PMC, 0xfcfe7b40),
+	PFC_REG(12, PIBC, 0xfcfe7f00),
+	{ },
+};
+
+const struct sh_pfc_soc_info r7s72100_pinmux_info = {
+	.name = "r7s72100_pfc",
+
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.pins = pinmux_pins,
+	.nr_pins = ARRAY_SIZE(pinmux_pins),
+	.groups = pinmux_groups,
+	.nr_groups = ARRAY_SIZE(pinmux_groups),
+	.functions = pinmux_functions,
+	.nr_functions = ARRAY_SIZE(pinmux_functions),
+
+	.cfg_regs = pinmux_config_regs,
+
+	.pinmux_data = pinmux_data,
+	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index e42cc7a..95a07c9 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -257,6 +257,7 @@ struct sh_pfc_soc_info {
 };
 
 extern const struct sh_pfc_soc_info emev2_pinmux_info;
+extern const struct sh_pfc_soc_info r7s72100_pinmux_info;
 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
@@ -484,14 +485,16 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
 #define GP_ALL(str)			CPU_ALL_PORT(_GP_ALL, str)
 
 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
-#define _GP_GPIO(bank, _pin, _name, sfx, cfg)				\
+#define _GP_GPIO(banksize, bank, _pin, _name, sfx, cfg)				\
 	{								\
-		.pin = (bank * 32) + _pin,				\
+		.pin = (bank * banksize) + _pin,			\
 		.name = __stringify(_name),				\
 		.enum_id = _name##_DATA,				\
 		.configs = cfg,						\
 	}
-#define PINMUX_GPIO_GP_ALL()		CPU_ALL_PORT(_GP_GPIO, unused)
+#define _GP_GPIO32(bank, _pin, _name, sfx, cfg)\
+  _GP_GPIO(32, bank, _pin, _name, sfx, cfg)
+#define PINMUX_GPIO_GP_ALL()		CPU_ALL_PORT(_GP_GPIO32, unused)
 
 /* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
 #define _GP_DATA(bank, pin, name, sfx, cfg)	PINMUX_DATA(name##_DATA, name##_FN)
-- 
2.7.4

Re: [PATCH v3 1/8] pinctrl: sh-pfc: Add r7s72100 PFC driver

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 1166 bytes --]


Just some very minor nits... Probably not worth the resend.

On Mon, Jan 16, 2017 at 01:12:45PM +0100, Jacopo Mondi wrote:
> From: Magnus Damm <damm@opensource.se>
> 
> Squash commits in Geert's renesas-driver/genmai-gpio-and-pfc branch that
> add support for r7s72100 PFC.
> This squash combines commits for Magnus' original driver, several
> "groups" definitions and minor fixes on top to forward-port it to a more
> recent kernel (v4.10)
> 
> Signed-off-by: Magnus Damm <damm@opensource.se>
> Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>

I'd prefer the "wsa+renesas@..." address here, too.

> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>

...

> diff --git a/drivers/pinctrl/sh-pfc/pfc-r7s72100.c b/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
> new file mode 100644
> index 0000000..72e1dff
> --- /dev/null
> +++ b/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
> @@ -0,0 +1,529 @@
> +/*
> + * R7S72100 processor support
> + *
> + * Copyright (C) 2013  Renesas Electronics Corporation

2013-2017?


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

[PATCH v3 2/8] pinctrl: sh-pfc: r7s72100: Configure I/O mode

[Jacopo Mondi]

When selecting an alternate function for one pin, set the PIPCn.PIPCnm
bit to 1 to enable direct IO mode control (the alternate function
drives the pin direction) and disable input buffer and bidirection
control functionalities (PIBCn.PIBCnm = 0 and PBDCn.PDBCnm = 0).
Enable input buffer and bidirection control for port mode configuration.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/pinctrl/sh-pfc/pfc-r7s72100.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r7s72100.c b/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
index 72e1dff..1923a11 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r7s72100.c
@@ -54,13 +54,16 @@ enum {
 #define _P_GPIO(bank, _pin, _name, sfx, cfg) \
 	_GP_GPIO(16, bank, _pin, _name, sfx, cfg)
 
-#define _P_DATA(bank, pin, name, sfx, cfg)					\
-	PINMUX_DATA(name##_DATA, name##_PMC_0,		\
-		    name##_PIBC_1, name##_PBDC_1)
+#define _P_DATA(bank, pin, n, sfx, cfg)		\
+	PINMUX_DATA(n##_DATA, n##_PMC_0,		\
+		    n##_PIPC_0, n##_PIBC_1, n##_PBDC_1)
 
-#define _P_FN(n, fn, pfcae, pfce, pfc)					\
+#define _P_FN(n, fn, pfcae, pfce, pfc)			\
 	PINMUX_DATA(n##_MARK_FN##fn, n##_PMC_1,		\
-		    n##_PFCAE_##pfcae, n##_PFCE_##pfce, n##_PFC_##pfc)
+		    n##_PFCAE_##pfcae,			\
+		    n##_PFCE_##pfce,			\
+		    n##_PFC_##pfc,			\
+		    n##_PIPC_1, n##_PIBC_0, n##_PBDC_0)
 
 #define _P_MARK_FN1(bank, pin, name, sfx, cfg) _P_FN(name, 1, 0, 0, 0)
 #define _P_MARK_FN2(bank, pin, name, sfx, cfg) _P_FN(name, 2, 0, 0, 1)
-- 
2.7.4

[PATCH v3 3/8] gpio: gpio-rz: GPIO driver for Renesas RZ series

[Jacopo Mondi]

From: Magnus Damm <damm@opensource.se>

This commit combines Magnus' original driver and minor fixes to
forward-port it to a more recent kernel version (v4.10).

Compared to the original driver the set of registers used to set/get
direction is changed to extend compatibility with other RZ-Series
processors.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/gpio/Kconfig   |   6 ++
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-rz.c | 211 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 218 insertions(+)
 create mode 100644 drivers/gpio/gpio-rz.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index d5d3654..e9ad7b4 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -369,6 +369,12 @@ config GPIO_RCAR
 	help
 	  Say yes here to support GPIO on Renesas R-Car SoCs.
 
+config GPIO_RZ
+	tristate "Renesas RZ GPIO"
+	depends on ARCH_RENESAS
+	help
+	  Say yes here to support GPIO on Renesas RZ SoCs.
+
 config GPIO_SPEAR_SPICS
 	bool "ST SPEAr13xx SPI Chip Select as GPIO support"
 	depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index a7676b8..f0b2713 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -96,6 +96,7 @@ obj-$(CONFIG_GPIO_PXA)		+= gpio-pxa.o
 obj-$(CONFIG_GPIO_RC5T583)	+= gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RDC321X)	+= gpio-rdc321x.o
 obj-$(CONFIG_GPIO_RCAR)		+= gpio-rcar.o
+obj-$(CONFIG_GPIO_RZ)		+= gpio-rz.o
 obj-$(CONFIG_ARCH_SA1100)	+= gpio-sa1100.o
 obj-$(CONFIG_GPIO_SCH)		+= gpio-sch.o
 obj-$(CONFIG_GPIO_SCH311X)	+= gpio-sch311x.o
diff --git a/drivers/gpio/gpio-rz.c b/drivers/gpio/gpio-rz.c
new file mode 100644
index 0000000..ad67975
--- /dev/null
+++ b/drivers/gpio/gpio-rz.c
@@ -0,0 +1,211 @@
+/*
+ * RZ GPIO Support - Ports
+ *
+ *  Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define RZ_GPIOS_PER_PORT 16
+#define PORT0_NUM_REGS	1
+
+enum { REG_P, REG_PPR, REG_PM, REG_NR };
+
+struct rz_gpio_priv {
+	void __iomem *io[REG_NR];
+	struct gpio_chip gpio_chip;
+	int nreg;
+};
+
+static inline struct rz_gpio_priv *gpio_to_priv(struct gpio_chip *chip)
+{
+	return gpiochip_get_data(chip);
+}
+
+static inline u16 rz_gpio_read(struct  gpio_chip *chip, int reg)
+{
+	return ioread16(gpio_to_priv(chip)->io[reg]);
+}
+
+static inline void rz_gpio_write(struct gpio_chip *chip, int reg, u16 val)
+{
+	iowrite16(val, gpio_to_priv(chip)->io[reg]);
+}
+
+static int rz_gpio_get(struct gpio_chip *chip, unsigned gpio)
+{
+	u16 tmp = rz_gpio_read(chip, REG_PPR);
+
+	return tmp & BIT(gpio);
+}
+
+static void rz_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
+{
+	u16 tmp;
+
+	if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
+		return;
+
+	tmp = rz_gpio_read(chip, REG_P);
+
+	if (value)
+		rz_gpio_write(chip, REG_P, tmp | BIT(gpio));
+	else
+		rz_gpio_write(chip, REG_P, tmp & ~BIT(gpio));
+}
+
+static int rz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+	/* Set bit in PM register (input buffer enabled by PFC for the pin) */
+	rz_gpio_write(chip, REG_PM, rz_gpio_read(chip, REG_PM) | BIT(gpio));
+
+	return 0;
+}
+
+static int rz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
+				   int value)
+{
+
+	if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
+		return -EINVAL;
+
+	/* Write GPIO value before selecting output mode of pin */
+	rz_gpio_set(chip, gpio, value);
+
+	/* Clear bit in PM register to enable output */
+	rz_gpio_write(chip, REG_PM, rz_gpio_read(chip, REG_PM) & BIT(gpio));
+
+	return 0;
+}
+
+static int rz_gpio_get_direction(struct gpio_chip *chip, unsigned gpio)
+{
+	if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
+		return 1;
+
+	return rz_gpio_read(chip, REG_PM) & BIT(gpio);
+}
+
+static int rz_gpio_request(struct gpio_chip *chip, unsigned gpio)
+{
+	return gpiochip_generic_request(chip, gpio);
+}
+
+static void rz_gpio_free(struct gpio_chip *chip, unsigned gpio)
+{
+	gpiochip_generic_free(chip, gpio);
+
+	/* Set the GPIO as an input to ensure that the next GPIO request won't
+	 * drive the GPIO pin as an output.
+	 */
+	rz_gpio_direction_input(chip, gpio);
+}
+
+static int rz_gpio_probe(struct platform_device *pdev)
+{
+	struct rz_gpio_priv *p;
+	struct resource *io[REG_NR - 1];
+	struct gpio_chip *gpio_chip;
+	struct device_node *np = pdev->dev.of_node;
+	struct of_phandle_args args;
+	int ret, k;
+
+	p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+	if (!p) {
+		dev_err(&pdev->dev, "failed to allocate driver data\n");
+		return -ENOMEM;
+	}
+
+	/* As registers for each port instance are scattered in the same
+	 * address space, we have to map them singularly */
+	for (k = 0; k < REG_NR; k++) {
+		io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
+
+		/* Port0 and JP0 are inuput only: has REG_PPR only */
+		if (!io[k])
+			break;
+
+		p->io[k] = devm_ioremap_resource(&pdev->dev, io[k]);
+		if (IS_ERR(p->io[k]))
+			return PTR_ERR(p->io[k]);
+
+		p->nreg++;
+	}
+
+	/* move REG_PPR in correct position for Port0 and JP0 */
+	if (p->nreg == PORT0_NUM_REGS) {
+		p->io[REG_PPR] = p->io[REG_P];
+		p->io[REG_P] = p->io[REG_PM] = NULL;
+	}
+
+	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
+
+	gpio_chip = &p->gpio_chip;
+	gpio_chip->get = rz_gpio_get;
+	gpio_chip->set = rz_gpio_set;
+	gpio_chip->direction_input = rz_gpio_direction_input;
+	gpio_chip->direction_output = rz_gpio_direction_output;
+	gpio_chip->get_direction = rz_gpio_get_direction;
+	gpio_chip->request = rz_gpio_request;
+	gpio_chip->free = rz_gpio_free;
+	gpio_chip->label = dev_name(&pdev->dev);
+	gpio_chip->parent = &pdev->dev;
+	gpio_chip->owner = THIS_MODULE;
+	gpio_chip->base = -1;
+	gpio_chip->ngpio = ret == 0 ? args.args[2] : RZ_GPIOS_PER_PORT;
+
+	ret = devm_gpiochip_add_data(&pdev->dev, gpio_chip, p);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to add GPIO controller\n");
+		return ret;
+	}
+
+	dev_info(&pdev->dev, "driving %d GPIOs\n", gpio_chip->ngpio);
+	return 0;
+}
+
+static const struct of_device_id rz_gpio_dt_ids[] = {
+	{ .compatible = "renesas,gpio-rz", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, rz_gpio_dt_ids);
+
+static struct platform_driver rz_gpio_device_driver = {
+	.probe		= rz_gpio_probe,
+	.driver		= {
+		.name	= "gpio_rz",
+		.of_match_table = rz_gpio_dt_ids,
+		.owner		= THIS_MODULE,
+	}
+};
+
+static int __init rz_gpio_init(void)
+{
+	return platform_driver_register(&rz_gpio_device_driver);
+}
+postcore_initcall(rz_gpio_init);
+
+static void __exit rz_gpio_exit(void)
+{
+	platform_driver_unregister(&rz_gpio_device_driver);
+}
+module_exit(rz_gpio_exit);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas RZ Port GPIO Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.7.4

Re: [PATCH v3 3/8] gpio: gpio-rz: GPIO driver for Renesas RZ series

[Linus Walleij]

On Mon, Jan 16, 2017 at 1:12 PM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:

> From: Magnus Damm <damm@opensource.se>
>
> This commit combines Magnus' original driver and minor fixes to
> forward-port it to a more recent kernel version (v4.10).
>
> Compared to the original driver the set of registers used to set/get
> direction is changed to extend compatibility with other RZ-Series
> processors.
>
> Signed-off-by: Magnus Damm <damm@opensource.se>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>

Sorry for not noting all you can do on first iteration... :/

> +config GPIO_RZ
> +       tristate "Renesas RZ GPIO"
> +       depends on ARCH_RENESAS

select GPIO_GENERIC

Trust me. It's gonna be real nice.

> +static inline struct rz_gpio_priv *gpio_to_priv(struct gpio_chip *chip)
> +{
> +       return gpiochip_get_data(chip);
> +}
> +
> +static inline u16 rz_gpio_read(struct  gpio_chip *chip, int reg)
> +{
> +       return ioread16(gpio_to_priv(chip)->io[reg]);
> +}
> +
> +static inline void rz_gpio_write(struct gpio_chip *chip, int reg, u16 val)
> +{
> +       iowrite16(val, gpio_to_priv(chip)->io[reg]);
> +}
> +
> +static int rz_gpio_get(struct gpio_chip *chip, unsigned gpio)
> +{
> +       u16 tmp = rz_gpio_read(chip, REG_PPR);
> +
> +       return tmp & BIT(gpio);
> +}
> +
> +static void rz_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
> +{
> +       u16 tmp;
> +
> +       if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
> +               return;
> +
> +       tmp = rz_gpio_read(chip, REG_P);
> +
> +       if (value)
> +               rz_gpio_write(chip, REG_P, tmp | BIT(gpio));
> +       else
> +               rz_gpio_write(chip, REG_P, tmp & ~BIT(gpio));
> +}
> +
> +static int rz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
> +{
> +       /* Set bit in PM register (input buffer enabled by PFC for the pin) */
> +       rz_gpio_write(chip, REG_PM, rz_gpio_read(chip, REG_PM) | BIT(gpio));
> +
> +       return 0;
> +}
> +
> +static int rz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
> +                                  int value)
> +{
> +
> +       if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
> +               return -EINVAL;
> +
> +       /* Write GPIO value before selecting output mode of pin */
> +       rz_gpio_set(chip, gpio, value);
> +
> +       /* Clear bit in PM register to enable output */
> +       rz_gpio_write(chip, REG_PM, rz_gpio_read(chip, REG_PM) & BIT(gpio));
> +
> +       return 0;
> +}
> +
> +static int rz_gpio_get_direction(struct gpio_chip *chip, unsigned gpio)
> +{
> +       if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
> +               return 1;
> +
> +       return rz_gpio_read(chip, REG_PM) & BIT(gpio);
> +}


Delete ALL the above functions.

> +static int rz_gpio_request(struct gpio_chip *chip, unsigned gpio)
> +{
> +       return gpiochip_generic_request(chip, gpio);
> +}
> +
> +static void rz_gpio_free(struct gpio_chip *chip, unsigned gpio)
> +{
> +       gpiochip_generic_free(chip, gpio);
> +
> +       /* Set the GPIO as an input to ensure that the next GPIO request won't
> +        * drive the GPIO pin as an output.
> +        */
> +       rz_gpio_direction_input(chip, gpio);

Change this line to:
chip->direction_input(chip, gpio);

> +static int rz_gpio_probe(struct platform_device *pdev)
> +{
> +       struct rz_gpio_priv *p;
> +       struct resource *io[REG_NR - 1];
> +       struct gpio_chip *gpio_chip;
> +       struct device_node *np = pdev->dev.of_node;
> +       struct of_phandle_args args;
> +       int ret, k;
> +
> +       p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
> +       if (!p) {
> +               dev_err(&pdev->dev, "failed to allocate driver data\n");
> +               return -ENOMEM;
> +       }
> +
> +       /* As registers for each port instance are scattered in the same
> +        * address space, we have to map them singularly */
> +       for (k = 0; k < REG_NR; k++) {
> +               io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
> +
> +               /* Port0 and JP0 are inuput only: has REG_PPR only */
> +               if (!io[k])
> +                       break;
> +
> +               p->io[k] = devm_ioremap_resource(&pdev->dev, io[k]);
> +               if (IS_ERR(p->io[k]))
> +                       return PTR_ERR(p->io[k]);
> +
> +               p->nreg++;
> +       }
> +
> +       /* move REG_PPR in correct position for Port0 and JP0 */
> +       if (p->nreg == PORT0_NUM_REGS) {
> +               p->io[REG_PPR] = p->io[REG_P];
> +               p->io[REG_P] = p->io[REG_PM] = NULL;
> +       }
> +
> +       ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
> +
> +       gpio_chip = &p->gpio_chip;

Replace from here:

> +       gpio_chip->get = rz_gpio_get;
> +       gpio_chip->set = rz_gpio_set;
> +       gpio_chip->direction_input = rz_gpio_direction_input;
> +       gpio_chip->direction_output = rz_gpio_direction_output;
> +       gpio_chip->get_direction = rz_gpio_get_direction;

To here with:

ret = bgpio_init(gpio_chip, &pdev->dev, 2,
                       p->io[REG_PPR], p->io[REG_P], NULL,
                       NULL, p->io[REG_PM], 0);
if (ret)
    return ret;

This might need some flags or I screwed something up, but I'm
convinced you can use GENERIC_GPIO like this.

The generic accessors also sets the value before switching
direction.

If you're uncertain about the sematics, read drivers/gpio/gpio-mmio.c.

> +       gpio_chip->request = rz_gpio_request;
> +       gpio_chip->free = rz_gpio_free;
> +       gpio_chip->label = dev_name(&pdev->dev);
> +       gpio_chip->parent = &pdev->dev;
> +       gpio_chip->owner = THIS_MODULE;
> +       gpio_chip->base = -1;
> +       gpio_chip->ngpio = ret == 0 ? args.args[2] : RZ_GPIOS_PER_PORT;

bgpio_init() will have already set this up to 16 (RZ_GPIOS_PER_PORT)
as we pass width 2 bytes.

Yours,
Linus Walleij

Re: [PATCH v3 3/8] gpio: gpio-rz: GPIO driver for Renesas RZ series

[Geert Uytterhoeven]

Hi Linus,

On Wed, Jan 18, 2017 at 2:58 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
>> +       gpio_chip->request = rz_gpio_request;
>> +       gpio_chip->free = rz_gpio_free;
>> +       gpio_chip->label = dev_name(&pdev->dev);
>> +       gpio_chip->parent = &pdev->dev;
>> +       gpio_chip->owner = THIS_MODULE;
>> +       gpio_chip->base = -1;
>> +       gpio_chip->ngpio = ret == 0 ? args.args[2] : RZ_GPIOS_PER_PORT;
>
> bgpio_init() will have already set this up to 16 (RZ_GPIOS_PER_PORT)
> as we pass width 2 bytes.

Note that some banks have less than 16 GPIOs, cfr. the last value of the
gpio-ranges tuple being less than 16.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 3/8] gpio: gpio-rz: GPIO driver for Renesas RZ series

[Linus Walleij]

On Wed, Jan 18, 2017 at 3:06 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> Hi Linus,
>
> On Wed, Jan 18, 2017 at 2:58 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
>>> +       gpio_chip->request = rz_gpio_request;
>>> +       gpio_chip->free = rz_gpio_free;
>>> +       gpio_chip->label = dev_name(&pdev->dev);
>>> +       gpio_chip->parent = &pdev->dev;
>>> +       gpio_chip->owner = THIS_MODULE;
>>> +       gpio_chip->base = -1;
>>> +       gpio_chip->ngpio = ret == 0 ? args.args[2] : RZ_GPIOS_PER_PORT;
>>
>> bgpio_init() will have already set this up to 16 (RZ_GPIOS_PER_PORT)
>> as we pass width 2 bytes.
>
> Note that some banks have less than 16 GPIOs, cfr. the last value of the
> gpio-ranges tuple being less than 16.

Aha OK then it is fine to override this default value calculate from
the register size.

But for that case we should use the standard DT property
ngpios described in
Documentation/devicetree/bindings/gpio/gpio.txt
It is for exactly this purpose.

Yours,
Linus Walleij

Re: [PATCH v3 3/8] gpio: gpio-rz: GPIO driver for Renesas RZ series

[Geert Uytterhoeven]

Hi Linus,

On Thu, Jan 19, 2017 at 10:27 AM, Linus Walleij
<linus.walleij@linaro.org> wrote:
> On Wed, Jan 18, 2017 at 3:06 PM, Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
>> On Wed, Jan 18, 2017 at 2:58 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
>>>> +       gpio_chip->request = rz_gpio_request;
>>>> +       gpio_chip->free = rz_gpio_free;
>>>> +       gpio_chip->label = dev_name(&pdev->dev);
>>>> +       gpio_chip->parent = &pdev->dev;
>>>> +       gpio_chip->owner = THIS_MODULE;
>>>> +       gpio_chip->base = -1;
>>>> +       gpio_chip->ngpio = ret == 0 ? args.args[2] : RZ_GPIOS_PER_PORT;
>>>
>>> bgpio_init() will have already set this up to 16 (RZ_GPIOS_PER_PORT)
>>> as we pass width 2 bytes.
>>
>> Note that some banks have less than 16 GPIOs, cfr. the last value of the
>> gpio-ranges tuple being less than 16.
>
> Aha OK then it is fine to override this default value calculate from
> the register size.
>
> But for that case we should use the standard DT property
> ngpios described in
> Documentation/devicetree/bindings/gpio/gpio.txt
> It is for exactly this purpose.

IC.

Note that gpio-rcar uses the same method, switching to "ngpios" would
break backwards compatibility.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 3/8] gpio: gpio-rz: GPIO driver for Renesas RZ series

[Linus Walleij]

On Thu, Jan 19, 2017 at 10:36 AM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Thu, Jan 19, 2017 at 10:27 AM, Linus Walleij
> <linus.walleij@linaro.org> wrote:
>> On Wed, Jan 18, 2017 at 3:06 PM, Geert Uytterhoeven
>> <geert@linux-m68k.org> wrote:
>>> On Wed, Jan 18, 2017 at 2:58 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
>>>>> +       gpio_chip->request = rz_gpio_request;
>>>>> +       gpio_chip->free = rz_gpio_free;
>>>>> +       gpio_chip->label = dev_name(&pdev->dev);
>>>>> +       gpio_chip->parent = &pdev->dev;
>>>>> +       gpio_chip->owner = THIS_MODULE;
>>>>> +       gpio_chip->base = -1;
>>>>> +       gpio_chip->ngpio = ret == 0 ? args.args[2] : RZ_GPIOS_PER_PORT;
>>>>
>>>> bgpio_init() will have already set this up to 16 (RZ_GPIOS_PER_PORT)
>>>> as we pass width 2 bytes.
>>>
>>> Note that some banks have less than 16 GPIOs, cfr. the last value of the
>>> gpio-ranges tuple being less than 16.
>>
>> Aha OK then it is fine to override this default value calculate from
>> the register size.
>>
>> But for that case we should use the standard DT property
>> ngpios described in
>> Documentation/devicetree/bindings/gpio/gpio.txt
>> It is for exactly this purpose.
>
> IC.
>
> Note that gpio-rcar uses the same method, switching to "ngpios" would
> break backwards compatibility.

Can we support both?

Yours,
Linus Walleij

Re: [PATCH v3 3/8] gpio: gpio-rz: GPIO driver for Renesas RZ series

[Geert Uytterhoeven]

Hi Linus,

On Thu, Jan 19, 2017 at 10:38 AM, Linus Walleij
<linus.walleij@linaro.org> wrote:
> On Thu, Jan 19, 2017 at 10:36 AM, Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
>> On Thu, Jan 19, 2017 at 10:27 AM, Linus Walleij
>> <linus.walleij@linaro.org> wrote:
>>> On Wed, Jan 18, 2017 at 3:06 PM, Geert Uytterhoeven
>>> <geert@linux-m68k.org> wrote:
>>>> On Wed, Jan 18, 2017 at 2:58 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
>>>>>> +       gpio_chip->request = rz_gpio_request;
>>>>>> +       gpio_chip->free = rz_gpio_free;
>>>>>> +       gpio_chip->label = dev_name(&pdev->dev);
>>>>>> +       gpio_chip->parent = &pdev->dev;
>>>>>> +       gpio_chip->owner = THIS_MODULE;
>>>>>> +       gpio_chip->base = -1;
>>>>>> +       gpio_chip->ngpio = ret == 0 ? args.args[2] : RZ_GPIOS_PER_PORT;
>>>>>
>>>>> bgpio_init() will have already set this up to 16 (RZ_GPIOS_PER_PORT)
>>>>> as we pass width 2 bytes.
>>>>
>>>> Note that some banks have less than 16 GPIOs, cfr. the last value of the
>>>> gpio-ranges tuple being less than 16.
>>>
>>> Aha OK then it is fine to override this default value calculate from
>>> the register size.
>>>
>>> But for that case we should use the standard DT property
>>> ngpios described in
>>> Documentation/devicetree/bindings/gpio/gpio.txt
>>> It is for exactly this purpose.
>>
>> IC.
>>
>> Note that gpio-rcar uses the same method, switching to "ngpios" would
>> break backwards compatibility.
>
> Can we support both?

Yes we can, I guess.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 3/8] gpio: gpio-rz: GPIO driver for Renesas RZ series

[jacopo mondi]

Hi Linus,
    thanks for review

On 18/01/2017 14:58, Linus Walleij wrote:
> On Mon, Jan 16, 2017 at 1:12 PM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
>
>> From: Magnus Damm <damm@opensource.se>
>>
>> This commit combines Magnus' original driver and minor fixes to
>> forward-port it to a more recent kernel version (v4.10).
>>
>> Compared to the original driver the set of registers used to set/get
>> direction is changed to extend compatibility with other RZ-Series
>> processors.
>>
>> Signed-off-by: Magnus Damm <damm@opensource.se>
>> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
>
> Sorry for not noting all you can do on first iteration... :/

Wow, it seems like there's lot of code already in place we can exploit here!

IF I'm going to send out v4 I'll move it to use gpio_generic.
If as it seems, we're going to try submit a new combined PFC+GPIO driver 
for RZ/A processor, I'll see if I can do the same there.

Thanks
    j


>
>> +config GPIO_RZ
>> +       tristate "Renesas RZ GPIO"
>> +       depends on ARCH_RENESAS
>
> select GPIO_GENERIC
>
> Trust me. It's gonna be real nice.
>
>> +static inline struct rz_gpio_priv *gpio_to_priv(struct gpio_chip *chip)
>> +{
>> +       return gpiochip_get_data(chip);
>> +}
>> +
>> +static inline u16 rz_gpio_read(struct  gpio_chip *chip, int reg)
>> +{
>> +       return ioread16(gpio_to_priv(chip)->io[reg]);
>> +}
>> +
>> +static inline void rz_gpio_write(struct gpio_chip *chip, int reg, u16 val)
>> +{
>> +       iowrite16(val, gpio_to_priv(chip)->io[reg]);
>> +}
>> +
>> +static int rz_gpio_get(struct gpio_chip *chip, unsigned gpio)
>> +{
>> +       u16 tmp = rz_gpio_read(chip, REG_PPR);
>> +
>> +       return tmp & BIT(gpio);
>> +}
>> +
>> +static void rz_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
>> +{
>> +       u16 tmp;
>> +
>> +       if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
>> +               return;
>> +
>> +       tmp = rz_gpio_read(chip, REG_P);
>> +
>> +       if (value)
>> +               rz_gpio_write(chip, REG_P, tmp | BIT(gpio));
>> +       else
>> +               rz_gpio_write(chip, REG_P, tmp & ~BIT(gpio));
>> +}
>> +
>> +static int rz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
>> +{
>> +       /* Set bit in PM register (input buffer enabled by PFC for the pin) */
>> +       rz_gpio_write(chip, REG_PM, rz_gpio_read(chip, REG_PM) | BIT(gpio));
>> +
>> +       return 0;
>> +}
>> +
>> +static int rz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
>> +                                  int value)
>> +{
>> +
>> +       if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
>> +               return -EINVAL;
>> +
>> +       /* Write GPIO value before selecting output mode of pin */
>> +       rz_gpio_set(chip, gpio, value);
>> +
>> +       /* Clear bit in PM register to enable output */
>> +       rz_gpio_write(chip, REG_PM, rz_gpio_read(chip, REG_PM) & BIT(gpio));
>> +
>> +       return 0;
>> +}
>> +
>> +static int rz_gpio_get_direction(struct gpio_chip *chip, unsigned gpio)
>> +{
>> +       if (gpio_to_priv(chip)->nreg == PORT0_NUM_REGS)
>> +               return 1;
>> +
>> +       return rz_gpio_read(chip, REG_PM) & BIT(gpio);
>> +}
>
>
> Delete ALL the above functions.
>
>> +static int rz_gpio_request(struct gpio_chip *chip, unsigned gpio)
>> +{
>> +       return gpiochip_generic_request(chip, gpio);
>> +}
>> +
>> +static void rz_gpio_free(struct gpio_chip *chip, unsigned gpio)
>> +{
>> +       gpiochip_generic_free(chip, gpio);
>> +
>> +       /* Set the GPIO as an input to ensure that the next GPIO request won't
>> +        * drive the GPIO pin as an output.
>> +        */
>> +       rz_gpio_direction_input(chip, gpio);
>
> Change this line to:
> chip->direction_input(chip, gpio);
>
>> +static int rz_gpio_probe(struct platform_device *pdev)
>> +{
>> +       struct rz_gpio_priv *p;
>> +       struct resource *io[REG_NR - 1];
>> +       struct gpio_chip *gpio_chip;
>> +       struct device_node *np = pdev->dev.of_node;
>> +       struct of_phandle_args args;
>> +       int ret, k;
>> +
>> +       p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
>> +       if (!p) {
>> +               dev_err(&pdev->dev, "failed to allocate driver data\n");
>> +               return -ENOMEM;
>> +       }
>> +
>> +       /* As registers for each port instance are scattered in the same
>> +        * address space, we have to map them singularly */
>> +       for (k = 0; k < REG_NR; k++) {
>> +               io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
>> +
>> +               /* Port0 and JP0 are inuput only: has REG_PPR only */
>> +               if (!io[k])
>> +                       break;
>> +
>> +               p->io[k] = devm_ioremap_resource(&pdev->dev, io[k]);
>> +               if (IS_ERR(p->io[k]))
>> +                       return PTR_ERR(p->io[k]);
>> +
>> +               p->nreg++;
>> +       }
>> +
>> +       /* move REG_PPR in correct position for Port0 and JP0 */
>> +       if (p->nreg == PORT0_NUM_REGS) {
>> +               p->io[REG_PPR] = p->io[REG_P];
>> +               p->io[REG_P] = p->io[REG_PM] = NULL;
>> +       }
>> +
>> +       ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
>> +
>> +       gpio_chip = &p->gpio_chip;
>
> Replace from here:
>
>> +       gpio_chip->get = rz_gpio_get;
>> +       gpio_chip->set = rz_gpio_set;
>> +       gpio_chip->direction_input = rz_gpio_direction_input;
>> +       gpio_chip->direction_output = rz_gpio_direction_output;
>> +       gpio_chip->get_direction = rz_gpio_get_direction;
>
> To here with:
>
> ret = bgpio_init(gpio_chip, &pdev->dev, 2,
>                        p->io[REG_PPR], p->io[REG_P], NULL,
>                        NULL, p->io[REG_PM], 0);
> if (ret)
>     return ret;
>
> This might need some flags or I screwed something up, but I'm
> convinced you can use GENERIC_GPIO like this.
>
> The generic accessors also sets the value before switching
> direction.
>
> If you're uncertain about the sematics, read drivers/gpio/gpio-mmio.c.
>
>> +       gpio_chip->request = rz_gpio_request;
>> +       gpio_chip->free = rz_gpio_free;
>> +       gpio_chip->label = dev_name(&pdev->dev);
>> +       gpio_chip->parent = &pdev->dev;
>> +       gpio_chip->owner = THIS_MODULE;
>> +       gpio_chip->base = -1;
>> +       gpio_chip->ngpio = ret == 0 ? args.args[2] : RZ_GPIOS_PER_PORT;
>
> bgpio_init() will have already set this up to 16 (RZ_GPIOS_PER_PORT)
> as we pass width 2 bytes.
>
> Yours,
> Linus Walleij
> --
> To unsubscribe from this list: send the line "unsubscribe linux-gpio" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>

[PATCH v3 4/8] arm: dts: r7s72100: GPIO and PFC device nodes

[Jacopo Mondi]

From: Magnus Damm <damm@opensource.se>

Add support for r7s72100 PFC and GPIO device nodes port0 -> port11
and jtagport0.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 arch/arm/boot/dts/r7s72100.dtsi | 136 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 136 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 3dd427d..4af7f01 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -359,6 +359,142 @@
 			<0xe8202000 0x1000>;
 	};
 
+	pfc: pfc@fcfe3300 {
+		compatible = "renesas,pfc-r7s72100";
+		reg = <0xfcfe3400 0x300>, /* PMC, PFC, PFCE */
+		      <0xfcfe3a00 0x100>, /* PFCAE */
+		      <0xfcfe7000 0x300>, /* PIBC, PBDC, PIPC */
+		      <0xfcfe7b40 0x04>, /* JPMC */
+		      <0xfcfe7b90 0x04>, /* JPMCSR */
+		      <0xfcfe7f00 0x04>; /* JPIBC */
+	};
+
+	port0: gpio@fcfe3000 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3200 0x2>; /* PPR0 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 0 6>;
+	};
+
+	port1: gpio@fcfe3004 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3004 0x2>, /* P1 */
+		      <0xfcfe3204 0x2>, /* PPR1 */
+		      <0xfcfe3304 0x2>; /* PM1 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 16 16>;
+	};
+
+	port2: gpio@fcfe3008 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3008 0x2>, /* P2 */
+		      <0xfcfe3208 0x2>, /* PPR2 */
+		      <0xfcfe3308 0x2>; /* PM2 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 32 16>;
+	};
+
+	port3: gpio@fcfe300c {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe300c 0x2>, /* P3 */
+		      <0xfcfe320c 0x2>, /* PPR3 */
+		      <0xfcfe330c 0x2>; /* PM3 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 48 16>;
+	};
+
+	port4: gpio@fcfe3010 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3010 0x2>, /* P4 */
+		      <0xfcfe3210 0x2>, /* PPR4 */
+		      <0xfcfe3310 0x2>; /* PM4 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 64 16>;
+	};
+
+	port5: gpio@fcfe3014 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3014 0x2>, /* P5 */
+		      <0xfcfe3214 0x2>, /* PPR5 */
+		      <0xfcfe3314 0x2>; /* PM5 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 80 11>;
+	};
+
+	port6: gpio@fcfe3018 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3018 0x2>, /* P6 */
+		      <0xfcfe3218 0x2>, /* PPR6 */
+		      <0xfcfe3318 0x2>; /* PM6 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 96 16>;
+	};
+
+	port7: gpio@fcfe301c {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe301c 0x2>, /* P7 */
+		      <0xfcfe321c 0x2>, /* PPR7 */
+		      <0xfcfe331c 0x2>; /* PM7 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 112 16>;
+	};
+
+	port8: gpio@fcfe3020 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3020 0x2>, /* P8 */
+		      <0xfcfe3220 0x2>, /* PPR8 */
+		      <0xfcfe3320 0x2>; /* PM8 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 128 16>;
+	};
+
+	port9: gpio@fcfe3024 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3024 0x2>, /* P9 */
+		      <0xfcfe3224 0x2>, /* PPR9 */
+		      <0xfcfe3324 0x2>; /* PM9 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 144 8>;
+	};
+
+	port10: gpio@fcfe3028 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe3028 0x2>, /* P10 */
+		      <0xfcfe3228 0x2>, /* PPR10 */
+		      <0xfcfe3328 0x2>; /* PM10 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 160 16>;
+	};
+
+	port11: gpio@fcfe302c {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe302c 0x2>, /* P11 */
+		      <0xfcfe322c 0x2>, /* PPR11 */
+		      <0xfcfe332c 0x2>; /* PM11 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 176 16>;
+	};
+
+	jtagport0: gpio@fcfe7b20 {
+		compatible = "renesas,gpio-r7s72100", "renesas,gpio-rz";
+		reg = <0xfcfe7b20 0x2>; /* JPPR0 */
+		#gpio-cells = <2>;
+		gpio-controller;
+		gpio-ranges = <&pfc 0 192 2>;
+	};
+
 	i2c0: i2c@fcfee000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-- 
2.7.4

[PATCH v3 5/8] arm: dts: r7s72100-genmai: SCIF2 PINCTRL configuration

[Jacopo Mondi]

From: Magnus Damm <damm@opensource.se>

Configure the r7s72100 PINCTRL hardware and select pin function
for the SCIF2 serial console.

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm/boot/dts/r7s72100-genmai.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 118a8e2..336716b 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -59,6 +59,16 @@
 	};
 };
 
+&pfc {
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+
+	scif2_pins: serial2 {
+		groups = "scif2_txd_p3_0", "scif2_rxd_p3_2";
+		function = "scif2";
+	};
+};
+
 &scif2 {
 	status = "okay";
 };
-- 
2.7.4

[PATCH v3 6/8] arm: dts: r7s72100-genmai: LED1 and LED2 support

[Jacopo Mondi]

From: Magnus Damm <damm@opensource.se>

Add support for Genmai board LED1 and LED2 via gpio-leds.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm/boot/dts/r7s72100-genmai.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 336716b..10f1d8b 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -11,6 +11,7 @@
 
 /dts-v1/;
 #include "r7s72100.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Genmai";
@@ -34,6 +35,16 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+		led1 {
+			gpios = <&port4 10 GPIO_ACTIVE_LOW>;
+		};
+		led2 {
+			gpios = <&port4 11 GPIO_ACTIVE_LOW>;
+		};
+	};
 };
 
 &extal_clk {
-- 
2.7.4

[PATCH v3 7/8] arm: dts: r7s72100-genmai:Add ethernet PFC node

[Jacopo Mondi]

From: Simon Horman <horms+renesas@verge.net.au>

Squash Simon's original commit with his fixup of sh_eth pin names

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 arch/arm/boot/dts/r7s72100-genmai.dts | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 10f1d8b..b36c84f 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -71,9 +71,32 @@
 };
 
 &pfc {
-	pinctrl-0 = <&scif2_pins>;
+	pinctrl-0 = <&ethernet_pins &scif2_pins>;
 	pinctrl-names = "default";
 
+	ethernet_pins: ethernet {
+		groups = "ethernet_rxdv_p3_6",
+			 "ethernet_rxer_p3_5",
+			 "ethernet_rxclk_p3_4",
+			 "ethernet_mdio_p3_3",
+			 "ethernet_rxd3_p2_11",
+			 "ethernet_rxd2_p2_10",
+			 "ethernet_rxd1_p2_9",
+			 "ethernet_rxd0_p2_8",
+			 "ethernet_txd3_p2_7",
+			 "ethernet_txd2_p2_6",
+			 "ethernet_txd1_p2_5",
+			 "ethernet_txd0_p2_4",
+			 "ethernet_txcrs_p2_3",
+			 "ethernet_txen_p2_2",
+			 "ethernet_txer_p2_1",
+			 "ethernet_txclk_p2_0",
+			 "ethernet_mdc_p5_9",
+			 "ethernet_col_p1_14",
+			 "ethernet_int_p1_15";
+		function = "ethernet";
+	};
+
 	scif2_pins: serial2 {
 		groups = "scif2_txd_p3_0", "scif2_rxd_p3_2";
 		function = "scif2";
-- 
2.7.4

[PATCH v3 8/8] arm: dts: r7s72100-genmai: Add pinctrl for RSPI

[Jacopo Mondi]

From: Geert Uytterhoeven <geert+renesas@glider.be>

Add pinctrl for the existing rspi4 node on Genmai.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 arch/arm/boot/dts/r7s72100-genmai.dts | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index b36c84f..01c08e0 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -71,7 +71,7 @@
 };
 
 &pfc {
-	pinctrl-0 = <&ethernet_pins &scif2_pins>;
+	pinctrl-0 = <&ethernet_pins &rspi4_pins &scif2_pins>;
 	pinctrl-names = "default";
 
 	ethernet_pins: ethernet {
@@ -97,6 +97,12 @@
 		function = "ethernet";
 	};
 
+	rspi4_pins: spi4 {
+		groups = "rspi4_rspck_p4_0", "rspi4_ssl0_p4_1",
+			 "rspi4_mosi_p4_2", "rspi4_miso_p4_3";
+		function = "rspi4";
+	};
+
 	scif2_pins: serial2 {
 		groups = "scif2_txd_p3_0", "scif2_rxd_p3_2";
 		function = "scif2";
-- 
2.7.4