* [PATCH 1/2] dt/bindings: gpio: Document ZTE zx296702 GPIO
@ 2015-06-12 8:35 Jun Nie
2015-06-12 8:35 ` [PATCH 2/2] gpio: zx: Add ZTE zx296702 GPIO support Jun Nie
0 siblings, 1 reply; 3+ messages in thread
From: Jun Nie @ 2015-06-12 8:35 UTC (permalink / raw)
To: linus.walleij, linux-gpio; +Cc: shawn.guo, wan.zhijun, jason.liu, Jun Nie
Add document of ZTE zx296702 GPIO binding
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
.../devicetree/bindings/gpio/zx296702-gpio.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
diff --git a/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt b/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
new file mode 100644
index 0000000..0dab156
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/zx296702-gpio.txt
@@ -0,0 +1,24 @@
+ZTE ZX296702 GPIO controller
+
+Required properties:
+- compatible : "zte,zx296702-gpio"
+- #gpio-cells : Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- interrupts : Interrupt mapping for GPIO IRQ.
+- gpio-ranges : Interaction with the PINCTRL subsystem.
+
+gpio1: gpio@b008040 {
+ compatible = "zte,zx296702-gpio";
+ reg = <0xb008040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clock-names = "gpio_pclk";
+ clocks = <&lsp0clk ZX296702_GPIO_CLK>;
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] gpio: zx: Add ZTE zx296702 GPIO support
2015-06-12 8:35 [PATCH 1/2] dt/bindings: gpio: Document ZTE zx296702 GPIO Jun Nie
@ 2015-06-12 8:35 ` Jun Nie
2015-06-17 8:18 ` Linus Walleij
0 siblings, 1 reply; 3+ messages in thread
From: Jun Nie @ 2015-06-12 8:35 UTC (permalink / raw)
To: linus.walleij, linux-gpio; +Cc: shawn.guo, wan.zhijun, jason.liu, Jun Nie
Add ZTE zx296702 GPIO controller support
Signed-off-by: Jun Nie <jun.nie@linaro.org>
---
drivers/gpio/Kconfig | 7 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-zx296702.c | 322 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 330 insertions(+)
create mode 100644 drivers/gpio/gpio-zx296702.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index caefe80..d513668 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -970,6 +970,13 @@ config GPIO_MC33880
SPI driver for Freescale MC33880 high-side/low-side switch.
This provides GPIO interface supporting inputs and outputs.
+config GPIO_ZX296702
+ bool "ZTE ZX296702 GPIO support"
+ select IRQ_DOMAIN
+ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to support the ZTE ZX296702 GPIO device
+
endmenu
menu "USB GPIO expanders"
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index f71bb97..c26d81e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -112,3 +112,4 @@ obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
+obj-$(CONFIG_GPIO_ZX296702) += gpio-zx296702.o
diff --git a/drivers/gpio/gpio-zx296702.c b/drivers/gpio/gpio-zx296702.c
new file mode 100644
index 0000000..2368c6b
--- /dev/null
+++ b/drivers/gpio/gpio-zx296702.c
@@ -0,0 +1,322 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/module.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#define ZX_GPIO_DIR 0x00
+#define ZX_GPIO_IVE 0x04
+#define ZX_GPIO_IV 0x08
+#define ZX_GPIO_IEP 0x0C
+#define ZX_GPIO_IEN 0x10
+#define ZX_GPIO_DI 0x14
+#define ZX_GPIO_DO1 0x18
+#define ZX_GPIO_DO0 0x1C
+#define ZX_GPIO_DO 0x20
+
+#define ZX_GPIO_IM 0x28
+#define ZX_GPIO_IE 0x2C
+
+#define ZX_GPIO_MIS 0x30
+#define ZX_GPIO_IC 0x34
+
+#define ZX_GPIO_NR 16
+
+struct zx_gpio {
+ spinlock_t lock;
+
+ void __iomem *base;
+ struct gpio_chip gc;
+ bool uses_pinctrl;
+ int irq;
+};
+
+static int zx_gpio_request(struct gpio_chip *gc, unsigned offset)
+{
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+ int gpio = gc->base + offset;
+
+ if (chip->uses_pinctrl)
+ return pinctrl_request_gpio(gpio);
+ return 0;
+}
+
+static void zx_gpio_free(struct gpio_chip *gc, unsigned offset)
+{
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+ int gpio = gc->base + offset;
+
+ if (chip->uses_pinctrl)
+ pinctrl_free_gpio(gpio);
+}
+
+static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+ unsigned long flags;
+ unsigned char gpiodir;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ spin_lock_irqsave(&chip->lock, flags);
+ gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
+ gpiodir &= ~(BIT(offset));
+ writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
+ spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
+ int value)
+{
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+ unsigned long flags;
+ unsigned char gpiodir;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ spin_lock_irqsave(&chip->lock, flags);
+ gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
+ gpiodir |= BIT(offset);
+ writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
+
+ if (value)
+ writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
+ else
+ writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
+ spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int zx_get_value(struct gpio_chip *gc, unsigned offset)
+{
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+
+ return !!(BIT(offset) & readw_relaxed(chip->base + ZX_GPIO_DI));
+}
+
+static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
+{
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+
+ if (value)
+ writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
+ else
+ writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
+}
+
+static int zx_irq_type(struct irq_data *d, unsigned trigger)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+ int offset = irqd_to_hwirq(d);
+ unsigned long flags;
+ u8 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
+ u8 bit = BIT(offset);
+
+ if (offset < 0 || offset >= ZX_GPIO_NR)
+ return -EINVAL;
+
+ spin_lock_irqsave(&chip->lock, flags);
+
+ gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
+ gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
+ gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
+ gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
+
+ if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
+ gpiois |= bit;
+ if (trigger & IRQ_TYPE_LEVEL_HIGH)
+ gpioiev |= bit;
+ else
+ gpioiev &= ~bit;
+ } else
+ gpiois &= ~bit;
+
+ if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
+ gpioi_epos |= bit;
+ gpioi_eneg |= bit;
+ } else {
+ if (trigger & IRQ_TYPE_EDGE_RISING) {
+ gpioi_epos |= bit;
+ gpioi_eneg &= ~bit;
+ } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
+ gpioi_eneg |= bit;
+ gpioi_epos &= ~bit;
+ }
+ }
+
+ writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
+ writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
+ writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
+ writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
+ spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static void zx_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+ unsigned long pending;
+ int offset;
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+ struct irq_chip *irqchip = irq_desc_get_chip(desc);
+
+ chained_irq_enter(irqchip, desc);
+
+ pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
+ writew_relaxed(pending, chip->base + ZX_GPIO_IC);
+ if (pending) {
+ for_each_set_bit(offset, &pending, ZX_GPIO_NR)
+ generic_handle_irq(irq_find_mapping(gc->irqdomain,
+ offset));
+ }
+
+ chained_irq_exit(irqchip, desc);
+}
+
+static void zx_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+ u8 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
+ u8 gpioie;
+
+ spin_lock(&chip->lock);
+ gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
+ writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
+ gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
+ writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
+ spin_unlock(&chip->lock);
+}
+
+static void zx_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
+ u8 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
+ u8 gpioie;
+
+ spin_lock(&chip->lock);
+ gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
+ writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
+ gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
+ writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
+ spin_unlock(&chip->lock);
+}
+
+static struct irq_chip zx_irqchip = {
+ .name = "zx",
+ .irq_mask = zx_irq_mask,
+ .irq_unmask = zx_irq_unmask,
+ .irq_set_type = zx_irq_type,
+};
+
+static int zx_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct zx_gpio *chip;
+ struct resource *res;
+ int id, ret, irq_base = 0;
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (chip == NULL)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ chip->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(chip->base))
+ return PTR_ERR(chip->base);
+
+ spin_lock_init(&chip->lock);
+ if (of_property_read_bool(dev->of_node, "gpio-ranges"))
+ chip->uses_pinctrl = true;
+
+ id = of_alias_get_id(dev->of_node, "gpio");
+ chip->gc.request = zx_gpio_request;
+ chip->gc.free = zx_gpio_free;
+ chip->gc.direction_input = zx_direction_input;
+ chip->gc.direction_output = zx_direction_output;
+ chip->gc.get = zx_get_value;
+ chip->gc.set = zx_set_value;
+ chip->gc.base = ZX_GPIO_NR * id;
+ chip->gc.ngpio = ZX_GPIO_NR;
+ chip->gc.label = dev_name(dev);
+ chip->gc.dev = dev;
+ chip->gc.owner = THIS_MODULE;
+
+ ret = gpiochip_add(&chip->gc);
+ if (ret)
+ return ret;
+
+ /*
+ * irq_chip support
+ */
+ writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
+ writew_relaxed(0, chip->base + ZX_GPIO_IE);
+ chip->irq = platform_get_irq(pdev, 0);
+ if (chip->irq < 0) {
+ dev_err(dev, "invalid IRQ\n");
+ return -ENODEV;
+ }
+
+ ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
+ irq_base, handle_simple_irq,
+ IRQ_TYPE_NONE);
+ if (ret) {
+ dev_info(dev, "could not add irqchip\n");
+ return ret;
+ }
+ gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
+ chip->irq, zx_irq_handler);
+
+ platform_set_drvdata(pdev, chip);
+ dev_info(dev, "ZX GPIO chip registered\n");
+
+ return 0;
+}
+
+#if defined(CONFIG_OF)
+static const struct of_device_id zx_gpio_match[] = {
+ {
+ .compatible = "zte,zx296702-gpio",
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, zx_gpio_match);
+#endif
+
+static struct platform_driver zx_gpio_driver = {
+ .probe = zx_gpio_probe,
+ .driver = {
+ .name = "zx_gpio",
+ .of_match_table = of_match_ptr(zx_gpio_match),
+ },
+};
+
+module_platform_driver(zx_gpio_driver)
+
+MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
+MODULE_DESCRIPTION("ZTE ZX296702 GPIO driver");
+MODULE_LICENSE("GPL");
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 2/2] gpio: zx: Add ZTE zx296702 GPIO support
2015-06-12 8:35 ` [PATCH 2/2] gpio: zx: Add ZTE zx296702 GPIO support Jun Nie
@ 2015-06-17 8:18 ` Linus Walleij
0 siblings, 0 replies; 3+ messages in thread
From: Linus Walleij @ 2015-06-17 8:18 UTC (permalink / raw)
To: Jun Nie; +Cc: linux-gpio, Shawn Guo, wan.zhijun, jason.liu
On Fri, Jun 12, 2015 at 10:35 AM, Jun Nie <jun.nie@linaro.org> wrote:
> Add ZTE zx296702 GPIO controller support
>
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
OK looks like a solid start!
> +config GPIO_ZX296702
> + bool "ZTE ZX296702 GPIO support"
> + select IRQ_DOMAIN
> + select GPIOLIB_IRQCHIP
You do not need to select IRQ_DOMAIN when you select GPIOLIB_IRQCHIP,
which selects that for you.
(...)
> +#include <linux/bitops.h>
> +#include <linux/device.h>
> +#include <linux/errno.h>
> +#include <linux/gpio.h>
Please use only:
#include <linux/gpio/driver.h>
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip/chained_irq.h>
You should not need the three last includes.
> +#include <linux/module.h>
> +#include <linux/pinctrl/consumer.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#define ZX_GPIO_DIR 0x00
> +#define ZX_GPIO_IVE 0x04
> +#define ZX_GPIO_IV 0x08
> +#define ZX_GPIO_IEP 0x0C
> +#define ZX_GPIO_IEN 0x10
> +#define ZX_GPIO_DI 0x14
> +#define ZX_GPIO_DO1 0x18
> +#define ZX_GPIO_DO0 0x1C
> +#define ZX_GPIO_DO 0x20
> +
> +#define ZX_GPIO_IM 0x28
> +#define ZX_GPIO_IE 0x2C
> +
> +#define ZX_GPIO_MIS 0x30
> +#define ZX_GPIO_IC 0x34
> +
> +#define ZX_GPIO_NR 16
> +
> +struct zx_gpio {
> + spinlock_t lock;
> +
> + void __iomem *base;
> + struct gpio_chip gc;
> + bool uses_pinctrl;
> + int irq;
Why do you need to save the irq number?
> +static int zx_gpio_request(struct gpio_chip *gc, unsigned offset)
> +{
> + struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
Please create a static inline to do this cast:
static inline struct zx_gpio *to_zx(struct gpio_chip *gc)
{
return container_of(gc, struct zx_gpio, gc);
}
Then just everywhere:
struct zx_gpio *zx = to_zx(gc);
> +static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
> +{
> + struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
> + unsigned long flags;
> + unsigned char gpiodir;
> +
> + if (offset >= gc->ngpio)
> + return -EINVAL;
> +
> + spin_lock_irqsave(&chip->lock, flags);
> + gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
> + gpiodir &= ~(BIT(offset));
Too much parentheses?
> +static int zx_get_value(struct gpio_chip *gc, unsigned offset)
> +{
> + struct zx_gpio *chip = container_of(gc, struct zx_gpio, gc);
> +
> + return !!(BIT(offset) & readw_relaxed(chip->base + ZX_GPIO_DI));
For some reason I always put it in the other order, first the read
then the &mask, but this is of course semantically equivalent.
> + /*
> + * irq_chip support
> + */
> + writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
> + writew_relaxed(0, chip->base + ZX_GPIO_IE);
> + chip->irq = platform_get_irq(pdev, 0);
> + if (chip->irq < 0) {
> + dev_err(dev, "invalid IRQ\n");
> + return -ENODEV;
> + }
No point in keeping chip->irq around, make it a local variable.
> + ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
> + irq_base, handle_simple_irq,
> + IRQ_TYPE_NONE);
> + if (ret) {
> + dev_info(dev, "could not add irqchip\n");
> + return ret;
> + }
Instead of passing irq_base as 0, just pass a zero here
instead of a variable it is less obscure.
Apart from these small things it looks nice!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-06-17 8:18 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-12 8:35 [PATCH 1/2] dt/bindings: gpio: Document ZTE zx296702 GPIO Jun Nie
2015-06-12 8:35 ` [PATCH 2/2] gpio: zx: Add ZTE zx296702 GPIO support Jun Nie
2015-06-17 8:18 ` Linus Walleij
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