* [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation
@ 2015-11-30 11:20 Qipeng Zha
2015-11-30 11:20 ` [PATCH V4 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN Qipeng Zha
2015-12-01 14:10 ` [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation Linus Walleij
0 siblings, 2 replies; 6+ messages in thread
From: Qipeng Zha @ 2015-11-30 11:20 UTC (permalink / raw)
To: linux-gpio; +Cc: linus.walleij, mika.westerberg, qi.zheng, qipeng.zha
The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS,
GPI_IE, are not 24 for Broxton, Add a parameter to allow
different platform to set correct value.
Signed-off-by: Qi Zheng <qi.zheng@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
---
change in v4:
no code change, re-send because the other patch set is update.
change in v3:
use community->gpp_size directly, not macro.
change in v2:
define gpp_size for sunrisepoint in its private structure.
---
drivers/pinctrl/intel/pinctrl-broxton.c | 1 +
drivers/pinctrl/intel/pinctrl-intel.c | 32 +++++++++++++---------------
drivers/pinctrl/intel/pinctrl-intel.h | 3 +++
drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 1 +
4 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
index e42d5d4..5979d38 100644
--- a/drivers/pinctrl/intel/pinctrl-broxton.c
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -28,6 +28,7 @@
.padcfglock_offset = BXT_PADCFGLOCK, \
.hostown_offset = BXT_HOSTSW_OWN, \
.ie_offset = BXT_GPI_IE, \
+ .gpp_size = 32, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
}
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 392e28d..06004d8 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -25,9 +25,6 @@
#include "pinctrl-intel.h"
-/* Maximum number of pads in each group */
-#define NPADS_IN_GPP 24
-
/* Offset from regs */
#define PADBAR 0x00c
#define GPI_IS 0x100
@@ -173,11 +170,11 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
return false;
padno = pin_to_padno(community, pin);
- gpp = padno / NPADS_IN_GPP;
+ gpp = padno / community->gpp_size;
offset = community->hostown_offset + gpp * 4;
hostown = community->regs + offset;
- return !(readl(hostown) & BIT(padno % NPADS_IN_GPP));
+ return !(readl(hostown) & BIT(padno % community->gpp_size));
}
static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
@@ -193,7 +190,7 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
return false;
padno = pin_to_padno(community, pin);
- gpp = padno / NPADS_IN_GPP;
+ gpp = padno / community->gpp_size;
/*
* If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
@@ -202,12 +199,12 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
*/
offset = community->padcfglock_offset + gpp * 8;
value = readl(community->regs + offset);
- if (value & BIT(pin % NPADS_IN_GPP))
+ if (value & BIT(pin % community->gpp_size))
return true;
offset = community->padcfglock_offset + 4 + gpp * 8;
value = readl(community->regs + offset);
- if (value & BIT(pin % NPADS_IN_GPP))
+ if (value & BIT(pin % community->gpp_size))
return true;
return false;
@@ -663,8 +660,8 @@ static void intel_gpio_irq_ack(struct irq_data *d)
community = intel_get_community(pctrl, pin);
if (community) {
unsigned padno = pin_to_padno(community, pin);
- unsigned gpp_offset = padno % NPADS_IN_GPP;
- unsigned gpp = padno / NPADS_IN_GPP;
+ unsigned gpp_offset = padno % community->gpp_size;
+ unsigned gpp = padno / community->gpp_size;
writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
}
@@ -685,8 +682,8 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
community = intel_get_community(pctrl, pin);
if (community) {
unsigned padno = pin_to_padno(community, pin);
- unsigned gpp_offset = padno % NPADS_IN_GPP;
- unsigned gpp = padno / NPADS_IN_GPP;
+ unsigned gpp_offset = padno % community->gpp_size;
+ unsigned gpp = padno / community->gpp_size;
void __iomem *reg;
u32 value;
@@ -780,8 +777,8 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
return -EINVAL;
padno = pin_to_padno(community, pin);
- gpp = padno / NPADS_IN_GPP;
- gpp_offset = padno % NPADS_IN_GPP;
+ gpp = padno / community->gpp_size;
+ gpp_offset = padno % community->gpp_size;
/* Clear the existing wake status */
writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
@@ -819,14 +816,14 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
/* Only interrupts that are enabled */
pending &= enabled;
- for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) {
+ for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
unsigned padno, irq;
/*
* The last group in community can have less pins
* than NPADS_IN_GPP.
*/
- padno = gpp_offset + gpp * NPADS_IN_GPP;
+ padno = gpp_offset + gpp * community->gpp_size;
if (padno >= community->npins)
break;
@@ -1002,7 +999,8 @@ int intel_pinctrl_probe(struct platform_device *pdev,
community->regs = regs;
community->pad_regs = regs + padbar;
- community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP);
+ community->ngpps = DIV_ROUND_UP(community->npins,
+ community->gpp_size);
}
irq = platform_get_irq(pdev, 0);
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index 4ec8b57..b602157 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -55,6 +55,8 @@ struct intel_function {
* ACPI).
* @ie_offset: Register offset of GPI_IE from @regs.
* @pin_base: Starting pin of pins in this community
+ * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
+ * HOSTSW_OWN, GPI_IS, GPI_IE, etc.
* @npins: Number of pins in this community
* @regs: Community specific common registers (reserved for core driver)
* @pad_regs: Community specific pad registers (reserved for core driver)
@@ -68,6 +70,7 @@ struct intel_community {
unsigned hostown_offset;
unsigned ie_offset;
unsigned pin_base;
+ unsigned gpp_size;
size_t npins;
void __iomem *regs;
void __iomem *pad_regs;
diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
index 1de9ae5..c725a53 100644
--- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
+++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
@@ -30,6 +30,7 @@
.padcfglock_offset = SPT_PADCFGLOCK, \
.hostown_offset = SPT_HOSTSW_OWN, \
.ie_offset = SPT_GPI_IE, \
+ .gpp_size = 24, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
}
--
1.8.3.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH V4 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN
2015-11-30 11:20 [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation Qipeng Zha
@ 2015-11-30 11:20 ` Qipeng Zha
2015-12-01 9:20 ` Mika Westerberg
2015-12-10 17:05 ` Linus Walleij
2015-12-01 14:10 ` [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation Linus Walleij
1 sibling, 2 replies; 6+ messages in thread
From: Qipeng Zha @ 2015-11-30 11:20 UTC (permalink / raw)
To: linux-gpio; +Cc: linus.walleij, mika.westerberg, qi.zheng, qipeng.zha
The calculation equation of PAD_OWN register offset is not
correct for Broxton, verified this fix will get right
offset for Broxton.
Signed-off-by: Qi Zheng <qi.zheng@intel.com>
Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
---
change in v4
fix the equation regarding to sunprisepoint platform.
---
drivers/pinctrl/intel/pinctrl-intel.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 06004d8..26f6b6f 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -34,6 +34,7 @@
#define PADOWN_BITS 4
#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
+#define PADOWN_GPP(p) ((p) / 8)
/* Offset from pad_regs */
#define PADCFG0 0x000
@@ -139,7 +140,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
{
const struct intel_community *community;
- unsigned padno, gpp, gpp_offset, offset;
+ unsigned padno, gpp, offset, group;
void __iomem *padown;
community = intel_get_community(pctrl, pin);
@@ -149,9 +150,9 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
return true;
padno = pin_to_padno(community, pin);
- gpp = padno / NPADS_IN_GPP;
- gpp_offset = padno % NPADS_IN_GPP;
- offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4;
+ group = padno / community->gpp_size;
+ gpp = PADOWN_GPP(padno % community->gpp_size);
+ offset = community->padown_offset + 0x10 * group + gpp * 4;
padown = community->regs + offset;
return !(readl(padown) & PADOWN_MASK(padno));
--
1.8.3.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V4 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN
2015-11-30 11:20 ` [PATCH V4 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN Qipeng Zha
@ 2015-12-01 9:20 ` Mika Westerberg
2015-12-10 17:05 ` Linus Walleij
1 sibling, 0 replies; 6+ messages in thread
From: Mika Westerberg @ 2015-12-01 9:20 UTC (permalink / raw)
To: Qipeng Zha; +Cc: linux-gpio, linus.walleij, qi.zheng
On Mon, Nov 30, 2015 at 07:20:16PM +0800, Qipeng Zha wrote:
> The calculation equation of PAD_OWN register offset is not
> correct for Broxton, verified this fix will get right
> offset for Broxton.
>
> Signed-off-by: Qi Zheng <qi.zheng@intel.com>
> Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation
2015-11-30 11:20 [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation Qipeng Zha
2015-11-30 11:20 ` [PATCH V4 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN Qipeng Zha
@ 2015-12-01 14:10 ` Linus Walleij
2015-12-09 13:07 ` Westerberg, Mika
1 sibling, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2015-12-01 14:10 UTC (permalink / raw)
To: Qipeng Zha; +Cc: linux-gpio, Westerberg, Mika, Qi Zheng
On Mon, Nov 30, 2015 at 12:20 PM, Qipeng Zha <qipeng.zha@intel.com> wrote:
> The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS,
> GPI_IE, are not 24 for Broxton, Add a parameter to allow
> different platform to set correct value.
>
> Signed-off-by: Qi Zheng <qi.zheng@intel.com>
> Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
>
> ---
> change in v4:
> no code change, re-send because the other patch set is update.
I've already applied the v3 version so no action :)
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation
2015-12-01 14:10 ` [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation Linus Walleij
@ 2015-12-09 13:07 ` Westerberg, Mika
0 siblings, 0 replies; 6+ messages in thread
From: Westerberg, Mika @ 2015-12-09 13:07 UTC (permalink / raw)
To: Linus Walleij; +Cc: Qipeng Zha, linux-gpio, Qi Zheng
On Tue, Dec 01, 2015 at 03:10:40PM +0100, Linus Walleij wrote:
> On Mon, Nov 30, 2015 at 12:20 PM, Qipeng Zha <qipeng.zha@intel.com> wrote:
>
> > The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS,
> > GPI_IE, are not 24 for Broxton, Add a parameter to allow
> > different platform to set correct value.
> >
> > Signed-off-by: Qi Zheng <qi.zheng@intel.com>
> > Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
> >
> > ---
> > change in v4:
> > no code change, re-send because the other patch set is update.
>
> I've already applied the v3 version so no action :)
Can you also take patch 2/2 of this series? It fixes the other bug
Qipeng found.
Thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V4 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN
2015-11-30 11:20 ` [PATCH V4 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN Qipeng Zha
2015-12-01 9:20 ` Mika Westerberg
@ 2015-12-10 17:05 ` Linus Walleij
1 sibling, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2015-12-10 17:05 UTC (permalink / raw)
To: Qipeng Zha; +Cc: linux-gpio, Westerberg, Mika, Qi Zheng
On Mon, Nov 30, 2015 at 12:20 PM, Qipeng Zha <qipeng.zha@intel.com> wrote:
> The calculation equation of PAD_OWN register offset is not
> correct for Broxton, verified this fix will get right
> offset for Broxton.
>
> Signed-off-by: Qi Zheng <qi.zheng@intel.com>
> Signed-off-by: Qipeng Zha <qipeng.zha@intel.com>
>
> ---
> change in v4
> fix the equation regarding to sunprisepoint platform.
Patch applied for fixes with Mika's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-12-10 17:05 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2015-11-30 11:20 [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation Qipeng Zha
2015-11-30 11:20 ` [PATCH V4 2/2] pinctrl: intel: fix offset calculation issue of register PAD_OWN Qipeng Zha
2015-12-01 9:20 ` Mika Westerberg
2015-12-10 17:05 ` Linus Walleij
2015-12-01 14:10 ` [PATCH V4 1/2] pinctrl: intel: fix bug of register offset calculation Linus Walleij
2015-12-09 13:07 ` Westerberg, Mika
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