* [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support
@ 2015-03-19 21:34 Carlo Caione
2015-03-19 21:34 ` [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver Carlo Caione
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Carlo Caione @ 2015-03-19 21:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Carlo Caione <carlo@endlessm.com>
This patchset extends the pinctrl driver to support AmLogic Meson8b.
The driver for Meson8 has been revised to make it shorter.
Changelog:
v3: * shorten the meson8/meson8b support files
* document GPIO banks for meson8b
v2: * fix holes in GPIOs numbering
v1: * initial version
Carlo Caione (3):
pinctrl: Cleanup Meson8 driver
documentation: Extend pinctrl docs for Meson8b
pinctrl: Add support for Meson8b
.../devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 +-
drivers/pinctrl/meson/Makefile | 2 +-
drivers/pinctrl/meson/pinctrl-meson.c | 9 +-
drivers/pinctrl/meson/pinctrl-meson.h | 9 +-
drivers/pinctrl/meson/pinctrl-meson8.c | 1050 +++++++++-----------
drivers/pinctrl/meson/pinctrl-meson8b.c | 900 +++++++++++++++++
include/dt-bindings/gpio/meson8b-gpio.h | 32 +
7 files changed, 1403 insertions(+), 601 deletions(-)
create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c
create mode 100644 include/dt-bindings/gpio/meson8b-gpio.h
--
1.9.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver
2015-03-19 21:34 [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support Carlo Caione
@ 2015-03-19 21:34 ` Carlo Caione
2015-03-28 9:47 ` Beniamino Galvani
2015-04-07 9:42 ` Linus Walleij
2015-03-19 21:34 ` [PATCH v3 2/3] documentation: Extend pinctrl docs for Meson8b Carlo Caione
` (2 subsequent siblings)
3 siblings, 2 replies; 11+ messages in thread
From: Carlo Caione @ 2015-03-19 21:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Carlo Caione <carlo@endlessm.com>
This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
---
drivers/pinctrl/meson/pinctrl-meson.h | 8 +-
drivers/pinctrl/meson/pinctrl-meson8.c | 1050 ++++++++++++++------------------
2 files changed, 461 insertions(+), 597 deletions(-)
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index bfea8ad..bc48c78 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -155,6 +155,8 @@ struct meson_pinctrl {
struct meson_domain *domains;
};
+#define PIN(x, b) (b + x)
+
#define GROUP(grp, r, b) \
{ \
.name = #grp, \
@@ -165,10 +167,10 @@ struct meson_pinctrl {
.domain = 0, \
}
-#define GPIO_GROUP(gpio) \
+#define GPIO_GROUP(gpio, b) \
{ \
.name = #gpio, \
- .pins = (const unsigned int[]){ PIN_ ## gpio}, \
+ .pins = (const unsigned int[]){ PIN(gpio, b) }, \
.num_pins = 1, \
.is_gpio = true, \
}
@@ -204,6 +206,6 @@ struct meson_pinctrl {
}, \
}
-#define MESON_PIN(x) PINCTRL_PIN(PIN_ ## x, #x)
+#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
extern struct meson_pinctrl_data meson8_pinctrl_data;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
index f8aa3a2..7b1cc91 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -14,620 +14,482 @@
#include <dt-bindings/gpio/meson8-gpio.h>
#include "pinctrl-meson.h"
-#define AO_OFFSET 120
-
-#define PIN_GPIOX_0 GPIOX_0
-#define PIN_GPIOX_1 GPIOX_1
-#define PIN_GPIOX_2 GPIOX_2
-#define PIN_GPIOX_3 GPIOX_3
-#define PIN_GPIOX_4 GPIOX_4
-#define PIN_GPIOX_5 GPIOX_5
-#define PIN_GPIOX_6 GPIOX_6
-#define PIN_GPIOX_7 GPIOX_7
-#define PIN_GPIOX_8 GPIOX_8
-#define PIN_GPIOX_9 GPIOX_9
-#define PIN_GPIOX_10 GPIOX_10
-#define PIN_GPIOX_11 GPIOX_11
-#define PIN_GPIOX_12 GPIOX_12
-#define PIN_GPIOX_13 GPIOX_13
-#define PIN_GPIOX_14 GPIOX_14
-#define PIN_GPIOX_15 GPIOX_15
-#define PIN_GPIOX_16 GPIOX_16
-#define PIN_GPIOX_17 GPIOX_17
-#define PIN_GPIOX_18 GPIOX_18
-#define PIN_GPIOX_19 GPIOX_19
-#define PIN_GPIOX_20 GPIOX_20
-#define PIN_GPIOX_21 GPIOX_21
-#define PIN_GPIOY_0 GPIOY_0
-#define PIN_GPIOY_1 GPIOY_1
-#define PIN_GPIOY_2 GPIOY_2
-#define PIN_GPIOY_3 GPIOY_3
-#define PIN_GPIOY_4 GPIOY_4
-#define PIN_GPIOY_5 GPIOY_5
-#define PIN_GPIOY_6 GPIOY_6
-#define PIN_GPIOY_7 GPIOY_7
-#define PIN_GPIOY_8 GPIOY_8
-#define PIN_GPIOY_9 GPIOY_9
-#define PIN_GPIOY_10 GPIOY_10
-#define PIN_GPIOY_11 GPIOY_11
-#define PIN_GPIOY_12 GPIOY_12
-#define PIN_GPIOY_13 GPIOY_13
-#define PIN_GPIOY_14 GPIOY_14
-#define PIN_GPIOY_15 GPIOY_15
-#define PIN_GPIOY_16 GPIOY_16
-#define PIN_GPIODV_0 GPIODV_0
-#define PIN_GPIODV_1 GPIODV_1
-#define PIN_GPIODV_2 GPIODV_2
-#define PIN_GPIODV_3 GPIODV_3
-#define PIN_GPIODV_4 GPIODV_4
-#define PIN_GPIODV_5 GPIODV_5
-#define PIN_GPIODV_6 GPIODV_6
-#define PIN_GPIODV_7 GPIODV_7
-#define PIN_GPIODV_8 GPIODV_8
-#define PIN_GPIODV_9 GPIODV_9
-#define PIN_GPIODV_10 GPIODV_10
-#define PIN_GPIODV_11 GPIODV_11
-#define PIN_GPIODV_12 GPIODV_12
-#define PIN_GPIODV_13 GPIODV_13
-#define PIN_GPIODV_14 GPIODV_14
-#define PIN_GPIODV_15 GPIODV_15
-#define PIN_GPIODV_16 GPIODV_16
-#define PIN_GPIODV_17 GPIODV_17
-#define PIN_GPIODV_18 GPIODV_18
-#define PIN_GPIODV_19 GPIODV_19
-#define PIN_GPIODV_20 GPIODV_20
-#define PIN_GPIODV_21 GPIODV_21
-#define PIN_GPIODV_22 GPIODV_22
-#define PIN_GPIODV_23 GPIODV_23
-#define PIN_GPIODV_24 GPIODV_24
-#define PIN_GPIODV_25 GPIODV_25
-#define PIN_GPIODV_26 GPIODV_26
-#define PIN_GPIODV_27 GPIODV_27
-#define PIN_GPIODV_28 GPIODV_28
-#define PIN_GPIODV_29 GPIODV_29
-#define PIN_GPIOH_0 GPIOH_0
-#define PIN_GPIOH_1 GPIOH_1
-#define PIN_GPIOH_2 GPIOH_2
-#define PIN_GPIOH_3 GPIOH_3
-#define PIN_GPIOH_4 GPIOH_4
-#define PIN_GPIOH_5 GPIOH_5
-#define PIN_GPIOH_6 GPIOH_6
-#define PIN_GPIOH_7 GPIOH_7
-#define PIN_GPIOH_8 GPIOH_8
-#define PIN_GPIOH_9 GPIOH_9
-#define PIN_GPIOZ_0 GPIOZ_0
-#define PIN_GPIOZ_1 GPIOZ_1
-#define PIN_GPIOZ_2 GPIOZ_2
-#define PIN_GPIOZ_3 GPIOZ_3
-#define PIN_GPIOZ_4 GPIOZ_4
-#define PIN_GPIOZ_5 GPIOZ_5
-#define PIN_GPIOZ_6 GPIOZ_6
-#define PIN_GPIOZ_7 GPIOZ_7
-#define PIN_GPIOZ_8 GPIOZ_8
-#define PIN_GPIOZ_9 GPIOZ_9
-#define PIN_GPIOZ_10 GPIOZ_10
-#define PIN_GPIOZ_11 GPIOZ_11
-#define PIN_GPIOZ_12 GPIOZ_12
-#define PIN_GPIOZ_13 GPIOZ_13
-#define PIN_GPIOZ_14 GPIOZ_14
-#define PIN_CARD_0 CARD_0
-#define PIN_CARD_1 CARD_1
-#define PIN_CARD_2 CARD_2
-#define PIN_CARD_3 CARD_3
-#define PIN_CARD_4 CARD_4
-#define PIN_CARD_5 CARD_5
-#define PIN_CARD_6 CARD_6
-#define PIN_BOOT_0 BOOT_0
-#define PIN_BOOT_1 BOOT_1
-#define PIN_BOOT_2 BOOT_2
-#define PIN_BOOT_3 BOOT_3
-#define PIN_BOOT_4 BOOT_4
-#define PIN_BOOT_5 BOOT_5
-#define PIN_BOOT_6 BOOT_6
-#define PIN_BOOT_7 BOOT_7
-#define PIN_BOOT_8 BOOT_8
-#define PIN_BOOT_9 BOOT_9
-#define PIN_BOOT_10 BOOT_10
-#define PIN_BOOT_11 BOOT_11
-#define PIN_BOOT_12 BOOT_12
-#define PIN_BOOT_13 BOOT_13
-#define PIN_BOOT_14 BOOT_14
-#define PIN_BOOT_15 BOOT_15
-#define PIN_BOOT_16 BOOT_16
-#define PIN_BOOT_17 BOOT_17
-#define PIN_BOOT_18 BOOT_18
-
-#define PIN_GPIOAO_0 (AO_OFFSET + GPIOAO_0)
-#define PIN_GPIOAO_1 (AO_OFFSET + GPIOAO_1)
-#define PIN_GPIOAO_2 (AO_OFFSET + GPIOAO_2)
-#define PIN_GPIOAO_3 (AO_OFFSET + GPIOAO_3)
-#define PIN_GPIOAO_4 (AO_OFFSET + GPIOAO_4)
-#define PIN_GPIOAO_5 (AO_OFFSET + GPIOAO_5)
-#define PIN_GPIOAO_6 (AO_OFFSET + GPIOAO_6)
-#define PIN_GPIOAO_7 (AO_OFFSET + GPIOAO_7)
-#define PIN_GPIOAO_8 (AO_OFFSET + GPIOAO_8)
-#define PIN_GPIOAO_9 (AO_OFFSET + GPIOAO_9)
-#define PIN_GPIOAO_10 (AO_OFFSET + GPIOAO_10)
-#define PIN_GPIOAO_11 (AO_OFFSET + GPIOAO_11)
-#define PIN_GPIOAO_12 (AO_OFFSET + GPIOAO_12)
-#define PIN_GPIOAO_13 (AO_OFFSET + GPIOAO_13)
-#define PIN_GPIO_BSD_EN (AO_OFFSET + GPIO_BSD_EN)
-#define PIN_GPIO_TEST_N (AO_OFFSET + GPIO_TEST_N)
+#define AO_OFF 120
static const struct pinctrl_pin_desc meson8_pins[] = {
- MESON_PIN(GPIOX_0),
- MESON_PIN(GPIOX_1),
- MESON_PIN(GPIOX_2),
- MESON_PIN(GPIOX_3),
- MESON_PIN(GPIOX_4),
- MESON_PIN(GPIOX_5),
- MESON_PIN(GPIOX_6),
- MESON_PIN(GPIOX_7),
- MESON_PIN(GPIOX_8),
- MESON_PIN(GPIOX_9),
- MESON_PIN(GPIOX_10),
- MESON_PIN(GPIOX_11),
- MESON_PIN(GPIOX_12),
- MESON_PIN(GPIOX_13),
- MESON_PIN(GPIOX_14),
- MESON_PIN(GPIOX_15),
- MESON_PIN(GPIOX_16),
- MESON_PIN(GPIOX_17),
- MESON_PIN(GPIOX_18),
- MESON_PIN(GPIOX_19),
- MESON_PIN(GPIOX_20),
- MESON_PIN(GPIOX_21),
- MESON_PIN(GPIOY_0),
- MESON_PIN(GPIOY_1),
- MESON_PIN(GPIOY_2),
- MESON_PIN(GPIOY_3),
- MESON_PIN(GPIOY_4),
- MESON_PIN(GPIOY_5),
- MESON_PIN(GPIOY_6),
- MESON_PIN(GPIOY_7),
- MESON_PIN(GPIOY_8),
- MESON_PIN(GPIOY_9),
- MESON_PIN(GPIOY_10),
- MESON_PIN(GPIOY_11),
- MESON_PIN(GPIOY_12),
- MESON_PIN(GPIOY_13),
- MESON_PIN(GPIOY_14),
- MESON_PIN(GPIOY_15),
- MESON_PIN(GPIOY_16),
- MESON_PIN(GPIODV_0),
- MESON_PIN(GPIODV_1),
- MESON_PIN(GPIODV_2),
- MESON_PIN(GPIODV_3),
- MESON_PIN(GPIODV_4),
- MESON_PIN(GPIODV_5),
- MESON_PIN(GPIODV_6),
- MESON_PIN(GPIODV_7),
- MESON_PIN(GPIODV_8),
- MESON_PIN(GPIODV_9),
- MESON_PIN(GPIODV_10),
- MESON_PIN(GPIODV_11),
- MESON_PIN(GPIODV_12),
- MESON_PIN(GPIODV_13),
- MESON_PIN(GPIODV_14),
- MESON_PIN(GPIODV_15),
- MESON_PIN(GPIODV_16),
- MESON_PIN(GPIODV_17),
- MESON_PIN(GPIODV_18),
- MESON_PIN(GPIODV_19),
- MESON_PIN(GPIODV_20),
- MESON_PIN(GPIODV_21),
- MESON_PIN(GPIODV_22),
- MESON_PIN(GPIODV_23),
- MESON_PIN(GPIODV_24),
- MESON_PIN(GPIODV_25),
- MESON_PIN(GPIODV_26),
- MESON_PIN(GPIODV_27),
- MESON_PIN(GPIODV_28),
- MESON_PIN(GPIODV_29),
- MESON_PIN(GPIOH_0),
- MESON_PIN(GPIOH_1),
- MESON_PIN(GPIOH_2),
- MESON_PIN(GPIOH_3),
- MESON_PIN(GPIOH_4),
- MESON_PIN(GPIOH_5),
- MESON_PIN(GPIOH_6),
- MESON_PIN(GPIOH_7),
- MESON_PIN(GPIOH_8),
- MESON_PIN(GPIOH_9),
- MESON_PIN(GPIOZ_0),
- MESON_PIN(GPIOZ_1),
- MESON_PIN(GPIOZ_2),
- MESON_PIN(GPIOZ_3),
- MESON_PIN(GPIOZ_4),
- MESON_PIN(GPIOZ_5),
- MESON_PIN(GPIOZ_6),
- MESON_PIN(GPIOZ_7),
- MESON_PIN(GPIOZ_8),
- MESON_PIN(GPIOZ_9),
- MESON_PIN(GPIOZ_10),
- MESON_PIN(GPIOZ_11),
- MESON_PIN(GPIOZ_12),
- MESON_PIN(GPIOZ_13),
- MESON_PIN(GPIOZ_14),
- MESON_PIN(CARD_0),
- MESON_PIN(CARD_1),
- MESON_PIN(CARD_2),
- MESON_PIN(CARD_3),
- MESON_PIN(CARD_4),
- MESON_PIN(CARD_5),
- MESON_PIN(CARD_6),
- MESON_PIN(BOOT_0),
- MESON_PIN(BOOT_1),
- MESON_PIN(BOOT_2),
- MESON_PIN(BOOT_3),
- MESON_PIN(BOOT_4),
- MESON_PIN(BOOT_5),
- MESON_PIN(BOOT_6),
- MESON_PIN(BOOT_7),
- MESON_PIN(BOOT_8),
- MESON_PIN(BOOT_9),
- MESON_PIN(BOOT_10),
- MESON_PIN(BOOT_11),
- MESON_PIN(BOOT_12),
- MESON_PIN(BOOT_13),
- MESON_PIN(BOOT_14),
- MESON_PIN(BOOT_15),
- MESON_PIN(BOOT_16),
- MESON_PIN(BOOT_17),
- MESON_PIN(BOOT_18),
- MESON_PIN(GPIOAO_0),
- MESON_PIN(GPIOAO_1),
- MESON_PIN(GPIOAO_2),
- MESON_PIN(GPIOAO_3),
- MESON_PIN(GPIOAO_4),
- MESON_PIN(GPIOAO_5),
- MESON_PIN(GPIOAO_6),
- MESON_PIN(GPIOAO_7),
- MESON_PIN(GPIOAO_8),
- MESON_PIN(GPIOAO_9),
- MESON_PIN(GPIOAO_10),
- MESON_PIN(GPIOAO_11),
- MESON_PIN(GPIOAO_12),
- MESON_PIN(GPIOAO_13),
- MESON_PIN(GPIO_BSD_EN),
- MESON_PIN(GPIO_TEST_N),
+ MESON_PIN(GPIOX_0, 0),
+ MESON_PIN(GPIOX_1, 0),
+ MESON_PIN(GPIOX_2, 0),
+ MESON_PIN(GPIOX_3, 0),
+ MESON_PIN(GPIOX_4, 0),
+ MESON_PIN(GPIOX_5, 0),
+ MESON_PIN(GPIOX_6, 0),
+ MESON_PIN(GPIOX_7, 0),
+ MESON_PIN(GPIOX_8, 0),
+ MESON_PIN(GPIOX_9, 0),
+ MESON_PIN(GPIOX_10, 0),
+ MESON_PIN(GPIOX_11, 0),
+ MESON_PIN(GPIOX_12, 0),
+ MESON_PIN(GPIOX_13, 0),
+ MESON_PIN(GPIOX_14, 0),
+ MESON_PIN(GPIOX_15, 0),
+ MESON_PIN(GPIOX_16, 0),
+ MESON_PIN(GPIOX_17, 0),
+ MESON_PIN(GPIOX_18, 0),
+ MESON_PIN(GPIOX_19, 0),
+ MESON_PIN(GPIOX_20, 0),
+ MESON_PIN(GPIOX_21, 0),
+ MESON_PIN(GPIOY_0, 0),
+ MESON_PIN(GPIOY_1, 0),
+ MESON_PIN(GPIOY_2, 0),
+ MESON_PIN(GPIOY_3, 0),
+ MESON_PIN(GPIOY_4, 0),
+ MESON_PIN(GPIOY_5, 0),
+ MESON_PIN(GPIOY_6, 0),
+ MESON_PIN(GPIOY_7, 0),
+ MESON_PIN(GPIOY_8, 0),
+ MESON_PIN(GPIOY_9, 0),
+ MESON_PIN(GPIOY_10, 0),
+ MESON_PIN(GPIOY_11, 0),
+ MESON_PIN(GPIOY_12, 0),
+ MESON_PIN(GPIOY_13, 0),
+ MESON_PIN(GPIOY_14, 0),
+ MESON_PIN(GPIOY_15, 0),
+ MESON_PIN(GPIOY_16, 0),
+ MESON_PIN(GPIODV_0, 0),
+ MESON_PIN(GPIODV_1, 0),
+ MESON_PIN(GPIODV_2, 0),
+ MESON_PIN(GPIODV_3, 0),
+ MESON_PIN(GPIODV_4, 0),
+ MESON_PIN(GPIODV_5, 0),
+ MESON_PIN(GPIODV_6, 0),
+ MESON_PIN(GPIODV_7, 0),
+ MESON_PIN(GPIODV_8, 0),
+ MESON_PIN(GPIODV_9, 0),
+ MESON_PIN(GPIODV_10, 0),
+ MESON_PIN(GPIODV_11, 0),
+ MESON_PIN(GPIODV_12, 0),
+ MESON_PIN(GPIODV_13, 0),
+ MESON_PIN(GPIODV_14, 0),
+ MESON_PIN(GPIODV_15, 0),
+ MESON_PIN(GPIODV_16, 0),
+ MESON_PIN(GPIODV_17, 0),
+ MESON_PIN(GPIODV_18, 0),
+ MESON_PIN(GPIODV_19, 0),
+ MESON_PIN(GPIODV_20, 0),
+ MESON_PIN(GPIODV_21, 0),
+ MESON_PIN(GPIODV_22, 0),
+ MESON_PIN(GPIODV_23, 0),
+ MESON_PIN(GPIODV_24, 0),
+ MESON_PIN(GPIODV_25, 0),
+ MESON_PIN(GPIODV_26, 0),
+ MESON_PIN(GPIODV_27, 0),
+ MESON_PIN(GPIODV_28, 0),
+ MESON_PIN(GPIODV_29, 0),
+ MESON_PIN(GPIOH_0, 0),
+ MESON_PIN(GPIOH_1, 0),
+ MESON_PIN(GPIOH_2, 0),
+ MESON_PIN(GPIOH_3, 0),
+ MESON_PIN(GPIOH_4, 0),
+ MESON_PIN(GPIOH_5, 0),
+ MESON_PIN(GPIOH_6, 0),
+ MESON_PIN(GPIOH_7, 0),
+ MESON_PIN(GPIOH_8, 0),
+ MESON_PIN(GPIOH_9, 0),
+ MESON_PIN(GPIOZ_0, 0),
+ MESON_PIN(GPIOZ_1, 0),
+ MESON_PIN(GPIOZ_2, 0),
+ MESON_PIN(GPIOZ_3, 0),
+ MESON_PIN(GPIOZ_4, 0),
+ MESON_PIN(GPIOZ_5, 0),
+ MESON_PIN(GPIOZ_6, 0),
+ MESON_PIN(GPIOZ_7, 0),
+ MESON_PIN(GPIOZ_8, 0),
+ MESON_PIN(GPIOZ_9, 0),
+ MESON_PIN(GPIOZ_10, 0),
+ MESON_PIN(GPIOZ_11, 0),
+ MESON_PIN(GPIOZ_12, 0),
+ MESON_PIN(GPIOZ_13, 0),
+ MESON_PIN(GPIOZ_14, 0),
+ MESON_PIN(CARD_0, 0),
+ MESON_PIN(CARD_1, 0),
+ MESON_PIN(CARD_2, 0),
+ MESON_PIN(CARD_3, 0),
+ MESON_PIN(CARD_4, 0),
+ MESON_PIN(CARD_5, 0),
+ MESON_PIN(CARD_6, 0),
+ MESON_PIN(BOOT_0, 0),
+ MESON_PIN(BOOT_1, 0),
+ MESON_PIN(BOOT_2, 0),
+ MESON_PIN(BOOT_3, 0),
+ MESON_PIN(BOOT_4, 0),
+ MESON_PIN(BOOT_5, 0),
+ MESON_PIN(BOOT_6, 0),
+ MESON_PIN(BOOT_7, 0),
+ MESON_PIN(BOOT_8, 0),
+ MESON_PIN(BOOT_9, 0),
+ MESON_PIN(BOOT_10, 0),
+ MESON_PIN(BOOT_11, 0),
+ MESON_PIN(BOOT_12, 0),
+ MESON_PIN(BOOT_13, 0),
+ MESON_PIN(BOOT_14, 0),
+ MESON_PIN(BOOT_15, 0),
+ MESON_PIN(BOOT_16, 0),
+ MESON_PIN(BOOT_17, 0),
+ MESON_PIN(BOOT_18, 0),
+ MESON_PIN(GPIOAO_0, AO_OFF),
+ MESON_PIN(GPIOAO_1, AO_OFF),
+ MESON_PIN(GPIOAO_2, AO_OFF),
+ MESON_PIN(GPIOAO_3, AO_OFF),
+ MESON_PIN(GPIOAO_4, AO_OFF),
+ MESON_PIN(GPIOAO_5, AO_OFF),
+ MESON_PIN(GPIOAO_6, AO_OFF),
+ MESON_PIN(GPIOAO_7, AO_OFF),
+ MESON_PIN(GPIOAO_8, AO_OFF),
+ MESON_PIN(GPIOAO_9, AO_OFF),
+ MESON_PIN(GPIOAO_10, AO_OFF),
+ MESON_PIN(GPIOAO_11, AO_OFF),
+ MESON_PIN(GPIOAO_12, AO_OFF),
+ MESON_PIN(GPIOAO_13, AO_OFF),
+ MESON_PIN(GPIO_BSD_EN, AO_OFF),
+ MESON_PIN(GPIO_TEST_N, AO_OFF),
};
/* bank X */
-static const unsigned int sd_d0_a_pins[] = { PIN_GPIOX_0 };
-static const unsigned int sd_d1_a_pins[] = { PIN_GPIOX_1 };
-static const unsigned int sd_d2_a_pins[] = { PIN_GPIOX_2 };
-static const unsigned int sd_d3_a_pins[] = { PIN_GPIOX_3 };
-static const unsigned int sd_clk_a_pins[] = { PIN_GPIOX_8 };
-static const unsigned int sd_cmd_a_pins[] = { PIN_GPIOX_9 };
-
-static const unsigned int sdxc_d0_a_pins[] = { PIN_GPIOX_0 };
-static const unsigned int sdxc_d13_a_pins[] = { PIN_GPIOX_1, PIN_GPIOX_2,
- PIN_GPIOX_3 };
-static const unsigned int sdxc_d47_a_pins[] = { PIN_GPIOX_4, PIN_GPIOX_5,
- PIN_GPIOX_6, PIN_GPIOX_7 };
-static const unsigned int sdxc_clk_a_pins[] = { PIN_GPIOX_8 };
-static const unsigned int sdxc_cmd_a_pins[] = { PIN_GPIOX_9 };
-
-static const unsigned int pcm_out_a_pins[] = { PIN_GPIOX_4 };
-static const unsigned int pcm_in_a_pins[] = { PIN_GPIOX_5 };
-static const unsigned int pcm_fs_a_pins[] = { PIN_GPIOX_6 };
-static const unsigned int pcm_clk_a_pins[] = { PIN_GPIOX_7 };
-
-static const unsigned int uart_tx_a0_pins[] = { PIN_GPIOX_4 };
-static const unsigned int uart_rx_a0_pins[] = { PIN_GPIOX_5 };
-static const unsigned int uart_cts_a0_pins[] = { PIN_GPIOX_6 };
-static const unsigned int uart_rts_a0_pins[] = { PIN_GPIOX_7 };
-
-static const unsigned int uart_tx_a1_pins[] = { PIN_GPIOX_12 };
-static const unsigned int uart_rx_a1_pins[] = { PIN_GPIOX_13 };
-static const unsigned int uart_cts_a1_pins[] = { PIN_GPIOX_14 };
-static const unsigned int uart_rts_a1_pins[] = { PIN_GPIOX_15 };
-
-static const unsigned int uart_tx_b0_pins[] = { PIN_GPIOX_16 };
-static const unsigned int uart_rx_b0_pins[] = { PIN_GPIOX_17 };
-static const unsigned int uart_cts_b0_pins[] = { PIN_GPIOX_18 };
-static const unsigned int uart_rts_b0_pins[] = { PIN_GPIOX_19 };
-
-static const unsigned int iso7816_det_pins[] = { PIN_GPIOX_16 };
-static const unsigned int iso7816_reset_pins[] = { PIN_GPIOX_17 };
-static const unsigned int iso7816_clk_pins[] = { PIN_GPIOX_18 };
-static const unsigned int iso7816_data_pins[] = { PIN_GPIOX_19 };
-
-static const unsigned int i2c_sda_d0_pins[] = { PIN_GPIOX_16 };
-static const unsigned int i2c_sck_d0_pins[] = { PIN_GPIOX_17 };
-
-static const unsigned int xtal_32k_out_pins[] = { PIN_GPIOX_10 };
-static const unsigned int xtal_24m_out_pins[] = { PIN_GPIOX_11 };
+static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
+static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
+static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
+static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
+static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
+static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
+
+static const unsigned int sdxc_d0_a_pins[] = { PIN(GPIOX_0, 0) };
+static const unsigned int sdxc_d13_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),
+ PIN(GPIOX_3, 0) };
+static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
+ PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };
+static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) };
+static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
+
+static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) };
+static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) };
+static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) };
+static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) };
+
+static const unsigned int uart_tx_a0_pins[] = { PIN(GPIOX_4, 0) };
+static const unsigned int uart_rx_a0_pins[] = { PIN(GPIOX_5, 0) };
+static const unsigned int uart_cts_a0_pins[] = { PIN(GPIOX_6, 0) };
+static const unsigned int uart_rts_a0_pins[] = { PIN(GPIOX_7, 0) };
+
+static const unsigned int uart_tx_a1_pins[] = { PIN(GPIOX_12, 0) };
+static const unsigned int uart_rx_a1_pins[] = { PIN(GPIOX_13, 0) };
+static const unsigned int uart_cts_a1_pins[] = { PIN(GPIOX_14, 0) };
+static const unsigned int uart_rts_a1_pins[] = { PIN(GPIOX_15, 0) };
+
+static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) };
+static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) };
+static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) };
+static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) };
+
+static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) };
+static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) };
+static const unsigned int iso7816_clk_pins[] = { PIN(GPIOX_18, 0) };
+static const unsigned int iso7816_data_pins[] = { PIN(GPIOX_19, 0) };
+
+static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) };
+static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) };
+
+static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) };
+static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) };
/* bank Y */
-static const unsigned int uart_tx_c_pins[] = { PIN_GPIOY_0 };
-static const unsigned int uart_rx_c_pins[] = { PIN_GPIOY_1 };
-static const unsigned int uart_cts_c_pins[] = { PIN_GPIOY_2 };
-static const unsigned int uart_rts_c_pins[] = { PIN_GPIOY_3 };
+static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) };
+static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) };
+static const unsigned int uart_cts_c_pins[] = { PIN(GPIOY_2, 0) };
+static const unsigned int uart_rts_c_pins[] = { PIN(GPIOY_3, 0) };
-static const unsigned int pcm_out_b_pins[] = { PIN_GPIOY_4 };
-static const unsigned int pcm_in_b_pins[] = { PIN_GPIOY_5 };
-static const unsigned int pcm_fs_b_pins[] = { PIN_GPIOY_6 };
-static const unsigned int pcm_clk_b_pins[] = { PIN_GPIOY_7 };
+static const unsigned int pcm_out_b_pins[] = { PIN(GPIOY_4, 0) };
+static const unsigned int pcm_in_b_pins[] = { PIN(GPIOY_5, 0) };
+static const unsigned int pcm_fs_b_pins[] = { PIN(GPIOY_6, 0) };
+static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) };
-static const unsigned int i2c_sda_c0_pins[] = { PIN_GPIOY_0 };
-static const unsigned int i2c_sck_c0_pins[] = { PIN_GPIOY_1 };
+static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) };
+static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) };
/* bank DV */
-static const unsigned int dvin_rgb_pins[] = { PIN_GPIODV_0, PIN_GPIODV_1,
- PIN_GPIODV_2, PIN_GPIODV_3,
- PIN_GPIODV_4, PIN_GPIODV_5,
- PIN_GPIODV_6, PIN_GPIODV_7,
- PIN_GPIODV_8, PIN_GPIODV_9,
- PIN_GPIODV_10, PIN_GPIODV_11,
- PIN_GPIODV_12, PIN_GPIODV_13,
- PIN_GPIODV_14, PIN_GPIODV_15,
- PIN_GPIODV_16, PIN_GPIODV_17,
- PIN_GPIODV_18, PIN_GPIODV_19,
- PIN_GPIODV_20, PIN_GPIODV_21,
- PIN_GPIODV_22, PIN_GPIODV_23 };
-static const unsigned int dvin_vs_pins[] = { PIN_GPIODV_24 };
-static const unsigned int dvin_hs_pins[] = { PIN_GPIODV_25 };
-static const unsigned int dvin_clk_pins[] = { PIN_GPIODV_26 };
-static const unsigned int dvin_de_pins[] = { PIN_GPIODV_27 };
-
-static const unsigned int enc_0_pins[] = { PIN_GPIODV_0 };
-static const unsigned int enc_1_pins[] = { PIN_GPIODV_1 };
-static const unsigned int enc_2_pins[] = { PIN_GPIODV_2 };
-static const unsigned int enc_3_pins[] = { PIN_GPIODV_3 };
-static const unsigned int enc_4_pins[] = { PIN_GPIODV_4 };
-static const unsigned int enc_5_pins[] = { PIN_GPIODV_5 };
-static const unsigned int enc_6_pins[] = { PIN_GPIODV_6 };
-static const unsigned int enc_7_pins[] = { PIN_GPIODV_7 };
-static const unsigned int enc_8_pins[] = { PIN_GPIODV_8 };
-static const unsigned int enc_9_pins[] = { PIN_GPIODV_9 };
-static const unsigned int enc_10_pins[] = { PIN_GPIODV_10 };
-static const unsigned int enc_11_pins[] = { PIN_GPIODV_11 };
-static const unsigned int enc_12_pins[] = { PIN_GPIODV_12 };
-static const unsigned int enc_13_pins[] = { PIN_GPIODV_13 };
-static const unsigned int enc_14_pins[] = { PIN_GPIODV_14 };
-static const unsigned int enc_15_pins[] = { PIN_GPIODV_15 };
-static const unsigned int enc_16_pins[] = { PIN_GPIODV_16 };
-static const unsigned int enc_17_pins[] = { PIN_GPIODV_17 };
-
-static const unsigned int uart_tx_b1_pins[] = { PIN_GPIODV_24 };
-static const unsigned int uart_rx_b1_pins[] = { PIN_GPIODV_25 };
-static const unsigned int uart_cts_b1_pins[] = { PIN_GPIODV_26 };
-static const unsigned int uart_rts_b1_pins[] = { PIN_GPIODV_27 };
-
-static const unsigned int vga_vs_pins[] = { PIN_GPIODV_24 };
-static const unsigned int vga_hs_pins[] = { PIN_GPIODV_25 };
+static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0),
+ PIN(GPIODV_2, 0), PIN(GPIODV_3, 0),
+ PIN(GPIODV_4, 0), PIN(GPIODV_5, 0),
+ PIN(GPIODV_6, 0), PIN(GPIODV_7, 0),
+ PIN(GPIODV_8, 0), PIN(GPIODV_9, 0),
+ PIN(GPIODV_10, 0), PIN(GPIODV_11, 0),
+ PIN(GPIODV_12, 0), PIN(GPIODV_13, 0),
+ PIN(GPIODV_14, 0), PIN(GPIODV_15, 0),
+ PIN(GPIODV_16, 0), PIN(GPIODV_17, 0),
+ PIN(GPIODV_18, 0), PIN(GPIODV_19, 0),
+ PIN(GPIODV_20, 0), PIN(GPIODV_21, 0),
+ PIN(GPIODV_22, 0), PIN(GPIODV_23, 0) };
+static const unsigned int dvin_vs_pins[] = { PIN(GPIODV_24, 0) };
+static const unsigned int dvin_hs_pins[] = { PIN(GPIODV_25, 0) };
+static const unsigned int dvin_clk_pins[] = { PIN(GPIODV_26, 0) };
+static const unsigned int dvin_de_pins[] = { PIN(GPIODV_27, 0) };
+
+static const unsigned int enc_0_pins[] = { PIN(GPIODV_0, 0) };
+static const unsigned int enc_1_pins[] = { PIN(GPIODV_1, 0) };
+static const unsigned int enc_2_pins[] = { PIN(GPIODV_2, 0) };
+static const unsigned int enc_3_pins[] = { PIN(GPIODV_3, 0) };
+static const unsigned int enc_4_pins[] = { PIN(GPIODV_4, 0) };
+static const unsigned int enc_5_pins[] = { PIN(GPIODV_5, 0) };
+static const unsigned int enc_6_pins[] = { PIN(GPIODV_6, 0) };
+static const unsigned int enc_7_pins[] = { PIN(GPIODV_7, 0) };
+static const unsigned int enc_8_pins[] = { PIN(GPIODV_8, 0) };
+static const unsigned int enc_9_pins[] = { PIN(GPIODV_9, 0) };
+static const unsigned int enc_10_pins[] = { PIN(GPIODV_10, 0) };
+static const unsigned int enc_11_pins[] = { PIN(GPIODV_11, 0) };
+static const unsigned int enc_12_pins[] = { PIN(GPIODV_12, 0) };
+static const unsigned int enc_13_pins[] = { PIN(GPIODV_13, 0) };
+static const unsigned int enc_14_pins[] = { PIN(GPIODV_14, 0) };
+static const unsigned int enc_15_pins[] = { PIN(GPIODV_15, 0) };
+static const unsigned int enc_16_pins[] = { PIN(GPIODV_16, 0) };
+static const unsigned int enc_17_pins[] = { PIN(GPIODV_17, 0) };
+
+static const unsigned int uart_tx_b1_pins[] = { PIN(GPIODV_24, 0) };
+static const unsigned int uart_rx_b1_pins[] = { PIN(GPIODV_25, 0) };
+static const unsigned int uart_cts_b1_pins[] = { PIN(GPIODV_26, 0) };
+static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) };
+
+static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) };
+static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) };
/* bank H */
-static const unsigned int hdmi_hpd_pins[] = { PIN_GPIOH_0 };
-static const unsigned int hdmi_sda_pins[] = { PIN_GPIOH_1 };
-static const unsigned int hdmi_scl_pins[] = { PIN_GPIOH_2 };
-static const unsigned int hdmi_cec_pins[] = { PIN_GPIOH_3 };
+static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) };
+static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) };
+static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) };
+static const unsigned int hdmi_cec_pins[] = { PIN(GPIOH_3, 0) };
-static const unsigned int spi_ss0_0_pins[] = { PIN_GPIOH_3 };
-static const unsigned int spi_miso_0_pins[] = { PIN_GPIOH_4 };
-static const unsigned int spi_mosi_0_pins[] = { PIN_GPIOH_5 };
-static const unsigned int spi_sclk_0_pins[] = { PIN_GPIOH_6 };
+static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOH_3, 0) };
+static const unsigned int spi_miso_0_pins[] = { PIN(GPIOH_4, 0) };
+static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOH_5, 0) };
+static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOH_6, 0) };
-static const unsigned int i2c_sda_d1_pins[] = { PIN_GPIOH_7 };
-static const unsigned int i2c_sck_d1_pins[] = { PIN_GPIOH_8 };
+static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) };
+static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) };
/* bank Z */
-static const unsigned int spi_ss0_1_pins[] = { PIN_GPIOZ_9 };
-static const unsigned int spi_ss1_1_pins[] = { PIN_GPIOZ_10 };
-static const unsigned int spi_sclk_1_pins[] = { PIN_GPIOZ_11 };
-static const unsigned int spi_mosi_1_pins[] = { PIN_GPIOZ_12 };
-static const unsigned int spi_miso_1_pins[] = { PIN_GPIOZ_13 };
-static const unsigned int spi_ss2_1_pins[] = { PIN_GPIOZ_14 };
-
-static const unsigned int eth_tx_clk_50m_pins[] = { PIN_GPIOZ_4 };
-static const unsigned int eth_tx_en_pins[] = { PIN_GPIOZ_5 };
-static const unsigned int eth_txd1_pins[] = { PIN_GPIOZ_6 };
-static const unsigned int eth_txd0_pins[] = { PIN_GPIOZ_7 };
-static const unsigned int eth_rx_clk_in_pins[] = { PIN_GPIOZ_8 };
-static const unsigned int eth_rx_dv_pins[] = { PIN_GPIOZ_9 };
-static const unsigned int eth_rxd1_pins[] = { PIN_GPIOZ_10 };
-static const unsigned int eth_rxd0_pins[] = { PIN_GPIOZ_11 };
-static const unsigned int eth_mdio_pins[] = { PIN_GPIOZ_12 };
-static const unsigned int eth_mdc_pins[] = { PIN_GPIOZ_13 };
-
-static const unsigned int i2c_sda_a0_pins[] = { PIN_GPIOZ_0 };
-static const unsigned int i2c_sck_a0_pins[] = { PIN_GPIOZ_1 };
-
-static const unsigned int i2c_sda_b_pins[] = { PIN_GPIOZ_2 };
-static const unsigned int i2c_sck_b_pins[] = { PIN_GPIOZ_3 };
-
-static const unsigned int i2c_sda_c1_pins[] = { PIN_GPIOZ_4 };
-static const unsigned int i2c_sck_c1_pins[] = { PIN_GPIOZ_5 };
-
-static const unsigned int i2c_sda_a1_pins[] = { PIN_GPIOZ_0 };
-static const unsigned int i2c_sck_a1_pins[] = { PIN_GPIOZ_1 };
-
-static const unsigned int i2c_sda_a2_pins[] = { PIN_GPIOZ_0 };
-static const unsigned int i2c_sck_a2_pins[] = { PIN_GPIOZ_1 };
+static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOZ_9, 0) };
+static const unsigned int spi_ss1_1_pins[] = { PIN(GPIOZ_10, 0) };
+static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOZ_11, 0) };
+static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOZ_12, 0) };
+static const unsigned int spi_miso_1_pins[] = { PIN(GPIOZ_13, 0) };
+static const unsigned int spi_ss2_1_pins[] = { PIN(GPIOZ_14, 0) };
+
+static const unsigned int eth_tx_clk_50m_pins[] = { PIN(GPIOZ_4, 0) };
+static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_5, 0) };
+static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_6, 0) };
+static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_7, 0) };
+static const unsigned int eth_rx_clk_in_pins[] = { PIN(GPIOZ_8, 0) };
+static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_9, 0) };
+static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_10, 0) };
+static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_11, 0) };
+static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_12, 0) };
+static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_13, 0) };
+
+static const unsigned int i2c_sda_a0_pins[] = { PIN(GPIOZ_0, 0) };
+static const unsigned int i2c_sck_a0_pins[] = { PIN(GPIOZ_1, 0) };
+
+static const unsigned int i2c_sda_b_pins[] = { PIN(GPIOZ_2, 0) };
+static const unsigned int i2c_sck_b_pins[] = { PIN(GPIOZ_3, 0) };
+
+static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOZ_4, 0) };
+static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOZ_5, 0) };
+
+static const unsigned int i2c_sda_a1_pins[] = { PIN(GPIOZ_0, 0) };
+static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) };
+
+static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) };
+static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) };
/* bank BOOT */
-static const unsigned int sd_d0_c_pins[] = { PIN_BOOT_0 };
-static const unsigned int sd_d1_c_pins[] = { PIN_BOOT_1 };
-static const unsigned int sd_d2_c_pins[] = { PIN_BOOT_2 };
-static const unsigned int sd_d3_c_pins[] = { PIN_BOOT_3 };
-static const unsigned int sd_cmd_c_pins[] = { PIN_BOOT_16 };
-static const unsigned int sd_clk_c_pins[] = { PIN_BOOT_17 };
-
-static const unsigned int sdxc_d0_c_pins[] = { PIN_BOOT_0};
-static const unsigned int sdxc_d13_c_pins[] = { PIN_BOOT_1, PIN_BOOT_2,
- PIN_BOOT_3 };
-static const unsigned int sdxc_d47_c_pins[] = { PIN_BOOT_4, PIN_BOOT_5,
- PIN_BOOT_6, PIN_BOOT_7 };
-static const unsigned int sdxc_cmd_c_pins[] = { PIN_BOOT_16 };
-static const unsigned int sdxc_clk_c_pins[] = { PIN_BOOT_17 };
-
-static const unsigned int nand_io_pins[] = { PIN_BOOT_0, PIN_BOOT_1,
- PIN_BOOT_2, PIN_BOOT_3,
- PIN_BOOT_4, PIN_BOOT_5,
- PIN_BOOT_6, PIN_BOOT_7 };
-static const unsigned int nand_io_ce0_pins[] = { PIN_BOOT_8 };
-static const unsigned int nand_io_ce1_pins[] = { PIN_BOOT_9 };
-static const unsigned int nand_io_rb0_pins[] = { PIN_BOOT_10 };
-static const unsigned int nand_ale_pins[] = { PIN_BOOT_11 };
-static const unsigned int nand_cle_pins[] = { PIN_BOOT_12 };
-static const unsigned int nand_wen_clk_pins[] = { PIN_BOOT_13 };
-static const unsigned int nand_ren_clk_pins[] = { PIN_BOOT_14 };
-static const unsigned int nand_dqs_pins[] = { PIN_BOOT_15 };
-static const unsigned int nand_ce2_pins[] = { PIN_BOOT_16 };
-static const unsigned int nand_ce3_pins[] = { PIN_BOOT_17 };
-
-static const unsigned int nor_d_pins[] = { PIN_BOOT_11 };
-static const unsigned int nor_q_pins[] = { PIN_BOOT_12 };
-static const unsigned int nor_c_pins[] = { PIN_BOOT_13 };
-static const unsigned int nor_cs_pins[] = { PIN_BOOT_18 };
+static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) };
+static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) };
+static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) };
+static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) };
+static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_16, 0) };
+static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_17, 0) };
+
+static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)};
+static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0),
+ PIN(BOOT_3, 0) };
+static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0),
+ PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
+static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_16, 0) };
+static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_17, 0) };
+
+static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0),
+ PIN(BOOT_2, 0), PIN(BOOT_3, 0),
+ PIN(BOOT_4, 0), PIN(BOOT_5, 0),
+ PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
+static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) };
+static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) };
+static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) };
+static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) };
+static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) };
+static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) };
+static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) };
+static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, 0) };
+static const unsigned int nand_ce2_pins[] = { PIN(BOOT_16, 0) };
+static const unsigned int nand_ce3_pins[] = { PIN(BOOT_17, 0) };
+
+static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) };
+static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) };
+static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) };
+static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) };
/* bank CARD */
-static const unsigned int sd_d1_b_pins[] = { PIN_CARD_0 };
-static const unsigned int sd_d0_b_pins[] = { PIN_CARD_1 };
-static const unsigned int sd_clk_b_pins[] = { PIN_CARD_2 };
-static const unsigned int sd_cmd_b_pins[] = { PIN_CARD_3 };
-static const unsigned int sd_d3_b_pins[] = { PIN_CARD_4 };
-static const unsigned int sd_d2_b_pins[] = { PIN_CARD_5 };
-
-static const unsigned int sdxc_d13_b_pins[] = { PIN_CARD_0, PIN_CARD_4,
- PIN_CARD_5 };
-static const unsigned int sdxc_d0_b_pins[] = { PIN_CARD_1 };
-static const unsigned int sdxc_clk_b_pins[] = { PIN_CARD_2 };
-static const unsigned int sdxc_cmd_b_pins[] = { PIN_CARD_3 };
+static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) };
+static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) };
+static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) };
+static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) };
+static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) };
+static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) };
+
+static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0),
+ PIN(CARD_5, 0) };
+static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) };
+static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) };
+static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) };
/* bank AO */
-static const unsigned int uart_tx_ao_a_pins[] = { PIN_GPIOAO_0 };
-static const unsigned int uart_rx_ao_a_pins[] = { PIN_GPIOAO_1 };
-static const unsigned int uart_cts_ao_a_pins[] = { PIN_GPIOAO_2 };
-static const unsigned int uart_rts_ao_a_pins[] = { PIN_GPIOAO_3 };
+static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) };
+static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) };
+static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) };
+static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) };
-static const unsigned int remote_input_pins[] = { PIN_GPIOAO_7 };
+static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) };
-static const unsigned int i2c_slave_sck_ao_pins[] = { PIN_GPIOAO_4 };
-static const unsigned int i2c_slave_sda_ao_pins[] = { PIN_GPIOAO_5 };
+static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
+static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
-static const unsigned int uart_tx_ao_b0_pins[] = { PIN_GPIOAO_0 };
-static const unsigned int uart_rx_ao_b0_pins[] = { PIN_GPIOAO_1 };
+static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) };
+static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) };
-static const unsigned int uart_tx_ao_b1_pins[] = { PIN_GPIOAO_4 };
-static const unsigned int uart_rx_ao_b1_pins[] = { PIN_GPIOAO_5 };
+static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) };
+static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
-static const unsigned int i2c_mst_sck_ao_pins[] = { PIN_GPIOAO_4 };
-static const unsigned int i2c_mst_sda_ao_pins[] = { PIN_GPIOAO_5 };
+static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
+static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
static struct meson_pmx_group meson8_groups[] = {
- GPIO_GROUP(GPIOX_0),
- GPIO_GROUP(GPIOX_1),
- GPIO_GROUP(GPIOX_2),
- GPIO_GROUP(GPIOX_3),
- GPIO_GROUP(GPIOX_4),
- GPIO_GROUP(GPIOX_5),
- GPIO_GROUP(GPIOX_6),
- GPIO_GROUP(GPIOX_7),
- GPIO_GROUP(GPIOX_8),
- GPIO_GROUP(GPIOX_9),
- GPIO_GROUP(GPIOX_10),
- GPIO_GROUP(GPIOX_11),
- GPIO_GROUP(GPIOX_12),
- GPIO_GROUP(GPIOX_13),
- GPIO_GROUP(GPIOX_14),
- GPIO_GROUP(GPIOX_15),
- GPIO_GROUP(GPIOX_16),
- GPIO_GROUP(GPIOX_17),
- GPIO_GROUP(GPIOX_18),
- GPIO_GROUP(GPIOX_19),
- GPIO_GROUP(GPIOX_20),
- GPIO_GROUP(GPIOX_21),
- GPIO_GROUP(GPIOY_0),
- GPIO_GROUP(GPIOY_1),
- GPIO_GROUP(GPIOY_2),
- GPIO_GROUP(GPIOY_3),
- GPIO_GROUP(GPIOY_4),
- GPIO_GROUP(GPIOY_5),
- GPIO_GROUP(GPIOY_6),
- GPIO_GROUP(GPIOY_7),
- GPIO_GROUP(GPIOY_8),
- GPIO_GROUP(GPIOY_9),
- GPIO_GROUP(GPIOY_10),
- GPIO_GROUP(GPIOY_11),
- GPIO_GROUP(GPIOY_12),
- GPIO_GROUP(GPIOY_13),
- GPIO_GROUP(GPIOY_14),
- GPIO_GROUP(GPIOY_15),
- GPIO_GROUP(GPIOY_16),
- GPIO_GROUP(GPIODV_0),
- GPIO_GROUP(GPIODV_1),
- GPIO_GROUP(GPIODV_2),
- GPIO_GROUP(GPIODV_3),
- GPIO_GROUP(GPIODV_4),
- GPIO_GROUP(GPIODV_5),
- GPIO_GROUP(GPIODV_6),
- GPIO_GROUP(GPIODV_7),
- GPIO_GROUP(GPIODV_8),
- GPIO_GROUP(GPIODV_9),
- GPIO_GROUP(GPIODV_10),
- GPIO_GROUP(GPIODV_11),
- GPIO_GROUP(GPIODV_12),
- GPIO_GROUP(GPIODV_13),
- GPIO_GROUP(GPIODV_14),
- GPIO_GROUP(GPIODV_15),
- GPIO_GROUP(GPIODV_16),
- GPIO_GROUP(GPIODV_17),
- GPIO_GROUP(GPIODV_18),
- GPIO_GROUP(GPIODV_19),
- GPIO_GROUP(GPIODV_20),
- GPIO_GROUP(GPIODV_21),
- GPIO_GROUP(GPIODV_22),
- GPIO_GROUP(GPIODV_23),
- GPIO_GROUP(GPIODV_24),
- GPIO_GROUP(GPIODV_25),
- GPIO_GROUP(GPIODV_26),
- GPIO_GROUP(GPIODV_27),
- GPIO_GROUP(GPIODV_28),
- GPIO_GROUP(GPIODV_29),
- GPIO_GROUP(GPIOH_0),
- GPIO_GROUP(GPIOH_1),
- GPIO_GROUP(GPIOH_2),
- GPIO_GROUP(GPIOH_3),
- GPIO_GROUP(GPIOH_4),
- GPIO_GROUP(GPIOH_5),
- GPIO_GROUP(GPIOH_6),
- GPIO_GROUP(GPIOH_7),
- GPIO_GROUP(GPIOH_8),
- GPIO_GROUP(GPIOH_9),
- GPIO_GROUP(GPIOZ_0),
- GPIO_GROUP(GPIOZ_1),
- GPIO_GROUP(GPIOZ_2),
- GPIO_GROUP(GPIOZ_3),
- GPIO_GROUP(GPIOZ_4),
- GPIO_GROUP(GPIOZ_5),
- GPIO_GROUP(GPIOZ_6),
- GPIO_GROUP(GPIOZ_7),
- GPIO_GROUP(GPIOZ_8),
- GPIO_GROUP(GPIOZ_9),
- GPIO_GROUP(GPIOZ_10),
- GPIO_GROUP(GPIOZ_11),
- GPIO_GROUP(GPIOZ_12),
- GPIO_GROUP(GPIOZ_13),
- GPIO_GROUP(GPIOZ_14),
- GPIO_GROUP(GPIOAO_0),
- GPIO_GROUP(GPIOAO_1),
- GPIO_GROUP(GPIOAO_2),
- GPIO_GROUP(GPIOAO_3),
- GPIO_GROUP(GPIOAO_4),
- GPIO_GROUP(GPIOAO_5),
- GPIO_GROUP(GPIOAO_6),
- GPIO_GROUP(GPIOAO_7),
- GPIO_GROUP(GPIOAO_8),
- GPIO_GROUP(GPIOAO_9),
- GPIO_GROUP(GPIOAO_10),
- GPIO_GROUP(GPIOAO_11),
- GPIO_GROUP(GPIOAO_12),
- GPIO_GROUP(GPIOAO_13),
- GPIO_GROUP(GPIO_BSD_EN),
- GPIO_GROUP(GPIO_TEST_N),
+ GPIO_GROUP(GPIOX_0, 0),
+ GPIO_GROUP(GPIOX_1, 0),
+ GPIO_GROUP(GPIOX_2, 0),
+ GPIO_GROUP(GPIOX_3, 0),
+ GPIO_GROUP(GPIOX_4, 0),
+ GPIO_GROUP(GPIOX_5, 0),
+ GPIO_GROUP(GPIOX_6, 0),
+ GPIO_GROUP(GPIOX_7, 0),
+ GPIO_GROUP(GPIOX_8, 0),
+ GPIO_GROUP(GPIOX_9, 0),
+ GPIO_GROUP(GPIOX_10, 0),
+ GPIO_GROUP(GPIOX_11, 0),
+ GPIO_GROUP(GPIOX_12, 0),
+ GPIO_GROUP(GPIOX_13, 0),
+ GPIO_GROUP(GPIOX_14, 0),
+ GPIO_GROUP(GPIOX_15, 0),
+ GPIO_GROUP(GPIOX_16, 0),
+ GPIO_GROUP(GPIOX_17, 0),
+ GPIO_GROUP(GPIOX_18, 0),
+ GPIO_GROUP(GPIOX_19, 0),
+ GPIO_GROUP(GPIOX_20, 0),
+ GPIO_GROUP(GPIOX_21, 0),
+ GPIO_GROUP(GPIOY_0, 0),
+ GPIO_GROUP(GPIOY_1, 0),
+ GPIO_GROUP(GPIOY_2, 0),
+ GPIO_GROUP(GPIOY_3, 0),
+ GPIO_GROUP(GPIOY_4, 0),
+ GPIO_GROUP(GPIOY_5, 0),
+ GPIO_GROUP(GPIOY_6, 0),
+ GPIO_GROUP(GPIOY_7, 0),
+ GPIO_GROUP(GPIOY_8, 0),
+ GPIO_GROUP(GPIOY_9, 0),
+ GPIO_GROUP(GPIOY_10, 0),
+ GPIO_GROUP(GPIOY_11, 0),
+ GPIO_GROUP(GPIOY_12, 0),
+ GPIO_GROUP(GPIOY_13, 0),
+ GPIO_GROUP(GPIOY_14, 0),
+ GPIO_GROUP(GPIOY_15, 0),
+ GPIO_GROUP(GPIOY_16, 0),
+ GPIO_GROUP(GPIODV_0, 0),
+ GPIO_GROUP(GPIODV_1, 0),
+ GPIO_GROUP(GPIODV_2, 0),
+ GPIO_GROUP(GPIODV_3, 0),
+ GPIO_GROUP(GPIODV_4, 0),
+ GPIO_GROUP(GPIODV_5, 0),
+ GPIO_GROUP(GPIODV_6, 0),
+ GPIO_GROUP(GPIODV_7, 0),
+ GPIO_GROUP(GPIODV_8, 0),
+ GPIO_GROUP(GPIODV_9, 0),
+ GPIO_GROUP(GPIODV_10, 0),
+ GPIO_GROUP(GPIODV_11, 0),
+ GPIO_GROUP(GPIODV_12, 0),
+ GPIO_GROUP(GPIODV_13, 0),
+ GPIO_GROUP(GPIODV_14, 0),
+ GPIO_GROUP(GPIODV_15, 0),
+ GPIO_GROUP(GPIODV_16, 0),
+ GPIO_GROUP(GPIODV_17, 0),
+ GPIO_GROUP(GPIODV_18, 0),
+ GPIO_GROUP(GPIODV_19, 0),
+ GPIO_GROUP(GPIODV_20, 0),
+ GPIO_GROUP(GPIODV_21, 0),
+ GPIO_GROUP(GPIODV_22, 0),
+ GPIO_GROUP(GPIODV_23, 0),
+ GPIO_GROUP(GPIODV_24, 0),
+ GPIO_GROUP(GPIODV_25, 0),
+ GPIO_GROUP(GPIODV_26, 0),
+ GPIO_GROUP(GPIODV_27, 0),
+ GPIO_GROUP(GPIODV_28, 0),
+ GPIO_GROUP(GPIODV_29, 0),
+ GPIO_GROUP(GPIOH_0, 0),
+ GPIO_GROUP(GPIOH_1, 0),
+ GPIO_GROUP(GPIOH_2, 0),
+ GPIO_GROUP(GPIOH_3, 0),
+ GPIO_GROUP(GPIOH_4, 0),
+ GPIO_GROUP(GPIOH_5, 0),
+ GPIO_GROUP(GPIOH_6, 0),
+ GPIO_GROUP(GPIOH_7, 0),
+ GPIO_GROUP(GPIOH_8, 0),
+ GPIO_GROUP(GPIOH_9, 0),
+ GPIO_GROUP(GPIOZ_0, 0),
+ GPIO_GROUP(GPIOZ_1, 0),
+ GPIO_GROUP(GPIOZ_2, 0),
+ GPIO_GROUP(GPIOZ_3, 0),
+ GPIO_GROUP(GPIOZ_4, 0),
+ GPIO_GROUP(GPIOZ_5, 0),
+ GPIO_GROUP(GPIOZ_6, 0),
+ GPIO_GROUP(GPIOZ_7, 0),
+ GPIO_GROUP(GPIOZ_8, 0),
+ GPIO_GROUP(GPIOZ_9, 0),
+ GPIO_GROUP(GPIOZ_10, 0),
+ GPIO_GROUP(GPIOZ_11, 0),
+ GPIO_GROUP(GPIOZ_12, 0),
+ GPIO_GROUP(GPIOZ_13, 0),
+ GPIO_GROUP(GPIOZ_14, 0),
+ GPIO_GROUP(GPIOAO_0, AO_OFF),
+ GPIO_GROUP(GPIOAO_1, AO_OFF),
+ GPIO_GROUP(GPIOAO_2, AO_OFF),
+ GPIO_GROUP(GPIOAO_3, AO_OFF),
+ GPIO_GROUP(GPIOAO_4, AO_OFF),
+ GPIO_GROUP(GPIOAO_5, AO_OFF),
+ GPIO_GROUP(GPIOAO_6, AO_OFF),
+ GPIO_GROUP(GPIOAO_7, AO_OFF),
+ GPIO_GROUP(GPIOAO_8, AO_OFF),
+ GPIO_GROUP(GPIOAO_9, AO_OFF),
+ GPIO_GROUP(GPIOAO_10, AO_OFF),
+ GPIO_GROUP(GPIOAO_11, AO_OFF),
+ GPIO_GROUP(GPIOAO_12, AO_OFF),
+ GPIO_GROUP(GPIOAO_13, AO_OFF),
+ GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
+ GPIO_GROUP(GPIO_TEST_N, AO_OFF),
/* bank X */
GROUP(sd_d0_a, 8, 5),
@@ -1045,19 +907,19 @@ static struct meson_pmx_func meson8_functions[] = {
};
static struct meson_bank meson8_banks[] = {
- /* name first last pullen pull dir out in */
- BANK("X", PIN_GPIOX_0, PIN_GPIOX_21, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
- BANK("Y", PIN_GPIOY_0, PIN_GPIOY_16, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
- BANK("DV", PIN_GPIODV_0, PIN_GPIODV_29, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
- BANK("H", PIN_GPIOH_0, PIN_GPIOH_9, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
- BANK("Z", PIN_GPIOZ_0, PIN_GPIOZ_14, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
- BANK("CARD", PIN_CARD_0, PIN_CARD_6, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
- BANK("BOOT", PIN_BOOT_0, PIN_BOOT_18, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
+ /* name first last pullen pull dir out in */
+ BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
+ BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
+ BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
+ BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
+ BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
+ BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
+ BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
};
static struct meson_bank meson8_ao_banks[] = {
- /* name first last pullen pull dir out in */
- BANK("AO", PIN_GPIOAO_0, PIN_GPIO_TEST_N, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
+ /* name first last pullen pull dir out in */
+ BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
};
static struct meson_domain_data meson8_domain_data[] = {
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 2/3] documentation: Extend pinctrl docs for Meson8b
2015-03-19 21:34 [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support Carlo Caione
2015-03-19 21:34 ` [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver Carlo Caione
@ 2015-03-19 21:34 ` Carlo Caione
2015-03-28 9:49 ` Beniamino Galvani
2015-04-07 9:43 ` Linus Walleij
2015-03-19 21:34 ` [PATCH v3 3/3] pinctrl: Add support " Carlo Caione
2015-03-27 9:02 ` [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support Linus Walleij
3 siblings, 2 replies; 11+ messages in thread
From: Carlo Caione @ 2015-03-19 21:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Carlo Caione <carlo@endlessm.com>
Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
---
Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 +-
drivers/pinctrl/meson/pinctrl-meson.c | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
index 17e7240..3f6a524 100644
--- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt
@@ -1,7 +1,7 @@
== Amlogic Meson pinmux controller ==
Required properties for the root node:
- - compatible: "amlogic,meson8-pinctrl"
+ - compatible: "amlogic,meson8-pinctrl" or "amlogic,meson8b-pinctrl"
- reg: address and size of registers controlling irq functionality
=== GPIO sub-nodes ===
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index a2bf49c..e0195c1 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -13,8 +13,9 @@
/*
* The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
- * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and
- * each bank has a variable number of pins.
+ * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
+ * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
+ * variable number of pins.
*
* The AO bank is special because it belongs to the Always-On power
* domain which can't be powered off; the bank also uses a set of
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 3/3] pinctrl: Add support for Meson8b
2015-03-19 21:34 [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support Carlo Caione
2015-03-19 21:34 ` [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver Carlo Caione
2015-03-19 21:34 ` [PATCH v3 2/3] documentation: Extend pinctrl docs for Meson8b Carlo Caione
@ 2015-03-19 21:34 ` Carlo Caione
2015-03-28 10:06 ` Beniamino Galvani
2015-03-27 9:02 ` [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support Linus Walleij
3 siblings, 1 reply; 11+ messages in thread
From: Carlo Caione @ 2015-03-19 21:34 UTC (permalink / raw)
To: linux-arm-kernel
From: Carlo Caione <carlo@endlessm.com>
This patch adds support for the AmLogic Meson8b SoC.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
---
drivers/pinctrl/meson/Makefile | 2 +-
drivers/pinctrl/meson/pinctrl-meson.c | 4 +
drivers/pinctrl/meson/pinctrl-meson.h | 1 +
drivers/pinctrl/meson/pinctrl-meson8b.c | 900 ++++++++++++++++++++++++++++++++
include/dt-bindings/gpio/meson8b-gpio.h | 32 ++
5 files changed, 938 insertions(+), 1 deletion(-)
create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c
create mode 100644 include/dt-bindings/gpio/meson8b-gpio.h
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index eafc216..c751d22 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -1,2 +1,2 @@
-obj-y += pinctrl-meson8.o
+obj-y += pinctrl-meson8.o pinctrl-meson8b.o
obj-y += pinctrl-meson.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index e0195c1..edcd140 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -545,6 +545,10 @@ static const struct of_device_id meson_pinctrl_dt_match[] = {
.compatible = "amlogic,meson8-pinctrl",
.data = &meson8_pinctrl_data,
},
+ {
+ .compatible = "amlogic,meson8b-pinctrl",
+ .data = &meson8b_pinctrl_data,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index bc48c78..0fe7d53 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -209,3 +209,4 @@ struct meson_pinctrl {
#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
extern struct meson_pinctrl_data meson8_pinctrl_data;
+extern struct meson_pinctrl_data meson8b_pinctrl_data;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c
new file mode 100644
index 0000000..b37b3a2
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
@@ -0,0 +1,900 @@
+/*
+ * Pin controller and GPIO driver for Amlogic Meson8b.
+ *
+ * Copyright (C) 2015 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <dt-bindings/gpio/meson8b-gpio.h>
+#include "pinctrl-meson.h"
+
+#define AO_OFF 120
+#define DIF_OFF 135
+
+static const struct pinctrl_pin_desc meson8b_pins[] = {
+ MESON_PIN(GPIOX_0, 0),
+ MESON_PIN(GPIOX_1, 0),
+ MESON_PIN(GPIOX_2, 0),
+ MESON_PIN(GPIOX_3, 0),
+ MESON_PIN(GPIOX_4, 0),
+ MESON_PIN(GPIOX_5, 0),
+ MESON_PIN(GPIOX_6, 0),
+ MESON_PIN(GPIOX_7, 0),
+ MESON_PIN(GPIOX_8, 0),
+ MESON_PIN(GPIOX_9, 0),
+ MESON_PIN(GPIOX_10, 0),
+ MESON_PIN(GPIOX_11, 0),
+ MESON_PIN(GPIOX_16, 0),
+ MESON_PIN(GPIOX_17, 0),
+ MESON_PIN(GPIOX_18, 0),
+ MESON_PIN(GPIOX_19, 0),
+ MESON_PIN(GPIOX_20, 0),
+ MESON_PIN(GPIOX_21, 0),
+
+ MESON_PIN(GPIOY_0, 0),
+ MESON_PIN(GPIOY_1, 0),
+ MESON_PIN(GPIOY_3, 0),
+ MESON_PIN(GPIOY_6, 0),
+ MESON_PIN(GPIOY_7, 0),
+ MESON_PIN(GPIOY_8, 0),
+ MESON_PIN(GPIOY_9, 0),
+ MESON_PIN(GPIOY_10, 0),
+ MESON_PIN(GPIOY_11, 0),
+ MESON_PIN(GPIOY_12, 0),
+ MESON_PIN(GPIOY_13, 0),
+ MESON_PIN(GPIOY_14, 0),
+
+ MESON_PIN(GPIODV_9, 0),
+ MESON_PIN(GPIODV_24, 0),
+ MESON_PIN(GPIODV_25, 0),
+ MESON_PIN(GPIODV_26, 0),
+ MESON_PIN(GPIODV_27, 0),
+ MESON_PIN(GPIODV_28, 0),
+ MESON_PIN(GPIODV_29, 0),
+
+ MESON_PIN(GPIOH_0, 0),
+ MESON_PIN(GPIOH_1, 0),
+ MESON_PIN(GPIOH_2, 0),
+ MESON_PIN(GPIOH_3, 0),
+ MESON_PIN(GPIOH_4, 0),
+ MESON_PIN(GPIOH_5, 0),
+ MESON_PIN(GPIOH_6, 0),
+ MESON_PIN(GPIOH_7, 0),
+ MESON_PIN(GPIOH_8, 0),
+ MESON_PIN(GPIOH_9, 0),
+
+ MESON_PIN(CARD_0, 0),
+ MESON_PIN(CARD_1, 0),
+ MESON_PIN(CARD_2, 0),
+ MESON_PIN(CARD_3, 0),
+ MESON_PIN(CARD_4, 0),
+ MESON_PIN(CARD_5, 0),
+ MESON_PIN(CARD_6, 0),
+
+ MESON_PIN(BOOT_0, 0),
+ MESON_PIN(BOOT_1, 0),
+ MESON_PIN(BOOT_2, 0),
+ MESON_PIN(BOOT_3, 0),
+ MESON_PIN(BOOT_4, 0),
+ MESON_PIN(BOOT_5, 0),
+ MESON_PIN(BOOT_6, 0),
+ MESON_PIN(BOOT_7, 0),
+ MESON_PIN(BOOT_8, 0),
+ MESON_PIN(BOOT_9, 0),
+ MESON_PIN(BOOT_10, 0),
+ MESON_PIN(BOOT_11, 0),
+ MESON_PIN(BOOT_12, 0),
+ MESON_PIN(BOOT_13, 0),
+ MESON_PIN(BOOT_14, 0),
+ MESON_PIN(BOOT_15, 0),
+ MESON_PIN(BOOT_16, 0),
+ MESON_PIN(BOOT_17, 0),
+ MESON_PIN(BOOT_18, 0),
+
+ MESON_PIN(GPIOAO_0, AO_OFF),
+ MESON_PIN(GPIOAO_1, AO_OFF),
+ MESON_PIN(GPIOAO_2, AO_OFF),
+ MESON_PIN(GPIOAO_3, AO_OFF),
+ MESON_PIN(GPIOAO_4, AO_OFF),
+ MESON_PIN(GPIOAO_5, AO_OFF),
+ MESON_PIN(GPIOAO_6, AO_OFF),
+ MESON_PIN(GPIOAO_7, AO_OFF),
+ MESON_PIN(GPIOAO_8, AO_OFF),
+ MESON_PIN(GPIOAO_9, AO_OFF),
+ MESON_PIN(GPIOAO_10, AO_OFF),
+ MESON_PIN(GPIOAO_11, AO_OFF),
+ MESON_PIN(GPIOAO_12, AO_OFF),
+ MESON_PIN(GPIOAO_13, AO_OFF),
+ MESON_PIN(GPIO_BSD_EN, AO_OFF),
+ MESON_PIN(GPIO_TEST_N, AO_OFF),
+
+ MESON_PIN(DIF_0_P, DIF_OFF),
+ MESON_PIN(DIF_0_N, DIF_OFF),
+ MESON_PIN(DIF_1_P, DIF_OFF),
+ MESON_PIN(DIF_1_N, DIF_OFF),
+ MESON_PIN(DIF_2_P, DIF_OFF),
+ MESON_PIN(DIF_2_N, DIF_OFF),
+ MESON_PIN(DIF_3_P, DIF_OFF),
+ MESON_PIN(DIF_3_N, DIF_OFF),
+ MESON_PIN(DIF_4_P, DIF_OFF),
+ MESON_PIN(DIF_4_N, DIF_OFF),
+};
+
+/* bank X */
+static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
+static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
+static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
+static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
+static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) };
+static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
+ PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };
+static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), PIN(GPIOX_6, 0),
+ PIN(GPIOX_7, 0) };
+static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
+static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
+static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) };
+static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) };
+static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) };
+static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) };
+static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) };
+static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) };
+
+static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, 0) };
+static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),
+ PIN(GPIOX_3, 0) };
+static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) };
+static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) };
+static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) };
+static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) };
+static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) };
+static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
+static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, 0) };
+static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) };
+static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, 0) };
+
+static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, 0) };
+static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, 0) };
+static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, 0) };
+static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, 0) };
+static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, 0) };
+static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, 0) };
+static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, 0) };
+static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, 0) };
+
+static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, 0) };
+static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, 0) };
+static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, 0) };
+static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, 0) };
+static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, 0) };
+static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) };
+static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) };
+static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, 0) };
+static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, 0) };
+static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, 0) };
+
+static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, 0) };
+static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, 0) };
+static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, 0) };
+static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, 0) };
+static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) };
+static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) };
+static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) };
+
+/* bank Y */
+static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) };
+static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, 0) };
+static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, 0), PIN(GPIOY_7, 0),
+ PIN(GPIOY_10, 0), PIN(GPIOY_11, 0),
+ PIN(GPIOY_12, 0), PIN(GPIOY_13, 0),
+ PIN(GPIOY_14, 0) };
+static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, 0) };
+static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, 0) };
+
+static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, 0) };
+
+static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, 0) };
+static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, 0) };
+static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) };
+
+/* bank DV */
+static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) };
+static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, 0) };
+
+static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, 0) };
+static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, 0) };
+static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, 0) };
+
+static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, 0) };
+
+static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, 0) };
+static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, 0) };
+static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, 0) };
+static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, 0) };
+
+static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, 0) };
+
+static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, 0) };
+static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, 0) };
+static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, 0) };
+static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, 0) };
+static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, 0) };
+static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, 0) };
+
+/* bank H */
+static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) };
+static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) };
+static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) };
+static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, 0) };
+static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, 0) };
+static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, 0) };
+static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, 0) };
+
+static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, 0) };
+static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, 0) };
+static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, 0) };
+static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, 0) };
+static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, 0) };
+static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, 0) };
+
+static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, 0) };
+static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, 0) };
+static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, 0) };
+
+static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, 0) };
+static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, 0) };
+static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, 0) };
+static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, 0) };
+static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) };
+static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) };
+
+/* bank BOOT */
+static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0),
+ PIN(BOOT_2, 0), PIN(BOOT_3, 0),
+ PIN(BOOT_4, 0), PIN(BOOT_5, 0),
+ PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
+static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) };
+static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) };
+static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) };
+static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) };
+static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) };
+static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) };
+static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) };
+static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, 0) };
+static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, 0) };
+
+static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)};
+static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0),
+ PIN(BOOT_3, 0) };
+static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0),
+ PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
+static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, 0) };
+static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, 0) };
+static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) };
+static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) };
+static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) };
+static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) };
+
+static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) };
+static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) };
+static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) };
+static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) };
+static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, 0) };
+static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, 0) };
+
+/* bank CARD */
+static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) };
+static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) };
+static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) };
+static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) };
+static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) };
+static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) };
+
+static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0),
+ PIN(CARD_5, 0) };
+static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) };
+static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) };
+static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) };
+
+/* bank AO */
+static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) };
+static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) };
+static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) };
+static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) };
+static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
+static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
+static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, AO_OFF) };
+static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) };
+static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, AO_OFF) };
+static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, AO_OFF) };
+
+static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, AO_OFF) };
+static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
+static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
+static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, AO_OFF) };
+static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, AO_OFF) };
+static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, AO_OFF) };
+static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, AO_OFF) };
+static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, AO_OFF) };
+
+static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) };
+static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) };
+static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, AO_OFF) };
+static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, AO_OFF) };
+static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) };
+static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
+static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, AO_OFF) };
+
+static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, AO_OFF) };
+static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, AO_OFF) };
+static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, AO_OFF) };
+
+/* bank DIF */
+static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, DIF_OFF) };
+static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, DIF_OFF) };
+static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, DIF_OFF) };
+static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, DIF_OFF) };
+static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, DIF_OFF) };
+static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, DIF_OFF) };
+static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, DIF_OFF) };
+static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, DIF_OFF) };
+static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, DIF_OFF) };
+static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, DIF_OFF) };
+
+static struct meson_pmx_group meson8b_groups[] = {
+ GPIO_GROUP(GPIOX_0, 0),
+ GPIO_GROUP(GPIOX_1, 0),
+ GPIO_GROUP(GPIOX_2, 0),
+ GPIO_GROUP(GPIOX_3, 0),
+ GPIO_GROUP(GPIOX_4, 0),
+ GPIO_GROUP(GPIOX_5, 0),
+ GPIO_GROUP(GPIOX_6, 0),
+ GPIO_GROUP(GPIOX_7, 0),
+ GPIO_GROUP(GPIOX_8, 0),
+ GPIO_GROUP(GPIOX_9, 0),
+ GPIO_GROUP(GPIOX_10, 0),
+ GPIO_GROUP(GPIOX_11, 0),
+ GPIO_GROUP(GPIOX_16, 0),
+ GPIO_GROUP(GPIOX_17, 0),
+ GPIO_GROUP(GPIOX_18, 0),
+ GPIO_GROUP(GPIOX_19, 0),
+ GPIO_GROUP(GPIOX_20, 0),
+ GPIO_GROUP(GPIOX_21, 0),
+
+ GPIO_GROUP(GPIOY_0, 0),
+ GPIO_GROUP(GPIOY_1, 0),
+ GPIO_GROUP(GPIOY_3, 0),
+ GPIO_GROUP(GPIOY_6, 0),
+ GPIO_GROUP(GPIOY_7, 0),
+ GPIO_GROUP(GPIOY_8, 0),
+ GPIO_GROUP(GPIOY_9, 0),
+ GPIO_GROUP(GPIOY_10, 0),
+ GPIO_GROUP(GPIOY_11, 0),
+ GPIO_GROUP(GPIOY_12, 0),
+ GPIO_GROUP(GPIOY_13, 0),
+ GPIO_GROUP(GPIOY_14, 0),
+
+ GPIO_GROUP(GPIODV_9, 0),
+ GPIO_GROUP(GPIODV_24, 0),
+ GPIO_GROUP(GPIODV_25, 0),
+ GPIO_GROUP(GPIODV_26, 0),
+ GPIO_GROUP(GPIODV_27, 0),
+ GPIO_GROUP(GPIODV_28, 0),
+ GPIO_GROUP(GPIODV_29, 0),
+
+ GPIO_GROUP(GPIOH_0, 0),
+ GPIO_GROUP(GPIOH_1, 0),
+ GPIO_GROUP(GPIOH_2, 0),
+ GPIO_GROUP(GPIOH_3, 0),
+ GPIO_GROUP(GPIOH_4, 0),
+ GPIO_GROUP(GPIOH_5, 0),
+ GPIO_GROUP(GPIOH_6, 0),
+ GPIO_GROUP(GPIOH_7, 0),
+ GPIO_GROUP(GPIOH_8, 0),
+ GPIO_GROUP(GPIOH_9, 0),
+
+ GPIO_GROUP(GPIOAO_0, AO_OFF),
+ GPIO_GROUP(GPIOAO_1, AO_OFF),
+ GPIO_GROUP(GPIOAO_2, AO_OFF),
+ GPIO_GROUP(GPIOAO_3, AO_OFF),
+ GPIO_GROUP(GPIOAO_4, AO_OFF),
+ GPIO_GROUP(GPIOAO_5, AO_OFF),
+ GPIO_GROUP(GPIOAO_6, AO_OFF),
+ GPIO_GROUP(GPIOAO_7, AO_OFF),
+ GPIO_GROUP(GPIOAO_8, AO_OFF),
+ GPIO_GROUP(GPIOAO_9, AO_OFF),
+ GPIO_GROUP(GPIOAO_10, AO_OFF),
+ GPIO_GROUP(GPIOAO_11, AO_OFF),
+ GPIO_GROUP(GPIOAO_12, AO_OFF),
+ GPIO_GROUP(GPIOAO_13, AO_OFF),
+ GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
+ GPIO_GROUP(GPIO_TEST_N, AO_OFF),
+
+ GPIO_GROUP(DIF_0_P, DIF_OFF),
+ GPIO_GROUP(DIF_0_N, DIF_OFF),
+ GPIO_GROUP(DIF_1_P, DIF_OFF),
+ GPIO_GROUP(DIF_1_N, DIF_OFF),
+ GPIO_GROUP(DIF_2_P, DIF_OFF),
+ GPIO_GROUP(DIF_2_N, DIF_OFF),
+ GPIO_GROUP(DIF_3_P, DIF_OFF),
+ GPIO_GROUP(DIF_3_N, DIF_OFF),
+ GPIO_GROUP(DIF_4_P, DIF_OFF),
+ GPIO_GROUP(DIF_4_N, DIF_OFF),
+
+ /* bank X */
+ GROUP(sd_d0_a, 8, 5),
+ GROUP(sd_d1_a, 8, 4),
+ GROUP(sd_d2_a, 8, 3),
+ GROUP(sd_d3_a, 8, 2),
+ GROUP(sdxc_d0_0_a, 5, 29),
+ GROUP(sdxc_d47_a, 5, 12),
+ GROUP(sdxc_d13_0_a, 5, 28),
+ GROUP(sd_clk_a, 8, 1),
+ GROUP(sd_cmd_a, 8, 0),
+ GROUP(xtal_32k_out, 3, 22),
+ GROUP(xtal_24m_out, 3, 20),
+ GROUP(uart_tx_b0, 4, 9),
+ GROUP(uart_rx_b0, 4, 8),
+ GROUP(uart_cts_b0, 4, 7),
+ GROUP(uart_rts_b0, 4, 6),
+ GROUP(sdxc_d0_1_a, 5, 14),
+ GROUP(sdxc_d13_1_a, 5, 13),
+ GROUP(pcm_out_a, 3, 30),
+ GROUP(pcm_in_a, 3, 29),
+ GROUP(pcm_fs_a, 3, 28),
+ GROUP(pcm_clk_a, 3, 27),
+ GROUP(sdxc_clk_a, 5, 11),
+ GROUP(sdxc_cmd_a, 5, 10),
+ GROUP(pwm_vs_0, 7, 31),
+ GROUP(pwm_e, 9, 19),
+ GROUP(pwm_vs_1, 7, 30),
+ GROUP(uart_tx_a, 4, 17),
+ GROUP(uart_rx_a, 4, 16),
+ GROUP(uart_cts_a, 4, 15),
+ GROUP(uart_rts_a, 4, 14),
+ GROUP(uart_tx_b1, 6, 19),
+ GROUP(uart_rx_b1, 6, 18),
+ GROUP(uart_cts_b1, 6, 17),
+ GROUP(uart_rts_b1, 6, 16),
+ GROUP(iso7816_0_clk, 5, 9),
+ GROUP(iso7816_0_data, 5, 8),
+ GROUP(spi_sclk_0, 4, 22),
+ GROUP(spi_miso_0, 4, 24),
+ GROUP(spi_mosi_0, 4, 23),
+ GROUP(iso7816_det, 4, 21),
+ GROUP(iso7816_reset, 4, 20),
+ GROUP(iso7816_1_clk, 4, 19),
+ GROUP(iso7816_1_data, 4, 18),
+ GROUP(spi_ss0_0, 4, 25),
+ GROUP(tsin_clk_b, 3, 6),
+ GROUP(tsin_sop_b, 3, 7),
+ GROUP(tsin_d0_b, 3, 8),
+ GROUP(pwm_b, 2, 3),
+ GROUP(i2c_sda_d0, 4, 5),
+ GROUP(i2c_sck_d0, 4, 4),
+ GROUP(tsin_d_valid_b, 3, 9),
+
+ /* bank Y */
+ GROUP(tsin_d_valid_a, 3, 2),
+ GROUP(tsin_sop_a, 3, 1),
+ GROUP(tsin_d17_a, 3, 5),
+ GROUP(tsin_clk_a, 3, 0),
+ GROUP(tsin_d0_a, 3, 4),
+ GROUP(spdif_out_0, 1, 7),
+ GROUP(xtal_24m, 3, 18),
+ GROUP(iso7816_2_clk, 5, 7),
+ GROUP(iso7816_2_data, 5, 6),
+
+ /* bank DV */
+ GROUP(pwm_d, 3, 26),
+ GROUP(pwm_c0, 3, 25),
+ GROUP(pwm_vs_2, 7, 28),
+ GROUP(pwm_vs_3, 7, 27),
+ GROUP(pwm_vs_4, 7, 26),
+ GROUP(xtal24_out, 7, 25),
+ GROUP(uart_tx_c, 6, 23),
+ GROUP(uart_rx_c, 6, 22),
+ GROUP(uart_cts_c, 6, 21),
+ GROUP(uart_rts_c, 6, 20),
+ GROUP(pwm_c1, 3, 24),
+ GROUP(i2c_sda_a, 9, 31),
+ GROUP(i2c_sck_a, 9, 30),
+ GROUP(i2c_sda_b0, 9, 29),
+ GROUP(i2c_sck_b0, 9, 28),
+ GROUP(i2c_sda_c0, 9, 27),
+ GROUP(i2c_sck_c0, 9, 26),
+
+ /* bank H */
+ GROUP(hdmi_hpd, 1, 26),
+ GROUP(hdmi_sda, 1, 25),
+ GROUP(hdmi_scl, 1, 24),
+ GROUP(hdmi_cec_0, 1, 23),
+ GROUP(eth_txd1_0, 7, 21),
+ GROUP(eth_txd0_0, 7, 20),
+ GROUP(clk_24m_out, 4, 1),
+ GROUP(spi_ss1, 8, 11),
+ GROUP(spi_ss2, 8, 12),
+ GROUP(spi_ss0_1, 9, 13),
+ GROUP(spi_miso_1, 9, 12),
+ GROUP(spi_mosi_1, 9, 11),
+ GROUP(spi_sclk_1, 9, 10),
+ GROUP(eth_txd3, 6, 13),
+ GROUP(eth_txd2, 6, 12),
+ GROUP(eth_tx_clk, 6, 11),
+ GROUP(i2c_sda_b1, 5, 27),
+ GROUP(i2c_sck_b1, 5, 26),
+ GROUP(i2c_sda_c1, 5, 25),
+ GROUP(i2c_sck_c1, 5, 24),
+ GROUP(i2c_sda_d1, 4, 3),
+ GROUP(i2c_sck_d1, 4, 2),
+
+ /* bank BOOT */
+ GROUP(nand_io, 2, 26),
+ GROUP(nand_io_ce0, 2, 25),
+ GROUP(nand_io_ce1, 2, 24),
+ GROUP(nand_io_rb0, 2, 17),
+ GROUP(nand_ale, 2, 21),
+ GROUP(nand_cle, 2, 20),
+ GROUP(nand_wen_clk, 2, 19),
+ GROUP(nand_ren_clk, 2, 18),
+ GROUP(nand_dqs_0, 2, 27),
+ GROUP(nand_dqs_1, 2, 28),
+ GROUP(sdxc_d0_c, 4, 30),
+ GROUP(sdxc_d13_c, 4, 29),
+ GROUP(sdxc_d47_c, 4, 28),
+ GROUP(sdxc_clk_c, 7, 19),
+ GROUP(sdxc_cmd_c, 7, 18),
+ GROUP(nor_d, 5, 1),
+ GROUP(nor_q, 5, 3),
+ GROUP(nor_c, 5, 2),
+ GROUP(nor_cs, 5, 0),
+ GROUP(sd_d0_c, 6, 29),
+ GROUP(sd_d1_c, 6, 28),
+ GROUP(sd_d2_c, 6, 27),
+ GROUP(sd_d3_c, 6, 26),
+ GROUP(sd_cmd_c, 6, 30),
+ GROUP(sd_clk_c, 6, 31),
+
+ /* bank CARD */
+ GROUP(sd_d1_b, 2, 14),
+ GROUP(sd_d0_b, 2, 15),
+ GROUP(sd_clk_b, 2, 11),
+ GROUP(sd_cmd_b, 2, 10),
+ GROUP(sd_d3_b, 2, 12),
+ GROUP(sd_d2_b, 2, 13),
+ GROUP(sdxc_d13_b, 2, 6),
+ GROUP(sdxc_d0_b, 2, 7),
+ GROUP(sdxc_clk_b, 2, 5),
+ GROUP(sdxc_cmd_b, 2, 4),
+
+ /* bank AO */
+ GROUP(uart_tx_ao_a, 0, 12),
+ GROUP(uart_rx_ao_a, 0, 11),
+ GROUP(uart_cts_ao_a, 0, 10),
+ GROUP(uart_rts_ao_a, 0, 9),
+ GROUP(i2c_mst_sck_ao, 0, 6),
+ GROUP(i2c_mst_sda_ao, 0, 5),
+ GROUP(clk_32k_in_out, 0, 18),
+ GROUP(remote_input, 0, 0),
+ GROUP(hdmi_cec_1, 0, 17),
+ GROUP(ir_blaster, 0, 31),
+ GROUP(pwm_c2, 0, 22),
+ GROUP(i2c_sck_ao, 0, 2),
+ GROUP(i2c_sda_ao, 0, 1),
+ GROUP(ir_remote_out, 0, 21),
+ GROUP(i2s_am_clk_out, 0, 30),
+ GROUP(i2s_ao_clk_out, 0, 29),
+ GROUP(i2s_lr_clk_out, 0, 28),
+ GROUP(i2s_out_01, 0, 27),
+ GROUP(uart_tx_ao_b0, 0, 26),
+ GROUP(uart_rx_ao_b0, 0, 25),
+ GROUP(uart_cts_ao_b, 0, 8),
+ GROUP(uart_rts_ao_b, 0, 7),
+ GROUP(uart_tx_ao_b1, 0, 24),
+ GROUP(uart_rx_ao_b1, 0, 23),
+ GROUP(spdif_out_1, 0, 16),
+ GROUP(i2s_in_ch01, 0, 13),
+ GROUP(i2s_ao_clk_in, 0, 15),
+ GROUP(i2s_lr_clk_in, 0, 14),
+
+ /* bank DIF */
+ GROUP(eth_rxd1, 6, 0),
+ GROUP(eth_rxd0, 6, 1),
+ GROUP(eth_rx_dv, 6, 2),
+ GROUP(eth_rx_clk, 6, 3),
+ GROUP(eth_txd0_1, 6, 4),
+ GROUP(eth_txd1_1, 6, 5),
+ GROUP(eth_tx_en, 6, 0),
+ GROUP(eth_ref_clk, 6, 8),
+ GROUP(eth_mdc, 6, 9),
+ GROUP(eth_mdio_en, 6, 10),
+};
+
+static const char * const gpio_groups[] = {
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18",
+ "GPIOX_19", "GPIOX_20", "GPIOX_21",
+
+ "GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7",
+ "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12",
+ "GPIOY_13", "GPIOY_14",
+
+ "GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26",
+ "GPIODV_27", "GPIODV_28", "GPIODV_29",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
+ "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
+
+ "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
+ "CARD_5", "CARD_6",
+
+ "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
+ "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
+ "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
+ "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
+
+ "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
+ "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
+ "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
+ "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N",
+
+ "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N",
+ "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N",
+ "DIF_4_P", "DIF_4_N"
+};
+
+static const char * const sd_a_groups[] = {
+ "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a",
+ "sd_cmd_a"
+};
+
+static const char * const sdxc_a_groups[] = {
+ "sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a",
+ "sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d0_13_1_a"
+};
+
+static const char * const pcm_a_groups[] = {
+ "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a"
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
+ "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
+};
+
+static const char * const iso7816_groups[] = {
+ "iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data",
+ "iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data"
+};
+
+static const char * const i2c_d_groups[] = {
+ "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
+};
+
+static const char * const xtal_groups[] = {
+ "xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out"
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
+};
+
+static const char * const i2c_c_groups[] = {
+ "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
+};
+
+static const char * const hdmi_groups[] = {
+ "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0",
+ "hdmi_cec_1"
+};
+
+static const char * const spi_groups[] = {
+ "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
+ "spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1",
+ "spi_miso_1", "spi_ss2"
+};
+
+static const char * const ethernet_groups[] = {
+ "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",
+ "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",
+ "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",
+ "eth_txd2", "eth_txd3"
+};
+
+static const char * const i2c_a_groups[] = {
+ "i2c_sda_a", "i2c_sck_a",
+};
+
+static const char * const i2c_b_groups[] = {
+ "i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1"
+};
+
+static const char * const sd_c_groups[] = {
+ "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
+ "sd_cmd_c", "sd_clk_c"
+};
+
+static const char * const sdxc_c_groups[] = {
+ "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
+ "sdxc_clk_c"
+};
+
+static const char * const nand_groups[] = {
+ "nand_io", "nand_io_ce0", "nand_io_ce1",
+ "nand_io_rb0", "nand_ale", "nand_cle",
+ "nand_wen_clk", "nand_ren_clk", "nand_dqs0",
+ "nand_dqs1"
+};
+
+static const char * const nor_groups[] = {
+ "nor_d", "nor_q", "nor_c", "nor_cs"
+};
+
+static const char * const sd_b_groups[] = {
+ "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
+ "sd_d3_b", "sd_d2_b"
+};
+
+static const char * const sdxc_b_groups[] = {
+ "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
+};
+
+static const char * const uart_ao_groups[] = {
+ "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
+};
+
+static const char * const remote_groups[] = {
+ "remote_input", "ir_blaster", "ir_remote_out"
+};
+
+static const char * const i2c_slave_ao_groups[] = {
+ "i2c_sck_ao", "i2c_sda_ao"
+};
+
+static const char * const uart_ao_b_groups[] = {
+ "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1",
+ "uart_cts_ao_b", "uart_rts_ao_b"
+};
+
+static const char * const i2c_mst_ao_groups[] = {
+ "i2c_mst_sck_ao", "i2c_mst_sda_ao"
+};
+
+static const char * const clk_groups[] = {
+ "clk_24m_out", "clk_32k_in_out"
+};
+
+static const char * const spdif_groups[] = {
+ "spdif_out_1", "spdif_out_0"
+};
+
+static const char * const i2s_groups[] = {
+ "i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out",
+ "i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in",
+ "i2s_lr_clk_in"
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b"
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c0", "pwm_c1", "pwm_c2"
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d"
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e"
+};
+
+static const char * const pwm_vs_groups[] = {
+ "pwm_vs_0", "pwm_vs_1", "pwm_vs_2",
+ "pwm_vs_3", "pwm_vs_4"
+};
+
+static const char * const tsin_a_groups[] = {
+ "tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a",
+ "tsin_d_valid_a"
+};
+
+static const char * const tsin_b_groups[] = {
+ "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
+};
+
+static struct meson_pmx_func meson8b_functions[] = {
+ FUNCTION(gpio),
+ FUNCTION(sd_a),
+ FUNCTION(sdxc_a),
+ FUNCTION(pcm_a),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(iso7816),
+ FUNCTION(i2c_d),
+ FUNCTION(xtal),
+ FUNCTION(uart_c),
+ FUNCTION(i2c_c),
+ FUNCTION(hdmi),
+ FUNCTION(spi),
+ FUNCTION(ethernet),
+ FUNCTION(i2c_a),
+ FUNCTION(i2c_b),
+ FUNCTION(sd_c),
+ FUNCTION(sdxc_c),
+ FUNCTION(nand),
+ FUNCTION(nor),
+ FUNCTION(sd_b),
+ FUNCTION(sdxc_b),
+ FUNCTION(uart_ao),
+ FUNCTION(remote),
+ FUNCTION(i2c_slave_ao),
+ FUNCTION(uart_ao_b),
+ FUNCTION(i2c_mst_ao),
+ FUNCTION(clk),
+ FUNCTION(spdif),
+ FUNCTION(i2s),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_vs),
+ FUNCTION(tsin_a),
+ FUNCTION(tsin_b),
+};
+
+static struct meson_bank meson8b_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
+ BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
+ BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
+ BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
+ BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
+ BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
+ BANK("DIF", PIN(DIF_0_P, DIF_OFF), PIN(DIF_4_N, DIF_OFF), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
+};
+
+static struct meson_bank meson8b_ao_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
+};
+
+static struct meson_domain_data meson8b_domain_data[] = {
+ {
+ .name = "banks",
+ .banks = meson8b_banks,
+ .num_banks = ARRAY_SIZE(meson8b_banks),
+ .pin_base = 0,
+ .num_pins = 83,
+ },
+ {
+ .name = "ao-bank",
+ .banks = meson8b_ao_banks,
+ .num_banks = ARRAY_SIZE(meson8b_ao_banks),
+ .pin_base = 83,
+ .num_pins = 16,
+ },
+};
+
+struct meson_pinctrl_data meson8b_pinctrl_data = {
+ .pins = meson8b_pins,
+ .groups = meson8b_groups,
+ .funcs = meson8b_functions,
+ .domain_data = meson8b_domain_data,
+ .num_pins = ARRAY_SIZE(meson8b_pins),
+ .num_groups = ARRAY_SIZE(meson8b_groups),
+ .num_funcs = ARRAY_SIZE(meson8b_functions),
+ .num_domains = ARRAY_SIZE(meson8b_domain_data),
+};
diff --git a/include/dt-bindings/gpio/meson8b-gpio.h b/include/dt-bindings/gpio/meson8b-gpio.h
new file mode 100644
index 0000000..8e02a05
--- /dev/null
+++ b/include/dt-bindings/gpio/meson8b-gpio.h
@@ -0,0 +1,32 @@
+/*
+ * GPIO definitions for Amlogic Meson8b SoCs
+ *
+ * Copyright (C) 2015 Endless Mobile, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _DT_BINDINGS_MESON8B_GPIO_H
+#define _DT_BINDINGS_MESON8B_GPIO_H
+
+#include <dt-bindings/gpio/meson8-gpio.h>
+
+/* GPIO Bank DIF */
+#define DIF_0_P 0
+#define DIF_0_N 1
+#define DIF_1_P 2
+#define DIF_1_N 3
+#define DIF_2_P 4
+#define DIF_2_N 5
+#define DIF_3_P 6
+#define DIF_3_N 7
+#define DIF_4_P 8
+#define DIF_4_N 9
+
+#endif /* _DT_BINDINGS_MESON8B_GPIO_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support
2015-03-19 21:34 [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support Carlo Caione
` (2 preceding siblings ...)
2015-03-19 21:34 ` [PATCH v3 3/3] pinctrl: Add support " Carlo Caione
@ 2015-03-27 9:02 ` Linus Walleij
3 siblings, 0 replies; 11+ messages in thread
From: Linus Walleij @ 2015-03-27 9:02 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 19, 2015 at 10:34 PM, Carlo Caione <carlo@caione.org> wrote:
> From: Carlo Caione <carlo@endlessm.com>
>
> This patchset extends the pinctrl driver to support AmLogic Meson8b.
> The driver for Meson8 has been revised to make it shorter.
>
> Changelog:
>
> v3: * shorten the meson8/meson8b support files
> * document GPIO banks for meson8b
> v2: * fix holes in GPIOs numbering
> v1: * initial version
Beniamino, can you look at this patch set? I want your ACK
before applying.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver
2015-03-19 21:34 ` [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver Carlo Caione
@ 2015-03-28 9:47 ` Beniamino Galvani
2015-04-07 9:42 ` Linus Walleij
1 sibling, 0 replies; 11+ messages in thread
From: Beniamino Galvani @ 2015-03-28 9:47 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 19, 2015 at 10:34:10PM +0100, Carlo Caione wrote:
> From: Carlo Caione <carlo@endlessm.com>
>
> This patch introduces a new PIN macro and few small modifications to
> simplify and shorten the Meson pinctrl drivers and cleanup the support
> file for the AmLogic Meson8 SoC.
Hi Carlo,
nice cleanup.
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/3] documentation: Extend pinctrl docs for Meson8b
2015-03-19 21:34 ` [PATCH v3 2/3] documentation: Extend pinctrl docs for Meson8b Carlo Caione
@ 2015-03-28 9:49 ` Beniamino Galvani
2015-04-07 9:43 ` Linus Walleij
1 sibling, 0 replies; 11+ messages in thread
From: Beniamino Galvani @ 2015-03-28 9:49 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 19, 2015 at 10:34:11PM +0100, Carlo Caione wrote:
> From: Carlo Caione <carlo@endlessm.com>
>
> Add the compatible string for Meson8b in Meson pinctrl documentation
> and add new information for Meson8b in source code comments.
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/3] pinctrl: Add support for Meson8b
2015-03-19 21:34 ` [PATCH v3 3/3] pinctrl: Add support " Carlo Caione
@ 2015-03-28 10:06 ` Beniamino Galvani
2015-03-28 10:24 ` Carlo Caione
0 siblings, 1 reply; 11+ messages in thread
From: Beniamino Galvani @ 2015-03-28 10:06 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 19, 2015 at 10:34:12PM +0100, Carlo Caione wrote:
> From: Carlo Caione <carlo@endlessm.com>
>
> This patch adds support for the AmLogic Meson8b SoC.
>
> Signed-off-by: Carlo Caione <carlo@endlessm.com>
> ---
> drivers/pinctrl/meson/Makefile | 2 +-
> drivers/pinctrl/meson/pinctrl-meson.c | 4 +
> drivers/pinctrl/meson/pinctrl-meson.h | 1 +
> drivers/pinctrl/meson/pinctrl-meson8b.c | 900 ++++++++++++++++++++++++++++++++
> include/dt-bindings/gpio/meson8b-gpio.h | 32 ++
> 5 files changed, 938 insertions(+), 1 deletion(-)
> create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c
> create mode 100644 include/dt-bindings/gpio/meson8b-gpio.h
>
> [...]
>
> +static struct meson_bank meson8b_banks[] = {
> + /* name first last pullen pull dir out in */
> + BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
> + BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
> + BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
> + BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
> + BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
> + BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
> + BANK("DIF", PIN(DIF_0_P, DIF_OFF), PIN(DIF_4_N, DIF_OFF), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
> +};
So DIF pins belong to the standard domain and this is ok since they
use the same range of registers of other non-AO pins, but see below...
> +
> +static struct meson_bank meson8b_ao_banks[] = {
> + /* name first last pullen pull dir out in */
> + BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
> +};
> +
>
> [...]
>
> --- /dev/null
> +++ b/include/dt-bindings/gpio/meson8b-gpio.h
> @@ -0,0 +1,32 @@
> +
> +#ifndef _DT_BINDINGS_MESON8B_GPIO_H
> +#define _DT_BINDINGS_MESON8B_GPIO_H
> +
> +#include <dt-bindings/gpio/meson8-gpio.h>
> +
> +/* GPIO Bank DIF */
> +#define DIF_0_P 0
> +#define DIF_0_N 1
> +#define DIF_1_P 2
> +#define DIF_1_N 3
> +#define DIF_2_P 4
> +#define DIF_2_N 5
> +#define DIF_3_P 6
> +#define DIF_3_N 7
> +#define DIF_4_P 8
> +#define DIF_4_N 9
> +
> +#endif /* _DT_BINDINGS_MESON8B_GPIO_H */
... however these definitions start from 0 and thus overlap with the
definitions in meson8-gpio.h.
This means that the following GPIO specifier in a DTS:
gpios = <&gpio DIF_0_P GPIO_ACTIVE_HIGH>
has the same effect as
gpios = <&gpio GPIOX_0 GPIO_ACTIVE_HIGH>
I think that DIF_* pins should have a different numbering, for example
starting just after the end of the last non-AO pin. AO pin should also
be shifted accordingly.
Beniamino
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/3] pinctrl: Add support for Meson8b
2015-03-28 10:06 ` Beniamino Galvani
@ 2015-03-28 10:24 ` Carlo Caione
0 siblings, 0 replies; 11+ messages in thread
From: Carlo Caione @ 2015-03-28 10:24 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Mar 28, 2015 at 11:06 AM, Beniamino Galvani <b.galvani@gmail.com> wrote:
> On Thu, Mar 19, 2015 at 10:34:12PM +0100, Carlo Caione wrote:
>> From: Carlo Caione <carlo@endlessm.com>
>>
>> This patch adds support for the AmLogic Meson8b SoC.
>>
>> Signed-off-by: Carlo Caione <carlo@endlessm.com>
>> ---
>> drivers/pinctrl/meson/Makefile | 2 +-
>> drivers/pinctrl/meson/pinctrl-meson.c | 4 +
>> drivers/pinctrl/meson/pinctrl-meson.h | 1 +
>> drivers/pinctrl/meson/pinctrl-meson8b.c | 900 ++++++++++++++++++++++++++++++++
>> include/dt-bindings/gpio/meson8b-gpio.h | 32 ++
>> 5 files changed, 938 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/pinctrl/meson/pinctrl-meson8b.c
>> create mode 100644 include/dt-bindings/gpio/meson8b-gpio.h
>>
>> [...]
>>
>> +static struct meson_bank meson8b_banks[] = {
>> + /* name first last pullen pull dir out in */
>> + BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
>> + BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
>> + BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
>> + BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
>> + BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
>> + BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
>> + BANK("DIF", PIN(DIF_0_P, DIF_OFF), PIN(DIF_4_N, DIF_OFF), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
>> +};
>
> So DIF pins belong to the standard domain and this is ok since they
> use the same range of registers of other non-AO pins, but see below...
>
>> +
>> +static struct meson_bank meson8b_ao_banks[] = {
>> + /* name first last pullen pull dir out in */
>> + BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
>> +};
>> +
>>
>> [...]
>>
>> --- /dev/null
>> +++ b/include/dt-bindings/gpio/meson8b-gpio.h
>> @@ -0,0 +1,32 @@
>> +
>> +#ifndef _DT_BINDINGS_MESON8B_GPIO_H
>> +#define _DT_BINDINGS_MESON8B_GPIO_H
>> +
>> +#include <dt-bindings/gpio/meson8-gpio.h>
>> +
>> +/* GPIO Bank DIF */
>> +#define DIF_0_P 0
>> +#define DIF_0_N 1
>> +#define DIF_1_P 2
>> +#define DIF_1_N 3
>> +#define DIF_2_P 4
>> +#define DIF_2_N 5
>> +#define DIF_3_P 6
>> +#define DIF_3_N 7
>> +#define DIF_4_P 8
>> +#define DIF_4_N 9
>> +
>> +#endif /* _DT_BINDINGS_MESON8B_GPIO_H */
>
> ... however these definitions start from 0 and thus overlap with the
> definitions in meson8-gpio.h.
>
> This means that the following GPIO specifier in a DTS:
>
> gpios = <&gpio DIF_0_P GPIO_ACTIVE_HIGH>
>
> has the same effect as
>
> gpios = <&gpio GPIOX_0 GPIO_ACTIVE_HIGH>
>
> I think that DIF_* pins should have a different numbering, for example
> starting just after the end of the last non-AO pin. AO pin should also
> be shifted accordingly.
Right. Fix in v4.
Thanks for the review.
--
Carlo Caione
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver
2015-03-19 21:34 ` [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver Carlo Caione
2015-03-28 9:47 ` Beniamino Galvani
@ 2015-04-07 9:42 ` Linus Walleij
1 sibling, 0 replies; 11+ messages in thread
From: Linus Walleij @ 2015-04-07 9:42 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 19, 2015 at 10:34 PM, Carlo Caione <carlo@caione.org> wrote:
> From: Carlo Caione <carlo@endlessm.com>
>
> This patch introduces a new PIN macro and few small modifications to
> simplify and shorten the Meson pinctrl drivers and cleanup the support
> file for the AmLogic Meson8 SoC.
>
> Signed-off-by: Carlo Caione <carlo@endlessm.com>
Patch applied with Beniamino's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/3] documentation: Extend pinctrl docs for Meson8b
2015-03-19 21:34 ` [PATCH v3 2/3] documentation: Extend pinctrl docs for Meson8b Carlo Caione
2015-03-28 9:49 ` Beniamino Galvani
@ 2015-04-07 9:43 ` Linus Walleij
1 sibling, 0 replies; 11+ messages in thread
From: Linus Walleij @ 2015-04-07 9:43 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 19, 2015 at 10:34 PM, Carlo Caione <carlo@caione.org> wrote:
> From: Carlo Caione <carlo@endlessm.com>
>
> Add the compatible string for Meson8b in Meson pinctrl documentation
> and add new information for Meson8b in source code comments.
>
> Signed-off-by: Carlo Caione <carlo@endlessm.com>
Patch applied with Beniamino's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-04-07 9:43 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-19 21:34 [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support Carlo Caione
2015-03-19 21:34 ` [PATCH v3 1/3] pinctrl: Cleanup Meson8 driver Carlo Caione
2015-03-28 9:47 ` Beniamino Galvani
2015-04-07 9:42 ` Linus Walleij
2015-03-19 21:34 ` [PATCH v3 2/3] documentation: Extend pinctrl docs for Meson8b Carlo Caione
2015-03-28 9:49 ` Beniamino Galvani
2015-04-07 9:43 ` Linus Walleij
2015-03-19 21:34 ` [PATCH v3 3/3] pinctrl: Add support " Carlo Caione
2015-03-28 10:06 ` Beniamino Galvani
2015-03-28 10:24 ` Carlo Caione
2015-03-27 9:02 ` [PATCH v3 0/3] Amlogic Meson8b pinctrl driver support Linus Walleij
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