[RESEND 0/6] Intel Atom C2000 series GPIO support

[RESEND 0/6] Intel Atom C2000 series GPIO support

[Vincent Donnefort]

This patch set is a resend which adds Lee Jones, MFD maintainer into the
thread and Aaron Sierra lpc_ich author, forgotten during the first send.

The purpose of this patch-set is to add support for GPIOs found on the Intel
Atom C2000 series (Avoton/Rangeley)

Vincent Donnefort (6):
  mfd: lpc_ich: Convert ICH GPIOs IDs to enum
  mfd: lpc_ich: Add support for Intel Avoton GPIOs
  gpio: ich: Add blink capability option
  gpio: ich: Add support for multiple register addresses
  gpio: ich: Add output levels cache support
  gpio: ich: Add support for Intel Avoton

 drivers/gpio/gpio-ich.c     | 96 ++++++++++++++++++++++++++++++++++++++-------
 drivers/mfd/lpc_ich.c       |  1 +
 include/linux/mfd/lpc_ich.h | 17 ++++----
 3 files changed, 93 insertions(+), 21 deletions(-)

-- 
1.8.3.2

[RESEND 1/6] mfd: lpc_ich: Convert ICH GPIOs IDs to enum

[Vincent Donnefort]

All those IDs are arbitrary and so can be encapsulated into an enumeration.

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
---
 include/linux/mfd/lpc_ich.h | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 3e1df64..293b062 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -31,13 +31,15 @@
 #define ICH_RES_GPE0	1
 
 /* GPIO compatibility */
-#define ICH_I3100_GPIO		0x401
-#define ICH_V5_GPIO		0x501
-#define ICH_V6_GPIO		0x601
-#define ICH_V7_GPIO		0x701
-#define ICH_V9_GPIO		0x801
-#define ICH_V10CORP_GPIO	0xa01
-#define ICH_V10CONS_GPIO	0xa11
+enum {
+	ICH_I3100_GPIO,
+	ICH_V5_GPIO,
+	ICH_V6_GPIO,
+	ICH_V7_GPIO,
+	ICH_V9_GPIO,
+	ICH_V10CORP_GPIO,
+	ICH_V10CONS_GPIO,
+};
 
 struct lpc_ich_info {
 	char name[32];
-- 
1.8.3.2

[RESEND 2/6] mfd: lpc_ich: Add support for Intel Avoton GPIOs

[Vincent Donnefort]

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
---
 drivers/mfd/lpc_ich.c       | 1 +
 include/linux/mfd/lpc_ich.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c
index be93fa2..f0e1b75 100644
--- a/drivers/mfd/lpc_ich.c
+++ b/drivers/mfd/lpc_ich.c
@@ -500,6 +500,7 @@ static struct lpc_ich_info lpc_chipset_info[] = {
 	[LPC_AVN] = {
 		.name = "Avoton SoC",
 		.iTCO_version = 1,
+		.gpio_version = AVOTON_GPIO,
 	},
 	[LPC_COLETO] = {
 		.name = "Coleto Creek",
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index 293b062..b2364dd 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -39,6 +39,7 @@ enum {
 	ICH_V9_GPIO,
 	ICH_V10CORP_GPIO,
 	ICH_V10CONS_GPIO,
+	AVOTON_GPIO,
 };
 
 struct lpc_ich_info {
-- 
1.8.3.2

[RESEND 3/6] gpio: ich: Add blink capability option

[Vincent Donnefort]

This patch allows gpio_ich driver to be aware of non blink capable chipsets.

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
---
 drivers/gpio/gpio-ich.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index f5bf3c3..82887c5 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -62,6 +62,9 @@ struct ichx_desc {
 	/* Max GPIO pins the chipset can have */
 	uint ngpio;
 
+	/* GPO_BLINK is available on this chipset */
+	bool have_blink;
+
 	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
 	bool uses_gpe0;
 
@@ -151,7 +154,7 @@ static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
 					int val)
 {
 	/* Disable blink hardware which is available for GPIOs from 0 to 31. */
-	if (nr < 32)
+	if (nr < 32 && ichx_priv.desc->have_blink)
 		ichx_write_bit(GPO_BLINK, nr, 0, 0);
 
 	/* Set GPIO output value. */
@@ -266,6 +269,7 @@ static struct ichx_desc ich6_desc = {
 	.uses_gpe0 = true,
 
 	.ngpio = 50,
+	.have_blink = true,
 };
 
 /* Intel 3100 */
@@ -290,19 +294,23 @@ static struct ichx_desc i3100_desc = {
 /* ICH7 and ICH8-based */
 static struct ichx_desc ich7_desc = {
 	.ngpio = 50,
+	.have_blink = true,
 };
 
 /* ICH9-based */
 static struct ichx_desc ich9_desc = {
 	.ngpio = 61,
+	.have_blink = true,
 };
 
 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
 static struct ichx_desc ich10_cons_desc = {
 	.ngpio = 61,
+	.have_blink = true,
 };
 static struct ichx_desc ich10_corp_desc = {
 	.ngpio = 72,
+	.have_blink = true,
 };
 
 /* Intel 5 series, 6 series, 3400 series, and C200 series */
-- 
1.8.3.2

[RESEND 4/6] gpio: ich: Add support for multiple register addresses

[Vincent Donnefort]

This patch introduces regs and reglen pointers which allow a chipset to have
register addresses differing from ICH ones.

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
---
 drivers/gpio/gpio-ich.c | 43 +++++++++++++++++++++++++++++++------------
 1 file changed, 31 insertions(+), 12 deletions(-)

diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index 82887c5..f3eb1c5 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -62,6 +62,10 @@ struct ichx_desc {
 	/* Max GPIO pins the chipset can have */
 	uint ngpio;
 
+	/* chipset registers */
+	const u8 (*regs)[3];
+	const u8 *reglen;
+
 	/* GPO_BLINK is available on this chipset */
 	bool have_blink;
 
@@ -102,13 +106,16 @@ static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
 
 	spin_lock_irqsave(&ichx_priv.lock, flags);
 
-	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
+	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
+			 ichx_priv.gpio_base);
 	if (val)
 		data |= 1 << bit;
 	else
 		data &= ~(1 << bit);
-	ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
-	tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
+	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
+			 ichx_priv.gpio_base);
+	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
+			ichx_priv.gpio_base);
 	if (verify && data != tmp)
 		ret = -EPERM;
 
@@ -126,7 +133,8 @@ static int ichx_read_bit(int reg, unsigned nr)
 
 	spin_lock_irqsave(&ichx_priv.lock, flags);
 
-	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
+	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
+			 ichx_priv.gpio_base);
 
 	spin_unlock_irqrestore(&ichx_priv.lock, flags);
 
@@ -295,27 +303,37 @@ static struct ichx_desc i3100_desc = {
 static struct ichx_desc ich7_desc = {
 	.ngpio = 50,
 	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
 };
 
 /* ICH9-based */
 static struct ichx_desc ich9_desc = {
 	.ngpio = 61,
 	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
 };
 
 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
 static struct ichx_desc ich10_cons_desc = {
 	.ngpio = 61,
 	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
 };
 static struct ichx_desc ich10_corp_desc = {
 	.ngpio = 72,
 	.have_blink = true,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
 };
 
 /* Intel 5 series, 6 series, 3400 series, and C200 series */
 static struct ichx_desc intel5_desc = {
 	.ngpio = 76,
+	.regs = ichx_regs,
+	.reglen = ichx_reglen,
 };
 
 static int ichx_gpio_request_regions(struct resource *res_base,
@@ -326,11 +344,12 @@ static int ichx_gpio_request_regions(struct resource *res_base,
 	if (!res_base || !res_base->start || !res_base->end)
 		return -ENODEV;
 
-	for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
+	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
 		if (!(use_gpio & (1 << i)))
 			continue;
-		if (!request_region(res_base->start + ichx_regs[0][i],
-				    ichx_reglen[i], name))
+		if (!request_region(
+				res_base->start + ichx_priv.desc->regs[0][i],
+				ichx_priv.desc->reglen[i], name))
 			goto request_err;
 	}
 	return 0;
@@ -340,8 +359,8 @@ request_err:
 	for (i--; i >= 0; i--) {
 		if (!(use_gpio & (1 << i)))
 			continue;
-		release_region(res_base->start + ichx_regs[0][i],
-			       ichx_reglen[i]);
+		release_region(res_base->start + ichx_priv.desc->regs[0][i],
+			       ichx_priv.desc->reglen[i]);
 	}
 	return -EBUSY;
 }
@@ -350,11 +369,11 @@ static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio)
 {
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(ichx_regs[0]); i++) {
+	for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
 		if (!(use_gpio & (1 << i)))
 			continue;
-		release_region(res_base->start + ichx_regs[0][i],
-			       ichx_reglen[i]);
+		release_region(res_base->start + ichx_priv.desc->regs[0][i],
+			       ichx_priv.desc->reglen[i]);
 	}
 }
 
-- 
1.8.3.2

[RESEND 5/6] gpio: ich: Add output levels cache support

[Vincent Donnefort]

This patch allows GPIO driver to cache GPIO_LVL output registers. The aim is to
support chipsets on which GPIO_LVL value can't be read for output pins.

Caching output levels implies the first output values reading as 0. The driver
so can't be aware of set values GPIOs by bootloader or BIOS.

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
---
 drivers/gpio/gpio-ich.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index f3eb1c5..bfef20f 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -78,6 +78,12 @@ struct ichx_desc {
 	/* Some chipsets have quirks, let these use their own request/get */
 	int (*request)(struct gpio_chip *chip, unsigned offset);
 	int (*get)(struct gpio_chip *chip, unsigned offset);
+
+	/*
+	 * Some chipsets don't let reading output values on GPIO_LVL register
+	 * this option allows driver caching written output values
+	 */
+	bool use_outlvl_cache;
 };
 
 static struct {
@@ -89,6 +95,7 @@ static struct {
 	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
 	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
 	u8 use_gpio;		/* Which GPIO groups are usable */
+	int outlvl_cache[3];	/* cached output values */
 } ichx_priv;
 
 static int modparam_gpiobase = -1;	/* dynamic */
@@ -106,14 +113,21 @@ static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
 
 	spin_lock_irqsave(&ichx_priv.lock, flags);
 
-	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
-			 ichx_priv.gpio_base);
+	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
+		data = ichx_priv.outlvl_cache[reg_nr];
+	else
+		data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
+				 ichx_priv.gpio_base);
+
 	if (val)
 		data |= 1 << bit;
 	else
 		data &= ~(1 << bit);
 	ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
 			 ichx_priv.gpio_base);
+	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
+		ichx_priv.outlvl_cache[reg_nr] = data;
+
 	tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
 			ichx_priv.gpio_base);
 	if (verify && data != tmp)
@@ -136,6 +150,9 @@ static int ichx_read_bit(int reg, unsigned nr)
 	data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
 			 ichx_priv.gpio_base);
 
+	if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
+		data = ichx_priv.outlvl_cache[reg_nr] | data;
+
 	spin_unlock_irqrestore(&ichx_priv.lock, flags);
 
 	return data & (1 << bit) ? 1 : 0;
-- 
1.8.3.2

[RESEND 6/6] gpio: ich: Add support for Intel Avoton

[Vincent Donnefort]

This patch adds support for Atom C2000 series (Avoton and Rangeley). And has
the following options:
  - New addresses register.
  - Caching output levels (see Intel external design spec, table 48-29)
  - No hardware blink.

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
---
 drivers/gpio/gpio-ich.c | 26 +++++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c
index bfef20f..e73c675 100644
--- a/drivers/gpio/gpio-ich.c
+++ b/drivers/gpio/gpio-ich.c
@@ -1,5 +1,5 @@
 /*
- * Intel ICH6-10, Series 5 and 6 GPIO driver
+ * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
  *
  * Copyright (C) 2010 Extreme Engineering Solutions.
  *
@@ -55,6 +55,16 @@ static const u8 ichx_reglen[3] = {
 	0x30, 0x10, 0x10,
 };
 
+static const u8 avoton_regs[4][3] = {
+	{0x00, 0x80, 0x00},
+	{0x04, 0x84, 0x00},
+	{0x08, 0x88, 0x00},
+};
+
+static const u8 avoton_reglen[3] = {
+	0x10, 0x10, 0x00,
+};
+
 #define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
 #define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)
 
@@ -353,6 +363,17 @@ static struct ichx_desc intel5_desc = {
 	.reglen = ichx_reglen,
 };
 
+/* Avoton */
+static struct ichx_desc avoton_desc = {
+	/* Avoton has only 59 GPIOs, but we assume the first set of register
+	 * (Core) has 32 instead of 31 to keep gpio-ich compliance
+	 */
+	.ngpio = 60,
+	.regs = avoton_regs,
+	.reglen = avoton_reglen,
+	.use_outlvl_cache = true,
+};
+
 static int ichx_gpio_request_regions(struct resource *res_base,
 						const char *name, u8 use_gpio)
 {
@@ -427,6 +448,9 @@ static int ichx_gpio_probe(struct platform_device *pdev)
 	case ICH_V10CONS_GPIO:
 		ichx_priv.desc = &ich10_cons_desc;
 		break;
+	case AVOTON_GPIO:
+		ichx_priv.desc = &avoton_desc;
+		break;
 	default:
 		return -ENODEV;
 	}
-- 
1.8.3.2

Re: [RESEND 0/6] Intel Atom C2000 series GPIO support

[Lee Jones]

> This patch set is a resend which adds Lee Jones, MFD maintainer into the
> thread and Aaron Sierra lpc_ich author, forgotten during the first send.
> 
> The purpose of this patch-set is to add support for GPIOs found on the Intel
> Atom C2000 series (Avoton/Rangeley)
> 
> Vincent Donnefort (6):
>   mfd: lpc_ich: Convert ICH GPIOs IDs to enum
>   mfd: lpc_ich: Add support for Intel Avoton GPIOs
>   gpio: ich: Add blink capability option
>   gpio: ich: Add support for multiple register addresses
>   gpio: ich: Add output levels cache support
>   gpio: ich: Add support for Intel Avoton
> 
>  drivers/gpio/gpio-ich.c     | 96 ++++++++++++++++++++++++++++++++++++++-------
>  drivers/mfd/lpc_ich.c       |  1 +
>  include/linux/mfd/lpc_ich.h | 17 ++++----
>  3 files changed, 93 insertions(+), 21 deletions(-)

I'm fine with the MFD patches in this set.

Linus,
  Do you want me to create an immutable branch for you to pull from?

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [RESEND 1/6] mfd: lpc_ich: Convert ICH GPIOs IDs to enum

[Linus Walleij]

On Fri, Feb 14, 2014 at 3:01 PM, Vincent Donnefort <vdonnefort@gmail.com> wrote:

> All those IDs are arbitrary and so can be encapsulated into an enumeration.
>
> Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>

OK Lee, how did we want to proceed with this? I think it's
easiest to put all patches into one tree, this is just too little
patches for cross-immutable branches & stuff.

You can either take the whole lot with my ACK (hereby
provided) or you can ACK patch 1+2 and I will put the whole
thing into the GPIO tree.

Yours,
Linus Walleij

Re: [RESEND 0/6] Intel Atom C2000 series GPIO support

[Linus Walleij]

On Fri, Feb 14, 2014 at 3:27 PM, Lee Jones <lee.jones@linaro.org> wrote:
>> This patch set is a resend which adds Lee Jones, MFD maintainer into the
>> thread and Aaron Sierra lpc_ich author, forgotten during the first send.
>>
>> The purpose of this patch-set is to add support for GPIOs found on the Intel
>> Atom C2000 series (Avoton/Rangeley)
>>
>> Vincent Donnefort (6):
>>   mfd: lpc_ich: Convert ICH GPIOs IDs to enum
>>   mfd: lpc_ich: Add support for Intel Avoton GPIOs
>>   gpio: ich: Add blink capability option
>>   gpio: ich: Add support for multiple register addresses
>>   gpio: ich: Add output levels cache support
>>   gpio: ich: Add support for Intel Avoton
>>
>>  drivers/gpio/gpio-ich.c     | 96 ++++++++++++++++++++++++++++++++++++++-------
>>  drivers/mfd/lpc_ich.c       |  1 +
>>  include/linux/mfd/lpc_ich.h | 17 ++++----
>>  3 files changed, 93 insertions(+), 21 deletions(-)
>
> I'm fine with the MFD patches in this set.
>
> Linus,
>   Do you want me to create an immutable branch for you to pull from?

Argh too little code for that. It won't collide anyway, either of us
gets to apply all of them.

Yours,
Linus Walleij

Re: [RESEND 1/6] mfd: lpc_ich: Convert ICH GPIOs IDs to enum

[Lee Jones]

On Mon, 24 Feb 2014, Linus Walleij wrote:

> On Fri, Feb 14, 2014 at 3:01 PM, Vincent Donnefort <vdonnefort@gmail.com> wrote:
> 
> > All those IDs are arbitrary and so can be encapsulated into an enumeration.
> >
> > Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
> 
> OK Lee, how did we want to proceed with this? I think it's
> easiest to put all patches into one tree, this is just too little
> patches for cross-immutable branches & stuff.
> 
> You can either take the whole lot with my ACK (hereby
> provided) or you can ACK patch 1+2 and I will put the whole
> thing into the GPIO tree.

I'll save you the trouble.

Applied, thanks.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [RESEND 1/6] mfd: lpc_ich: Convert ICH GPIOs IDs to enum

[Linus Walleij]

On Mon, Feb 24, 2014 at 4:40 PM, Lee Jones <lee.jones@linaro.org> wrote:
> On Mon, 24 Feb 2014, Linus Walleij wrote:
>
>> On Fri, Feb 14, 2014 at 3:01 PM, Vincent Donnefort <vdonnefort@gmail.com> wrote:
>>
>> > All those IDs are arbitrary and so can be encapsulated into an enumeration.
>> >
>> > Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
>>
>> OK Lee, how did we want to proceed with this? I think it's
>> easiest to put all patches into one tree, this is just too little
>> patches for cross-immutable branches & stuff.
>>
>> You can either take the whole lot with my ACK (hereby
>> provided) or you can ACK patch 1+2 and I will put the whole
>> thing into the GPIO tree.
>
> I'll save you the trouble.
>
> Applied, thanks.

Thanks Lee!

Linus Walleij