* [PATCH] pinctrl/amd: fix gpio irq level in debugfs
@ 2018-07-17 1:07 ` Daniel Kurtz
0 siblings, 0 replies; 3+ messages in thread
From: Daniel Kurtz @ 2018-07-17 1:07 UTC (permalink / raw)
Cc: Shyam Sundar S K, Nehal Shah, Ken Xue, Daniel Kurtz,
Linus Walleij, open list:PIN CONTROL SUBSYSTEM, open list
According to the AMD BKDG, the GPIO ActiveLevel bits (10:9) map to:
00 Active High
01 Active Low
10 Active on both edges iff LevelTrig (bit 8) == 0
11 Reserved
The current code has a bug where it interprets 00 => Active Low, and
01 => Active High.
Fix the bug, restrict "Active on both" to just the edge trigger case, and
refactor a bit to make the logic more readable.
Change-Id: Id7775ae4cb61d193fa7fbb83967a8c5a7cdd0de6
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
---
drivers/pinctrl/pinctrl-amd.c | 14 +++++++-------
drivers/pinctrl/pinctrl-amd.h | 4 ++++
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 04ae139671c8a8..5df5e8d64c57e7 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -247,16 +247,16 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
+ u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
+ ACTIVE_LEVEL_MASK;
interrupt_enable = "interrupt is enabled|";
- if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
- !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
- active_level = "Active low|";
- else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) &&
- !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
+ if (level == ACTIVE_LEVEL_HIGH)
active_level = "Active high|";
- else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
- pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))
+ else if (level == ACTIVE_LEVEL_LOW)
+ active_level = "Active low|";
+ else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
+ level == ACTIVE_LEVEL_BOTH)
active_level = "Active on both|";
else
active_level = "Unknown Active level|";
diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h
index 8fa453a59da5e6..22af7edfdb38e8 100644
--- a/drivers/pinctrl/pinctrl-amd.h
+++ b/drivers/pinctrl/pinctrl-amd.h
@@ -54,6 +54,10 @@
#define ACTIVE_LEVEL_MASK 0x3UL
#define DRV_STRENGTH_SEL_MASK 0x3UL
+#define ACTIVE_LEVEL_HIGH 0x0UL
+#define ACTIVE_LEVEL_LOW 0x1UL
+#define ACTIVE_LEVEL_BOTH 0x2UL
+
#define DB_TYPE_NO_DEBOUNCE 0x0UL
#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL
#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL
--
2.18.0.203.gfac676dfb9-goog
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] pinctrl/amd: fix gpio irq level in debugfs
@ 2018-07-17 1:07 ` Daniel Kurtz
0 siblings, 0 replies; 3+ messages in thread
From: Daniel Kurtz @ 2018-07-17 1:07 UTC (permalink / raw)
Cc: Shyam Sundar S K, Nehal Shah, Ken Xue, Daniel Kurtz,
Linus Walleij, open list:PIN CONTROL SUBSYSTEM, open list
According to the AMD BKDG, the GPIO ActiveLevel bits (10:9) map to:
00 Active High
01 Active Low
10 Active on both edges iff LevelTrig (bit 8) == 0
11 Reserved
The current code has a bug where it interprets 00 => Active Low, and
01 => Active High.
Fix the bug, restrict "Active on both" to just the edge trigger case, and
refactor a bit to make the logic more readable.
Change-Id: Id7775ae4cb61d193fa7fbb83967a8c5a7cdd0de6
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
---
drivers/pinctrl/pinctrl-amd.c | 14 +++++++-------
drivers/pinctrl/pinctrl-amd.h | 4 ++++
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 04ae139671c8a8..5df5e8d64c57e7 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -247,16 +247,16 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
+ u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
+ ACTIVE_LEVEL_MASK;
interrupt_enable = "interrupt is enabled|";
- if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
- !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
- active_level = "Active low|";
- else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) &&
- !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
+ if (level == ACTIVE_LEVEL_HIGH)
active_level = "Active high|";
- else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
- pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))
+ else if (level == ACTIVE_LEVEL_LOW)
+ active_level = "Active low|";
+ else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
+ level == ACTIVE_LEVEL_BOTH)
active_level = "Active on both|";
else
active_level = "Unknown Active level|";
diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h
index 8fa453a59da5e6..22af7edfdb38e8 100644
--- a/drivers/pinctrl/pinctrl-amd.h
+++ b/drivers/pinctrl/pinctrl-amd.h
@@ -54,6 +54,10 @@
#define ACTIVE_LEVEL_MASK 0x3UL
#define DRV_STRENGTH_SEL_MASK 0x3UL
+#define ACTIVE_LEVEL_HIGH 0x0UL
+#define ACTIVE_LEVEL_LOW 0x1UL
+#define ACTIVE_LEVEL_BOTH 0x2UL
+
#define DB_TYPE_NO_DEBOUNCE 0x0UL
#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL
#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL
--
2.18.0.203.gfac676dfb9-goog
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] pinctrl/amd: fix gpio irq level in debugfs
2018-07-17 1:07 ` Daniel Kurtz
(?)
@ 2018-07-29 20:21 ` Linus Walleij
-1 siblings, 0 replies; 3+ messages in thread
From: Linus Walleij @ 2018-07-29 20:21 UTC (permalink / raw)
To: Daniel Kurtz
Cc: S-k, Shyam-sundar, Shah, Nehal-bakulchandra, Ken Xue,
open list:GPIO SUBSYSTEM, linux-kernel
On Tue, Jul 17, 2018 at 3:07 AM Daniel Kurtz <djkurtz@chromium.org> wrote:
> According to the AMD BKDG, the GPIO ActiveLevel bits (10:9) map to:
> 00 Active High
> 01 Active Low
> 10 Active on both edges iff LevelTrig (bit 8) == 0
> 11 Reserved
>
> The current code has a bug where it interprets 00 => Active Low, and
> 01 => Active High.
>
> Fix the bug, restrict "Active on both" to just the edge trigger case, and
> refactor a bit to make the logic more readable.
>
> Change-Id: Id7775ae4cb61d193fa7fbb83967a8c5a7cdd0de6
I stripped that off.
> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Patch applied!
Thanks for your fixing and attention to detail!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-07-29 20:21 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2018-07-17 1:07 [PATCH] pinctrl/amd: fix gpio irq level in debugfs Daniel Kurtz
2018-07-17 1:07 ` Daniel Kurtz
2018-07-29 20:21 ` Linus Walleij
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