From: Linus Walleij <linus.walleij@linaro.org>
To: Rob Herring <robh@kernel.org>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Hans Ulli Kroll <ulli.kroll@googlemail.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Janos Laube <janos.dev@gmail.com>,
Paulius Zaleckas <paulius.zaleckas@gmail.com>,
openwrt-devel@openwrt.org, Arnd Bergmann <arnd@arndb.de>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini
Date: Sat, 28 Jan 2017 22:56:56 +0100 [thread overview]
Message-ID: <CACRpkdZbWwfQfdfrAx=HFc6g-PWAt2ZmU88wL3XJYfnPO74Gng@mail.gmail.com> (raw)
In-Reply-To: <20170123202105.qslqna4ckeyfwame@rob-hp-laptop>
On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring <robh@kernel.org> wrote:
> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote:
>> This adds the top level SoC bindings for Cortina systems Gemini
>> platforms.
(...)
>> +- intcon: the root node must have an interrupt controller node pointing to
>
> intcon is just a source label and not meaningful for the binding.
OK
>> +Example:
>> +
>> +/ {
>> + interrupt-parent = <&intcon>;
>> +
>> + syscon: syscon@40000000 {
>
> This chip has no internal bus? Put all these nodes under a bus.
Are you thinking something of the form:
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
syscon: syscon@40000000 {
(...)
?
Yours,
Linus Walleij
WARNING: multiple messages have this Message-ID (diff)
From: Linus Walleij <linus.walleij@linaro.org>
To: Rob Herring <robh@kernel.org>
Cc: openwrt-devel@openwrt.org,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Paulius Zaleckas <paulius.zaleckas@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Janos Laube <janos.dev@gmail.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini
Date: Sat, 28 Jan 2017 22:56:56 +0100 [thread overview]
Message-ID: <CACRpkdZbWwfQfdfrAx=HFc6g-PWAt2ZmU88wL3XJYfnPO74Gng@mail.gmail.com> (raw)
In-Reply-To: <20170123202105.qslqna4ckeyfwame@rob-hp-laptop>
On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring <robh@kernel.org> wrote:
> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote:
>> This adds the top level SoC bindings for Cortina systems Gemini
>> platforms.
(...)
>> +- intcon: the root node must have an interrupt controller node pointing to
>
> intcon is just a source label and not meaningful for the binding.
OK
>> +Example:
>> +
>> +/ {
>> + interrupt-parent = <&intcon>;
>> +
>> + syscon: syscon@40000000 {
>
> This chip has no internal bus? Put all these nodes under a bus.
Are you thinking something of the form:
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
syscon: syscon@40000000 {
(...)
?
Yours,
Linus Walleij
_______________________________________________
openwrt-devel mailing list
openwrt-devel@lists.openwrt.org
https://lists.openwrt.org/cgi-bin/mailman/listinfo/openwrt-devel
WARNING: multiple messages have this Message-ID (diff)
From: linus.walleij@linaro.org (Linus Walleij)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini
Date: Sat, 28 Jan 2017 22:56:56 +0100 [thread overview]
Message-ID: <CACRpkdZbWwfQfdfrAx=HFc6g-PWAt2ZmU88wL3XJYfnPO74Gng@mail.gmail.com> (raw)
In-Reply-To: <20170123202105.qslqna4ckeyfwame@rob-hp-laptop>
On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring <robh@kernel.org> wrote:
> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote:
>> This adds the top level SoC bindings for Cortina systems Gemini
>> platforms.
(...)
>> +- intcon: the root node must have an interrupt controller node pointing to
>
> intcon is just a source label and not meaningful for the binding.
OK
>> +Example:
>> +
>> +/ {
>> + interrupt-parent = <&intcon>;
>> +
>> + syscon: syscon at 40000000 {
>
> This chip has no internal bus? Put all these nodes under a bus.
Are you thinking something of the form:
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
syscon: syscon at 40000000 {
(...)
?
Yours,
Linus Walleij
next prev parent reply other threads:[~2017-01-28 21:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-22 12:22 [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini Linus Walleij
2017-01-22 12:22 ` Linus Walleij
2017-01-22 12:22 ` Linus Walleij
2017-01-23 20:21 ` Rob Herring
2017-01-23 20:21 ` Rob Herring
2017-01-28 21:56 ` Linus Walleij [this message]
2017-01-28 21:56 ` Linus Walleij
2017-01-28 21:56 ` Linus Walleij
2017-01-30 17:21 ` Rob Herring
2017-01-30 17:21 ` Rob Herring
2017-01-30 17:21 ` Rob Herring
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