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* [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops
@ 2014-07-19 23:48 Heiko Stübner
  2014-07-19 23:49 ` [PATCH 2/3] pinctrl: rockchip: add separate type for rk3288 Heiko Stübner
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Heiko Stübner @ 2014-07-19 23:48 UTC (permalink / raw)
  To: linux-arm-kernel

The rockchip pinctrl driver implements the generic pinconfig, therefore
also state this, so that the default pinconf dump functions work.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/pinctrl/pinctrl-rockchip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 169c3db..37339a1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -946,6 +946,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 static const struct pinconf_ops rockchip_pinconf_ops = {
 	.pin_config_get			= rockchip_pinconf_get,
 	.pin_config_set			= rockchip_pinconf_set,
+	.is_generic			= true,
 };
 
 static const struct of_device_id rockchip_bank_match[] = {
-- 
1.9.0

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 2/3] pinctrl: rockchip: add separate type for rk3288
  2014-07-19 23:48 [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops Heiko Stübner
@ 2014-07-19 23:49 ` Heiko Stübner
  2014-07-23 14:40   ` Linus Walleij
  2014-07-19 23:50 ` [PATCH 3/3] pinctrl: rockchip: add drive-strength control " Heiko Stübner
  2014-07-23 14:38 ` [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops Linus Walleij
  2 siblings, 1 reply; 6+ messages in thread
From: Heiko Stübner @ 2014-07-19 23:49 UTC (permalink / raw)
  To: linux-arm-kernel

An upcoming pinctrl function of the rk3288 differs again from everything else,
so we'll need a separate type for it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/pinctrl/pinctrl-rockchip.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 37339a1..58c4647 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -62,6 +62,7 @@ enum rockchip_pinctrl_type {
 	RK2928,
 	RK3066B,
 	RK3188,
+	RK3288,
 };
 
 /**
@@ -597,7 +598,8 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 		return !(data & BIT(bit))
 				? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 				: PIN_CONFIG_BIAS_DISABLE;
 	case RK3188:
+	case RK3288:
 		data >>= bit;
 		data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
 
@@ -651,6 +653,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 		spin_unlock_irqrestore(&bank->slock, flags);
 		break;
 	case RK3188:
+	case RK3288:
 		spin_lock_irqsave(&bank->slock, flags);
 
 		/* enable the write to the equivalent lower bits */
@@ -830,6 +833,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 	case RK3066B:
 		return pull ? false : true;
 	case RK3188:
+	case RK3288:
 		return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 	}
 
@@ -1864,7 +1868,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
 		.pin_banks		= rk3288_pin_banks,
 		.nr_banks		= ARRAY_SIZE(rk3288_pin_banks),
 		.label			= "RK3288-GPIO",
-		.type			= RK3188,
+		.type			= RK3288,
 		.grf_mux_offset		= 0x0,
 		.pmu_mux_offset		= 0x84,
 		.pull_calc_reg		= rk3288_calc_pull_reg_and_bit,
-- 
1.9.0

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 3/3] pinctrl: rockchip: add drive-strength control for rk3288
  2014-07-19 23:48 [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops Heiko Stübner
  2014-07-19 23:49 ` [PATCH 2/3] pinctrl: rockchip: add separate type for rk3288 Heiko Stübner
@ 2014-07-19 23:50 ` Heiko Stübner
  2014-07-23 14:50   ` Linus Walleij
  2014-07-23 14:38 ` [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops Linus Walleij
  2 siblings, 1 reply; 6+ messages in thread
From: Heiko Stübner @ 2014-07-19 23:50 UTC (permalink / raw)
  To: linux-arm-kernel

The rk3288 is the first Rockchip soc handling the drive strength on a per-pin
basis, while the older ones can set the drive-strength only for specific
pin-groups. Therefore limit setting the drive-strength to this soc for now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/pinctrl/pinctrl-rockchip.c | 112 +++++++++++++++++++++++++++++++++++++
 1 file changed, 112 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 58c4647..c15f7f9 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -573,6 +573,98 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 	}
 }
 
+#define RK3288_DRV_PMU_OFFSET		0x70
+#define RK3288_DRV_GRF_OFFSET		0x1c0
+#define RK3288_DRV_BITS_PER_PIN		2
+#define RK3288_DRV_PINS_PER_REG		8
+#define RK3288_DRV_BANK_STRIDE		16
+static int rk3288_drv_list[] = { 2, 4, 8, 12 };
+
+static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+				    int pin_num, struct regmap **regmap,
+				    int *reg, u8 *bit)
+{
+	struct rockchip_pinctrl *info = bank->drvdata;
+
+	/* The first 24 pins of the first bank are located in PMU */
+	if (bank->bank_num == 0) {
+		*regmap = info->regmap_pmu;
+		*reg = RK3288_DRV_PMU_OFFSET;
+
+		*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+		*bit = pin_num % RK3288_DRV_PINS_PER_REG;
+		*bit *= RK3288_DRV_BITS_PER_PIN;
+	} else {
+		*regmap = info->regmap_base;
+		*reg = RK3288_DRV_GRF_OFFSET;
+
+		/* correct the offset, as we're starting with the 2nd bank */
+		*reg -= 0x10;
+		*reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
+		*reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+
+		*bit = (pin_num % RK3288_DRV_PINS_PER_REG);
+		*bit *= RK3288_DRV_BITS_PER_PIN;
+	}
+}
+
+static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data;
+	u8 bit;
+
+	rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+	ret = regmap_read(regmap, reg, &data);
+	if (ret)
+		return ret;
+
+	data >>= bit;
+	data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
+
+	return rk3288_drv_list[data];
+}
+
+static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
+			    int strength)
+{
+	struct rockchip_pinctrl *info = bank->drvdata;
+	struct regmap *regmap;
+	unsigned long flags;
+	int reg, ret, i;
+	u32 data;
+	u8 bit;
+
+	rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+	ret = -EINVAL;
+	for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
+		if (rk3288_drv_list[i] == strength) {
+			ret = i;
+			break;
+		}
+	}
+
+	if (ret < 0) {
+		dev_err(info->dev, "unsupported driver strength %d\n",
+			strength);
+		return ret;
+	}
+
+	spin_lock_irqsave(&bank->slock, flags);
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << RK3288_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+
+	ret = regmap_write(regmap, reg, data);
+	spin_unlock_irqrestore(&bank->slock, flags);
+
+	return ret;
+}
+
 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 {
 	struct rockchip_pinctrl *info = bank->drvdata;
@@ -888,6 +980,15 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 			if (rc)
 				return rc;
 			break;
+		case PIN_CONFIG_DRIVE_STRENGTH:
+			/* rk3288 is the first with per-pin drive-strength */
+			if (info->ctrl->type != RK3288)
+				return -ENOTSUPP;
+
+			rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
+			if (rc < 0)
+				return rc;
+			break;
 		default:
 			return -ENOTSUPP;
 			break;
@@ -937,6 +1038,17 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 
 		arg = rc ? 1 : 0;
 		break;
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		/* rk3288 is the first with per-pin drive-strength */
+		if (info->ctrl->type != RK3288)
+			return -ENOTSUPP;
+
+		rc = rk3288_get_drive(bank, pin - bank->pin_base);
+		if (rc < 0)
+			return rc;
+
+		arg = rc;
+		break;
 	default:
 		return -ENOTSUPP;
 		break;
-- 
1.9.0

^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops
  2014-07-19 23:48 [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops Heiko Stübner
  2014-07-19 23:49 ` [PATCH 2/3] pinctrl: rockchip: add separate type for rk3288 Heiko Stübner
  2014-07-19 23:50 ` [PATCH 3/3] pinctrl: rockchip: add drive-strength control " Heiko Stübner
@ 2014-07-23 14:38 ` Linus Walleij
  2 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2014-07-23 14:38 UTC (permalink / raw)
  To: linux-arm-kernel

On Sun, Jul 20, 2014 at 1:48 AM, Heiko St?bner <heiko@sntech.de> wrote:

> The rockchip pinctrl driver implements the generic pinconfig, therefore
> also state this, so that the default pinconf dump functions work.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Patch applied.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH 2/3] pinctrl: rockchip: add separate type for rk3288
  2014-07-19 23:49 ` [PATCH 2/3] pinctrl: rockchip: add separate type for rk3288 Heiko Stübner
@ 2014-07-23 14:40   ` Linus Walleij
  0 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2014-07-23 14:40 UTC (permalink / raw)
  To: linux-arm-kernel

On Sun, Jul 20, 2014 at 1:49 AM, Heiko St?bner <heiko@sntech.de> wrote:

> An upcoming pinctrl function of the rk3288 differs again from everything else,
> so we'll need a separate type for it.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Patch applied. I have one of those on my desk now...

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 6+ messages in thread
* [PATCH 3/3] pinctrl: rockchip: add drive-strength control for rk3288
  2014-07-19 23:50 ` [PATCH 3/3] pinctrl: rockchip: add drive-strength control " Heiko Stübner
@ 2014-07-23 14:50   ` Linus Walleij
  0 siblings, 0 replies; 6+ messages in thread
From: Linus Walleij @ 2014-07-23 14:50 UTC (permalink / raw)
  To: linux-arm-kernel

On Sun, Jul 20, 2014 at 1:50 AM, Heiko St?bner <heiko@sntech.de> wrote:

> The rk3288 is the first Rockchip soc handling the drive strength on a per-pin
> basis, while the older ones can set the drive-strength only for specific
> pin-groups. Therefore limit setting the drive-strength to this soc for now.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>

Patch applied.

Others SoC:s have opted to create sub-drivers on a per-soc basis
when stuff gets too complicated, please keep this in mind if the
file starts growing wild...

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2014-07-23 14:50 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-07-19 23:48 [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops Heiko Stübner
2014-07-19 23:49 ` [PATCH 2/3] pinctrl: rockchip: add separate type for rk3288 Heiko Stübner
2014-07-23 14:40   ` Linus Walleij
2014-07-19 23:50 ` [PATCH 3/3] pinctrl: rockchip: add drive-strength control " Heiko Stübner
2014-07-23 14:50   ` Linus Walleij
2014-07-23 14:38 ` [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops Linus Walleij

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