* [PATCH RESEND V3 0/2] pinctrl: imx: add imx8qxp pinctrl support
@ 2018-10-30 14:10 ` A.s. Dong
0 siblings, 0 replies; 18+ messages in thread
From: A.s. Dong @ 2018-10-30 14:10 UTC (permalink / raw)
To: linux-gpio
Cc: A.s. Dong, dongas86, linus.walleij, stefan, dl-linux-imx, kernel,
Fabio Estevam, shawnguo, linux-arm-kernel
Rebased with latest pinctrl/for-next tree, compiling and function
tested on IMX6Q SDB.
This patch series adds i.MX8QXP pinctrl support which is based on
the pad service provided by SCU firmware.
The binding part is also merged into scu binding doc according to
Rob's suggestion.
https://www.spinics.net/lists/arm-kernel/msg680738.html
v2->v3:
* Pad name update (add IMX8QXP prefix)
v1->v2:
* scu firmware headfile path update
* structure name and api usage update
* move SCU Pad API implementation into driver
* add binding headfile pad-imx8qxp.h
Dong Aisheng (2):
pinctrl: fsl: add scu based pinctrl support
pinctrl: imx: add imx8qxp driver
drivers/pinctrl/freescale/Kconfig | 11 +
drivers/pinctrl/freescale/Makefile | 2 +
drivers/pinctrl/freescale/pinctrl-imx.c | 425 ++++++++++------
drivers/pinctrl/freescale/pinctrl-imx.h | 67 ++-
drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 +++++++++
drivers/pinctrl/freescale/pinctrl-scu.c | 121 +++++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 ++++++++++++++++++++++++++++
7 files changed, 1439 insertions(+), 170 deletions(-)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8qxp.c
create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 0/2] pinctrl: imx: add imx8qxp pinctrl support
@ 2018-10-30 14:10 ` A.s. Dong
0 siblings, 0 replies; 18+ messages in thread
From: A.s. Dong @ 2018-10-30 14:10 UTC (permalink / raw)
To: linux-arm-kernel
Rebased with latest pinctrl/for-next tree, compiling and function
tested on IMX6Q SDB.
This patch series adds i.MX8QXP pinctrl support which is based on
the pad service provided by SCU firmware.
The binding part is also merged into scu binding doc according to
Rob's suggestion.
https://www.spinics.net/lists/arm-kernel/msg680738.html
v2->v3:
* Pad name update (add IMX8QXP prefix)
v1->v2:
* scu firmware headfile path update
* structure name and api usage update
* move SCU Pad API implementation into driver
* add binding headfile pad-imx8qxp.h
Dong Aisheng (2):
pinctrl: fsl: add scu based pinctrl support
pinctrl: imx: add imx8qxp driver
drivers/pinctrl/freescale/Kconfig | 11 +
drivers/pinctrl/freescale/Makefile | 2 +
drivers/pinctrl/freescale/pinctrl-imx.c | 425 ++++++++++------
drivers/pinctrl/freescale/pinctrl-imx.h | 67 ++-
drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 +++++++++
drivers/pinctrl/freescale/pinctrl-scu.c | 121 +++++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 ++++++++++++++++++++++++++++
7 files changed, 1439 insertions(+), 170 deletions(-)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8qxp.c
create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
2018-10-30 14:10 ` A.s. Dong
@ 2018-10-30 14:10 ` A.s. Dong
-1 siblings, 0 replies; 18+ messages in thread
From: A.s. Dong @ 2018-10-30 14:10 UTC (permalink / raw)
To: linux-gpio
Cc: A.s. Dong, dongas86, Fabio Estevam, linus.walleij, stefan,
dl-linux-imx, kernel, Fabio Estevam, shawnguo, linux-arm-kernel
Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
that is responsible for controlling the pad setting of the IPs that
are present. Communication between the host processor running an OS
and the system controller happens through a SCU protocol.
This patch classifies the pad settings into two categories: MMIO and SCU.
For the original MMIO method, no functional changes except organize them
into a few imx_*_mmio() functions. Besides that, we add the SCU based
Pad Mux and Pinconf setting support which are implemented in pinctrl-scu.c.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* scu firmware headfile path update
* structure name and api usage update
* move SCU Pad API implementation into driver
---
drivers/pinctrl/freescale/Kconfig | 4 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx.c | 425 ++++++++++++++++++++------------
drivers/pinctrl/freescale/pinctrl-imx.h | 67 ++++-
drivers/pinctrl/freescale/pinctrl-scu.c | 121 +++++++++
5 files changed, 448 insertions(+), 170 deletions(-)
create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index dccf64c..94dcdb5 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -5,6 +5,10 @@ config PINCTRL_IMX
select GENERIC_PINCONF
select REGMAP
+config PINCTRL_IMX_SCU
+ bool
+ select PINCTRL_IMX
+
config PINCTRL_IMX1_CORE
bool
select PINMUX
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 73175b3..7ac8daf 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 4e8cf0e..78d33df 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -57,9 +57,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct group_desc *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
+ struct imx_pin *pin;
int map_num = 1;
int i, j;
@@ -73,11 +75,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- for (i = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL))
- map_num++;
+ if (info->flags & IMX_USE_SCU) {
+ map_num += grp->num_pins;
+ } else {
+ for (i = 0; i < grp->num_pins; i++) {
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
+ map_num++;
+ }
}
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
@@ -102,16 +107,26 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
/* create config map */
new_map++;
for (i = j = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL)) {
- new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
- new_map[j].data.configs.group_or_pin =
+ pin = &((struct imx_pin *)(grp->data))[i];
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
- new_map[j].data.configs.configs = &pin->config;
+
+ if (info->flags & IMX_USE_SCU) {
+ /*
+ * For SCU case, we set mux and conf together
+ * in one IPC call
+ */
+ new_map[j].data.configs.configs =
+ (unsigned long *)&pin->conf.scu;
+ new_map[j].data.configs.num_configs = 2;
+ } else if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) {
+ new_map[j].data.configs.configs =
+ &pin->conf.mmio.config;
new_map[j].data.configs.num_configs = 1;
- j++;
}
+
+ j++;
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
@@ -133,19 +148,96 @@ static const struct pinctrl_ops imx_pctrl_ops = {
.pin_dbg_show = imx_pin_dbg_show,
.dt_node_to_map = imx_dt_node_to_map,
.dt_free_map = imx_dt_free_map,
-
};
+static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
+ struct imx_pin *pin)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
+ const struct imx_pin_reg *pin_reg;
+ unsigned int pin_id;
+
+ pin_id = pin->pin;
+ pin_reg = &ipctl->pin_regs[pin_id];
+
+ if (pin_reg->mux_reg == -1) {
+ dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
+ info->pins[pin_id].name);
+ return 0;
+ }
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ reg &= ~info->mux_mask;
+ reg |= (pin_mmio->mux_mode << info->mux_shift);
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, reg);
+ } else {
+ writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, pin_mmio->mux_mode);
+ }
+
+ /*
+ * If the select input value begins with 0xff, it's a quirky
+ * select input and the value should be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the select
+ * input for some pin is not implemented in the select
+ * input register but in some general purpose register.
+ * We encode the select input value, width and shift of
+ * the bit field into input_val cell of pin function ID
+ * in device tree, and then decode them here for setting
+ * up the select input bits in general purpose register.
+ */
+ if (pin_mmio->input_val >> 24 == 0xff) {
+ u32 val = pin_mmio->input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some IOMUXC general
+ * purpose register, not regular select input register.
+ */
+ val = readl(ipctl->base + pin_mmio->input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, ipctl->base + pin_mmio->input_reg);
+ } else if (pin_mmio->input_reg) {
+ /*
+ * Regular select input register can never be at offset
+ * 0, and we only print register value for regular case.
+ */
+ if (ipctl->input_sel_base)
+ writel(pin_mmio->input_val, ipctl->input_sel_base +
+ pin_mmio->input_reg);
+ else
+ writel(pin_mmio->input_val, ipctl->base +
+ pin_mmio->input_reg);
+ dev_dbg(ipctl->dev,
+ "==>select_input: offset 0x%x val 0x%x\n",
+ pin_mmio->input_reg, pin_mmio->input_val);
+ }
+
+ return 0;
+}
+
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg;
- unsigned int npins, pin_id;
- int i;
- struct group_desc *grp = NULL;
- struct function_desc *func = NULL;
+ struct function_desc *func;
+ struct group_desc *grp;
+ struct imx_pin *pin;
+ unsigned int npins;
+ int i, err;
/*
* Configure the mux mode for each pin in the group for a specific
@@ -165,72 +257,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
func->name, grp->name);
for (i = 0; i < npins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- pin_id = pin->pin;
- pin_reg = &ipctl->pin_regs[pin_id];
-
- if (pin_reg->mux_reg == -1) {
- dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
- info->pins[pin_id].name);
- continue;
- }
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- u32 reg;
- reg = readl(ipctl->base + pin_reg->mux_reg);
- reg &= ~info->mux_mask;
- reg |= (pin->mux_mode << info->mux_shift);
- writel(reg, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, reg);
- } else {
- writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, pin->mux_mode);
- }
-
/*
- * If the select input value begins with 0xff, it's a quirky
- * select input and the value should be interpreted as below.
- * 31 23 15 7 0
- * | 0xff | shift | width | select |
- * It's used to work around the problem that the select
- * input for some pin is not implemented in the select
- * input register but in some general purpose register.
- * We encode the select input value, width and shift of
- * the bit field into input_val cell of pin function ID
- * in device tree, and then decode them here for setting
- * up the select input bits in general purpose register.
+ * For IMX_USE_SCU case, we postpone the mux setting
+ * until config is set as we can set them together
+ * in one IPC call
*/
- if (pin->input_val >> 24 == 0xff) {
- u32 val = pin->input_val;
- u8 select = val & 0xff;
- u8 width = (val >> 8) & 0xff;
- u8 shift = (val >> 16) & 0xff;
- u32 mask = ((1 << width) - 1) << shift;
- /*
- * The input_reg[i] here is actually some IOMUXC general
- * purpose register, not regular select input register.
- */
- val = readl(ipctl->base + pin->input_reg);
- val &= ~mask;
- val |= select << shift;
- writel(val, ipctl->base + pin->input_reg);
- } else if (pin->input_reg) {
- /*
- * Regular select input register can never be at offset
- * 0, and we only print register value for regular case.
- */
- if (ipctl->input_sel_base)
- writel(pin->input_val, ipctl->input_sel_base +
- pin->input_reg);
- else
- writel(pin->input_val, ipctl->base +
- pin->input_reg);
- dev_dbg(ipctl->dev,
- "==>select_input: offset 0x%x val 0x%x\n",
- pin->input_reg, pin->input_val);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(info->flags & IMX_USE_SCU)) {
+ err = imx_pmx_set_one_pin_mmio(ipctl, pin);
+ if (err)
+ return err;
}
}
@@ -300,8 +336,8 @@ static u32 imx_pinconf_parse_generic_config(struct device_node *np,
return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
}
-static int imx_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *config)
+static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -321,9 +357,21 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
return 0;
}
-static int imx_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_get_scu(pctldev, pin_id, config);
+ else
+ return imx_pinconf_get_mmio(pctldev, pin_id, config);
+}
+
+static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -358,19 +406,48 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
return 0;
}
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_set_scu(pctldev, pin_id,
+ configs, num_configs);
+ else
+ return imx_pinconf_set_mmio(pctldev, pin_id,
+ configs, num_configs);
+}
+
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
unsigned long config;
+ int ret;
- if (!pin_reg || pin_reg->conf_reg == -1) {
- seq_puts(s, "N/A");
- return;
+ if (info->flags & IMX_USE_SCU) {
+ ret = imx_pinconf_get_scu(pctldev, pin_id, &config);
+ if (ret) {
+ dev_err(ipctl->dev, "failed to get %s pinconf\n",
+ pin_get_name(pctldev, pin_id));
+ seq_puts(s, "N/A");
+ return;
+ }
+ } else {
+ pin_reg = &ipctl->pin_regs[pin_id];
+ if (!pin_reg || pin_reg->conf_reg == -1) {
+ seq_puts(s, "N/A");
+ return;
+ }
+
+ config = readl(ipctl->base + pin_reg->conf_reg);
}
- config = readl(ipctl->base + pin_reg->conf_reg);
seq_printf(s, "0x%lx", config);
}
@@ -418,9 +495,63 @@ static const struct pinconf_ops imx_pinconf_ops = {
* <mux_reg conf_reg input_reg mux_mode input_val>
* SHARE_MUX_CONF_REG:
* <mux_conf_reg input_reg mux_mode input_val>
+ * IMX_USE_SCU:
+ * <pin_id mux_mode>
*/
#define FSL_PIN_SIZE 24
#define FSL_PIN_SHARE_SIZE 20
+#define FSL_SCU_PIN_SIZE 12
+
+static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p,
+ struct device_node *np)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
+ struct imx_pin_reg *pin_reg;
+ const __be32 *list = *list_p;
+ u32 mux_reg, conf_reg;
+ u32 config;
+
+ mux_reg = be32_to_cpu(*list++);
+
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ conf_reg = mux_reg;
+ } else {
+ conf_reg = be32_to_cpu(*list++);
+ if (!conf_reg)
+ conf_reg = -1;
+ }
+
+ *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
+ pin_reg = &ipctl->pin_regs[*pin_id];
+ pin->pin = *pin_id;
+ pin_reg->mux_reg = mux_reg;
+ pin_reg->conf_reg = conf_reg;
+ pin_mmio->input_reg = be32_to_cpu(*list++);
+ pin_mmio->mux_mode = be32_to_cpu(*list++);
+ pin_mmio->input_val = be32_to_cpu(*list++);
+
+ if (info->generic_pinconf) {
+ /* generic pin config decoded */
+ pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
+ } else {
+ /* legacy pin config read from devicetree */
+ config = be32_to_cpu(*list++);
+
+ /* SION bit is in mux register */
+ if (config & IMX_PAD_SION)
+ pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
+ pin_mmio->config = config & ~IMX_PAD_SION;
+ }
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
+ pin_mmio->mux_mode, pin_mmio->config);
+}
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
@@ -428,14 +559,16 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
u32 index)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin *pin;
int size, pin_size;
const __be32 *list;
int i;
- u32 config;
dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX_USE_SCU)
+ pin_size = FSL_SCU_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
@@ -472,9 +605,6 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -EINVAL;
}
- /* first try to parse the generic pin config */
- config = imx_pinconf_parse_generic_config(np, ipctl);
-
grp->num_pins = size / pin_size;
grp->data = devm_kcalloc(ipctl->dev,
grp->num_pins, sizeof(struct imx_pin),
@@ -486,48 +616,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -ENOMEM;
for (i = 0; i < grp->num_pins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
- u32 conf_reg;
- unsigned int pin_id;
- struct imx_pin_reg *pin_reg;
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
- conf_reg = -1;
- }
-
- pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
- pin_reg = &ipctl->pin_regs[pin_id];
- pin->pin = pin_id;
- grp->pins[i] = pin_id;
- pin_reg->mux_reg = mux_reg;
- pin_reg->conf_reg = conf_reg;
- pin->input_reg = be32_to_cpu(*list++);
- pin->mux_mode = be32_to_cpu(*list++);
- pin->input_val = be32_to_cpu(*list++);
-
- if (info->generic_pinconf) {
- /* generic pin config decoded */
- pin->config = config;
- } else {
- /* legacy pin config read from devicetree */
- config = be32_to_cpu(*list++);
-
- /* SION bit is in mux register */
- if (config & IMX_PAD_SION)
- pin->mux_mode |= IOMUXC_CONFIG_SION;
- pin->config = config & ~IMX_PAD_SION;
- }
-
- dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
- pin->mux_mode, pin->config);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (info->flags & IMX_USE_SCU)
+ imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i],
+ pin, &list);
+ else
+ imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
+ pin, &list, np);
}
return 0;
@@ -699,35 +794,37 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
- ipctl->pin_regs = devm_kmalloc_array(&pdev->dev,
- info->npins, sizeof(*ipctl->pin_regs),
- GFP_KERNEL);
- if (!ipctl->pin_regs)
- return -ENOMEM;
+ if (!(info->flags & IMX_USE_SCU)) {
+ ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
+ sizeof(*ipctl->pin_regs),
+ GFP_KERNEL);
+ if (!ipctl->pin_regs)
+ return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- ipctl->pin_regs[i].mux_reg = -1;
- ipctl->pin_regs[i].conf_reg = -1;
- }
+ for (i = 0; i < info->npins; i++) {
+ ipctl->pin_regs[i].mux_reg = -1;
+ ipctl->pin_regs[i].conf_reg = -1;
+ }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ipctl->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ipctl->base))
- return PTR_ERR(ipctl->base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ipctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ipctl->base))
+ return PTR_ERR(ipctl->base);
- if (of_property_read_bool(dev_np, "fsl,input-sel")) {
- np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
- if (!np) {
- dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
- return -EINVAL;
- }
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (!np) {
+ dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
+ return -EINVAL;
+ }
- ipctl->input_sel_base = of_iomap(np, 0);
- of_node_put(np);
- if (!ipctl->input_sel_base) {
- dev_err(&pdev->dev,
- "iomuxc input select base address not found\n");
- return -ENOMEM;
+ ipctl->input_sel_base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!ipctl->input_sel_base) {
+ dev_err(&pdev->dev,
+ "iomuxc input select base address not found\n");
+ return -ENOMEM;
+ }
}
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 4b8225c..98a4889 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -19,16 +19,14 @@ struct platform_device;
extern struct pinmux_ops imx_pmx_ops;
/**
- * struct imx_pin - describes a single i.MX pin
- * @pin: the pin_id of this pin
+ * struct imx_pin_mmio - MMIO pin configurations
* @mux_mode: the mux mode for this pin.
* @input_reg: the select input register offset for this pin if any
* 0 if no select input setting needed.
* @input_val: the select input value for this pin.
* @configs: the config for this pin.
*/
-struct imx_pin {
- unsigned int pin;
+struct imx_pin_mmio {
unsigned int mux_mode;
u16 input_reg;
unsigned int input_val;
@@ -36,6 +34,29 @@ struct imx_pin {
};
/**
+ * struct imx_pin_scu - SCU pin configurations
+ * @mux: the mux mode for this pin.
+ * @configs: the config for this pin.
+ */
+struct imx_pin_scu {
+ unsigned int mux_mode;
+ unsigned long config;
+};
+
+/**
+ * struct imx_pin - describes a single i.MX pin
+ * @pin: the pin_id of this pin
+ * @conf: config type of this pin, either mmio or scu
+ */
+struct imx_pin {
+ unsigned int pin;
+ union {
+ struct imx_pin_mmio mmio;
+ struct imx_pin_scu scu;
+ } conf;
+};
+
+/**
* struct imx_pin_reg - describe a pin reg map
* @mux_reg: mux register offset
* @conf_reg: config register offset
@@ -99,8 +120,9 @@ struct imx_pinctrl {
#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
{ .param = p, .mask = m, .shift = o, .invert = true, }
-#define SHARE_MUX_CONF_REG 0x1
-#define ZERO_OFFSET_VALID 0x2
+#define SHARE_MUX_CONF_REG BIT(0)
+#define ZERO_OFFSET_VALID BIT(1)
+#define IMX_USE_SCU BIT(2)
#define NO_MUX 0x0
#define NO_PAD 0x0
@@ -113,4 +135,37 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
+
+#ifdef CONFIG_PINCTRL_IMX_SCU
+#define BM_PAD_CTL_GP_ENABLE BIT(30)
+#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
+#define BP_PAD_CTL_IFMUX 27
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config);
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs);
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p);
+#else
+static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ return -EINVAL;
+}
+static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ return -EINVAL;
+}
+static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id,
+ struct imx_pin *pin,
+ const __be32 **list_p)
+{
+}
+#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c
new file mode 100644
index 0000000..83e69c0
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-scu.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/err.h>
+#include <linux/firmware/imx/sci.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "../core.h"
+#include "pinctrl-imx.h"
+
+enum pad_func_e {
+ IMX_SC_PAD_FUNC_SET = 15,
+ IMX_SC_PAD_FUNC_GET = 16,
+};
+
+struct imx_sc_msg_req_pad_set {
+ struct imx_sc_rpc_msg hdr;
+ u32 val;
+ u16 pad;
+} __packed;
+
+struct imx_sc_msg_req_pad_get {
+ struct imx_sc_rpc_msg hdr;
+ u16 pad;
+} __packed;
+
+struct imx_sc_msg_resp_pad_get {
+ struct imx_sc_rpc_msg hdr;
+ u32 val;
+} __packed;
+
+struct imx_sc_ipc *pinctrl_ipc_handle;
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
+{
+ return imx_scu_get_handle(&pinctrl_ipc_handle);
+}
+
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
+{
+ struct imx_sc_msg_req_pad_get msg;
+ struct imx_sc_msg_resp_pad_get *resp;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+ int ret;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PAD;
+ hdr->func = IMX_SC_PAD_FUNC_GET;
+ hdr->size = 2;
+
+ msg.pad = pin_id;
+
+ ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
+ if (ret)
+ return ret;
+
+ resp = (struct imx_sc_msg_resp_pad_get *)&msg;
+ *config = resp->val;
+
+ return 0;
+}
+
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ struct imx_sc_msg_req_pad_set msg;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+ unsigned int mux = configs[0];
+ unsigned int conf = configs[1];
+ unsigned int val;
+ int ret;
+
+ /*
+ * Set mux and conf together in one IPC call
+ */
+ WARN_ON(num_configs != 2);
+
+ val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
+ val |= mux << BP_PAD_CTL_IFMUX;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PAD;
+ hdr->func = IMX_SC_PAD_FUNC_SET;
+ hdr->size = 3;
+
+ msg.pad = pin_id;
+ msg.val = val;
+
+ ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
+
+ dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n",
+ pin_id, conf, val);
+
+ return ret;
+}
+
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_scu *pin_scu = &pin->conf.scu;
+ const __be32 *list = *list_p;
+
+ pin->pin = be32_to_cpu(*list++);
+ *pin_id = pin->pin;
+ pin_scu->mux_mode = be32_to_cpu(*list++);
+ pin_scu->config = be32_to_cpu(*list++);
+ *list_p = list;
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
+ pin_scu->mux_mode, pin_scu->config);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
@ 2018-10-30 14:10 ` A.s. Dong
0 siblings, 0 replies; 18+ messages in thread
From: A.s. Dong @ 2018-10-30 14:10 UTC (permalink / raw)
To: linux-arm-kernel
Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
that is responsible for controlling the pad setting of the IPs that
are present. Communication between the host processor running an OS
and the system controller happens through a SCU protocol.
This patch classifies the pad settings into two categories: MMIO and SCU.
For the original MMIO method, no functional changes except organize them
into a few imx_*_mmio() functions. Besides that, we add the SCU based
Pad Mux and Pinconf setting support which are implemented in pinctrl-scu.c.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* no changes
v1->v2:
* scu firmware headfile path update
* structure name and api usage update
* move SCU Pad API implementation into driver
---
drivers/pinctrl/freescale/Kconfig | 4 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx.c | 425 ++++++++++++++++++++------------
drivers/pinctrl/freescale/pinctrl-imx.h | 67 ++++-
drivers/pinctrl/freescale/pinctrl-scu.c | 121 +++++++++
5 files changed, 448 insertions(+), 170 deletions(-)
create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index dccf64c..94dcdb5 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -5,6 +5,10 @@ config PINCTRL_IMX
select GENERIC_PINCONF
select REGMAP
+config PINCTRL_IMX_SCU
+ bool
+ select PINCTRL_IMX
+
config PINCTRL_IMX1_CORE
bool
select PINMUX
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 73175b3..7ac8daf 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 4e8cf0e..78d33df 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -57,9 +57,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct group_desc *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
+ struct imx_pin *pin;
int map_num = 1;
int i, j;
@@ -73,11 +75,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- for (i = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL))
- map_num++;
+ if (info->flags & IMX_USE_SCU) {
+ map_num += grp->num_pins;
+ } else {
+ for (i = 0; i < grp->num_pins; i++) {
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
+ map_num++;
+ }
}
new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
@@ -102,16 +107,26 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
/* create config map */
new_map++;
for (i = j = 0; i < grp->num_pins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(pin->config & IMX_NO_PAD_CTL)) {
- new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
- new_map[j].data.configs.group_or_pin =
+ pin = &((struct imx_pin *)(grp->data))[i];
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
pin_get_name(pctldev, pin->pin);
- new_map[j].data.configs.configs = &pin->config;
+
+ if (info->flags & IMX_USE_SCU) {
+ /*
+ * For SCU case, we set mux and conf together
+ * in one IPC call
+ */
+ new_map[j].data.configs.configs =
+ (unsigned long *)&pin->conf.scu;
+ new_map[j].data.configs.num_configs = 2;
+ } else if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) {
+ new_map[j].data.configs.configs =
+ &pin->conf.mmio.config;
new_map[j].data.configs.num_configs = 1;
- j++;
}
+
+ j++;
}
dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
@@ -133,19 +148,96 @@ static const struct pinctrl_ops imx_pctrl_ops = {
.pin_dbg_show = imx_pin_dbg_show,
.dt_node_to_map = imx_dt_node_to_map,
.dt_free_map = imx_dt_free_map,
-
};
+static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
+ struct imx_pin *pin)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
+ const struct imx_pin_reg *pin_reg;
+ unsigned int pin_id;
+
+ pin_id = pin->pin;
+ pin_reg = &ipctl->pin_regs[pin_id];
+
+ if (pin_reg->mux_reg == -1) {
+ dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
+ info->pins[pin_id].name);
+ return 0;
+ }
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ reg &= ~info->mux_mask;
+ reg |= (pin_mmio->mux_mode << info->mux_shift);
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, reg);
+ } else {
+ writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
+ dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
+ pin_reg->mux_reg, pin_mmio->mux_mode);
+ }
+
+ /*
+ * If the select input value begins with 0xff, it's a quirky
+ * select input and the value should be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the select
+ * input for some pin is not implemented in the select
+ * input register but in some general purpose register.
+ * We encode the select input value, width and shift of
+ * the bit field into input_val cell of pin function ID
+ * in device tree, and then decode them here for setting
+ * up the select input bits in general purpose register.
+ */
+ if (pin_mmio->input_val >> 24 == 0xff) {
+ u32 val = pin_mmio->input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some IOMUXC general
+ * purpose register, not regular select input register.
+ */
+ val = readl(ipctl->base + pin_mmio->input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, ipctl->base + pin_mmio->input_reg);
+ } else if (pin_mmio->input_reg) {
+ /*
+ * Regular select input register can never be at offset
+ * 0, and we only print register value for regular case.
+ */
+ if (ipctl->input_sel_base)
+ writel(pin_mmio->input_val, ipctl->input_sel_base +
+ pin_mmio->input_reg);
+ else
+ writel(pin_mmio->input_val, ipctl->base +
+ pin_mmio->input_reg);
+ dev_dbg(ipctl->dev,
+ "==>select_input: offset 0x%x val 0x%x\n",
+ pin_mmio->input_reg, pin_mmio->input_val);
+ }
+
+ return 0;
+}
+
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg;
- unsigned int npins, pin_id;
- int i;
- struct group_desc *grp = NULL;
- struct function_desc *func = NULL;
+ struct function_desc *func;
+ struct group_desc *grp;
+ struct imx_pin *pin;
+ unsigned int npins;
+ int i, err;
/*
* Configure the mux mode for each pin in the group for a specific
@@ -165,72 +257,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
func->name, grp->name);
for (i = 0; i < npins; i++) {
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- pin_id = pin->pin;
- pin_reg = &ipctl->pin_regs[pin_id];
-
- if (pin_reg->mux_reg == -1) {
- dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
- info->pins[pin_id].name);
- continue;
- }
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- u32 reg;
- reg = readl(ipctl->base + pin_reg->mux_reg);
- reg &= ~info->mux_mask;
- reg |= (pin->mux_mode << info->mux_shift);
- writel(reg, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, reg);
- } else {
- writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
- dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
- pin_reg->mux_reg, pin->mux_mode);
- }
-
/*
- * If the select input value begins with 0xff, it's a quirky
- * select input and the value should be interpreted as below.
- * 31 23 15 7 0
- * | 0xff | shift | width | select |
- * It's used to work around the problem that the select
- * input for some pin is not implemented in the select
- * input register but in some general purpose register.
- * We encode the select input value, width and shift of
- * the bit field into input_val cell of pin function ID
- * in device tree, and then decode them here for setting
- * up the select input bits in general purpose register.
+ * For IMX_USE_SCU case, we postpone the mux setting
+ * until config is set as we can set them together
+ * in one IPC call
*/
- if (pin->input_val >> 24 == 0xff) {
- u32 val = pin->input_val;
- u8 select = val & 0xff;
- u8 width = (val >> 8) & 0xff;
- u8 shift = (val >> 16) & 0xff;
- u32 mask = ((1 << width) - 1) << shift;
- /*
- * The input_reg[i] here is actually some IOMUXC general
- * purpose register, not regular select input register.
- */
- val = readl(ipctl->base + pin->input_reg);
- val &= ~mask;
- val |= select << shift;
- writel(val, ipctl->base + pin->input_reg);
- } else if (pin->input_reg) {
- /*
- * Regular select input register can never be at offset
- * 0, and we only print register value for regular case.
- */
- if (ipctl->input_sel_base)
- writel(pin->input_val, ipctl->input_sel_base +
- pin->input_reg);
- else
- writel(pin->input_val, ipctl->base +
- pin->input_reg);
- dev_dbg(ipctl->dev,
- "==>select_input: offset 0x%x val 0x%x\n",
- pin->input_reg, pin->input_val);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (!(info->flags & IMX_USE_SCU)) {
+ err = imx_pmx_set_one_pin_mmio(ipctl, pin);
+ if (err)
+ return err;
}
}
@@ -300,8 +336,8 @@ static u32 imx_pinconf_parse_generic_config(struct device_node *np,
return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
}
-static int imx_pinconf_get(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *config)
+static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -321,9 +357,21 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
return 0;
}
-static int imx_pinconf_set(struct pinctrl_dev *pctldev,
- unsigned pin_id, unsigned long *configs,
- unsigned num_configs)
+static int imx_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_get_scu(pctldev, pin_id, config);
+ else
+ return imx_pinconf_get_mmio(pctldev, pin_id, config);
+}
+
+static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@@ -358,19 +406,48 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
return 0;
}
+static int imx_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+
+ if (info->flags & IMX_USE_SCU)
+ return imx_pinconf_set_scu(pctldev, pin_id,
+ configs, num_configs);
+ else
+ return imx_pinconf_set_mmio(pctldev, pin_id,
+ configs, num_configs);
+}
+
static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg;
unsigned long config;
+ int ret;
- if (!pin_reg || pin_reg->conf_reg == -1) {
- seq_puts(s, "N/A");
- return;
+ if (info->flags & IMX_USE_SCU) {
+ ret = imx_pinconf_get_scu(pctldev, pin_id, &config);
+ if (ret) {
+ dev_err(ipctl->dev, "failed to get %s pinconf\n",
+ pin_get_name(pctldev, pin_id));
+ seq_puts(s, "N/A");
+ return;
+ }
+ } else {
+ pin_reg = &ipctl->pin_regs[pin_id];
+ if (!pin_reg || pin_reg->conf_reg == -1) {
+ seq_puts(s, "N/A");
+ return;
+ }
+
+ config = readl(ipctl->base + pin_reg->conf_reg);
}
- config = readl(ipctl->base + pin_reg->conf_reg);
seq_printf(s, "0x%lx", config);
}
@@ -418,9 +495,63 @@ static const struct pinconf_ops imx_pinconf_ops = {
* <mux_reg conf_reg input_reg mux_mode input_val>
* SHARE_MUX_CONF_REG:
* <mux_conf_reg input_reg mux_mode input_val>
+ * IMX_USE_SCU:
+ * <pin_id mux_mode>
*/
#define FSL_PIN_SIZE 24
#define FSL_PIN_SHARE_SIZE 20
+#define FSL_SCU_PIN_SIZE 12
+
+static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p,
+ struct device_node *np)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
+ struct imx_pin_reg *pin_reg;
+ const __be32 *list = *list_p;
+ u32 mux_reg, conf_reg;
+ u32 config;
+
+ mux_reg = be32_to_cpu(*list++);
+
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ conf_reg = mux_reg;
+ } else {
+ conf_reg = be32_to_cpu(*list++);
+ if (!conf_reg)
+ conf_reg = -1;
+ }
+
+ *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
+ pin_reg = &ipctl->pin_regs[*pin_id];
+ pin->pin = *pin_id;
+ pin_reg->mux_reg = mux_reg;
+ pin_reg->conf_reg = conf_reg;
+ pin_mmio->input_reg = be32_to_cpu(*list++);
+ pin_mmio->mux_mode = be32_to_cpu(*list++);
+ pin_mmio->input_val = be32_to_cpu(*list++);
+
+ if (info->generic_pinconf) {
+ /* generic pin config decoded */
+ pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
+ } else {
+ /* legacy pin config read from devicetree */
+ config = be32_to_cpu(*list++);
+
+ /* SION bit is in mux register */
+ if (config & IMX_PAD_SION)
+ pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
+ pin_mmio->config = config & ~IMX_PAD_SION;
+ }
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
+ pin_mmio->mux_mode, pin_mmio->config);
+}
static int imx_pinctrl_parse_groups(struct device_node *np,
struct group_desc *grp,
@@ -428,14 +559,16 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
u32 index)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin *pin;
int size, pin_size;
const __be32 *list;
int i;
- u32 config;
dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
- if (info->flags & SHARE_MUX_CONF_REG)
+ if (info->flags & IMX_USE_SCU)
+ pin_size = FSL_SCU_PIN_SIZE;
+ else if (info->flags & SHARE_MUX_CONF_REG)
pin_size = FSL_PIN_SHARE_SIZE;
else
pin_size = FSL_PIN_SIZE;
@@ -472,9 +605,6 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -EINVAL;
}
- /* first try to parse the generic pin config */
- config = imx_pinconf_parse_generic_config(np, ipctl);
-
grp->num_pins = size / pin_size;
grp->data = devm_kcalloc(ipctl->dev,
grp->num_pins, sizeof(struct imx_pin),
@@ -486,48 +616,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
return -ENOMEM;
for (i = 0; i < grp->num_pins; i++) {
- u32 mux_reg = be32_to_cpu(*list++);
- u32 conf_reg;
- unsigned int pin_id;
- struct imx_pin_reg *pin_reg;
- struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
-
- if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
- mux_reg = -1;
-
- if (info->flags & SHARE_MUX_CONF_REG) {
- conf_reg = mux_reg;
- } else {
- conf_reg = be32_to_cpu(*list++);
- if (!conf_reg)
- conf_reg = -1;
- }
-
- pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
- pin_reg = &ipctl->pin_regs[pin_id];
- pin->pin = pin_id;
- grp->pins[i] = pin_id;
- pin_reg->mux_reg = mux_reg;
- pin_reg->conf_reg = conf_reg;
- pin->input_reg = be32_to_cpu(*list++);
- pin->mux_mode = be32_to_cpu(*list++);
- pin->input_val = be32_to_cpu(*list++);
-
- if (info->generic_pinconf) {
- /* generic pin config decoded */
- pin->config = config;
- } else {
- /* legacy pin config read from devicetree */
- config = be32_to_cpu(*list++);
-
- /* SION bit is in mux register */
- if (config & IMX_PAD_SION)
- pin->mux_mode |= IOMUXC_CONFIG_SION;
- pin->config = config & ~IMX_PAD_SION;
- }
-
- dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
- pin->mux_mode, pin->config);
+ pin = &((struct imx_pin *)(grp->data))[i];
+ if (info->flags & IMX_USE_SCU)
+ imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i],
+ pin, &list);
+ else
+ imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
+ pin, &list, np);
}
return 0;
@@ -699,35 +794,37 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
- ipctl->pin_regs = devm_kmalloc_array(&pdev->dev,
- info->npins, sizeof(*ipctl->pin_regs),
- GFP_KERNEL);
- if (!ipctl->pin_regs)
- return -ENOMEM;
+ if (!(info->flags & IMX_USE_SCU)) {
+ ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
+ sizeof(*ipctl->pin_regs),
+ GFP_KERNEL);
+ if (!ipctl->pin_regs)
+ return -ENOMEM;
- for (i = 0; i < info->npins; i++) {
- ipctl->pin_regs[i].mux_reg = -1;
- ipctl->pin_regs[i].conf_reg = -1;
- }
+ for (i = 0; i < info->npins; i++) {
+ ipctl->pin_regs[i].mux_reg = -1;
+ ipctl->pin_regs[i].conf_reg = -1;
+ }
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ipctl->base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(ipctl->base))
- return PTR_ERR(ipctl->base);
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ipctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ipctl->base))
+ return PTR_ERR(ipctl->base);
- if (of_property_read_bool(dev_np, "fsl,input-sel")) {
- np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
- if (!np) {
- dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
- return -EINVAL;
- }
+ if (of_property_read_bool(dev_np, "fsl,input-sel")) {
+ np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
+ if (!np) {
+ dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
+ return -EINVAL;
+ }
- ipctl->input_sel_base = of_iomap(np, 0);
- of_node_put(np);
- if (!ipctl->input_sel_base) {
- dev_err(&pdev->dev,
- "iomuxc input select base address not found\n");
- return -ENOMEM;
+ ipctl->input_sel_base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!ipctl->input_sel_base) {
+ dev_err(&pdev->dev,
+ "iomuxc input select base address not found\n");
+ return -ENOMEM;
+ }
}
}
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 4b8225c..98a4889 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -19,16 +19,14 @@ struct platform_device;
extern struct pinmux_ops imx_pmx_ops;
/**
- * struct imx_pin - describes a single i.MX pin
- * @pin: the pin_id of this pin
+ * struct imx_pin_mmio - MMIO pin configurations
* @mux_mode: the mux mode for this pin.
* @input_reg: the select input register offset for this pin if any
* 0 if no select input setting needed.
* @input_val: the select input value for this pin.
* @configs: the config for this pin.
*/
-struct imx_pin {
- unsigned int pin;
+struct imx_pin_mmio {
unsigned int mux_mode;
u16 input_reg;
unsigned int input_val;
@@ -36,6 +34,29 @@ struct imx_pin {
};
/**
+ * struct imx_pin_scu - SCU pin configurations
+ * @mux: the mux mode for this pin.
+ * @configs: the config for this pin.
+ */
+struct imx_pin_scu {
+ unsigned int mux_mode;
+ unsigned long config;
+};
+
+/**
+ * struct imx_pin - describes a single i.MX pin
+ * @pin: the pin_id of this pin
+ * @conf: config type of this pin, either mmio or scu
+ */
+struct imx_pin {
+ unsigned int pin;
+ union {
+ struct imx_pin_mmio mmio;
+ struct imx_pin_scu scu;
+ } conf;
+};
+
+/**
* struct imx_pin_reg - describe a pin reg map
* @mux_reg: mux register offset
* @conf_reg: config register offset
@@ -99,8 +120,9 @@ struct imx_pinctrl {
#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
{ .param = p, .mask = m, .shift = o, .invert = true, }
-#define SHARE_MUX_CONF_REG 0x1
-#define ZERO_OFFSET_VALID 0x2
+#define SHARE_MUX_CONF_REG BIT(0)
+#define ZERO_OFFSET_VALID BIT(1)
+#define IMX_USE_SCU BIT(2)
#define NO_MUX 0x0
#define NO_PAD 0x0
@@ -113,4 +135,37 @@ struct imx_pinctrl {
int imx_pinctrl_probe(struct platform_device *pdev,
const struct imx_pinctrl_soc_info *info);
+
+#ifdef CONFIG_PINCTRL_IMX_SCU
+#define BM_PAD_CTL_GP_ENABLE BIT(30)
+#define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
+#define BP_PAD_CTL_IFMUX 27
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config);
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs);
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p);
+#else
+static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ return -EINVAL;
+}
+static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ return -EINVAL;
+}
+static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id,
+ struct imx_pin *pin,
+ const __be32 **list_p)
+{
+}
+#endif
#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c
new file mode 100644
index 0000000..83e69c0
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-scu.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/err.h>
+#include <linux/firmware/imx/sci.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "../core.h"
+#include "pinctrl-imx.h"
+
+enum pad_func_e {
+ IMX_SC_PAD_FUNC_SET = 15,
+ IMX_SC_PAD_FUNC_GET = 16,
+};
+
+struct imx_sc_msg_req_pad_set {
+ struct imx_sc_rpc_msg hdr;
+ u32 val;
+ u16 pad;
+} __packed;
+
+struct imx_sc_msg_req_pad_get {
+ struct imx_sc_rpc_msg hdr;
+ u16 pad;
+} __packed;
+
+struct imx_sc_msg_resp_pad_get {
+ struct imx_sc_rpc_msg hdr;
+ u32 val;
+} __packed;
+
+struct imx_sc_ipc *pinctrl_ipc_handle;
+
+int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
+{
+ return imx_scu_get_handle(&pinctrl_ipc_handle);
+}
+
+int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
+{
+ struct imx_sc_msg_req_pad_get msg;
+ struct imx_sc_msg_resp_pad_get *resp;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+ int ret;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PAD;
+ hdr->func = IMX_SC_PAD_FUNC_GET;
+ hdr->size = 2;
+
+ msg.pad = pin_id;
+
+ ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
+ if (ret)
+ return ret;
+
+ resp = (struct imx_sc_msg_resp_pad_get *)&msg;
+ *config = resp->val;
+
+ return 0;
+}
+
+int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *configs, unsigned num_configs)
+{
+ struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ struct imx_sc_msg_req_pad_set msg;
+ struct imx_sc_rpc_msg *hdr = &msg.hdr;
+ unsigned int mux = configs[0];
+ unsigned int conf = configs[1];
+ unsigned int val;
+ int ret;
+
+ /*
+ * Set mux and conf together in one IPC call
+ */
+ WARN_ON(num_configs != 2);
+
+ val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
+ val |= mux << BP_PAD_CTL_IFMUX;
+
+ hdr->ver = IMX_SC_RPC_VERSION;
+ hdr->svc = IMX_SC_RPC_SVC_PAD;
+ hdr->func = IMX_SC_PAD_FUNC_SET;
+ hdr->size = 3;
+
+ msg.pad = pin_id;
+ msg.val = val;
+
+ ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
+
+ dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n",
+ pin_id, conf, val);
+
+ return ret;
+}
+
+void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
+ unsigned int *pin_id, struct imx_pin *pin,
+ const __be32 **list_p)
+{
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ struct imx_pin_scu *pin_scu = &pin->conf.scu;
+ const __be32 *list = *list_p;
+
+ pin->pin = be32_to_cpu(*list++);
+ *pin_id = pin->pin;
+ pin_scu->mux_mode = be32_to_cpu(*list++);
+ pin_scu->config = be32_to_cpu(*list++);
+ *list_p = list;
+
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
+ pin_scu->mux_mode, pin_scu->config);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 2/2] pinctrl: imx: add imx8qxp driver
2018-10-30 14:10 ` A.s. Dong
@ 2018-10-30 14:10 ` A.s. Dong
-1 siblings, 0 replies; 18+ messages in thread
From: A.s. Dong @ 2018-10-30 14:10 UTC (permalink / raw)
To: linux-gpio
Cc: A.s. Dong, dongas86, Fabio Estevam, linus.walleij, stefan,
dl-linux-imx, kernel, Fabio Estevam, shawnguo, linux-arm-kernel
MX8QXP contains a system controller that is responsible for controlling
the pad setting of the IPs that are present. Communication between the
host processor running an OS and the system controller happens through
a SCU protocol. This patch adds the SCU based MX8QXP pinctrl driver.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* add 'IMX8QXP_' prefix for pad name definition
v1->v2:
* scu headfile path update
* add binding headfile pad-imx8qxp.h
* Note the binding part is merged into scu binding doc which has been picked
by Shawn.
https://www.spinics.net/lists/arm-kernel/msg680738.html
---
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 +++++++++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 ++++++++++++++++++++++++++++
4 files changed, 991 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8qxp.c
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 94dcdb5..2d6db43 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -128,6 +128,13 @@ config PINCTRL_IMX8MQ
help
Say Y here to enable the imx8mq pinctrl driver
+config PINCTRL_IMX8QXP
+ bool "IMX8QXP pinctrl driver"
+ depends on SOC_IMX8QXP
+ select PINCTRL_IMX_SCU
+ help
+ Say Y here to enable the imx8qxp pinctrl driver
+
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 7ac8daf..6ee398a 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
+obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
new file mode 100644
index 0000000..1131dc3
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#include <linux/err.h>
+#include <linux/firmware/imx/sci.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_PERST_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_CLKREQ_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_WAKE_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC0),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC1),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC2),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CMD),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA4),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA5),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA6),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA7),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_STROBE),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_RESET_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_RESET_B),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_VSELECT),
+ IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_RE_P_N),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_WP),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CD_B),
+ IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_DQS_P_N),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CMD),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXC),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TX_CTL),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD2),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXC),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RX_CTL),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD2),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_REFCLK_125M_25M),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDIO),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDC),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FSR),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FST),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKR),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKT),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX0),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX1),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX2_RX3),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX3_RX2),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX4_RX1),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX5_RX0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_EXT_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS1),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN1),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN0),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_OUT0),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_RTS_B),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_CTS_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXC),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_RXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXFS),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXC),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXFS),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS1),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN1),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN0),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN3),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN2),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN5),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN4),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART2_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART2_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
+ IMX_PINCTRL_PIN(IMX8QXP_JTAG_TRST_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_INT_B),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_PMIC_STANDBY),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE0),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE1),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE2),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE3),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D00),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D01),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D02),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D03),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D04),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D05),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D06),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D07),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_HSYNC),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_VSYNC),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_PCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_MCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_EN),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_RESET),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_MCLK_OUT),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DQS),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS0_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS1_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DQS),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS0_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS1_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
+};
+
+static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
+ .pins = imx8qxp_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
+ .flags = IMX_USE_SCU,
+};
+
+static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx8qxp-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = imx_pinctrl_sc_ipc_init(pdev);
+ if (ret)
+ return ret;
+
+ return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
+}
+
+static struct platform_driver imx8qxp_pinctrl_driver = {
+ .driver = {
+ .name = "imx8qxp-pinctrl",
+ .of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match),
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx8qxp_pinctrl_probe,
+};
+
+static int __init imx8qxp_pinctrl_init(void)
+{
+ return platform_driver_register(&imx8qxp_pinctrl_driver);
+}
+arch_initcall(imx8qxp_pinctrl_init);
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
new file mode 100644
index 0000000..fbfee7e
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -0,0 +1,751 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ */
+
+#ifndef _IMX8QXP_PADS_H
+#define _IMX8QXP_PADS_H
+
+/* pin id */
+#define IMX8QXP_PCIE_CTRL0_PERST_B 0
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1
+#define IMX8QXP_PCIE_CTRL0_WAKE_B 2
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
+#define IMX8QXP_USB_SS3_TC0 4
+#define IMX8QXP_USB_SS3_TC1 5
+#define IMX8QXP_USB_SS3_TC2 6
+#define IMX8QXP_USB_SS3_TC3 7
+#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 8
+#define IMX8QXP_EMMC0_CLK 9
+#define IMX8QXP_EMMC0_CMD 10
+#define IMX8QXP_EMMC0_DATA0 11
+#define IMX8QXP_EMMC0_DATA1 12
+#define IMX8QXP_EMMC0_DATA2 13
+#define IMX8QXP_EMMC0_DATA3 14
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
+#define IMX8QXP_EMMC0_DATA4 16
+#define IMX8QXP_EMMC0_DATA5 17
+#define IMX8QXP_EMMC0_DATA6 18
+#define IMX8QXP_EMMC0_DATA7 19
+#define IMX8QXP_EMMC0_STROBE 20
+#define IMX8QXP_EMMC0_RESET_B 21
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
+#define IMX8QXP_USDHC1_RESET_B 23
+#define IMX8QXP_USDHC1_VSELECT 24
+#define IMX8QXP_CTL_NAND_RE_P_N 25
+#define IMX8QXP_USDHC1_WP 26
+#define IMX8QXP_USDHC1_CD_B 27
+#define IMX8QXP_CTL_NAND_DQS_P_N 28
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
+#define IMX8QXP_USDHC1_CLK 30
+#define IMX8QXP_USDHC1_CMD 31
+#define IMX8QXP_USDHC1_DATA0 32
+#define IMX8QXP_USDHC1_DATA1 33
+#define IMX8QXP_USDHC1_DATA2 34
+#define IMX8QXP_USDHC1_DATA3 35
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
+#define IMX8QXP_ENET0_RGMII_TXC 37
+#define IMX8QXP_ENET0_RGMII_TX_CTL 38
+#define IMX8QXP_ENET0_RGMII_TXD0 39
+#define IMX8QXP_ENET0_RGMII_TXD1 40
+#define IMX8QXP_ENET0_RGMII_TXD2 41
+#define IMX8QXP_ENET0_RGMII_TXD3 42
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
+#define IMX8QXP_ENET0_RGMII_RXC 44
+#define IMX8QXP_ENET0_RGMII_RX_CTL 45
+#define IMX8QXP_ENET0_RGMII_RXD0 46
+#define IMX8QXP_ENET0_RGMII_RXD1 47
+#define IMX8QXP_ENET0_RGMII_RXD2 48
+#define IMX8QXP_ENET0_RGMII_RXD3 49
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
+#define IMX8QXP_ENET0_REFCLK_125M_25M 51
+#define IMX8QXP_ENET0_MDIO 52
+#define IMX8QXP_ENET0_MDC 53
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
+#define IMX8QXP_ESAI0_FSR 55
+#define IMX8QXP_ESAI0_FST 56
+#define IMX8QXP_ESAI0_SCKR 57
+#define IMX8QXP_ESAI0_SCKT 58
+#define IMX8QXP_ESAI0_TX0 59
+#define IMX8QXP_ESAI0_TX1 60
+#define IMX8QXP_ESAI0_TX2_RX3 61
+#define IMX8QXP_ESAI0_TX3_RX2 62
+#define IMX8QXP_ESAI0_TX4_RX1 63
+#define IMX8QXP_ESAI0_TX5_RX0 64
+#define IMX8QXP_SPDIF0_RX 65
+#define IMX8QXP_SPDIF0_TX 66
+#define IMX8QXP_SPDIF0_EXT_CLK 67
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
+#define IMX8QXP_SPI3_SCK 69
+#define IMX8QXP_SPI3_SDO 70
+#define IMX8QXP_SPI3_SDI 71
+#define IMX8QXP_SPI3_CS0 72
+#define IMX8QXP_SPI3_CS1 73
+#define IMX8QXP_MCLK_IN1 74
+#define IMX8QXP_MCLK_IN0 75
+#define IMX8QXP_MCLK_OUT0 76
+#define IMX8QXP_UART1_TX 77
+#define IMX8QXP_UART1_RX 78
+#define IMX8QXP_UART1_RTS_B 79
+#define IMX8QXP_UART1_CTS_B 80
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
+#define IMX8QXP_SAI0_TXD 82
+#define IMX8QXP_SAI0_TXC 83
+#define IMX8QXP_SAI0_RXD 84
+#define IMX8QXP_SAI0_TXFS 85
+#define IMX8QXP_SAI1_RXD 86
+#define IMX8QXP_SAI1_RXC 87
+#define IMX8QXP_SAI1_RXFS 88
+#define IMX8QXP_SPI2_CS0 89
+#define IMX8QXP_SPI2_SDO 90
+#define IMX8QXP_SPI2_SDI 91
+#define IMX8QXP_SPI2_SCK 92
+#define IMX8QXP_SPI0_SCK 93
+#define IMX8QXP_SPI0_SDI 94
+#define IMX8QXP_SPI0_SDO 95
+#define IMX8QXP_SPI0_CS1 96
+#define IMX8QXP_SPI0_CS0 97
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
+#define IMX8QXP_ADC_IN1 99
+#define IMX8QXP_ADC_IN0 100
+#define IMX8QXP_ADC_IN3 101
+#define IMX8QXP_ADC_IN2 102
+#define IMX8QXP_ADC_IN5 103
+#define IMX8QXP_ADC_IN4 104
+#define IMX8QXP_FLEXCAN0_RX 105
+#define IMX8QXP_FLEXCAN0_TX 106
+#define IMX8QXP_FLEXCAN1_RX 107
+#define IMX8QXP_FLEXCAN1_TX 108
+#define IMX8QXP_FLEXCAN2_RX 109
+#define IMX8QXP_FLEXCAN2_TX 110
+#define IMX8QXP_UART0_RX 111
+#define IMX8QXP_UART0_TX 112
+#define IMX8QXP_UART2_TX 113
+#define IMX8QXP_UART2_RX 114
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL 116
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA 117
+#define IMX8QXP_MIPI_DSI0_GPIO0_00 118
+#define IMX8QXP_MIPI_DSI0_GPIO0_01 119
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL 120
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA 121
+#define IMX8QXP_MIPI_DSI1_GPIO0_00 122
+#define IMX8QXP_MIPI_DSI1_GPIO0_01 123
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
+#define IMX8QXP_JTAG_TRST_B 125
+#define IMX8QXP_PMIC_I2C_SCL 126
+#define IMX8QXP_PMIC_I2C_SDA 127
+#define IMX8QXP_PMIC_INT_B 128
+#define IMX8QXP_SCU_GPIO0_00 129
+#define IMX8QXP_SCU_GPIO0_01 130
+#define IMX8QXP_SCU_PMIC_STANDBY 131
+#define IMX8QXP_SCU_BOOT_MODE0 132
+#define IMX8QXP_SCU_BOOT_MODE1 133
+#define IMX8QXP_SCU_BOOT_MODE2 134
+#define IMX8QXP_SCU_BOOT_MODE3 135
+#define IMX8QXP_CSI_D00 136
+#define IMX8QXP_CSI_D01 137
+#define IMX8QXP_CSI_D02 138
+#define IMX8QXP_CSI_D03 139
+#define IMX8QXP_CSI_D04 140
+#define IMX8QXP_CSI_D05 141
+#define IMX8QXP_CSI_D06 142
+#define IMX8QXP_CSI_D07 143
+#define IMX8QXP_CSI_HSYNC 144
+#define IMX8QXP_CSI_VSYNC 145
+#define IMX8QXP_CSI_PCLK 146
+#define IMX8QXP_CSI_MCLK 147
+#define IMX8QXP_CSI_EN 148
+#define IMX8QXP_CSI_RESET 149
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT 151
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL 152
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA 153
+#define IMX8QXP_MIPI_CSI0_GPIO0_01 154
+#define IMX8QXP_MIPI_CSI0_GPIO0_00 155
+#define IMX8QXP_QSPI0A_DATA0 156
+#define IMX8QXP_QSPI0A_DATA1 157
+#define IMX8QXP_QSPI0A_DATA2 158
+#define IMX8QXP_QSPI0A_DATA3 159
+#define IMX8QXP_QSPI0A_DQS 160
+#define IMX8QXP_QSPI0A_SS0_B 161
+#define IMX8QXP_QSPI0A_SS1_B 162
+#define IMX8QXP_QSPI0A_SCLK 163
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
+#define IMX8QXP_QSPI0B_SCLK 165
+#define IMX8QXP_QSPI0B_DATA0 166
+#define IMX8QXP_QSPI0B_DATA1 167
+#define IMX8QXP_QSPI0B_DATA2 168
+#define IMX8QXP_QSPI0B_DATA3 169
+#define IMX8QXP_QSPI0B_DQS 170
+#define IMX8QXP_QSPI0B_SS0_B 171
+#define IMX8QXP_QSPI0B_SS1_B 172
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
+
+/*
+ * format: <pin_id mux_mode>
+ */
+#define IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QXP_PCIE_CTRL0_PERST_B 0
+#define IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QXP_PCIE_CTRL0_CLKREQ_B 0
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4
+#define IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QXP_PCIE_CTRL0_WAKE_B 0
+#define IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4
+#define IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC0 0
+#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QXP_USB_SS3_TC0 1
+#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC0 2
+#define IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4
+#define IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC1 0
+#define IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC1 1
+#define IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4
+#define IMX8QXP_USB_SS3_TC2_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC2 0
+#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QXP_USB_SS3_TC2 1
+#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC2 2
+#define IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QXP_USB_SS3_TC2 4
+#define IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC3 0
+#define IMX8QXP_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC3 1
+#define IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QXP_USB_SS3_TC3 4
+#define IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK IMX8QXP_EMMC0_CLK 0
+#define IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B IMX8QXP_EMMC0_CLK 1
+#define IMX8QXP_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8QXP_EMMC0_CLK 4
+#define IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD IMX8QXP_EMMC0_CMD 0
+#define IMX8QXP_EMMC0_CMD_CONN_NAND_DQS IMX8QXP_EMMC0_CMD 1
+#define IMX8QXP_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8QXP_EMMC0_CMD 4
+#define IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QXP_EMMC0_DATA0 0
+#define IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QXP_EMMC0_DATA0 1
+#define IMX8QXP_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8QXP_EMMC0_DATA0 4
+#define IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QXP_EMMC0_DATA1 0
+#define IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QXP_EMMC0_DATA1 1
+#define IMX8QXP_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8QXP_EMMC0_DATA1 4
+#define IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QXP_EMMC0_DATA2 0
+#define IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QXP_EMMC0_DATA2 1
+#define IMX8QXP_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8QXP_EMMC0_DATA2 4
+#define IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QXP_EMMC0_DATA3 0
+#define IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QXP_EMMC0_DATA3 1
+#define IMX8QXP_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8QXP_EMMC0_DATA3 4
+#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QXP_EMMC0_DATA4 0
+#define IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QXP_EMMC0_DATA4 1
+#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_WP IMX8QXP_EMMC0_DATA4 3
+#define IMX8QXP_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8QXP_EMMC0_DATA4 4
+#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QXP_EMMC0_DATA5 0
+#define IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QXP_EMMC0_DATA5 1
+#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_VSELECT IMX8QXP_EMMC0_DATA5 3
+#define IMX8QXP_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8QXP_EMMC0_DATA5 4
+#define IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QXP_EMMC0_DATA6 0
+#define IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QXP_EMMC0_DATA6 1
+#define IMX8QXP_EMMC0_DATA6_CONN_MLB_CLK IMX8QXP_EMMC0_DATA6 3
+#define IMX8QXP_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8QXP_EMMC0_DATA6 4
+#define IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QXP_EMMC0_DATA7 0
+#define IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QXP_EMMC0_DATA7 1
+#define IMX8QXP_EMMC0_DATA7_CONN_MLB_SIG IMX8QXP_EMMC0_DATA7 3
+#define IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8QXP_EMMC0_DATA7 4
+#define IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QXP_EMMC0_STROBE 0
+#define IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE IMX8QXP_EMMC0_STROBE 1
+#define IMX8QXP_EMMC0_STROBE_CONN_MLB_DATA IMX8QXP_EMMC0_STROBE 3
+#define IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8QXP_EMMC0_STROBE 4
+#define IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QXP_EMMC0_RESET_B 0
+#define IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QXP_EMMC0_RESET_B 1
+#define IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8QXP_EMMC0_RESET_B 4
+#define IMX8QXP_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QXP_USDHC1_RESET_B 0
+#define IMX8QXP_USDHC1_RESET_B_CONN_NAND_RE_N IMX8QXP_USDHC1_RESET_B 1
+#define IMX8QXP_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8QXP_USDHC1_RESET_B 2
+#define IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8QXP_USDHC1_RESET_B 4
+#define IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QXP_USDHC1_VSELECT 0
+#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_P IMX8QXP_USDHC1_VSELECT 1
+#define IMX8QXP_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8QXP_USDHC1_VSELECT 2
+#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B IMX8QXP_USDHC1_VSELECT 3
+#define IMX8QXP_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8QXP_USDHC1_VSELECT 4
+#define IMX8QXP_USDHC1_WP_CONN_USDHC1_WP IMX8QXP_USDHC1_WP 0
+#define IMX8QXP_USDHC1_WP_CONN_NAND_DQS_N IMX8QXP_USDHC1_WP 1
+#define IMX8QXP_USDHC1_WP_ADMA_SPI2_SDI IMX8QXP_USDHC1_WP 2
+#define IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 IMX8QXP_USDHC1_WP 4
+#define IMX8QXP_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8QXP_USDHC1_CD_B 0
+#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS_P IMX8QXP_USDHC1_CD_B 1
+#define IMX8QXP_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8QXP_USDHC1_CD_B 2
+#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS IMX8QXP_USDHC1_CD_B 3
+#define IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8QXP_USDHC1_CD_B 4
+#define IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK IMX8QXP_USDHC1_CLK 0
+#define IMX8QXP_USDHC1_CLK_ADMA_UART3_RX IMX8QXP_USDHC1_CLK 2
+#define IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 IMX8QXP_USDHC1_CLK 4
+#define IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD IMX8QXP_USDHC1_CMD 0
+#define IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B IMX8QXP_USDHC1_CMD 1
+#define IMX8QXP_USDHC1_CMD_ADMA_MQS_R IMX8QXP_USDHC1_CMD 2
+#define IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 IMX8QXP_USDHC1_CMD 4
+#define IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QXP_USDHC1_DATA0 0
+#define IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B IMX8QXP_USDHC1_DATA0 1
+#define IMX8QXP_USDHC1_DATA0_ADMA_MQS_L IMX8QXP_USDHC1_DATA0 2
+#define IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 IMX8QXP_USDHC1_DATA0 4
+#define IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QXP_USDHC1_DATA1 0
+#define IMX8QXP_USDHC1_DATA1_CONN_NAND_RE_B IMX8QXP_USDHC1_DATA1 1
+#define IMX8QXP_USDHC1_DATA1_ADMA_UART3_TX IMX8QXP_USDHC1_DATA1 2
+#define IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 IMX8QXP_USDHC1_DATA1 4
+#define IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QXP_USDHC1_DATA2 0
+#define IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B IMX8QXP_USDHC1_DATA2 1
+#define IMX8QXP_USDHC1_DATA2_ADMA_UART3_CTS_B IMX8QXP_USDHC1_DATA2 2
+#define IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 IMX8QXP_USDHC1_DATA2 4
+#define IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QXP_USDHC1_DATA3 0
+#define IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE IMX8QXP_USDHC1_DATA3 1
+#define IMX8QXP_USDHC1_DATA3_ADMA_UART3_RTS_B IMX8QXP_USDHC1_DATA3 2
+#define IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 IMX8QXP_USDHC1_DATA3 4
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QXP_ENET0_RGMII_TXC 0
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QXP_ENET0_RGMII_TXC 1
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QXP_ENET0_RGMII_TXC 2
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8QXP_ENET0_RGMII_TXC 3
+#define IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8QXP_ENET0_RGMII_TXC 4
+#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QXP_ENET0_RGMII_TX_CTL 0
+#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8QXP_ENET0_RGMII_TX_CTL 3
+#define IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8QXP_ENET0_RGMII_TX_CTL 4
+#define IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QXP_ENET0_RGMII_TXD0 0
+#define IMX8QXP_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8QXP_ENET0_RGMII_TXD0 3
+#define IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8QXP_ENET0_RGMII_TXD0 4
+#define IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QXP_ENET0_RGMII_TXD1 0
+#define IMX8QXP_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8QXP_ENET0_RGMII_TXD1 3
+#define IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8QXP_ENET0_RGMII_TXD1 4
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QXP_ENET0_RGMII_TXD2 0
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_MLB_CLK IMX8QXP_ENET0_RGMII_TXD2 1
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8QXP_ENET0_RGMII_TXD2 2
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8QXP_ENET0_RGMII_TXD2 3
+#define IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8QXP_ENET0_RGMII_TXD2 4
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QXP_ENET0_RGMII_TXD3 0
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_MLB_SIG IMX8QXP_ENET0_RGMII_TXD3 1
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8QXP_ENET0_RGMII_TXD3 2
+#define IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8QXP_ENET0_RGMII_TXD3 4
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QXP_ENET0_RGMII_RXC 0
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_MLB_DATA IMX8QXP_ENET0_RGMII_RXC 1
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8QXP_ENET0_RGMII_RXC 2
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8QXP_ENET0_RGMII_RXC 3
+#define IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8QXP_ENET0_RGMII_RXC 4
+#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QXP_ENET0_RGMII_RX_CTL 0
+#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8QXP_ENET0_RGMII_RX_CTL 3
+#define IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8QXP_ENET0_RGMII_RX_CTL 4
+#define IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QXP_ENET0_RGMII_RXD0 0
+#define IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8QXP_ENET0_RGMII_RXD0 3
+#define IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8QXP_ENET0_RGMII_RXD0 4
+#define IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QXP_ENET0_RGMII_RXD1 0
+#define IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8QXP_ENET0_RGMII_RXD1 3
+#define IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8QXP_ENET0_RGMII_RXD1 4
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QXP_ENET0_RGMII_RXD2 0
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QXP_ENET0_RGMII_RXD2 1
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8QXP_ENET0_RGMII_RXD2 3
+#define IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8QXP_ENET0_RGMII_RXD2 4
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QXP_ENET0_RGMII_RXD3 0
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8QXP_ENET0_RGMII_RXD3 2
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8QXP_ENET0_RGMII_RXD3 3
+#define IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8QXP_ENET0_RGMII_RXD3 4
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QXP_ENET0_REFCLK_125M_25M 0
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QXP_ENET0_REFCLK_125M_25M 1
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QXP_ENET0_REFCLK_125M_25M 2
+#define IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8QXP_ENET0_REFCLK_125M_25M 4
+#define IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO IMX8QXP_ENET0_MDIO 0
+#define IMX8QXP_ENET0_MDIO_ADMA_I2C3_SDA IMX8QXP_ENET0_MDIO 1
+#define IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO IMX8QXP_ENET0_MDIO 2
+#define IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8QXP_ENET0_MDIO 4
+#define IMX8QXP_ENET0_MDC_CONN_ENET0_MDC IMX8QXP_ENET0_MDC 0
+#define IMX8QXP_ENET0_MDC_ADMA_I2C3_SCL IMX8QXP_ENET0_MDC 1
+#define IMX8QXP_ENET0_MDC_CONN_ENET1_MDC IMX8QXP_ENET0_MDC 2
+#define IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 IMX8QXP_ENET0_MDC 4
+#define IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR IMX8QXP_ESAI0_FSR 0
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT IMX8QXP_ESAI0_FSR 1
+#define IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 IMX8QXP_ESAI0_FSR 2
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC IMX8QXP_ESAI0_FSR 3
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN IMX8QXP_ESAI0_FSR 4
+#define IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST IMX8QXP_ESAI0_FST 0
+#define IMX8QXP_ESAI0_FST_CONN_MLB_CLK IMX8QXP_ESAI0_FST 1
+#define IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 IMX8QXP_ESAI0_FST 2
+#define IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 IMX8QXP_ESAI0_FST 3
+#define IMX8QXP_ESAI0_FST_LSIO_GPIO0_IO01 IMX8QXP_ESAI0_FST 4
+#define IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR IMX8QXP_ESAI0_SCKR 0
+#define IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 IMX8QXP_ESAI0_SCKR 2
+#define IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL IMX8QXP_ESAI0_SCKR 3
+#define IMX8QXP_ESAI0_SCKR_LSIO_GPIO0_IO02 IMX8QXP_ESAI0_SCKR 4
+#define IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT IMX8QXP_ESAI0_SCKT 0
+#define IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG IMX8QXP_ESAI0_SCKT 1
+#define IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 IMX8QXP_ESAI0_SCKT 2
+#define IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 IMX8QXP_ESAI0_SCKT 3
+#define IMX8QXP_ESAI0_SCKT_LSIO_GPIO0_IO03 IMX8QXP_ESAI0_SCKT 4
+#define IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 IMX8QXP_ESAI0_TX0 0
+#define IMX8QXP_ESAI0_TX0_CONN_MLB_DATA IMX8QXP_ESAI0_TX0 1
+#define IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 IMX8QXP_ESAI0_TX0 2
+#define IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC IMX8QXP_ESAI0_TX0 3
+#define IMX8QXP_ESAI0_TX0_LSIO_GPIO0_IO04 IMX8QXP_ESAI0_TX0 4
+#define IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 IMX8QXP_ESAI0_TX1 0
+#define IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 IMX8QXP_ESAI0_TX1 2
+#define IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 IMX8QXP_ESAI0_TX1 3
+#define IMX8QXP_ESAI0_TX1_LSIO_GPIO0_IO05 IMX8QXP_ESAI0_TX1 4
+#define IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 IMX8QXP_ESAI0_TX2_RX3 0
+#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER IMX8QXP_ESAI0_TX2_RX3 1
+#define IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 IMX8QXP_ESAI0_TX2_RX3 2
+#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 IMX8QXP_ESAI0_TX2_RX3 3
+#define IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 IMX8QXP_ESAI0_TX2_RX3 4
+#define IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 IMX8QXP_ESAI0_TX3_RX2 0
+#define IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 IMX8QXP_ESAI0_TX3_RX2 2
+#define IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 IMX8QXP_ESAI0_TX3_RX2 3
+#define IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 IMX8QXP_ESAI0_TX3_RX2 4
+#define IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 IMX8QXP_ESAI0_TX4_RX1 0
+#define IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 IMX8QXP_ESAI0_TX4_RX1 2
+#define IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 IMX8QXP_ESAI0_TX4_RX1 3
+#define IMX8QXP_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 IMX8QXP_ESAI0_TX4_RX1 4
+#define IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 IMX8QXP_ESAI0_TX5_RX0 0
+#define IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 IMX8QXP_ESAI0_TX5_RX0 2
+#define IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 IMX8QXP_ESAI0_TX5_RX0 3
+#define IMX8QXP_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 IMX8QXP_ESAI0_TX5_RX0 4
+#define IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX IMX8QXP_SPDIF0_RX 0
+#define IMX8QXP_SPDIF0_RX_ADMA_MQS_R IMX8QXP_SPDIF0_RX 1
+#define IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 IMX8QXP_SPDIF0_RX 2
+#define IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 IMX8QXP_SPDIF0_RX 3
+#define IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10 IMX8QXP_SPDIF0_RX 4
+#define IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX IMX8QXP_SPDIF0_TX 0
+#define IMX8QXP_SPDIF0_TX_ADMA_MQS_L IMX8QXP_SPDIF0_TX 1
+#define IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 IMX8QXP_SPDIF0_TX 2
+#define IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL IMX8QXP_SPDIF0_TX 3
+#define IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11 IMX8QXP_SPDIF0_TX 4
+#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK IMX8QXP_SPDIF0_EXT_CLK 0
+#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 IMX8QXP_SPDIF0_EXT_CLK 2
+#define IMX8QXP_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M IMX8QXP_SPDIF0_EXT_CLK 3
+#define IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 IMX8QXP_SPDIF0_EXT_CLK 4
+#define IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK IMX8QXP_SPI3_SCK 0
+#define IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 IMX8QXP_SPI3_SCK 2
+#define IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 IMX8QXP_SPI3_SCK 4
+#define IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO IMX8QXP_SPI3_SDO 0
+#define IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 IMX8QXP_SPI3_SDO 2
+#define IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 IMX8QXP_SPI3_SDO 4
+#define IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI IMX8QXP_SPI3_SDI 0
+#define IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 IMX8QXP_SPI3_SDI 2
+#define IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 IMX8QXP_SPI3_SDI 4
+#define IMX8QXP_SPI3_CS0_ADMA_SPI3_CS0 IMX8QXP_SPI3_CS0 0
+#define IMX8QXP_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8QXP_SPI3_CS0 1
+#define IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8QXP_SPI3_CS0 2
+#define IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 IMX8QXP_SPI3_CS0 4
+#define IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 IMX8QXP_SPI3_CS1 0
+#define IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL IMX8QXP_SPI3_CS1 1
+#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET IMX8QXP_SPI3_CS1 2
+#define IMX8QXP_SPI3_CS1_ADMA_SPI2_CS0 IMX8QXP_SPI3_CS1 3
+#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 IMX8QXP_SPI3_CS1 4
+#define IMX8QXP_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8QXP_MCLK_IN1 0
+#define IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA IMX8QXP_MCLK_IN1 1
+#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN IMX8QXP_MCLK_IN1 2
+#define IMX8QXP_MCLK_IN1_ADMA_SPI2_SCK IMX8QXP_MCLK_IN1 3
+#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_D17 IMX8QXP_MCLK_IN1 4
+#define IMX8QXP_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8QXP_MCLK_IN0 0
+#define IMX8QXP_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK IMX8QXP_MCLK_IN0 1
+#define IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8QXP_MCLK_IN0 2
+#define IMX8QXP_MCLK_IN0_ADMA_SPI2_SDI IMX8QXP_MCLK_IN0 3
+#define IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19 IMX8QXP_MCLK_IN0 4
+#define IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8QXP_MCLK_OUT0 0
+#define IMX8QXP_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK IMX8QXP_MCLK_OUT0 1
+#define IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK IMX8QXP_MCLK_OUT0 2
+#define IMX8QXP_MCLK_OUT0_ADMA_SPI2_SDO IMX8QXP_MCLK_OUT0 3
+#define IMX8QXP_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8QXP_MCLK_OUT0 4
+#define IMX8QXP_UART1_TX_ADMA_UART1_TX IMX8QXP_UART1_TX 0
+#define IMX8QXP_UART1_TX_LSIO_PWM0_OUT IMX8QXP_UART1_TX 1
+#define IMX8QXP_UART1_TX_LSIO_GPT0_CAPTURE IMX8QXP_UART1_TX 2
+#define IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 IMX8QXP_UART1_TX 4
+#define IMX8QXP_UART1_RX_ADMA_UART1_RX IMX8QXP_UART1_RX 0
+#define IMX8QXP_UART1_RX_LSIO_PWM1_OUT IMX8QXP_UART1_RX 1
+#define IMX8QXP_UART1_RX_LSIO_GPT0_COMPARE IMX8QXP_UART1_RX 2
+#define IMX8QXP_UART1_RX_LSIO_GPT1_CLK IMX8QXP_UART1_RX 3
+#define IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 IMX8QXP_UART1_RX 4
+#define IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B IMX8QXP_UART1_RTS_B 0
+#define IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT IMX8QXP_UART1_RTS_B 1
+#define IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 IMX8QXP_UART1_RTS_B 2
+#define IMX8QXP_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8QXP_UART1_RTS_B 3
+#define IMX8QXP_UART1_RTS_B_LSIO_GPT0_CLK IMX8QXP_UART1_RTS_B 4
+#define IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B IMX8QXP_UART1_CTS_B 0
+#define IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT IMX8QXP_UART1_CTS_B 1
+#define IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 IMX8QXP_UART1_CTS_B 2
+#define IMX8QXP_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8QXP_UART1_CTS_B 3
+#define IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8QXP_UART1_CTS_B 4
+#define IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD IMX8QXP_SAI0_TXD 0
+#define IMX8QXP_SAI0_TXD_ADMA_SAI1_RXC IMX8QXP_SAI0_TXD 1
+#define IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO IMX8QXP_SAI0_TXD 2
+#define IMX8QXP_SAI0_TXD_ADMA_LCDIF_D18 IMX8QXP_SAI0_TXD 3
+#define IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 IMX8QXP_SAI0_TXD 4
+#define IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC IMX8QXP_SAI0_TXC 0
+#define IMX8QXP_SAI0_TXC_ADMA_SAI1_TXD IMX8QXP_SAI0_TXC 1
+#define IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI IMX8QXP_SAI0_TXC 2
+#define IMX8QXP_SAI0_TXC_ADMA_LCDIF_D19 IMX8QXP_SAI0_TXC 3
+#define IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 IMX8QXP_SAI0_TXC 4
+#define IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD IMX8QXP_SAI0_RXD 0
+#define IMX8QXP_SAI0_RXD_ADMA_SAI1_RXFS IMX8QXP_SAI0_RXD 1
+#define IMX8QXP_SAI0_RXD_ADMA_SPI1_CS0 IMX8QXP_SAI0_RXD 2
+#define IMX8QXP_SAI0_RXD_ADMA_LCDIF_D20 IMX8QXP_SAI0_RXD 3
+#define IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 IMX8QXP_SAI0_RXD 4
+#define IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS IMX8QXP_SAI0_TXFS 0
+#define IMX8QXP_SAI0_TXFS_ADMA_SPI2_CS1 IMX8QXP_SAI0_TXFS 1
+#define IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK IMX8QXP_SAI0_TXFS 2
+#define IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 IMX8QXP_SAI0_TXFS 4
+#define IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD IMX8QXP_SAI1_RXD 0
+#define IMX8QXP_SAI1_RXD_ADMA_SAI0_RXFS IMX8QXP_SAI1_RXD 1
+#define IMX8QXP_SAI1_RXD_ADMA_SPI1_CS1 IMX8QXP_SAI1_RXD 2
+#define IMX8QXP_SAI1_RXD_ADMA_LCDIF_D21 IMX8QXP_SAI1_RXD 3
+#define IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 IMX8QXP_SAI1_RXD 4
+#define IMX8QXP_SAI1_RXC_ADMA_SAI1_RXC IMX8QXP_SAI1_RXC 0
+#define IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC IMX8QXP_SAI1_RXC 1
+#define IMX8QXP_SAI1_RXC_ADMA_LCDIF_D22 IMX8QXP_SAI1_RXC 3
+#define IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 IMX8QXP_SAI1_RXC 4
+#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_RXFS IMX8QXP_SAI1_RXFS 0
+#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS IMX8QXP_SAI1_RXFS 1
+#define IMX8QXP_SAI1_RXFS_ADMA_LCDIF_D23 IMX8QXP_SAI1_RXFS 3
+#define IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 IMX8QXP_SAI1_RXFS 4
+#define IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 IMX8QXP_SPI2_CS0 0
+#define IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 IMX8QXP_SPI2_CS0 4
+#define IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO IMX8QXP_SPI2_SDO 0
+#define IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 IMX8QXP_SPI2_SDO 4
+#define IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI IMX8QXP_SPI2_SDI 0
+#define IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 IMX8QXP_SPI2_SDI 4
+#define IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK IMX8QXP_SPI2_SCK 0
+#define IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 IMX8QXP_SPI2_SCK 4
+#define IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK IMX8QXP_SPI0_SCK 0
+#define IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC IMX8QXP_SPI0_SCK 1
+#define IMX8QXP_SPI0_SCK_M40_I2C0_SCL IMX8QXP_SPI0_SCK 2
+#define IMX8QXP_SPI0_SCK_M40_GPIO0_IO00 IMX8QXP_SPI0_SCK 3
+#define IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 IMX8QXP_SPI0_SCK 4
+#define IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI IMX8QXP_SPI0_SDI 0
+#define IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD IMX8QXP_SPI0_SDI 1
+#define IMX8QXP_SPI0_SDI_M40_TPM0_CH0 IMX8QXP_SPI0_SDI 2
+#define IMX8QXP_SPI0_SDI_M40_GPIO0_IO02 IMX8QXP_SPI0_SDI 3
+#define IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 IMX8QXP_SPI0_SDI 4
+#define IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO IMX8QXP_SPI0_SDO 0
+#define IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS IMX8QXP_SPI0_SDO 1
+#define IMX8QXP_SPI0_SDO_M40_I2C0_SDA IMX8QXP_SPI0_SDO 2
+#define IMX8QXP_SPI0_SDO_M40_GPIO0_IO01 IMX8QXP_SPI0_SDO 3
+#define IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 IMX8QXP_SPI0_SDO 4
+#define IMX8QXP_SPI0_CS1_ADMA_SPI0_CS1 IMX8QXP_SPI0_CS1 0
+#define IMX8QXP_SPI0_CS1_ADMA_SAI0_RXC IMX8QXP_SPI0_CS1 1
+#define IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD IMX8QXP_SPI0_CS1 2
+#define IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8QXP_SPI0_CS1 3
+#define IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 IMX8QXP_SPI0_CS1 4
+#define IMX8QXP_SPI0_CS0_ADMA_SPI0_CS0 IMX8QXP_SPI0_CS0 0
+#define IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD IMX8QXP_SPI0_CS0 1
+#define IMX8QXP_SPI0_CS0_M40_TPM0_CH1 IMX8QXP_SPI0_CS0 2
+#define IMX8QXP_SPI0_CS0_M40_GPIO0_IO03 IMX8QXP_SPI0_CS0 3
+#define IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 IMX8QXP_SPI0_CS0 4
+#define IMX8QXP_ADC_IN1_ADMA_ADC_IN1 IMX8QXP_ADC_IN1 0
+#define IMX8QXP_ADC_IN1_M40_I2C0_SDA IMX8QXP_ADC_IN1 1
+#define IMX8QXP_ADC_IN1_M40_GPIO0_IO01 IMX8QXP_ADC_IN1 2
+#define IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 IMX8QXP_ADC_IN1 4
+#define IMX8QXP_ADC_IN0_ADMA_ADC_IN0 IMX8QXP_ADC_IN0 0
+#define IMX8QXP_ADC_IN0_M40_I2C0_SCL IMX8QXP_ADC_IN0 1
+#define IMX8QXP_ADC_IN0_M40_GPIO0_IO00 IMX8QXP_ADC_IN0 2
+#define IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 IMX8QXP_ADC_IN0 4
+#define IMX8QXP_ADC_IN3_ADMA_ADC_IN3 IMX8QXP_ADC_IN3 0
+#define IMX8QXP_ADC_IN3_M40_UART0_TX IMX8QXP_ADC_IN3 1
+#define IMX8QXP_ADC_IN3_M40_GPIO0_IO03 IMX8QXP_ADC_IN3 2
+#define IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8QXP_ADC_IN3 3
+#define IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 IMX8QXP_ADC_IN3 4
+#define IMX8QXP_ADC_IN2_ADMA_ADC_IN2 IMX8QXP_ADC_IN2 0
+#define IMX8QXP_ADC_IN2_M40_UART0_RX IMX8QXP_ADC_IN2 1
+#define IMX8QXP_ADC_IN2_M40_GPIO0_IO02 IMX8QXP_ADC_IN2 2
+#define IMX8QXP_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8QXP_ADC_IN2 3
+#define IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 IMX8QXP_ADC_IN2 4
+#define IMX8QXP_ADC_IN5_ADMA_ADC_IN5 IMX8QXP_ADC_IN5 0
+#define IMX8QXP_ADC_IN5_M40_TPM0_CH1 IMX8QXP_ADC_IN5 1
+#define IMX8QXP_ADC_IN5_M40_GPIO0_IO05 IMX8QXP_ADC_IN5 2
+#define IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 IMX8QXP_ADC_IN5 4
+#define IMX8QXP_ADC_IN4_ADMA_ADC_IN4 IMX8QXP_ADC_IN4 0
+#define IMX8QXP_ADC_IN4_M40_TPM0_CH0 IMX8QXP_ADC_IN4 1
+#define IMX8QXP_ADC_IN4_M40_GPIO0_IO04 IMX8QXP_ADC_IN4 2
+#define IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 IMX8QXP_ADC_IN4 4
+#define IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8QXP_FLEXCAN0_RX 0
+#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8QXP_FLEXCAN0_RX 1
+#define IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8QXP_FLEXCAN0_RX 2
+#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8QXP_FLEXCAN0_RX 3
+#define IMX8QXP_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8QXP_FLEXCAN0_RX 4
+#define IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8QXP_FLEXCAN0_TX 0
+#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8QXP_FLEXCAN0_TX 1
+#define IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8QXP_FLEXCAN0_TX 2
+#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8QXP_FLEXCAN0_TX 3
+#define IMX8QXP_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8QXP_FLEXCAN0_TX 4
+#define IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8QXP_FLEXCAN1_RX 0
+#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8QXP_FLEXCAN1_RX 1
+#define IMX8QXP_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8QXP_FLEXCAN1_RX 2
+#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8QXP_FLEXCAN1_RX 3
+#define IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8QXP_FLEXCAN1_RX 4
+#define IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8QXP_FLEXCAN1_TX 0
+#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8QXP_FLEXCAN1_TX 1
+#define IMX8QXP_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8QXP_FLEXCAN1_TX 2
+#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8QXP_FLEXCAN1_TX 3
+#define IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8QXP_FLEXCAN1_TX 4
+#define IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8QXP_FLEXCAN2_RX 0
+#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8QXP_FLEXCAN2_RX 1
+#define IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX IMX8QXP_FLEXCAN2_RX 2
+#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8QXP_FLEXCAN2_RX 3
+#define IMX8QXP_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8QXP_FLEXCAN2_RX 4
+#define IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8QXP_FLEXCAN2_TX 0
+#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8QXP_FLEXCAN2_TX 1
+#define IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX IMX8QXP_FLEXCAN2_TX 2
+#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8QXP_FLEXCAN2_TX 3
+#define IMX8QXP_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8QXP_FLEXCAN2_TX 4
+#define IMX8QXP_UART0_RX_ADMA_UART0_RX IMX8QXP_UART0_RX 0
+#define IMX8QXP_UART0_RX_ADMA_MQS_R IMX8QXP_UART0_RX 1
+#define IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX IMX8QXP_UART0_RX 2
+#define IMX8QXP_UART0_RX_LSIO_GPIO1_IO21 IMX8QXP_UART0_RX 4
+#define IMX8QXP_UART0_TX_ADMA_UART0_TX IMX8QXP_UART0_TX 0
+#define IMX8QXP_UART0_TX_ADMA_MQS_L IMX8QXP_UART0_TX 1
+#define IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX IMX8QXP_UART0_TX 2
+#define IMX8QXP_UART0_TX_LSIO_GPIO1_IO22 IMX8QXP_UART0_TX 4
+#define IMX8QXP_UART2_TX_ADMA_UART2_TX IMX8QXP_UART2_TX 0
+#define IMX8QXP_UART2_TX_ADMA_FTM_CH1 IMX8QXP_UART2_TX 1
+#define IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX IMX8QXP_UART2_TX 2
+#define IMX8QXP_UART2_TX_LSIO_GPIO1_IO23 IMX8QXP_UART2_TX 4
+#define IMX8QXP_UART2_RX_ADMA_UART2_RX IMX8QXP_UART2_RX 0
+#define IMX8QXP_UART2_RX_ADMA_FTM_CH0 IMX8QXP_UART2_RX 1
+#define IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX IMX8QXP_UART2_RX 2
+#define IMX8QXP_UART2_RX_LSIO_GPIO1_IO24 IMX8QXP_UART2_RX 4
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QXP_MIPI_DSI0_I2C0_SCL 0
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 IMX8QXP_MIPI_DSI0_I2C0_SCL 1
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QXP_MIPI_DSI0_I2C0_SCL 4
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QXP_MIPI_DSI0_I2C0_SDA 0
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 IMX8QXP_MIPI_DSI0_I2C0_SDA 1
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QXP_MIPI_DSI0_I2C0_SDA 4
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QXP_MIPI_DSI0_GPIO0_00 0
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL IMX8QXP_MIPI_DSI0_GPIO0_00 1
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QXP_MIPI_DSI0_GPIO0_00 2
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QXP_MIPI_DSI0_GPIO0_00 4
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QXP_MIPI_DSI0_GPIO0_01 0
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA IMX8QXP_MIPI_DSI0_GPIO0_01 1
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QXP_MIPI_DSI0_GPIO0_01 4
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QXP_MIPI_DSI1_I2C0_SCL 0
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 IMX8QXP_MIPI_DSI1_I2C0_SCL 1
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 IMX8QXP_MIPI_DSI1_I2C0_SCL 4
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QXP_MIPI_DSI1_I2C0_SDA 0
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 IMX8QXP_MIPI_DSI1_I2C0_SDA 1
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 IMX8QXP_MIPI_DSI1_I2C0_SDA 4
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QXP_MIPI_DSI1_GPIO0_00 0
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL IMX8QXP_MIPI_DSI1_GPIO0_00 1
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QXP_MIPI_DSI1_GPIO0_00 2
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 IMX8QXP_MIPI_DSI1_GPIO0_00 4
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QXP_MIPI_DSI1_GPIO0_01 0
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA IMX8QXP_MIPI_DSI1_GPIO0_01 1
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 IMX8QXP_MIPI_DSI1_GPIO0_01 4
+#define IMX8QXP_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8QXP_JTAG_TRST_B 0
+#define IMX8QXP_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8QXP_JTAG_TRST_B 1
+#define IMX8QXP_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QXP_PMIC_I2C_SCL 0
+#define IMX8QXP_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8QXP_PMIC_I2C_SCL 1
+#define IMX8QXP_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8QXP_PMIC_I2C_SCL 4
+#define IMX8QXP_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QXP_PMIC_I2C_SDA 0
+#define IMX8QXP_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8QXP_PMIC_I2C_SDA 1
+#define IMX8QXP_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8QXP_PMIC_I2C_SDA 4
+#define IMX8QXP_PMIC_INT_B_SCU_DIMX8QXPMIC_INT_B IMX8QXP_PMIC_INT_B 0
+#define IMX8QXP_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QXP_SCU_GPIO0_00 0
+#define IMX8QXP_SCU_GPIO0_00_SCU_UART0_RX IMX8QXP_SCU_GPIO0_00 1
+#define IMX8QXP_SCU_GPIO0_00_M40_UART0_RX IMX8QXP_SCU_GPIO0_00 2
+#define IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX IMX8QXP_SCU_GPIO0_00 3
+#define IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8QXP_SCU_GPIO0_00 4
+#define IMX8QXP_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QXP_SCU_GPIO0_01 0
+#define IMX8QXP_SCU_GPIO0_01_SCU_UART0_TX IMX8QXP_SCU_GPIO0_01 1
+#define IMX8QXP_SCU_GPIO0_01_M40_UART0_TX IMX8QXP_SCU_GPIO0_01 2
+#define IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX IMX8QXP_SCU_GPIO0_01 3
+#define IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8QXP_SCU_GPIO0_01 4
+#define IMX8QXP_SCU_PMIC_STANDBY_SCU_DIMX8QXPMIC_STANDBY IMX8QXP_SCU_PMIC_STANDBY 0
+#define IMX8QXP_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QXP_SCU_BOOT_MODE0 0
+#define IMX8QXP_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QXP_SCU_BOOT_MODE1 0
+#define IMX8QXP_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QXP_SCU_BOOT_MODE2 0
+#define IMX8QXP_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA IMX8QXP_SCU_BOOT_MODE2 1
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QXP_SCU_BOOT_MODE3 0
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL IMX8QXP_SCU_BOOT_MODE3 1
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QXP_SCU_BOOT_MODE3 3
+#define IMX8QXP_CSI_D00_CI_PI_D02 IMX8QXP_CSI_D00 0
+#define IMX8QXP_CSI_D00_ADMA_SAI0_RXC IMX8QXP_CSI_D00 2
+#define IMX8QXP_CSI_D01_CI_PI_D03 IMX8QXP_CSI_D01 0
+#define IMX8QXP_CSI_D01_ADMA_SAI0_RXD IMX8QXP_CSI_D01 2
+#define IMX8QXP_CSI_D02_CI_PI_D04 IMX8QXP_CSI_D02 0
+#define IMX8QXP_CSI_D02_ADMA_SAI0_RXFS IMX8QXP_CSI_D02 2
+#define IMX8QXP_CSI_D03_CI_PI_D05 IMX8QXP_CSI_D03 0
+#define IMX8QXP_CSI_D03_ADMA_SAI2_RXC IMX8QXP_CSI_D03 2
+#define IMX8QXP_CSI_D04_CI_PI_D06 IMX8QXP_CSI_D04 0
+#define IMX8QXP_CSI_D04_ADMA_SAI2_RXD IMX8QXP_CSI_D04 2
+#define IMX8QXP_CSI_D05_CI_PI_D07 IMX8QXP_CSI_D05 0
+#define IMX8QXP_CSI_D05_ADMA_SAI2_RXFS IMX8QXP_CSI_D05 2
+#define IMX8QXP_CSI_D06_CI_PI_D08 IMX8QXP_CSI_D06 0
+#define IMX8QXP_CSI_D06_ADMA_SAI3_RXC IMX8QXP_CSI_D06 2
+#define IMX8QXP_CSI_D07_CI_PI_D09 IMX8QXP_CSI_D07 0
+#define IMX8QXP_CSI_D07_ADMA_SAI3_RXD IMX8QXP_CSI_D07 2
+#define IMX8QXP_CSI_HSYNC_CI_PI_HSYNC IMX8QXP_CSI_HSYNC 0
+#define IMX8QXP_CSI_HSYNC_CI_PI_D00 IMX8QXP_CSI_HSYNC 1
+#define IMX8QXP_CSI_HSYNC_ADMA_SAI3_RXFS IMX8QXP_CSI_HSYNC 2
+#define IMX8QXP_CSI_VSYNC_CI_PI_VSYNC IMX8QXP_CSI_VSYNC 0
+#define IMX8QXP_CSI_VSYNC_CI_PI_D01 IMX8QXP_CSI_VSYNC 1
+#define IMX8QXP_CSI_PCLK_CI_PI_PCLK IMX8QXP_CSI_PCLK 0
+#define IMX8QXP_CSI_PCLK_MIPI_CSI0_I2C0_SCL IMX8QXP_CSI_PCLK 1
+#define IMX8QXP_CSI_PCLK_ADMA_SPI1_SCK IMX8QXP_CSI_PCLK 3
+#define IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 IMX8QXP_CSI_PCLK 4
+#define IMX8QXP_CSI_MCLK_CI_PI_MCLK IMX8QXP_CSI_MCLK 0
+#define IMX8QXP_CSI_MCLK_MIPI_CSI0_I2C0_SDA IMX8QXP_CSI_MCLK 1
+#define IMX8QXP_CSI_MCLK_ADMA_SPI1_SDO IMX8QXP_CSI_MCLK 3
+#define IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 IMX8QXP_CSI_MCLK 4
+#define IMX8QXP_CSI_EN_CI_PI_EN IMX8QXP_CSI_EN 0
+#define IMX8QXP_CSI_EN_CI_PI_I2C_SCL IMX8QXP_CSI_EN 1
+#define IMX8QXP_CSI_EN_ADMA_I2C3_SCL IMX8QXP_CSI_EN 2
+#define IMX8QXP_CSI_EN_ADMA_SPI1_SDI IMX8QXP_CSI_EN 3
+#define IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 IMX8QXP_CSI_EN 4
+#define IMX8QXP_CSI_RESET_CI_PI_RESET IMX8QXP_CSI_RESET 0
+#define IMX8QXP_CSI_RESET_CI_PI_I2C_SDA IMX8QXP_CSI_RESET 1
+#define IMX8QXP_CSI_RESET_ADMA_I2C3_SDA IMX8QXP_CSI_RESET 2
+#define IMX8QXP_CSI_RESET_ADMA_SPI1_CS0 IMX8QXP_CSI_RESET 3
+#define IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 IMX8QXP_CSI_RESET 4
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QXP_MIPI_CSI0_MCLK_OUT 0
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 IMX8QXP_MIPI_CSI0_MCLK_OUT 4
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QXP_MIPI_CSI0_I2C0_SCL 0
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 IMX8QXP_MIPI_CSI0_I2C0_SCL 1
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 IMX8QXP_MIPI_CSI0_I2C0_SCL 4
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QXP_MIPI_CSI0_I2C0_SDA 0
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 IMX8QXP_MIPI_CSI0_I2C0_SDA 1
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 IMX8QXP_MIPI_CSI0_I2C0_SDA 4
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QXP_MIPI_CSI0_GPIO0_01 0
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA IMX8QXP_MIPI_CSI0_GPIO0_01 1
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 IMX8QXP_MIPI_CSI0_GPIO0_01 4
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QXP_MIPI_CSI0_GPIO0_00 0
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL IMX8QXP_MIPI_CSI0_GPIO0_00 1
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 IMX8QXP_MIPI_CSI0_GPIO0_00 4
+#define IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QXP_QSPI0A_DATA0 0
+#define IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8QXP_QSPI0A_DATA0 4
+#define IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QXP_QSPI0A_DATA1 0
+#define IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8QXP_QSPI0A_DATA1 4
+#define IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QXP_QSPI0A_DATA2 0
+#define IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8QXP_QSPI0A_DATA2 4
+#define IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QXP_QSPI0A_DATA3 0
+#define IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8QXP_QSPI0A_DATA3 4
+#define IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QXP_QSPI0A_DQS 0
+#define IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8QXP_QSPI0A_DQS 4
+#define IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QXP_QSPI0A_SS0_B 0
+#define IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8QXP_QSPI0A_SS0_B 4
+#define IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QXP_QSPI0A_SS1_B 0
+#define IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 IMX8QXP_QSPI0A_SS1_B 4
+#define IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QXP_QSPI0A_SCLK 0
+#define IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8QXP_QSPI0A_SCLK 4
+#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QXP_QSPI0B_SCLK 0
+#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI1A_SCLK IMX8QXP_QSPI0B_SCLK 1
+#define IMX8QXP_QSPI0B_SCLK_LSIO_KPP0_COL0 IMX8QXP_QSPI0B_SCLK 2
+#define IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8QXP_QSPI0B_SCLK 4
+#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QXP_QSPI0B_DATA0 0
+#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 IMX8QXP_QSPI0B_DATA0 1
+#define IMX8QXP_QSPI0B_DATA0_LSIO_KPP0_COL1 IMX8QXP_QSPI0B_DATA0 2
+#define IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8QXP_QSPI0B_DATA0 4
+#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QXP_QSPI0B_DATA1 0
+#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 IMX8QXP_QSPI0B_DATA1 1
+#define IMX8QXP_QSPI0B_DATA1_LSIO_KPP0_COL2 IMX8QXP_QSPI0B_DATA1 2
+#define IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8QXP_QSPI0B_DATA1 4
+#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QXP_QSPI0B_DATA2 0
+#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 IMX8QXP_QSPI0B_DATA2 1
+#define IMX8QXP_QSPI0B_DATA2_LSIO_KPP0_COL3 IMX8QXP_QSPI0B_DATA2 2
+#define IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8QXP_QSPI0B_DATA2 4
+#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QXP_QSPI0B_DATA3 0
+#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 IMX8QXP_QSPI0B_DATA3 1
+#define IMX8QXP_QSPI0B_DATA3_LSIO_KPP0_ROW0 IMX8QXP_QSPI0B_DATA3 2
+#define IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8QXP_QSPI0B_DATA3 4
+#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QXP_QSPI0B_DQS 0
+#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI1A_DQS IMX8QXP_QSPI0B_DQS 1
+#define IMX8QXP_QSPI0B_DQS_LSIO_KPP0_ROW1 IMX8QXP_QSPI0B_DQS 2
+#define IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8QXP_QSPI0B_DQS 4
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QXP_QSPI0B_SS0_B 0
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B IMX8QXP_QSPI0B_SS0_B 1
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_KPP0_ROW2 IMX8QXP_QSPI0B_SS0_B 2
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8QXP_QSPI0B_SS0_B 4
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QXP_QSPI0B_SS1_B 0
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B IMX8QXP_QSPI0B_SS1_B 1
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4
+
+#endif /* _IMX8QXP_PADS_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 2/2] pinctrl: imx: add imx8qxp driver
@ 2018-10-30 14:10 ` A.s. Dong
0 siblings, 0 replies; 18+ messages in thread
From: A.s. Dong @ 2018-10-30 14:10 UTC (permalink / raw)
To: linux-arm-kernel
MX8QXP contains a system controller that is responsible for controlling
the pad setting of the IPs that are present. Communication between the
host processor running an OS and the system controller happens through
a SCU protocol. This patch adds the SCU based MX8QXP pinctrl driver.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v2->v3:
* add 'IMX8QXP_' prefix for pad name definition
v1->v2:
* scu headfile path update
* add binding headfile pad-imx8qxp.h
* Note the binding part is merged into scu binding doc which has been picked
by Shawn.
https://www.spinics.net/lists/arm-kernel/msg680738.html
---
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 +++++++++
include/dt-bindings/pinctrl/pads-imx8qxp.h | 751 ++++++++++++++++++++++++++++
4 files changed, 991 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8qxp.c
create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 94dcdb5..2d6db43 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -128,6 +128,13 @@ config PINCTRL_IMX8MQ
help
Say Y here to enable the imx8mq pinctrl driver
+config PINCTRL_IMX8QXP
+ bool "IMX8QXP pinctrl driver"
+ depends on SOC_IMX8QXP
+ select PINCTRL_IMX_SCU
+ help
+ Say Y here to enable the imx8qxp pinctrl driver
+
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index 7ac8daf..6ee398a 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
+obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
new file mode 100644
index 0000000..1131dc3
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ * Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+#include <linux/err.h>
+#include <linux/firmware/imx/sci.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static const struct pinctrl_pin_desc imx8qxp_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_PERST_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_CLKREQ_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PCIE_CTRL0_WAKE_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC0),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC1),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC2),
+ IMX_PINCTRL_PIN(IMX8QXP_USB_SS3_TC3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_CMD),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA4),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA5),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA6),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_DATA7),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_STROBE),
+ IMX_PINCTRL_PIN(IMX8QXP_EMMC0_RESET_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_RESET_B),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_VSELECT),
+ IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_RE_P_N),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_WP),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CD_B),
+ IMX_PINCTRL_PIN(IMX8QXP_CTL_NAND_DQS_P_N),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_CMD),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_USDHC1_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXC),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TX_CTL),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD2),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_TXD3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXC),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RX_CTL),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD0),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD2),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_RGMII_RXD3),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_REFCLK_125M_25M),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDIO),
+ IMX_PINCTRL_PIN(IMX8QXP_ENET0_MDC),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FSR),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_FST),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKR),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_SCKT),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX0),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX1),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX2_RX3),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX3_RX2),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX4_RX1),
+ IMX_PINCTRL_PIN(IMX8QXP_ESAI0_TX5_RX0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_SPDIF0_EXT_CLK),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI3_CS1),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN1),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_IN0),
+ IMX_PINCTRL_PIN(IMX8QXP_MCLK_OUT0),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_RTS_B),
+ IMX_PINCTRL_PIN(IMX8QXP_UART1_CTS_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXC),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_RXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI0_TXFS),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXD),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXC),
+ IMX_PINCTRL_PIN(IMX8QXP_SAI1_RXFS),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI2_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SCK),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDI),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_SDO),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS1),
+ IMX_PINCTRL_PIN(IMX8QXP_SPI0_CS0),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN1),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN0),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN3),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN2),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN5),
+ IMX_PINCTRL_PIN(IMX8QXP_ADC_IN4),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN1_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_FLEXCAN2_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART0_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART0_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART2_TX),
+ IMX_PINCTRL_PIN(IMX8QXP_UART2_RX),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_DSI1_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO),
+ IMX_PINCTRL_PIN(IMX8QXP_JTAG_TRST_B),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_I2C_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_PMIC_INT_B),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_PMIC_STANDBY),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE0),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE1),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE2),
+ IMX_PINCTRL_PIN(IMX8QXP_SCU_BOOT_MODE3),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D00),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D01),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D02),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D03),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D04),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D05),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D06),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_D07),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_HSYNC),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_VSYNC),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_PCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_MCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_EN),
+ IMX_PINCTRL_PIN(IMX8QXP_CSI_RESET),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_MCLK_OUT),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SCL),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_I2C0_SDA),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_01),
+ IMX_PINCTRL_PIN(IMX8QXP_MIPI_CSI0_GPIO0_00),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_DQS),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS0_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SS1_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0A_SCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SCLK),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA0),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA1),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA2),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DATA3),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_DQS),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS0_B),
+ IMX_PINCTRL_PIN(IMX8QXP_QSPI0B_SS1_B),
+ IMX_PINCTRL_PIN(IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B),
+};
+
+static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = {
+ .pins = imx8qxp_pinctrl_pads,
+ .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads),
+ .flags = IMX_USE_SCU,
+};
+
+static const struct of_device_id imx8qxp_pinctrl_of_match[] = {
+ { .compatible = "fsl,imx8qxp-iomuxc", },
+ { /* sentinel */ }
+};
+
+static int imx8qxp_pinctrl_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ ret = imx_pinctrl_sc_ipc_init(pdev);
+ if (ret)
+ return ret;
+
+ return imx_pinctrl_probe(pdev, &imx8qxp_pinctrl_info);
+}
+
+static struct platform_driver imx8qxp_pinctrl_driver = {
+ .driver = {
+ .name = "imx8qxp-pinctrl",
+ .of_match_table = of_match_ptr(imx8qxp_pinctrl_of_match),
+ .suppress_bind_attrs = true,
+ },
+ .probe = imx8qxp_pinctrl_probe,
+};
+
+static int __init imx8qxp_pinctrl_init(void)
+{
+ return platform_driver_register(&imx8qxp_pinctrl_driver);
+}
+arch_initcall(imx8qxp_pinctrl_init);
diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h
new file mode 100644
index 0000000..fbfee7e
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h
@@ -0,0 +1,751 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017~2018 NXP
+ */
+
+#ifndef _IMX8QXP_PADS_H
+#define _IMX8QXP_PADS_H
+
+/* pin id */
+#define IMX8QXP_PCIE_CTRL0_PERST_B 0
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B 1
+#define IMX8QXP_PCIE_CTRL0_WAKE_B 2
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
+#define IMX8QXP_USB_SS3_TC0 4
+#define IMX8QXP_USB_SS3_TC1 5
+#define IMX8QXP_USB_SS3_TC2 6
+#define IMX8QXP_USB_SS3_TC3 7
+#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 8
+#define IMX8QXP_EMMC0_CLK 9
+#define IMX8QXP_EMMC0_CMD 10
+#define IMX8QXP_EMMC0_DATA0 11
+#define IMX8QXP_EMMC0_DATA1 12
+#define IMX8QXP_EMMC0_DATA2 13
+#define IMX8QXP_EMMC0_DATA3 14
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15
+#define IMX8QXP_EMMC0_DATA4 16
+#define IMX8QXP_EMMC0_DATA5 17
+#define IMX8QXP_EMMC0_DATA6 18
+#define IMX8QXP_EMMC0_DATA7 19
+#define IMX8QXP_EMMC0_STROBE 20
+#define IMX8QXP_EMMC0_RESET_B 21
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22
+#define IMX8QXP_USDHC1_RESET_B 23
+#define IMX8QXP_USDHC1_VSELECT 24
+#define IMX8QXP_CTL_NAND_RE_P_N 25
+#define IMX8QXP_USDHC1_WP 26
+#define IMX8QXP_USDHC1_CD_B 27
+#define IMX8QXP_CTL_NAND_DQS_P_N 28
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29
+#define IMX8QXP_USDHC1_CLK 30
+#define IMX8QXP_USDHC1_CMD 31
+#define IMX8QXP_USDHC1_DATA0 32
+#define IMX8QXP_USDHC1_DATA1 33
+#define IMX8QXP_USDHC1_DATA2 34
+#define IMX8QXP_USDHC1_DATA3 35
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 36
+#define IMX8QXP_ENET0_RGMII_TXC 37
+#define IMX8QXP_ENET0_RGMII_TX_CTL 38
+#define IMX8QXP_ENET0_RGMII_TXD0 39
+#define IMX8QXP_ENET0_RGMII_TXD1 40
+#define IMX8QXP_ENET0_RGMII_TXD2 41
+#define IMX8QXP_ENET0_RGMII_TXD3 42
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43
+#define IMX8QXP_ENET0_RGMII_RXC 44
+#define IMX8QXP_ENET0_RGMII_RX_CTL 45
+#define IMX8QXP_ENET0_RGMII_RXD0 46
+#define IMX8QXP_ENET0_RGMII_RXD1 47
+#define IMX8QXP_ENET0_RGMII_RXD2 48
+#define IMX8QXP_ENET0_RGMII_RXD3 49
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50
+#define IMX8QXP_ENET0_REFCLK_125M_25M 51
+#define IMX8QXP_ENET0_MDIO 52
+#define IMX8QXP_ENET0_MDC 53
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54
+#define IMX8QXP_ESAI0_FSR 55
+#define IMX8QXP_ESAI0_FST 56
+#define IMX8QXP_ESAI0_SCKR 57
+#define IMX8QXP_ESAI0_SCKT 58
+#define IMX8QXP_ESAI0_TX0 59
+#define IMX8QXP_ESAI0_TX1 60
+#define IMX8QXP_ESAI0_TX2_RX3 61
+#define IMX8QXP_ESAI0_TX3_RX2 62
+#define IMX8QXP_ESAI0_TX4_RX1 63
+#define IMX8QXP_ESAI0_TX5_RX0 64
+#define IMX8QXP_SPDIF0_RX 65
+#define IMX8QXP_SPDIF0_TX 66
+#define IMX8QXP_SPDIF0_EXT_CLK 67
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68
+#define IMX8QXP_SPI3_SCK 69
+#define IMX8QXP_SPI3_SDO 70
+#define IMX8QXP_SPI3_SDI 71
+#define IMX8QXP_SPI3_CS0 72
+#define IMX8QXP_SPI3_CS1 73
+#define IMX8QXP_MCLK_IN1 74
+#define IMX8QXP_MCLK_IN0 75
+#define IMX8QXP_MCLK_OUT0 76
+#define IMX8QXP_UART1_TX 77
+#define IMX8QXP_UART1_RX 78
+#define IMX8QXP_UART1_RTS_B 79
+#define IMX8QXP_UART1_CTS_B 80
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81
+#define IMX8QXP_SAI0_TXD 82
+#define IMX8QXP_SAI0_TXC 83
+#define IMX8QXP_SAI0_RXD 84
+#define IMX8QXP_SAI0_TXFS 85
+#define IMX8QXP_SAI1_RXD 86
+#define IMX8QXP_SAI1_RXC 87
+#define IMX8QXP_SAI1_RXFS 88
+#define IMX8QXP_SPI2_CS0 89
+#define IMX8QXP_SPI2_SDO 90
+#define IMX8QXP_SPI2_SDI 91
+#define IMX8QXP_SPI2_SCK 92
+#define IMX8QXP_SPI0_SCK 93
+#define IMX8QXP_SPI0_SDI 94
+#define IMX8QXP_SPI0_SDO 95
+#define IMX8QXP_SPI0_CS1 96
+#define IMX8QXP_SPI0_CS0 97
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98
+#define IMX8QXP_ADC_IN1 99
+#define IMX8QXP_ADC_IN0 100
+#define IMX8QXP_ADC_IN3 101
+#define IMX8QXP_ADC_IN2 102
+#define IMX8QXP_ADC_IN5 103
+#define IMX8QXP_ADC_IN4 104
+#define IMX8QXP_FLEXCAN0_RX 105
+#define IMX8QXP_FLEXCAN0_TX 106
+#define IMX8QXP_FLEXCAN1_RX 107
+#define IMX8QXP_FLEXCAN1_TX 108
+#define IMX8QXP_FLEXCAN2_RX 109
+#define IMX8QXP_FLEXCAN2_TX 110
+#define IMX8QXP_UART0_RX 111
+#define IMX8QXP_UART0_TX 112
+#define IMX8QXP_UART2_TX 113
+#define IMX8QXP_UART2_RX 114
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL 116
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA 117
+#define IMX8QXP_MIPI_DSI0_GPIO0_00 118
+#define IMX8QXP_MIPI_DSI0_GPIO0_01 119
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL 120
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA 121
+#define IMX8QXP_MIPI_DSI1_GPIO0_00 122
+#define IMX8QXP_MIPI_DSI1_GPIO0_01 123
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124
+#define IMX8QXP_JTAG_TRST_B 125
+#define IMX8QXP_PMIC_I2C_SCL 126
+#define IMX8QXP_PMIC_I2C_SDA 127
+#define IMX8QXP_PMIC_INT_B 128
+#define IMX8QXP_SCU_GPIO0_00 129
+#define IMX8QXP_SCU_GPIO0_01 130
+#define IMX8QXP_SCU_PMIC_STANDBY 131
+#define IMX8QXP_SCU_BOOT_MODE0 132
+#define IMX8QXP_SCU_BOOT_MODE1 133
+#define IMX8QXP_SCU_BOOT_MODE2 134
+#define IMX8QXP_SCU_BOOT_MODE3 135
+#define IMX8QXP_CSI_D00 136
+#define IMX8QXP_CSI_D01 137
+#define IMX8QXP_CSI_D02 138
+#define IMX8QXP_CSI_D03 139
+#define IMX8QXP_CSI_D04 140
+#define IMX8QXP_CSI_D05 141
+#define IMX8QXP_CSI_D06 142
+#define IMX8QXP_CSI_D07 143
+#define IMX8QXP_CSI_HSYNC 144
+#define IMX8QXP_CSI_VSYNC 145
+#define IMX8QXP_CSI_PCLK 146
+#define IMX8QXP_CSI_MCLK 147
+#define IMX8QXP_CSI_EN 148
+#define IMX8QXP_CSI_RESET 149
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT 151
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL 152
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA 153
+#define IMX8QXP_MIPI_CSI0_GPIO0_01 154
+#define IMX8QXP_MIPI_CSI0_GPIO0_00 155
+#define IMX8QXP_QSPI0A_DATA0 156
+#define IMX8QXP_QSPI0A_DATA1 157
+#define IMX8QXP_QSPI0A_DATA2 158
+#define IMX8QXP_QSPI0A_DATA3 159
+#define IMX8QXP_QSPI0A_DQS 160
+#define IMX8QXP_QSPI0A_SS0_B 161
+#define IMX8QXP_QSPI0A_SS1_B 162
+#define IMX8QXP_QSPI0A_SCLK 163
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164
+#define IMX8QXP_QSPI0B_SCLK 165
+#define IMX8QXP_QSPI0B_DATA0 166
+#define IMX8QXP_QSPI0B_DATA1 167
+#define IMX8QXP_QSPI0B_DATA2 168
+#define IMX8QXP_QSPI0B_DATA3 169
+#define IMX8QXP_QSPI0B_DQS 170
+#define IMX8QXP_QSPI0B_SS0_B 171
+#define IMX8QXP_QSPI0B_SS1_B 172
+#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173
+
+/*
+ * format: <pin_id mux_mode>
+ */
+#define IMX8QXP_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8QXP_PCIE_CTRL0_PERST_B 0
+#define IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8QXP_PCIE_CTRL0_PERST_B 4
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8QXP_PCIE_CTRL0_CLKREQ_B 0
+#define IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8QXP_PCIE_CTRL0_CLKREQ_B 4
+#define IMX8QXP_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8QXP_PCIE_CTRL0_WAKE_B 0
+#define IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8QXP_PCIE_CTRL0_WAKE_B 4
+#define IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC0 0
+#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8QXP_USB_SS3_TC0 1
+#define IMX8QXP_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC0 2
+#define IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8QXP_USB_SS3_TC0 4
+#define IMX8QXP_USB_SS3_TC1_ADMA_I2C1_SCL IMX8QXP_USB_SS3_TC1 0
+#define IMX8QXP_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8QXP_USB_SS3_TC1 1
+#define IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8QXP_USB_SS3_TC1 4
+#define IMX8QXP_USB_SS3_TC2_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC2 0
+#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8QXP_USB_SS3_TC2 1
+#define IMX8QXP_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC2 2
+#define IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8QXP_USB_SS3_TC2 4
+#define IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA IMX8QXP_USB_SS3_TC3 0
+#define IMX8QXP_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8QXP_USB_SS3_TC3 1
+#define IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8QXP_USB_SS3_TC3 4
+#define IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK IMX8QXP_EMMC0_CLK 0
+#define IMX8QXP_EMMC0_CLK_CONN_NAND_READY_B IMX8QXP_EMMC0_CLK 1
+#define IMX8QXP_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8QXP_EMMC0_CLK 4
+#define IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD IMX8QXP_EMMC0_CMD 0
+#define IMX8QXP_EMMC0_CMD_CONN_NAND_DQS IMX8QXP_EMMC0_CMD 1
+#define IMX8QXP_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8QXP_EMMC0_CMD 4
+#define IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8QXP_EMMC0_DATA0 0
+#define IMX8QXP_EMMC0_DATA0_CONN_NAND_DATA00 IMX8QXP_EMMC0_DATA0 1
+#define IMX8QXP_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8QXP_EMMC0_DATA0 4
+#define IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8QXP_EMMC0_DATA1 0
+#define IMX8QXP_EMMC0_DATA1_CONN_NAND_DATA01 IMX8QXP_EMMC0_DATA1 1
+#define IMX8QXP_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8QXP_EMMC0_DATA1 4
+#define IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8QXP_EMMC0_DATA2 0
+#define IMX8QXP_EMMC0_DATA2_CONN_NAND_DATA02 IMX8QXP_EMMC0_DATA2 1
+#define IMX8QXP_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8QXP_EMMC0_DATA2 4
+#define IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8QXP_EMMC0_DATA3 0
+#define IMX8QXP_EMMC0_DATA3_CONN_NAND_DATA03 IMX8QXP_EMMC0_DATA3 1
+#define IMX8QXP_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8QXP_EMMC0_DATA3 4
+#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8QXP_EMMC0_DATA4 0
+#define IMX8QXP_EMMC0_DATA4_CONN_NAND_DATA04 IMX8QXP_EMMC0_DATA4 1
+#define IMX8QXP_EMMC0_DATA4_CONN_EMMC0_WP IMX8QXP_EMMC0_DATA4 3
+#define IMX8QXP_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8QXP_EMMC0_DATA4 4
+#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8QXP_EMMC0_DATA5 0
+#define IMX8QXP_EMMC0_DATA5_CONN_NAND_DATA05 IMX8QXP_EMMC0_DATA5 1
+#define IMX8QXP_EMMC0_DATA5_CONN_EMMC0_VSELECT IMX8QXP_EMMC0_DATA5 3
+#define IMX8QXP_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8QXP_EMMC0_DATA5 4
+#define IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8QXP_EMMC0_DATA6 0
+#define IMX8QXP_EMMC0_DATA6_CONN_NAND_DATA06 IMX8QXP_EMMC0_DATA6 1
+#define IMX8QXP_EMMC0_DATA6_CONN_MLB_CLK IMX8QXP_EMMC0_DATA6 3
+#define IMX8QXP_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8QXP_EMMC0_DATA6 4
+#define IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8QXP_EMMC0_DATA7 0
+#define IMX8QXP_EMMC0_DATA7_CONN_NAND_DATA07 IMX8QXP_EMMC0_DATA7 1
+#define IMX8QXP_EMMC0_DATA7_CONN_MLB_SIG IMX8QXP_EMMC0_DATA7 3
+#define IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8QXP_EMMC0_DATA7 4
+#define IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8QXP_EMMC0_STROBE 0
+#define IMX8QXP_EMMC0_STROBE_CONN_NAND_CLE IMX8QXP_EMMC0_STROBE 1
+#define IMX8QXP_EMMC0_STROBE_CONN_MLB_DATA IMX8QXP_EMMC0_STROBE 3
+#define IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8QXP_EMMC0_STROBE 4
+#define IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8QXP_EMMC0_RESET_B 0
+#define IMX8QXP_EMMC0_RESET_B_CONN_NAND_WP_B IMX8QXP_EMMC0_RESET_B 1
+#define IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8QXP_EMMC0_RESET_B 4
+#define IMX8QXP_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8QXP_USDHC1_RESET_B 0
+#define IMX8QXP_USDHC1_RESET_B_CONN_NAND_RE_N IMX8QXP_USDHC1_RESET_B 1
+#define IMX8QXP_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8QXP_USDHC1_RESET_B 2
+#define IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8QXP_USDHC1_RESET_B 4
+#define IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8QXP_USDHC1_VSELECT 0
+#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_P IMX8QXP_USDHC1_VSELECT 1
+#define IMX8QXP_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8QXP_USDHC1_VSELECT 2
+#define IMX8QXP_USDHC1_VSELECT_CONN_NAND_RE_B IMX8QXP_USDHC1_VSELECT 3
+#define IMX8QXP_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8QXP_USDHC1_VSELECT 4
+#define IMX8QXP_USDHC1_WP_CONN_USDHC1_WP IMX8QXP_USDHC1_WP 0
+#define IMX8QXP_USDHC1_WP_CONN_NAND_DQS_N IMX8QXP_USDHC1_WP 1
+#define IMX8QXP_USDHC1_WP_ADMA_SPI2_SDI IMX8QXP_USDHC1_WP 2
+#define IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 IMX8QXP_USDHC1_WP 4
+#define IMX8QXP_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8QXP_USDHC1_CD_B 0
+#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS_P IMX8QXP_USDHC1_CD_B 1
+#define IMX8QXP_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8QXP_USDHC1_CD_B 2
+#define IMX8QXP_USDHC1_CD_B_CONN_NAND_DQS IMX8QXP_USDHC1_CD_B 3
+#define IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8QXP_USDHC1_CD_B 4
+#define IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK IMX8QXP_USDHC1_CLK 0
+#define IMX8QXP_USDHC1_CLK_ADMA_UART3_RX IMX8QXP_USDHC1_CLK 2
+#define IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 IMX8QXP_USDHC1_CLK 4
+#define IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD IMX8QXP_USDHC1_CMD 0
+#define IMX8QXP_USDHC1_CMD_CONN_NAND_CE0_B IMX8QXP_USDHC1_CMD 1
+#define IMX8QXP_USDHC1_CMD_ADMA_MQS_R IMX8QXP_USDHC1_CMD 2
+#define IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 IMX8QXP_USDHC1_CMD 4
+#define IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 IMX8QXP_USDHC1_DATA0 0
+#define IMX8QXP_USDHC1_DATA0_CONN_NAND_CE1_B IMX8QXP_USDHC1_DATA0 1
+#define IMX8QXP_USDHC1_DATA0_ADMA_MQS_L IMX8QXP_USDHC1_DATA0 2
+#define IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 IMX8QXP_USDHC1_DATA0 4
+#define IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 IMX8QXP_USDHC1_DATA1 0
+#define IMX8QXP_USDHC1_DATA1_CONN_NAND_RE_B IMX8QXP_USDHC1_DATA1 1
+#define IMX8QXP_USDHC1_DATA1_ADMA_UART3_TX IMX8QXP_USDHC1_DATA1 2
+#define IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 IMX8QXP_USDHC1_DATA1 4
+#define IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 IMX8QXP_USDHC1_DATA2 0
+#define IMX8QXP_USDHC1_DATA2_CONN_NAND_WE_B IMX8QXP_USDHC1_DATA2 1
+#define IMX8QXP_USDHC1_DATA2_ADMA_UART3_CTS_B IMX8QXP_USDHC1_DATA2 2
+#define IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 IMX8QXP_USDHC1_DATA2 4
+#define IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 IMX8QXP_USDHC1_DATA3 0
+#define IMX8QXP_USDHC1_DATA3_CONN_NAND_ALE IMX8QXP_USDHC1_DATA3 1
+#define IMX8QXP_USDHC1_DATA3_ADMA_UART3_RTS_B IMX8QXP_USDHC1_DATA3 2
+#define IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 IMX8QXP_USDHC1_DATA3 4
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8QXP_ENET0_RGMII_TXC 0
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8QXP_ENET0_RGMII_TXC 1
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8QXP_ENET0_RGMII_TXC 2
+#define IMX8QXP_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8QXP_ENET0_RGMII_TXC 3
+#define IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8QXP_ENET0_RGMII_TXC 4
+#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8QXP_ENET0_RGMII_TX_CTL 0
+#define IMX8QXP_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8QXP_ENET0_RGMII_TX_CTL 3
+#define IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8QXP_ENET0_RGMII_TX_CTL 4
+#define IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8QXP_ENET0_RGMII_TXD0 0
+#define IMX8QXP_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8QXP_ENET0_RGMII_TXD0 3
+#define IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8QXP_ENET0_RGMII_TXD0 4
+#define IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8QXP_ENET0_RGMII_TXD1 0
+#define IMX8QXP_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8QXP_ENET0_RGMII_TXD1 3
+#define IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8QXP_ENET0_RGMII_TXD1 4
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8QXP_ENET0_RGMII_TXD2 0
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_MLB_CLK IMX8QXP_ENET0_RGMII_TXD2 1
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8QXP_ENET0_RGMII_TXD2 2
+#define IMX8QXP_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8QXP_ENET0_RGMII_TXD2 3
+#define IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8QXP_ENET0_RGMII_TXD2 4
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8QXP_ENET0_RGMII_TXD3 0
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_MLB_SIG IMX8QXP_ENET0_RGMII_TXD3 1
+#define IMX8QXP_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8QXP_ENET0_RGMII_TXD3 2
+#define IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8QXP_ENET0_RGMII_TXD3 4
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8QXP_ENET0_RGMII_RXC 0
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_MLB_DATA IMX8QXP_ENET0_RGMII_RXC 1
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8QXP_ENET0_RGMII_RXC 2
+#define IMX8QXP_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8QXP_ENET0_RGMII_RXC 3
+#define IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8QXP_ENET0_RGMII_RXC 4
+#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8QXP_ENET0_RGMII_RX_CTL 0
+#define IMX8QXP_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8QXP_ENET0_RGMII_RX_CTL 3
+#define IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8QXP_ENET0_RGMII_RX_CTL 4
+#define IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8QXP_ENET0_RGMII_RXD0 0
+#define IMX8QXP_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8QXP_ENET0_RGMII_RXD0 3
+#define IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8QXP_ENET0_RGMII_RXD0 4
+#define IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8QXP_ENET0_RGMII_RXD1 0
+#define IMX8QXP_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8QXP_ENET0_RGMII_RXD1 3
+#define IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8QXP_ENET0_RGMII_RXD1 4
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8QXP_ENET0_RGMII_RXD2 0
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8QXP_ENET0_RGMII_RXD2 1
+#define IMX8QXP_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8QXP_ENET0_RGMII_RXD2 3
+#define IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8QXP_ENET0_RGMII_RXD2 4
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8QXP_ENET0_RGMII_RXD3 0
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8QXP_ENET0_RGMII_RXD3 2
+#define IMX8QXP_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8QXP_ENET0_RGMII_RXD3 3
+#define IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8QXP_ENET0_RGMII_RXD3 4
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8QXP_ENET0_REFCLK_125M_25M 0
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8QXP_ENET0_REFCLK_125M_25M 1
+#define IMX8QXP_ENET0_REFCLK_125M_25M_CONN_ENET1_PPS IMX8QXP_ENET0_REFCLK_125M_25M 2
+#define IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8QXP_ENET0_REFCLK_125M_25M 4
+#define IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO IMX8QXP_ENET0_MDIO 0
+#define IMX8QXP_ENET0_MDIO_ADMA_I2C3_SDA IMX8QXP_ENET0_MDIO 1
+#define IMX8QXP_ENET0_MDIO_CONN_ENET1_MDIO IMX8QXP_ENET0_MDIO 2
+#define IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8QXP_ENET0_MDIO 4
+#define IMX8QXP_ENET0_MDC_CONN_ENET0_MDC IMX8QXP_ENET0_MDC 0
+#define IMX8QXP_ENET0_MDC_ADMA_I2C3_SCL IMX8QXP_ENET0_MDC 1
+#define IMX8QXP_ENET0_MDC_CONN_ENET1_MDC IMX8QXP_ENET0_MDC 2
+#define IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 IMX8QXP_ENET0_MDC 4
+#define IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR IMX8QXP_ESAI0_FSR 0
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_OUT IMX8QXP_ESAI0_FSR 1
+#define IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 IMX8QXP_ESAI0_FSR 2
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC IMX8QXP_ESAI0_FSR 3
+#define IMX8QXP_ESAI0_FSR_CONN_ENET1_RCLK50M_IN IMX8QXP_ESAI0_FSR 4
+#define IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST IMX8QXP_ESAI0_FST 0
+#define IMX8QXP_ESAI0_FST_CONN_MLB_CLK IMX8QXP_ESAI0_FST 1
+#define IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 IMX8QXP_ESAI0_FST 2
+#define IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 IMX8QXP_ESAI0_FST 3
+#define IMX8QXP_ESAI0_FST_LSIO_GPIO0_IO01 IMX8QXP_ESAI0_FST 4
+#define IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR IMX8QXP_ESAI0_SCKR 0
+#define IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 IMX8QXP_ESAI0_SCKR 2
+#define IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL IMX8QXP_ESAI0_SCKR 3
+#define IMX8QXP_ESAI0_SCKR_LSIO_GPIO0_IO02 IMX8QXP_ESAI0_SCKR 4
+#define IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT IMX8QXP_ESAI0_SCKT 0
+#define IMX8QXP_ESAI0_SCKT_CONN_MLB_SIG IMX8QXP_ESAI0_SCKT 1
+#define IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 IMX8QXP_ESAI0_SCKT 2
+#define IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 IMX8QXP_ESAI0_SCKT 3
+#define IMX8QXP_ESAI0_SCKT_LSIO_GPIO0_IO03 IMX8QXP_ESAI0_SCKT 4
+#define IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 IMX8QXP_ESAI0_TX0 0
+#define IMX8QXP_ESAI0_TX0_CONN_MLB_DATA IMX8QXP_ESAI0_TX0 1
+#define IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 IMX8QXP_ESAI0_TX0 2
+#define IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC IMX8QXP_ESAI0_TX0 3
+#define IMX8QXP_ESAI0_TX0_LSIO_GPIO0_IO04 IMX8QXP_ESAI0_TX0 4
+#define IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 IMX8QXP_ESAI0_TX1 0
+#define IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 IMX8QXP_ESAI0_TX1 2
+#define IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 IMX8QXP_ESAI0_TX1 3
+#define IMX8QXP_ESAI0_TX1_LSIO_GPIO0_IO05 IMX8QXP_ESAI0_TX1 4
+#define IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 IMX8QXP_ESAI0_TX2_RX3 0
+#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER IMX8QXP_ESAI0_TX2_RX3 1
+#define IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 IMX8QXP_ESAI0_TX2_RX3 2
+#define IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 IMX8QXP_ESAI0_TX2_RX3 3
+#define IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 IMX8QXP_ESAI0_TX2_RX3 4
+#define IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 IMX8QXP_ESAI0_TX3_RX2 0
+#define IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 IMX8QXP_ESAI0_TX3_RX2 2
+#define IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 IMX8QXP_ESAI0_TX3_RX2 3
+#define IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 IMX8QXP_ESAI0_TX3_RX2 4
+#define IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 IMX8QXP_ESAI0_TX4_RX1 0
+#define IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 IMX8QXP_ESAI0_TX4_RX1 2
+#define IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 IMX8QXP_ESAI0_TX4_RX1 3
+#define IMX8QXP_ESAI0_TX4_RX1_LSIO_GPIO0_IO08 IMX8QXP_ESAI0_TX4_RX1 4
+#define IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 IMX8QXP_ESAI0_TX5_RX0 0
+#define IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 IMX8QXP_ESAI0_TX5_RX0 2
+#define IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 IMX8QXP_ESAI0_TX5_RX0 3
+#define IMX8QXP_ESAI0_TX5_RX0_LSIO_GPIO0_IO09 IMX8QXP_ESAI0_TX5_RX0 4
+#define IMX8QXP_SPDIF0_RX_ADMA_SPDIF0_RX IMX8QXP_SPDIF0_RX 0
+#define IMX8QXP_SPDIF0_RX_ADMA_MQS_R IMX8QXP_SPDIF0_RX 1
+#define IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 IMX8QXP_SPDIF0_RX 2
+#define IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 IMX8QXP_SPDIF0_RX 3
+#define IMX8QXP_SPDIF0_RX_LSIO_GPIO0_IO10 IMX8QXP_SPDIF0_RX 4
+#define IMX8QXP_SPDIF0_TX_ADMA_SPDIF0_TX IMX8QXP_SPDIF0_TX 0
+#define IMX8QXP_SPDIF0_TX_ADMA_MQS_L IMX8QXP_SPDIF0_TX 1
+#define IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 IMX8QXP_SPDIF0_TX 2
+#define IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL IMX8QXP_SPDIF0_TX 3
+#define IMX8QXP_SPDIF0_TX_LSIO_GPIO0_IO11 IMX8QXP_SPDIF0_TX 4
+#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_SPDIF0_EXT_CLK IMX8QXP_SPDIF0_EXT_CLK 0
+#define IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 IMX8QXP_SPDIF0_EXT_CLK 2
+#define IMX8QXP_SPDIF0_EXT_CLK_CONN_ENET1_REFCLK_125M_25M IMX8QXP_SPDIF0_EXT_CLK 3
+#define IMX8QXP_SPDIF0_EXT_CLK_LSIO_GPIO0_IO12 IMX8QXP_SPDIF0_EXT_CLK 4
+#define IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK IMX8QXP_SPI3_SCK 0
+#define IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 IMX8QXP_SPI3_SCK 2
+#define IMX8QXP_SPI3_SCK_LSIO_GPIO0_IO13 IMX8QXP_SPI3_SCK 4
+#define IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO IMX8QXP_SPI3_SDO 0
+#define IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 IMX8QXP_SPI3_SDO 2
+#define IMX8QXP_SPI3_SDO_LSIO_GPIO0_IO14 IMX8QXP_SPI3_SDO 4
+#define IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI IMX8QXP_SPI3_SDI 0
+#define IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 IMX8QXP_SPI3_SDI 2
+#define IMX8QXP_SPI3_SDI_LSIO_GPIO0_IO15 IMX8QXP_SPI3_SDI 4
+#define IMX8QXP_SPI3_CS0_ADMA_SPI3_CS0 IMX8QXP_SPI3_CS0 0
+#define IMX8QXP_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8QXP_SPI3_CS0 1
+#define IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8QXP_SPI3_CS0 2
+#define IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 IMX8QXP_SPI3_CS0 4
+#define IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 IMX8QXP_SPI3_CS1 0
+#define IMX8QXP_SPI3_CS1_ADMA_I2C3_SCL IMX8QXP_SPI3_CS1 1
+#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_RESET IMX8QXP_SPI3_CS1 2
+#define IMX8QXP_SPI3_CS1_ADMA_SPI2_CS0 IMX8QXP_SPI3_CS1 3
+#define IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 IMX8QXP_SPI3_CS1 4
+#define IMX8QXP_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8QXP_MCLK_IN1 0
+#define IMX8QXP_MCLK_IN1_ADMA_I2C3_SDA IMX8QXP_MCLK_IN1 1
+#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN IMX8QXP_MCLK_IN1 2
+#define IMX8QXP_MCLK_IN1_ADMA_SPI2_SCK IMX8QXP_MCLK_IN1 3
+#define IMX8QXP_MCLK_IN1_ADMA_LCDIF_D17 IMX8QXP_MCLK_IN1 4
+#define IMX8QXP_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8QXP_MCLK_IN0 0
+#define IMX8QXP_MCLK_IN0_ADMA_ESAI0_RX_HF_CLK IMX8QXP_MCLK_IN0 1
+#define IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8QXP_MCLK_IN0 2
+#define IMX8QXP_MCLK_IN0_ADMA_SPI2_SDI IMX8QXP_MCLK_IN0 3
+#define IMX8QXP_MCLK_IN0_LSIO_GPIO0_IO19 IMX8QXP_MCLK_IN0 4
+#define IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8QXP_MCLK_OUT0 0
+#define IMX8QXP_MCLK_OUT0_ADMA_ESAI0_TX_HF_CLK IMX8QXP_MCLK_OUT0 1
+#define IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK IMX8QXP_MCLK_OUT0 2
+#define IMX8QXP_MCLK_OUT0_ADMA_SPI2_SDO IMX8QXP_MCLK_OUT0 3
+#define IMX8QXP_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8QXP_MCLK_OUT0 4
+#define IMX8QXP_UART1_TX_ADMA_UART1_TX IMX8QXP_UART1_TX 0
+#define IMX8QXP_UART1_TX_LSIO_PWM0_OUT IMX8QXP_UART1_TX 1
+#define IMX8QXP_UART1_TX_LSIO_GPT0_CAPTURE IMX8QXP_UART1_TX 2
+#define IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 IMX8QXP_UART1_TX 4
+#define IMX8QXP_UART1_RX_ADMA_UART1_RX IMX8QXP_UART1_RX 0
+#define IMX8QXP_UART1_RX_LSIO_PWM1_OUT IMX8QXP_UART1_RX 1
+#define IMX8QXP_UART1_RX_LSIO_GPT0_COMPARE IMX8QXP_UART1_RX 2
+#define IMX8QXP_UART1_RX_LSIO_GPT1_CLK IMX8QXP_UART1_RX 3
+#define IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 IMX8QXP_UART1_RX 4
+#define IMX8QXP_UART1_RTS_B_ADMA_UART1_RTS_B IMX8QXP_UART1_RTS_B 0
+#define IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT IMX8QXP_UART1_RTS_B 1
+#define IMX8QXP_UART1_RTS_B_ADMA_LCDIF_D16 IMX8QXP_UART1_RTS_B 2
+#define IMX8QXP_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8QXP_UART1_RTS_B 3
+#define IMX8QXP_UART1_RTS_B_LSIO_GPT0_CLK IMX8QXP_UART1_RTS_B 4
+#define IMX8QXP_UART1_CTS_B_ADMA_UART1_CTS_B IMX8QXP_UART1_CTS_B 0
+#define IMX8QXP_UART1_CTS_B_LSIO_PWM3_OUT IMX8QXP_UART1_CTS_B 1
+#define IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 IMX8QXP_UART1_CTS_B 2
+#define IMX8QXP_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8QXP_UART1_CTS_B 3
+#define IMX8QXP_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8QXP_UART1_CTS_B 4
+#define IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD IMX8QXP_SAI0_TXD 0
+#define IMX8QXP_SAI0_TXD_ADMA_SAI1_RXC IMX8QXP_SAI0_TXD 1
+#define IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO IMX8QXP_SAI0_TXD 2
+#define IMX8QXP_SAI0_TXD_ADMA_LCDIF_D18 IMX8QXP_SAI0_TXD 3
+#define IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 IMX8QXP_SAI0_TXD 4
+#define IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC IMX8QXP_SAI0_TXC 0
+#define IMX8QXP_SAI0_TXC_ADMA_SAI1_TXD IMX8QXP_SAI0_TXC 1
+#define IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI IMX8QXP_SAI0_TXC 2
+#define IMX8QXP_SAI0_TXC_ADMA_LCDIF_D19 IMX8QXP_SAI0_TXC 3
+#define IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 IMX8QXP_SAI0_TXC 4
+#define IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD IMX8QXP_SAI0_RXD 0
+#define IMX8QXP_SAI0_RXD_ADMA_SAI1_RXFS IMX8QXP_SAI0_RXD 1
+#define IMX8QXP_SAI0_RXD_ADMA_SPI1_CS0 IMX8QXP_SAI0_RXD 2
+#define IMX8QXP_SAI0_RXD_ADMA_LCDIF_D20 IMX8QXP_SAI0_RXD 3
+#define IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 IMX8QXP_SAI0_RXD 4
+#define IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS IMX8QXP_SAI0_TXFS 0
+#define IMX8QXP_SAI0_TXFS_ADMA_SPI2_CS1 IMX8QXP_SAI0_TXFS 1
+#define IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK IMX8QXP_SAI0_TXFS 2
+#define IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 IMX8QXP_SAI0_TXFS 4
+#define IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD IMX8QXP_SAI1_RXD 0
+#define IMX8QXP_SAI1_RXD_ADMA_SAI0_RXFS IMX8QXP_SAI1_RXD 1
+#define IMX8QXP_SAI1_RXD_ADMA_SPI1_CS1 IMX8QXP_SAI1_RXD 2
+#define IMX8QXP_SAI1_RXD_ADMA_LCDIF_D21 IMX8QXP_SAI1_RXD 3
+#define IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 IMX8QXP_SAI1_RXD 4
+#define IMX8QXP_SAI1_RXC_ADMA_SAI1_RXC IMX8QXP_SAI1_RXC 0
+#define IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC IMX8QXP_SAI1_RXC 1
+#define IMX8QXP_SAI1_RXC_ADMA_LCDIF_D22 IMX8QXP_SAI1_RXC 3
+#define IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 IMX8QXP_SAI1_RXC 4
+#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_RXFS IMX8QXP_SAI1_RXFS 0
+#define IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS IMX8QXP_SAI1_RXFS 1
+#define IMX8QXP_SAI1_RXFS_ADMA_LCDIF_D23 IMX8QXP_SAI1_RXFS 3
+#define IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 IMX8QXP_SAI1_RXFS 4
+#define IMX8QXP_SPI2_CS0_ADMA_SPI2_CS0 IMX8QXP_SPI2_CS0 0
+#define IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 IMX8QXP_SPI2_CS0 4
+#define IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO IMX8QXP_SPI2_SDO 0
+#define IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 IMX8QXP_SPI2_SDO 4
+#define IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI IMX8QXP_SPI2_SDI 0
+#define IMX8QXP_SPI2_SDI_LSIO_GPIO1_IO02 IMX8QXP_SPI2_SDI 4
+#define IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK IMX8QXP_SPI2_SCK 0
+#define IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 IMX8QXP_SPI2_SCK 4
+#define IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK IMX8QXP_SPI0_SCK 0
+#define IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC IMX8QXP_SPI0_SCK 1
+#define IMX8QXP_SPI0_SCK_M40_I2C0_SCL IMX8QXP_SPI0_SCK 2
+#define IMX8QXP_SPI0_SCK_M40_GPIO0_IO00 IMX8QXP_SPI0_SCK 3
+#define IMX8QXP_SPI0_SCK_LSIO_GPIO1_IO04 IMX8QXP_SPI0_SCK 4
+#define IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI IMX8QXP_SPI0_SDI 0
+#define IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD IMX8QXP_SPI0_SDI 1
+#define IMX8QXP_SPI0_SDI_M40_TPM0_CH0 IMX8QXP_SPI0_SDI 2
+#define IMX8QXP_SPI0_SDI_M40_GPIO0_IO02 IMX8QXP_SPI0_SDI 3
+#define IMX8QXP_SPI0_SDI_LSIO_GPIO1_IO05 IMX8QXP_SPI0_SDI 4
+#define IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO IMX8QXP_SPI0_SDO 0
+#define IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS IMX8QXP_SPI0_SDO 1
+#define IMX8QXP_SPI0_SDO_M40_I2C0_SDA IMX8QXP_SPI0_SDO 2
+#define IMX8QXP_SPI0_SDO_M40_GPIO0_IO01 IMX8QXP_SPI0_SDO 3
+#define IMX8QXP_SPI0_SDO_LSIO_GPIO1_IO06 IMX8QXP_SPI0_SDO 4
+#define IMX8QXP_SPI0_CS1_ADMA_SPI0_CS1 IMX8QXP_SPI0_CS1 0
+#define IMX8QXP_SPI0_CS1_ADMA_SAI0_RXC IMX8QXP_SPI0_CS1 1
+#define IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD IMX8QXP_SPI0_CS1 2
+#define IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8QXP_SPI0_CS1 3
+#define IMX8QXP_SPI0_CS1_LSIO_GPIO1_IO07 IMX8QXP_SPI0_CS1 4
+#define IMX8QXP_SPI0_CS0_ADMA_SPI0_CS0 IMX8QXP_SPI0_CS0 0
+#define IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD IMX8QXP_SPI0_CS0 1
+#define IMX8QXP_SPI0_CS0_M40_TPM0_CH1 IMX8QXP_SPI0_CS0 2
+#define IMX8QXP_SPI0_CS0_M40_GPIO0_IO03 IMX8QXP_SPI0_CS0 3
+#define IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 IMX8QXP_SPI0_CS0 4
+#define IMX8QXP_ADC_IN1_ADMA_ADC_IN1 IMX8QXP_ADC_IN1 0
+#define IMX8QXP_ADC_IN1_M40_I2C0_SDA IMX8QXP_ADC_IN1 1
+#define IMX8QXP_ADC_IN1_M40_GPIO0_IO01 IMX8QXP_ADC_IN1 2
+#define IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 IMX8QXP_ADC_IN1 4
+#define IMX8QXP_ADC_IN0_ADMA_ADC_IN0 IMX8QXP_ADC_IN0 0
+#define IMX8QXP_ADC_IN0_M40_I2C0_SCL IMX8QXP_ADC_IN0 1
+#define IMX8QXP_ADC_IN0_M40_GPIO0_IO00 IMX8QXP_ADC_IN0 2
+#define IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 IMX8QXP_ADC_IN0 4
+#define IMX8QXP_ADC_IN3_ADMA_ADC_IN3 IMX8QXP_ADC_IN3 0
+#define IMX8QXP_ADC_IN3_M40_UART0_TX IMX8QXP_ADC_IN3 1
+#define IMX8QXP_ADC_IN3_M40_GPIO0_IO03 IMX8QXP_ADC_IN3 2
+#define IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8QXP_ADC_IN3 3
+#define IMX8QXP_ADC_IN3_LSIO_GPIO1_IO11 IMX8QXP_ADC_IN3 4
+#define IMX8QXP_ADC_IN2_ADMA_ADC_IN2 IMX8QXP_ADC_IN2 0
+#define IMX8QXP_ADC_IN2_M40_UART0_RX IMX8QXP_ADC_IN2 1
+#define IMX8QXP_ADC_IN2_M40_GPIO0_IO02 IMX8QXP_ADC_IN2 2
+#define IMX8QXP_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8QXP_ADC_IN2 3
+#define IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 IMX8QXP_ADC_IN2 4
+#define IMX8QXP_ADC_IN5_ADMA_ADC_IN5 IMX8QXP_ADC_IN5 0
+#define IMX8QXP_ADC_IN5_M40_TPM0_CH1 IMX8QXP_ADC_IN5 1
+#define IMX8QXP_ADC_IN5_M40_GPIO0_IO05 IMX8QXP_ADC_IN5 2
+#define IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 IMX8QXP_ADC_IN5 4
+#define IMX8QXP_ADC_IN4_ADMA_ADC_IN4 IMX8QXP_ADC_IN4 0
+#define IMX8QXP_ADC_IN4_M40_TPM0_CH0 IMX8QXP_ADC_IN4 1
+#define IMX8QXP_ADC_IN4_M40_GPIO0_IO04 IMX8QXP_ADC_IN4 2
+#define IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 IMX8QXP_ADC_IN4 4
+#define IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8QXP_FLEXCAN0_RX 0
+#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8QXP_FLEXCAN0_RX 1
+#define IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8QXP_FLEXCAN0_RX 2
+#define IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8QXP_FLEXCAN0_RX 3
+#define IMX8QXP_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8QXP_FLEXCAN0_RX 4
+#define IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8QXP_FLEXCAN0_TX 0
+#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8QXP_FLEXCAN0_TX 1
+#define IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8QXP_FLEXCAN0_TX 2
+#define IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8QXP_FLEXCAN0_TX 3
+#define IMX8QXP_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8QXP_FLEXCAN0_TX 4
+#define IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8QXP_FLEXCAN1_RX 0
+#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8QXP_FLEXCAN1_RX 1
+#define IMX8QXP_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8QXP_FLEXCAN1_RX 2
+#define IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8QXP_FLEXCAN1_RX 3
+#define IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8QXP_FLEXCAN1_RX 4
+#define IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8QXP_FLEXCAN1_TX 0
+#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8QXP_FLEXCAN1_TX 1
+#define IMX8QXP_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8QXP_FLEXCAN1_TX 2
+#define IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8QXP_FLEXCAN1_TX 3
+#define IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8QXP_FLEXCAN1_TX 4
+#define IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8QXP_FLEXCAN2_RX 0
+#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8QXP_FLEXCAN2_RX 1
+#define IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX IMX8QXP_FLEXCAN2_RX 2
+#define IMX8QXP_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8QXP_FLEXCAN2_RX 3
+#define IMX8QXP_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8QXP_FLEXCAN2_RX 4
+#define IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8QXP_FLEXCAN2_TX 0
+#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8QXP_FLEXCAN2_TX 1
+#define IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX IMX8QXP_FLEXCAN2_TX 2
+#define IMX8QXP_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8QXP_FLEXCAN2_TX 3
+#define IMX8QXP_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8QXP_FLEXCAN2_TX 4
+#define IMX8QXP_UART0_RX_ADMA_UART0_RX IMX8QXP_UART0_RX 0
+#define IMX8QXP_UART0_RX_ADMA_MQS_R IMX8QXP_UART0_RX 1
+#define IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX IMX8QXP_UART0_RX 2
+#define IMX8QXP_UART0_RX_LSIO_GPIO1_IO21 IMX8QXP_UART0_RX 4
+#define IMX8QXP_UART0_TX_ADMA_UART0_TX IMX8QXP_UART0_TX 0
+#define IMX8QXP_UART0_TX_ADMA_MQS_L IMX8QXP_UART0_TX 1
+#define IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX IMX8QXP_UART0_TX 2
+#define IMX8QXP_UART0_TX_LSIO_GPIO1_IO22 IMX8QXP_UART0_TX 4
+#define IMX8QXP_UART2_TX_ADMA_UART2_TX IMX8QXP_UART2_TX 0
+#define IMX8QXP_UART2_TX_ADMA_FTM_CH1 IMX8QXP_UART2_TX 1
+#define IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX IMX8QXP_UART2_TX 2
+#define IMX8QXP_UART2_TX_LSIO_GPIO1_IO23 IMX8QXP_UART2_TX 4
+#define IMX8QXP_UART2_RX_ADMA_UART2_RX IMX8QXP_UART2_RX 0
+#define IMX8QXP_UART2_RX_ADMA_FTM_CH0 IMX8QXP_UART2_RX 1
+#define IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX IMX8QXP_UART2_RX 2
+#define IMX8QXP_UART2_RX_LSIO_GPIO1_IO24 IMX8QXP_UART2_RX 4
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL IMX8QXP_MIPI_DSI0_I2C0_SCL 0
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI1_GPIO0_IO02 IMX8QXP_MIPI_DSI0_I2C0_SCL 1
+#define IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 IMX8QXP_MIPI_DSI0_I2C0_SCL 4
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA IMX8QXP_MIPI_DSI0_I2C0_SDA 0
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI1_GPIO0_IO03 IMX8QXP_MIPI_DSI0_I2C0_SDA 1
+#define IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 IMX8QXP_MIPI_DSI0_I2C0_SDA 4
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_IO00 IMX8QXP_MIPI_DSI0_GPIO0_00 0
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL IMX8QXP_MIPI_DSI0_GPIO0_00 1
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT IMX8QXP_MIPI_DSI0_GPIO0_00 2
+#define IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27 IMX8QXP_MIPI_DSI0_GPIO0_00 4
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_IO01 IMX8QXP_MIPI_DSI0_GPIO0_01 0
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA IMX8QXP_MIPI_DSI0_GPIO0_01 1
+#define IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 IMX8QXP_MIPI_DSI0_GPIO0_01 4
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL IMX8QXP_MIPI_DSI1_I2C0_SCL 0
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI0_GPIO0_IO02 IMX8QXP_MIPI_DSI1_I2C0_SCL 1
+#define IMX8QXP_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO29 IMX8QXP_MIPI_DSI1_I2C0_SCL 4
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA IMX8QXP_MIPI_DSI1_I2C0_SDA 0
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI0_GPIO0_IO03 IMX8QXP_MIPI_DSI1_I2C0_SDA 1
+#define IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 IMX8QXP_MIPI_DSI1_I2C0_SDA 4
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_IO00 IMX8QXP_MIPI_DSI1_GPIO0_00 0
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL IMX8QXP_MIPI_DSI1_GPIO0_00 1
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT IMX8QXP_MIPI_DSI1_GPIO0_00 2
+#define IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 IMX8QXP_MIPI_DSI1_GPIO0_00 4
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_IO01 IMX8QXP_MIPI_DSI1_GPIO0_01 0
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA IMX8QXP_MIPI_DSI1_GPIO0_01 1
+#define IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 IMX8QXP_MIPI_DSI1_GPIO0_01 4
+#define IMX8QXP_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8QXP_JTAG_TRST_B 0
+#define IMX8QXP_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8QXP_JTAG_TRST_B 1
+#define IMX8QXP_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8QXP_PMIC_I2C_SCL 0
+#define IMX8QXP_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8QXP_PMIC_I2C_SCL 1
+#define IMX8QXP_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8QXP_PMIC_I2C_SCL 4
+#define IMX8QXP_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8QXP_PMIC_I2C_SDA 0
+#define IMX8QXP_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8QXP_PMIC_I2C_SDA 1
+#define IMX8QXP_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8QXP_PMIC_I2C_SDA 4
+#define IMX8QXP_PMIC_INT_B_SCU_DIMX8QXPMIC_INT_B IMX8QXP_PMIC_INT_B 0
+#define IMX8QXP_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8QXP_SCU_GPIO0_00 0
+#define IMX8QXP_SCU_GPIO0_00_SCU_UART0_RX IMX8QXP_SCU_GPIO0_00 1
+#define IMX8QXP_SCU_GPIO0_00_M40_UART0_RX IMX8QXP_SCU_GPIO0_00 2
+#define IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX IMX8QXP_SCU_GPIO0_00 3
+#define IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8QXP_SCU_GPIO0_00 4
+#define IMX8QXP_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8QXP_SCU_GPIO0_01 0
+#define IMX8QXP_SCU_GPIO0_01_SCU_UART0_TX IMX8QXP_SCU_GPIO0_01 1
+#define IMX8QXP_SCU_GPIO0_01_M40_UART0_TX IMX8QXP_SCU_GPIO0_01 2
+#define IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX IMX8QXP_SCU_GPIO0_01 3
+#define IMX8QXP_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8QXP_SCU_GPIO0_01 4
+#define IMX8QXP_SCU_PMIC_STANDBY_SCU_DIMX8QXPMIC_STANDBY IMX8QXP_SCU_PMIC_STANDBY 0
+#define IMX8QXP_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8QXP_SCU_BOOT_MODE0 0
+#define IMX8QXP_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8QXP_SCU_BOOT_MODE1 0
+#define IMX8QXP_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8QXP_SCU_BOOT_MODE2 0
+#define IMX8QXP_SCU_BOOT_MODE2_SCU_PMIC_I2C_SDA IMX8QXP_SCU_BOOT_MODE2 1
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 IMX8QXP_SCU_BOOT_MODE3 0
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_PMIC_I2C_SCL IMX8QXP_SCU_BOOT_MODE3 1
+#define IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8QXP_SCU_BOOT_MODE3 3
+#define IMX8QXP_CSI_D00_CI_PI_D02 IMX8QXP_CSI_D00 0
+#define IMX8QXP_CSI_D00_ADMA_SAI0_RXC IMX8QXP_CSI_D00 2
+#define IMX8QXP_CSI_D01_CI_PI_D03 IMX8QXP_CSI_D01 0
+#define IMX8QXP_CSI_D01_ADMA_SAI0_RXD IMX8QXP_CSI_D01 2
+#define IMX8QXP_CSI_D02_CI_PI_D04 IMX8QXP_CSI_D02 0
+#define IMX8QXP_CSI_D02_ADMA_SAI0_RXFS IMX8QXP_CSI_D02 2
+#define IMX8QXP_CSI_D03_CI_PI_D05 IMX8QXP_CSI_D03 0
+#define IMX8QXP_CSI_D03_ADMA_SAI2_RXC IMX8QXP_CSI_D03 2
+#define IMX8QXP_CSI_D04_CI_PI_D06 IMX8QXP_CSI_D04 0
+#define IMX8QXP_CSI_D04_ADMA_SAI2_RXD IMX8QXP_CSI_D04 2
+#define IMX8QXP_CSI_D05_CI_PI_D07 IMX8QXP_CSI_D05 0
+#define IMX8QXP_CSI_D05_ADMA_SAI2_RXFS IMX8QXP_CSI_D05 2
+#define IMX8QXP_CSI_D06_CI_PI_D08 IMX8QXP_CSI_D06 0
+#define IMX8QXP_CSI_D06_ADMA_SAI3_RXC IMX8QXP_CSI_D06 2
+#define IMX8QXP_CSI_D07_CI_PI_D09 IMX8QXP_CSI_D07 0
+#define IMX8QXP_CSI_D07_ADMA_SAI3_RXD IMX8QXP_CSI_D07 2
+#define IMX8QXP_CSI_HSYNC_CI_PI_HSYNC IMX8QXP_CSI_HSYNC 0
+#define IMX8QXP_CSI_HSYNC_CI_PI_D00 IMX8QXP_CSI_HSYNC 1
+#define IMX8QXP_CSI_HSYNC_ADMA_SAI3_RXFS IMX8QXP_CSI_HSYNC 2
+#define IMX8QXP_CSI_VSYNC_CI_PI_VSYNC IMX8QXP_CSI_VSYNC 0
+#define IMX8QXP_CSI_VSYNC_CI_PI_D01 IMX8QXP_CSI_VSYNC 1
+#define IMX8QXP_CSI_PCLK_CI_PI_PCLK IMX8QXP_CSI_PCLK 0
+#define IMX8QXP_CSI_PCLK_MIPI_CSI0_I2C0_SCL IMX8QXP_CSI_PCLK 1
+#define IMX8QXP_CSI_PCLK_ADMA_SPI1_SCK IMX8QXP_CSI_PCLK 3
+#define IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 IMX8QXP_CSI_PCLK 4
+#define IMX8QXP_CSI_MCLK_CI_PI_MCLK IMX8QXP_CSI_MCLK 0
+#define IMX8QXP_CSI_MCLK_MIPI_CSI0_I2C0_SDA IMX8QXP_CSI_MCLK 1
+#define IMX8QXP_CSI_MCLK_ADMA_SPI1_SDO IMX8QXP_CSI_MCLK 3
+#define IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 IMX8QXP_CSI_MCLK 4
+#define IMX8QXP_CSI_EN_CI_PI_EN IMX8QXP_CSI_EN 0
+#define IMX8QXP_CSI_EN_CI_PI_I2C_SCL IMX8QXP_CSI_EN 1
+#define IMX8QXP_CSI_EN_ADMA_I2C3_SCL IMX8QXP_CSI_EN 2
+#define IMX8QXP_CSI_EN_ADMA_SPI1_SDI IMX8QXP_CSI_EN 3
+#define IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 IMX8QXP_CSI_EN 4
+#define IMX8QXP_CSI_RESET_CI_PI_RESET IMX8QXP_CSI_RESET 0
+#define IMX8QXP_CSI_RESET_CI_PI_I2C_SDA IMX8QXP_CSI_RESET 1
+#define IMX8QXP_CSI_RESET_ADMA_I2C3_SDA IMX8QXP_CSI_RESET 2
+#define IMX8QXP_CSI_RESET_ADMA_SPI1_CS0 IMX8QXP_CSI_RESET 3
+#define IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 IMX8QXP_CSI_RESET 4
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT IMX8QXP_MIPI_CSI0_MCLK_OUT 0
+#define IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 IMX8QXP_MIPI_CSI0_MCLK_OUT 4
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL IMX8QXP_MIPI_CSI0_I2C0_SCL 0
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_GPIO0_IO02 IMX8QXP_MIPI_CSI0_I2C0_SCL 1
+#define IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 IMX8QXP_MIPI_CSI0_I2C0_SCL 4
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA IMX8QXP_MIPI_CSI0_I2C0_SDA 0
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_GPIO0_IO03 IMX8QXP_MIPI_CSI0_I2C0_SDA 1
+#define IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 IMX8QXP_MIPI_CSI0_I2C0_SDA 4
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 IMX8QXP_MIPI_CSI0_GPIO0_01 0
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA IMX8QXP_MIPI_CSI0_GPIO0_01 1
+#define IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 IMX8QXP_MIPI_CSI0_GPIO0_01 4
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 IMX8QXP_MIPI_CSI0_GPIO0_00 0
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL IMX8QXP_MIPI_CSI0_GPIO0_00 1
+#define IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 IMX8QXP_MIPI_CSI0_GPIO0_00 4
+#define IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8QXP_QSPI0A_DATA0 0
+#define IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8QXP_QSPI0A_DATA0 4
+#define IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8QXP_QSPI0A_DATA1 0
+#define IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8QXP_QSPI0A_DATA1 4
+#define IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8QXP_QSPI0A_DATA2 0
+#define IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8QXP_QSPI0A_DATA2 4
+#define IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8QXP_QSPI0A_DATA3 0
+#define IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8QXP_QSPI0A_DATA3 4
+#define IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8QXP_QSPI0A_DQS 0
+#define IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8QXP_QSPI0A_DQS 4
+#define IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8QXP_QSPI0A_SS0_B 0
+#define IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8QXP_QSPI0A_SS0_B 4
+#define IMX8QXP_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B IMX8QXP_QSPI0A_SS1_B 0
+#define IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 IMX8QXP_QSPI0A_SS1_B 4
+#define IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8QXP_QSPI0A_SCLK 0
+#define IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8QXP_QSPI0A_SCLK 4
+#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8QXP_QSPI0B_SCLK 0
+#define IMX8QXP_QSPI0B_SCLK_LSIO_QSPI1A_SCLK IMX8QXP_QSPI0B_SCLK 1
+#define IMX8QXP_QSPI0B_SCLK_LSIO_KPP0_COL0 IMX8QXP_QSPI0B_SCLK 2
+#define IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8QXP_QSPI0B_SCLK 4
+#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8QXP_QSPI0B_DATA0 0
+#define IMX8QXP_QSPI0B_DATA0_LSIO_QSPI1A_DATA0 IMX8QXP_QSPI0B_DATA0 1
+#define IMX8QXP_QSPI0B_DATA0_LSIO_KPP0_COL1 IMX8QXP_QSPI0B_DATA0 2
+#define IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8QXP_QSPI0B_DATA0 4
+#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8QXP_QSPI0B_DATA1 0
+#define IMX8QXP_QSPI0B_DATA1_LSIO_QSPI1A_DATA1 IMX8QXP_QSPI0B_DATA1 1
+#define IMX8QXP_QSPI0B_DATA1_LSIO_KPP0_COL2 IMX8QXP_QSPI0B_DATA1 2
+#define IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8QXP_QSPI0B_DATA1 4
+#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8QXP_QSPI0B_DATA2 0
+#define IMX8QXP_QSPI0B_DATA2_LSIO_QSPI1A_DATA2 IMX8QXP_QSPI0B_DATA2 1
+#define IMX8QXP_QSPI0B_DATA2_LSIO_KPP0_COL3 IMX8QXP_QSPI0B_DATA2 2
+#define IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8QXP_QSPI0B_DATA2 4
+#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8QXP_QSPI0B_DATA3 0
+#define IMX8QXP_QSPI0B_DATA3_LSIO_QSPI1A_DATA3 IMX8QXP_QSPI0B_DATA3 1
+#define IMX8QXP_QSPI0B_DATA3_LSIO_KPP0_ROW0 IMX8QXP_QSPI0B_DATA3 2
+#define IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8QXP_QSPI0B_DATA3 4
+#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8QXP_QSPI0B_DQS 0
+#define IMX8QXP_QSPI0B_DQS_LSIO_QSPI1A_DQS IMX8QXP_QSPI0B_DQS 1
+#define IMX8QXP_QSPI0B_DQS_LSIO_KPP0_ROW1 IMX8QXP_QSPI0B_DQS 2
+#define IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8QXP_QSPI0B_DQS 4
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8QXP_QSPI0B_SS0_B 0
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI1A_SS0_B IMX8QXP_QSPI0B_SS0_B 1
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_KPP0_ROW2 IMX8QXP_QSPI0B_SS0_B 2
+#define IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8QXP_QSPI0B_SS0_B 4
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B IMX8QXP_QSPI0B_SS1_B 0
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI1A_SS1_B IMX8QXP_QSPI0B_SS1_B 1
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2
+#define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4
+
+#endif /* _IMX8QXP_PADS_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* RE: [PATCH RESEND V3 0/2] pinctrl: imx: add imx8qxp pinctrl support
2018-10-30 14:10 ` A.s. Dong
@ 2018-10-30 14:13 ` A.s. Dong
-1 siblings, 0 replies; 18+ messages in thread
From: A.s. Dong @ 2018-10-30 14:13 UTC (permalink / raw)
To: linus.walleij
Cc: dongas86, stefan, linux-gpio, dl-linux-imx, kernel,
Fabio Estevam, shawnguo, linux-arm-kernel
Hi Linus,
> -----Original Message-----
> From: A.s. Dong
> Sent: Tuesday, October 30, 2018 10:11 PM
> To: linux-gpio@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org; linus.walleij@linaro.org;
> shawnguo@kernel.org; stefan@agner.ch; A.s. Dong <aisheng.dong@nxp.com>;
> dongas86@gmail.com; dl-linux-imx <linux-imx@nxp.com>;
> kernel@pengutronix.de; Fabio Estevam <fabio.estevam@nxp.com>
> Subject: [PATCH RESEND V3 0/2] pinctrl: imx: add imx8qxp pinctrl support
>
> Rebased with latest pinctrl/for-next tree, compiling and function tested on
> IMX6Q SDB.
>
Can you please check if this version can be applied?
Regards
Dong Aisheng
> This patch series adds i.MX8QXP pinctrl support which is based on the pad
> service provided by SCU firmware.
>
> The binding part is also merged into scu binding doc according to Rob's
> suggestion.
> https://www.spinics.net/lists/arm-kernel/msg680738.html
>
> v2->v3:
> * Pad name update (add IMX8QXP prefix)
>
> v1->v2:
> * scu firmware headfile path update
> * structure name and api usage update
> * move SCU Pad API implementation into driver
> * add binding headfile pad-imx8qxp.h
>
> Dong Aisheng (2):
> pinctrl: fsl: add scu based pinctrl support
> pinctrl: imx: add imx8qxp driver
>
> drivers/pinctrl/freescale/Kconfig | 11 +
> drivers/pinctrl/freescale/Makefile | 2 +
> drivers/pinctrl/freescale/pinctrl-imx.c | 425 ++++++++++------
> drivers/pinctrl/freescale/pinctrl-imx.h | 67 ++-
> drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 +++++++++
> drivers/pinctrl/freescale/pinctrl-scu.c | 121 +++++
> include/dt-bindings/pinctrl/pads-imx8qxp.h | 751
> ++++++++++++++++++++++++++++
> 7 files changed, 1439 insertions(+), 170 deletions(-) create mode 100644
> drivers/pinctrl/freescale/pinctrl-imx8qxp.c
> create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
> create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 0/2] pinctrl: imx: add imx8qxp pinctrl support
@ 2018-10-30 14:13 ` A.s. Dong
0 siblings, 0 replies; 18+ messages in thread
From: A.s. Dong @ 2018-10-30 14:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi Linus,
> -----Original Message-----
> From: A.s. Dong
> Sent: Tuesday, October 30, 2018 10:11 PM
> To: linux-gpio at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org; linus.walleij at linaro.org;
> shawnguo at kernel.org; stefan at agner.ch; A.s. Dong <aisheng.dong@nxp.com>;
> dongas86 at gmail.com; dl-linux-imx <linux-imx@nxp.com>;
> kernel at pengutronix.de; Fabio Estevam <fabio.estevam@nxp.com>
> Subject: [PATCH RESEND V3 0/2] pinctrl: imx: add imx8qxp pinctrl support
>
> Rebased with latest pinctrl/for-next tree, compiling and function tested on
> IMX6Q SDB.
>
Can you please check if this version can be applied?
Regards
Dong Aisheng
> This patch series adds i.MX8QXP pinctrl support which is based on the pad
> service provided by SCU firmware.
>
> The binding part is also merged into scu binding doc according to Rob's
> suggestion.
> https://www.spinics.net/lists/arm-kernel/msg680738.html
>
> v2->v3:
> * Pad name update (add IMX8QXP prefix)
>
> v1->v2:
> * scu firmware headfile path update
> * structure name and api usage update
> * move SCU Pad API implementation into driver
> * add binding headfile pad-imx8qxp.h
>
> Dong Aisheng (2):
> pinctrl: fsl: add scu based pinctrl support
> pinctrl: imx: add imx8qxp driver
>
> drivers/pinctrl/freescale/Kconfig | 11 +
> drivers/pinctrl/freescale/Makefile | 2 +
> drivers/pinctrl/freescale/pinctrl-imx.c | 425 ++++++++++------
> drivers/pinctrl/freescale/pinctrl-imx.h | 67 ++-
> drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 232 +++++++++
> drivers/pinctrl/freescale/pinctrl-scu.c | 121 +++++
> include/dt-bindings/pinctrl/pads-imx8qxp.h | 751
> ++++++++++++++++++++++++++++
> 7 files changed, 1439 insertions(+), 170 deletions(-) create mode 100644
> drivers/pinctrl/freescale/pinctrl-imx8qxp.c
> create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c
> create mode 100644 include/dt-bindings/pinctrl/pads-imx8qxp.h
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
2018-10-30 14:10 ` A.s. Dong
@ 2018-10-31 11:00 ` Linus Walleij
-1 siblings, 0 replies; 18+ messages in thread
From: Linus Walleij @ 2018-10-31 11:00 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, Fabio Estevam, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Shawn Guo, Linux ARM
On Tue, Oct 30, 2018 at 3:10 PM A.s. Dong <aisheng.dong@nxp.com> wrote:
> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> that is responsible for controlling the pad setting of the IPs that
> are present. Communication between the host processor running an OS
> and the system controller happens through a SCU protocol.
>
> This patch classifies the pad settings into two categories: MMIO and SCU.
> For the original MMIO method, no functional changes except organize them
> into a few imx_*_mmio() functions. Besides that, we add the SCU based
> Pad Mux and Pinconf setting support which are implemented in pinctrl-scu.c.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
@ 2018-10-31 11:00 ` Linus Walleij
0 siblings, 0 replies; 18+ messages in thread
From: Linus Walleij @ 2018-10-31 11:00 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Oct 30, 2018 at 3:10 PM A.s. Dong <aisheng.dong@nxp.com> wrote:
> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> that is responsible for controlling the pad setting of the IPs that
> are present. Communication between the host processor running an OS
> and the system controller happens through a SCU protocol.
>
> This patch classifies the pad settings into two categories: MMIO and SCU.
> For the original MMIO method, no functional changes except organize them
> into a few imx_*_mmio() functions. Besides that, we add the SCU based
> Pad Mux and Pinconf setting support which are implemented in pinctrl-scu.c.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND V3 2/2] pinctrl: imx: add imx8qxp driver
2018-10-30 14:10 ` A.s. Dong
@ 2018-10-31 11:01 ` Linus Walleij
-1 siblings, 0 replies; 18+ messages in thread
From: Linus Walleij @ 2018-10-31 11:01 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, Fabio Estevam, Stefan Agner,
open list:GPIO SUBSYSTEM, NXP Linux Team, Sascha Hauer,
Fabio Estevam, Shawn Guo, Linux ARM
On Tue, Oct 30, 2018 at 3:10 PM A.s. Dong <aisheng.dong@nxp.com> wrote:
> MX8QXP contains a system controller that is responsible for controlling
> the pad setting of the IPs that are present. Communication between the
> host processor running an OS and the system controller happens through
> a SCU protocol. This patch adds the SCU based MX8QXP pinctrl driver.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 2/2] pinctrl: imx: add imx8qxp driver
@ 2018-10-31 11:01 ` Linus Walleij
0 siblings, 0 replies; 18+ messages in thread
From: Linus Walleij @ 2018-10-31 11:01 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Oct 30, 2018 at 3:10 PM A.s. Dong <aisheng.dong@nxp.com> wrote:
> MX8QXP contains a system controller that is responsible for controlling
> the pad setting of the IPs that are present. Communication between the
> host processor running an OS and the system controller happens through
> a SCU protocol. This patch adds the SCU based MX8QXP pinctrl driver.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
2018-10-30 14:10 ` A.s. Dong
@ 2018-11-15 0:26 ` Kevin Hilman
-1 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2018-11-15 0:26 UTC (permalink / raw)
To: linux-gpio
Cc: A.s. Dong, dongas86, shawnguo, linus.walleij, stefan, Mark Brown,
dl-linux-imx, kernel, Fabio Estevam, Fabio Estevam,
linux-arm-kernel
"A.s. Dong" <aisheng.dong@nxp.com> writes:
> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> that is responsible for controlling the pad setting of the IPs that
> are present. Communication between the host processor running an OS
> and the system controller happens through a SCU protocol.
>
> This patch classifies the pad settings into two categories: MMIO and SCU.
> For the original MMIO method, no functional changes except organize them
> into a few imx_*_mmio() functions. Besides that, we add the SCU based
> Pad Mux and Pinconf setting support which are implemented in pinctrl-scu.c.
kernelCI found boot failure caused by this patch.
imx6 started failing in kernelCI in next-20181114 on several wand
boards[1]. There was no kernel output, after uboot started the kernel.
Using the imx6q-wandboard, I bisected it down to this commit.
I verified that reverting this commit on top of next-20181114 fixes the
problem.
Kevin
[1]
https://kernelci.org/boot/all/job/next/branch/master/kernel/next-20181114/
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
@ 2018-11-15 0:26 ` Kevin Hilman
0 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2018-11-15 0:26 UTC (permalink / raw)
To: linux-arm-kernel
"A.s. Dong" <aisheng.dong@nxp.com> writes:
> Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller
> that is responsible for controlling the pad setting of the IPs that
> are present. Communication between the host processor running an OS
> and the system controller happens through a SCU protocol.
>
> This patch classifies the pad settings into two categories: MMIO and SCU.
> For the original MMIO method, no functional changes except organize them
> into a few imx_*_mmio() functions. Besides that, we add the SCU based
> Pad Mux and Pinconf setting support which are implemented in pinctrl-scu.c.
kernelCI found boot failure caused by this patch.
imx6 started failing in kernelCI in next-20181114 on several wand
boards[1]. There was no kernel output, after uboot started the kernel.
Using the imx6q-wandboard, I bisected it down to this commit.
I verified that reverting this commit on top of next-20181114 fixes the
problem.
Kevin
[1]
https://kernelci.org/boot/all/job/next/branch/master/kernel/next-20181114/
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
2018-11-15 0:26 ` Kevin Hilman
@ 2018-11-15 0:32 ` Fabio Estevam
-1 siblings, 0 replies; 18+ messages in thread
From: Fabio Estevam @ 2018-11-15 0:32 UTC (permalink / raw)
To: Kevin Hilman
Cc: Dong Aisheng, Dong Aisheng, Linus Walleij, Stefan Agner,
open list:GPIO SUBSYSTEM, Mark Brown, NXP Linux Team,
Sascha Hauer, Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Kevin,
On Wed, Nov 14, 2018 at 10:26 PM Kevin Hilman <khilman@baylibre.com> wrote:
> kernelCI found boot failure caused by this patch.
>
> imx6 started failing in kernelCI in next-20181114 on several wand
> boards[1]. There was no kernel output, after uboot started the kernel.
>
> Using the imx6q-wandboard, I bisected it down to this commit.
>
> I verified that reverting this commit on top of next-20181114 fixes the
> problem.
Thanks for the report.
Dong has sent a fix for this issue:
https://www.spinics.net/lists/arm-kernel/msg686738.html
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
@ 2018-11-15 0:32 ` Fabio Estevam
0 siblings, 0 replies; 18+ messages in thread
From: Fabio Estevam @ 2018-11-15 0:32 UTC (permalink / raw)
To: linux-arm-kernel
Hi Kevin,
On Wed, Nov 14, 2018 at 10:26 PM Kevin Hilman <khilman@baylibre.com> wrote:
> kernelCI found boot failure caused by this patch.
>
> imx6 started failing in kernelCI in next-20181114 on several wand
> boards[1]. There was no kernel output, after uboot started the kernel.
>
> Using the imx6q-wandboard, I bisected it down to this commit.
>
> I verified that reverting this commit on top of next-20181114 fixes the
> problem.
Thanks for the report.
Dong has sent a fix for this issue:
https://www.spinics.net/lists/arm-kernel/msg686738.html
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
2018-11-15 0:32 ` Fabio Estevam
@ 2018-11-15 1:02 ` Kevin Hilman
-1 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2018-11-15 1:02 UTC (permalink / raw)
To: Fabio Estevam
Cc: Dong Aisheng, Dong Aisheng, Linus Walleij, Stefan Agner,
open list:GPIO SUBSYSTEM, Mark Brown, NXP Linux Team,
Sascha Hauer, Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Fabio Estevam <festevam@gmail.com> writes:
> Hi Kevin,
>
> On Wed, Nov 14, 2018 at 10:26 PM Kevin Hilman <khilman@baylibre.com> wrote:
>
>> kernelCI found boot failure caused by this patch.
>>
>> imx6 started failing in kernelCI in next-20181114 on several wand
>> boards[1]. There was no kernel output, after uboot started the kernel.
>>
>> Using the imx6q-wandboard, I bisected it down to this commit.
>>
>> I verified that reverting this commit on top of next-20181114 fixes the
>> problem.
>
> Thanks for the report.
>
> Dong has sent a fix for this issue:
> https://www.spinics.net/lists/arm-kernel/msg686738.html
Ah, I was too slow. ;)
Anyways, I tested/validated that patch and replied on list.
Kevin
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based pinctrl support
@ 2018-11-15 1:02 ` Kevin Hilman
0 siblings, 0 replies; 18+ messages in thread
From: Kevin Hilman @ 2018-11-15 1:02 UTC (permalink / raw)
To: linux-arm-kernel
Fabio Estevam <festevam@gmail.com> writes:
> Hi Kevin,
>
> On Wed, Nov 14, 2018 at 10:26 PM Kevin Hilman <khilman@baylibre.com> wrote:
>
>> kernelCI found boot failure caused by this patch.
>>
>> imx6 started failing in kernelCI in next-20181114 on several wand
>> boards[1]. There was no kernel output, after uboot started the kernel.
>>
>> Using the imx6q-wandboard, I bisected it down to this commit.
>>
>> I verified that reverting this commit on top of next-20181114 fixes the
>> problem.
>
> Thanks for the report.
>
> Dong has sent a fix for this issue:
> https://www.spinics.net/lists/arm-kernel/msg686738.html
Ah, I was too slow. ;)
Anyways, I tested/validated that patch and replied on list.
Kevin
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-11-15 1:02 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-30 14:10 [PATCH RESEND V3 0/2] pinctrl: imx: add imx8qxp pinctrl support A.s. Dong
2018-10-30 14:10 ` A.s. Dong
2018-10-30 14:10 ` [PATCH RESEND V3 1/2] pinctrl: fsl: add scu based " A.s. Dong
2018-10-30 14:10 ` A.s. Dong
2018-10-31 11:00 ` Linus Walleij
2018-10-31 11:00 ` Linus Walleij
2018-11-15 0:26 ` Kevin Hilman
2018-11-15 0:26 ` Kevin Hilman
2018-11-15 0:32 ` Fabio Estevam
2018-11-15 0:32 ` Fabio Estevam
2018-11-15 1:02 ` Kevin Hilman
2018-11-15 1:02 ` Kevin Hilman
2018-10-30 14:10 ` [PATCH RESEND V3 2/2] pinctrl: imx: add imx8qxp driver A.s. Dong
2018-10-30 14:10 ` A.s. Dong
2018-10-31 11:01 ` Linus Walleij
2018-10-31 11:01 ` Linus Walleij
2018-10-30 14:13 ` [PATCH RESEND V3 0/2] pinctrl: imx: add imx8qxp pinctrl support A.s. Dong
2018-10-30 14:13 ` A.s. Dong
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