[PATCH v3 0/2] pinctrl: ocelot: add shared reset

[PATCH v3 0/2] pinctrl: ocelot: add shared reset

[Michael Walle]

On LAN966x SoCs, there is an internal reset which is used to reset the
switch core. But this will also reset the GPIO and the SGPIO. Thus add
support for this shared reset line.

changes since v2:
 - use dev_err_probe(), thanks Horatiu

changes since v1:
 - rebased onto linus' devel tree, former patch was still based on
   v1 of the YAML conversion patch

Michael Walle (2):
  dt-bindings: pinctrl: ocelot: add reset property
  pinctrl: ocelot: add optional shared reset

 .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml  | 8 ++++++++
 drivers/pinctrl/pinctrl-ocelot.c                          | 8 ++++++++
 2 files changed, 16 insertions(+)

-- 
2.30.2

[PATCH v3 1/2] dt-bindings: pinctrl: ocelot: add reset property

[Michael Walle]

On the LAN966x SoC the GPIO controller will be resetted together with
the SGPIO and the switch core. Add a phandle to register the shared
reset line.

Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml  | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
index 7149a6655623..98d547c34ef3 100644
--- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
@@ -42,6 +42,14 @@ properties:
   "#interrupt-cells":
     const: 2
 
+  resets:
+    maxItems: 1
+
+  reset-names:
+    description: Optional shared switch reset.
+    items:
+      - const: switch
+
 patternProperties:
   '-pins$':
     type: object
-- 
2.30.2

[PATCH v3 2/2] pinctrl: ocelot: add optional shared reset

[Michael Walle]

On the LAN9668 there is a shared reset line which affects GPIO, SGPIO
and the switch core. Add support for this shared reset line.

Signed-off-by: Michael Walle <michael@walle.cc>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
---
 drivers/pinctrl/pinctrl-ocelot.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index 1bdced67464b..843704fa8625 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -19,6 +19,7 @@
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 
 #include "core.h"
@@ -1912,6 +1913,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct ocelot_pinctrl *info;
+	struct reset_control *reset;
 	struct regmap *pincfg;
 	void __iomem *base;
 	int ret;
@@ -1927,6 +1929,12 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
 
 	info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
 
+	reset = devm_reset_control_get_optional_shared(dev, "switch");
+	if (IS_ERR(reset))
+		return dev_err_probe(dev, PTR_ERR(reset),
+				     "Failed to get reset\n");
+	reset_control_reset(reset);
+
 	base = devm_ioremap_resource(dev,
 			platform_get_resource(pdev, IORESOURCE_MEM, 0));
 	if (IS_ERR(base))
-- 
2.30.2

Re: [PATCH v3 0/2] pinctrl: ocelot: add shared reset

[Linus Walleij]

On Wed, Apr 20, 2022 at 9:19 PM Michael Walle <michael@walle.cc> wrote:

> On LAN966x SoCs, there is an internal reset which is used to reset the
> switch core. But this will also reset the GPIO and the SGPIO. Thus add
> support for this shared reset line.
>
> changes since v2:
>  - use dev_err_probe(), thanks Horatiu

Picked this v3 version rather than v2.

Thanks!
Yours,
Linus Walleij