[PATCH v3 0/6] pinctrl: ocelot: convert to YAML format

[PATCH v3 0/6] pinctrl: ocelot: convert to YAML format

[Michael Walle]

Convert the pinctrl ocelot binding to the new YAML format. Pin
configuration nodes should have a "-pins" postfix. But unfortunately,
there are many device trees which don't follow this. First rename
all these nodes and then convert the binding to the YAML format so
that the validation will pass.

Because there were no maintainers before and there is none in
MAINTAINERS I added Alexandre Belloni and Lars Povlsen, juding by
the commits - to the binding as maintainers. Please tell me if you
disagree.

changes since v2:
 - drop Fixes tag (and any "fix" or similar)
 - one patch per SoC
 - document difference between original txt and yaml binging in the
   commit message

changes since v1:
 - drop "Device Tree Binding" from the title of the binding
 - describe reg properties and provide minItems and set it differently
   depending on the compatible string
 - skip interrupt description
 - move required section after patternProperties

Michael Walle (6):
  MIPS: mscc: jaguar2: rename pinctrl nodes
  MIPS: mscc: ocelot: rename pinctrl nodes
  MIPS: mscc: serval: rename pinctrl nodes
  arm64: dts: sparx5: rename pinctrl nodes
  ARM: dts: lan966x: rename pinctrl nodes
  dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

 .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
 .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
 arch/arm/boot/dts/lan966x-pcb8291.dts         |   2 +-
 .../dts/microchip/sparx5_pcb134_board.dtsi    |  26 ++---
 .../dts/microchip/sparx5_pcb135_board.dtsi    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts    |   6 +-
 arch/mips/boot/dts/mscc/ocelot.dtsi           |   4 +-
 arch/mips/boot/dts/mscc/ocelot_pcb120.dts     |   6 +-
 arch/mips/boot/dts/mscc/serval_common.dtsi    |  14 +--
 11 files changed, 152 insertions(+), 86 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml

-- 
2.30.2

[PATCH v3 0/6] pinctrl: ocelot: convert to YAML format

[Michael Walle]

Convert the pinctrl ocelot binding to the new YAML format. Pin
configuration nodes should have a "-pins" postfix. But unfortunately,
there are many device trees which don't follow this. First rename
all these nodes and then convert the binding to the YAML format so
that the validation will pass.

Because there were no maintainers before and there is none in
MAINTAINERS I added Alexandre Belloni and Lars Povlsen, juding by
the commits - to the binding as maintainers. Please tell me if you
disagree.

changes since v2:
 - drop Fixes tag (and any "fix" or similar)
 - one patch per SoC
 - document difference between original txt and yaml binging in the
   commit message

changes since v1:
 - drop "Device Tree Binding" from the title of the binding
 - describe reg properties and provide minItems and set it differently
   depending on the compatible string
 - skip interrupt description
 - move required section after patternProperties

Michael Walle (6):
  MIPS: mscc: jaguar2: rename pinctrl nodes
  MIPS: mscc: ocelot: rename pinctrl nodes
  MIPS: mscc: serval: rename pinctrl nodes
  arm64: dts: sparx5: rename pinctrl nodes
  ARM: dts: lan966x: rename pinctrl nodes
  dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

 .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
 .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
 arch/arm/boot/dts/lan966x-pcb8291.dts         |   2 +-
 .../dts/microchip/sparx5_pcb134_board.dtsi    |  26 ++---
 .../dts/microchip/sparx5_pcb135_board.dtsi    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts    |   6 +-
 arch/mips/boot/dts/mscc/ocelot.dtsi           |   4 +-
 arch/mips/boot/dts/mscc/ocelot_pcb120.dts     |   6 +-
 arch/mips/boot/dts/mscc/serval_common.dtsi    |  14 +--
 11 files changed, 152 insertions(+), 86 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml

-- 
2.30.2


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[PATCH v3 1/6] MIPS: mscc: jaguar2: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 10 +++++-----
 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 10 +++++-----
 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts |  6 +++---
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
index d80cd6842b2a..0ea7bc5b5746 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
@@ -180,27 +180,27 @@ synce_builtin_pins: synce-builtin-pins {
 		pins = "GPIO_49";
 		function = "si";
 	};
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
index 813c5e16013c..05d8c6a96dc4 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
@@ -79,27 +79,27 @@ cpld_fifo_pins: synce-builtin-pins {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_18";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
index 27c644f2d17f..cf2cf591a211 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
@@ -39,17 +39,17 @@ i2c151: i2c@1 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_16";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_16";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2

[PATCH v3 1/6] MIPS: mscc: jaguar2: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 10 +++++-----
 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 10 +++++-----
 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts |  6 +++---
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
index d80cd6842b2a..0ea7bc5b5746 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
@@ -180,27 +180,27 @@ synce_builtin_pins: synce-builtin-pins {
 		pins = "GPIO_49";
 		function = "si";
 	};
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
index 813c5e16013c..05d8c6a96dc4 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
@@ -79,27 +79,27 @@ cpld_fifo_pins: synce-builtin-pins {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_18";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
index 27c644f2d17f..cf2cf591a211 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
@@ -39,17 +39,17 @@ i2c151: i2c@1 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_16";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_16";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2


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[PATCH v3 2/6] MIPS: mscc: ocelot: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/ocelot.dtsi       | 4 ++--
 arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index e51db651af13..cfc219a72bdd 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -225,7 +225,7 @@ uart2_pins: uart2-pins {
 				function = "uart2";
 			};
 
-			miim1: miim1 {
+			miim1_pins: miim1-pins {
 				pins = "GPIO_14", "GPIO_15";
 				function = "miim";
 			};
@@ -261,7 +261,7 @@ mdio1: mdio@10700c0 {
 			reg = <0x10700c0 0x24>;
 			interrupts = <15>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&miim1>;
+			pinctrl-0 = <&miim1_pins>;
 			status = "disabled";
 		};
 
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index bd240690cb37..d348742c233d 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -22,12 +22,12 @@ memory@0 {
 };
 
 &gpio {
-	phy_int_pins: phy_int_pins {
+	phy_int_pins: phy-int-pins {
 		pins = "GPIO_4";
 		function = "gpio";
 	};
 
-	phy_load_save_pins: phy_load_save_pins {
+	phy_load_save_pins: phy-load-save-pins {
 		pins = "GPIO_10";
 		function = "ptp2";
 	};
@@ -40,7 +40,7 @@ &mdio0 {
 &mdio1 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
+	pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
 
 	phy7: ethernet-phy@0 {
 		reg = <0>;
-- 
2.30.2

[PATCH v3 2/6] MIPS: mscc: ocelot: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/ocelot.dtsi       | 4 ++--
 arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index e51db651af13..cfc219a72bdd 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -225,7 +225,7 @@ uart2_pins: uart2-pins {
 				function = "uart2";
 			};
 
-			miim1: miim1 {
+			miim1_pins: miim1-pins {
 				pins = "GPIO_14", "GPIO_15";
 				function = "miim";
 			};
@@ -261,7 +261,7 @@ mdio1: mdio@10700c0 {
 			reg = <0x10700c0 0x24>;
 			interrupts = <15>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&miim1>;
+			pinctrl-0 = <&miim1_pins>;
 			status = "disabled";
 		};
 
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index bd240690cb37..d348742c233d 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -22,12 +22,12 @@ memory@0 {
 };
 
 &gpio {
-	phy_int_pins: phy_int_pins {
+	phy_int_pins: phy-int-pins {
 		pins = "GPIO_4";
 		function = "gpio";
 	};
 
-	phy_load_save_pins: phy_load_save_pins {
+	phy_load_save_pins: phy-load-save-pins {
 		pins = "GPIO_10";
 		function = "ptp2";
 	};
@@ -40,7 +40,7 @@ &mdio0 {
 &mdio1 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
+	pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
 
 	phy7: ethernet-phy@0 {
 		reg = <0>;
-- 
2.30.2


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v3 3/6] MIPS: mscc: serval: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/serval_common.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/serval_common.dtsi b/arch/mips/boot/dts/mscc/serval_common.dtsi
index 5b404836db5e..0893de420e27 100644
--- a/arch/mips/boot/dts/mscc/serval_common.dtsi
+++ b/arch/mips/boot/dts/mscc/serval_common.dtsi
@@ -82,38 +82,38 @@ i2c_pins: i2c-pins {
 		pins = "GPIO_7"; /* No "default" scl for i2c0 */
 		function = "twi";
 	};
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
 			"GPIO_20", "GPIO_21";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_11";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_12";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_19";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_4: i2cmux-4 {
+	i2cmux_4: i2cmux-4-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_5: i2cmux-5 {
+	i2cmux_5: i2cmux-5-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2

[PATCH v3 3/6] MIPS: mscc: serval: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/serval_common.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/serval_common.dtsi b/arch/mips/boot/dts/mscc/serval_common.dtsi
index 5b404836db5e..0893de420e27 100644
--- a/arch/mips/boot/dts/mscc/serval_common.dtsi
+++ b/arch/mips/boot/dts/mscc/serval_common.dtsi
@@ -82,38 +82,38 @@ i2c_pins: i2c-pins {
 		pins = "GPIO_7"; /* No "default" scl for i2c0 */
 		function = "twi";
 	};
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
 			"GPIO_20", "GPIO_21";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_11";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_12";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_19";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_4: i2cmux-4 {
+	i2cmux_4: i2cmux-4-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_5: i2cmux-5 {
+	i2cmux_5: i2cmux-5-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2


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[PATCH v3 4/6] arm64: dts: sparx5: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 .../dts/microchip/sparx5_pcb134_board.dtsi    | 26 +++++++++----------
 .../dts/microchip/sparx5_pcb135_board.dtsi    | 10 +++----
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 33faf1f3264f..6f488e774215 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -325,69 +325,69 @@ &sgpio2 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 	       pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
 		      "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
 		      "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_16";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_19";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_4: i2cmux-4 {
+	i2cmux_4: i2cmux-4-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_5: i2cmux-5 {
+	i2cmux_5: i2cmux-5-pins {
 		pins = "GPIO_22";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_6: i2cmux-6 {
+	i2cmux_6: i2cmux-6-pins {
 		pins = "GPIO_36";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_7: i2cmux-7 {
+	i2cmux_7: i2cmux-7-pins {
 		pins = "GPIO_35";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_8: i2cmux-8 {
+	i2cmux_8: i2cmux-8-pins {
 		pins = "GPIO_50";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_9: i2cmux-9 {
+	i2cmux_9: i2cmux-9-pins {
 		pins = "GPIO_51";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_10: i2cmux-10 {
+	i2cmux_10: i2cmux-10-pins {
 		pins = "GPIO_56";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_11: i2cmux-11 {
+	i2cmux_11: i2cmux-11-pins {
 		pins = "GPIO_57";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index ef96e6d8c6b3..d9e519bfbf68 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -59,28 +59,28 @@ led@7 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 	       pins = "GPIO_35", "GPIO_36",
 		      "GPIO_50", "GPIO_51";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_s29: i2cmux-0 {
+	i2cmux_s29: i2cmux-0-pins {
 		pins = "GPIO_35";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s30: i2cmux-1 {
+	i2cmux_s30: i2cmux-1-pins {
 		pins = "GPIO_36";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s31: i2cmux-2 {
+	i2cmux_s31: i2cmux-2-pins {
 		pins = "GPIO_50";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s32: i2cmux-3 {
+	i2cmux_s32: i2cmux-3-pins {
 		pins = "GPIO_51";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2

[PATCH v3 4/6] arm64: dts: sparx5: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 .../dts/microchip/sparx5_pcb134_board.dtsi    | 26 +++++++++----------
 .../dts/microchip/sparx5_pcb135_board.dtsi    | 10 +++----
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 33faf1f3264f..6f488e774215 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -325,69 +325,69 @@ &sgpio2 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 	       pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
 		      "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
 		      "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_16";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_19";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_4: i2cmux-4 {
+	i2cmux_4: i2cmux-4-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_5: i2cmux-5 {
+	i2cmux_5: i2cmux-5-pins {
 		pins = "GPIO_22";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_6: i2cmux-6 {
+	i2cmux_6: i2cmux-6-pins {
 		pins = "GPIO_36";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_7: i2cmux-7 {
+	i2cmux_7: i2cmux-7-pins {
 		pins = "GPIO_35";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_8: i2cmux-8 {
+	i2cmux_8: i2cmux-8-pins {
 		pins = "GPIO_50";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_9: i2cmux-9 {
+	i2cmux_9: i2cmux-9-pins {
 		pins = "GPIO_51";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_10: i2cmux-10 {
+	i2cmux_10: i2cmux-10-pins {
 		pins = "GPIO_56";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_11: i2cmux-11 {
+	i2cmux_11: i2cmux-11-pins {
 		pins = "GPIO_57";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index ef96e6d8c6b3..d9e519bfbf68 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -59,28 +59,28 @@ led@7 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 	       pins = "GPIO_35", "GPIO_36",
 		      "GPIO_50", "GPIO_51";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_s29: i2cmux-0 {
+	i2cmux_s29: i2cmux-0-pins {
 		pins = "GPIO_35";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s30: i2cmux-1 {
+	i2cmux_s30: i2cmux-1-pins {
 		pins = "GPIO_36";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s31: i2cmux-2 {
+	i2cmux_s31: i2cmux-2-pins {
 		pins = "GPIO_50";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s32: i2cmux-3 {
+	i2cmux_s32: i2cmux-3-pins {
 		pins = "GPIO_51";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2


_______________________________________________
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[PATCH v3 5/6] ARM: dts: lan966x: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
index 3281af90ac6d..3c7e3a7d6f14 100644
--- a/arch/arm/boot/dts/lan966x-pcb8291.dts
+++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
@@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
 		function = "fc3_b";
 	};
 
-	can0_b_pins:  can0_b_pins {
+	can0_b_pins:  can0-b-pins {
 		/* RX, TX */
 		pins = "GPIO_35", "GPIO_36";
 		function = "can0_b";
-- 
2.30.2

[PATCH v3 5/6] ARM: dts: lan966x: rename pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
index 3281af90ac6d..3c7e3a7d6f14 100644
--- a/arch/arm/boot/dts/lan966x-pcb8291.dts
+++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
@@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
 		function = "fc3_b";
 	};
 
-	can0_b_pins:  can0_b_pins {
+	can0_b_pins:  can0-b-pins {
 		/* RX, TX */
 		pins = "GPIO_35", "GPIO_36";
 		function = "can0_b";
-- 
2.30.2


_______________________________________________
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[PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Convert the ocelot-pinctrl device tree binding to the new YAML format.

Additionally to the original binding documentation, add interrupt
properties which are optional and already used on several SoCs like
SparX-5, Luton, Ocelot and LAN966x but were not documented before.

Also, on the sparx5 and the lan966x SoCs there are two items for the
reg property.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
 .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
 2 files changed, 108 insertions(+), 42 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
deleted file mode 100644
index 5d84fd299ccf..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Microsemi Ocelot pin controller Device Tree Bindings
-----------------------------------------------------
-
-Required properties:
- - compatible		: Should be "mscc,ocelot-pinctrl",
-			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
-			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
-			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
- - reg			: Address and length of the register set for the device
- - gpio-controller	: Indicates this device is a GPIO controller
- - #gpio-cells		: Must be 2.
-			  The first cell is the pin number and the
-			  second cell specifies GPIO flags, as defined in
-			  <dt-bindings/gpio/gpio.h>.
- - gpio-ranges		: Range of pins managed by the GPIO controller.
-
-
-The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
-configuration documented in pinctrl-bindings.txt.
-
-The following generic properties are supported:
- - function
- - pins
-
-Example:
-	gpio: pinctrl@71070034 {
-		compatible = "mscc,ocelot-pinctrl";
-		reg = <0x71070034 0x28>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-ranges = <&gpio 0 0 22>;
-
-		uart_pins: uart-pins {
-				pins = "GPIO_6", "GPIO_7";
-				function = "uart";
-		};
-
-		uart2_pins: uart2-pins {
-				pins = "GPIO_12", "GPIO_13";
-				function = "uart2";
-		};
-	};
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
new file mode 100644
index 000000000000..7149a6655623
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microsemi Ocelot pin controller
+
+maintainers:
+  - Alexandre Belloni <alexandre.belloni@bootlin.com>
+  - Lars Povlsen <lars.povlsen@microchip.com>
+
+properties:
+  compatible:
+    enum:
+      - microchip,lan966x-pinctrl
+      - microchip,sparx5-pinctrl
+      - mscc,jaguar2-pinctrl
+      - mscc,luton-pinctrl
+      - mscc,ocelot-pinctrl
+      - mscc,serval-pinctrl
+      - mscc,servalt-pinctrl
+
+  reg:
+    items:
+      - description: Base address
+      - description: Extended pin configuration registers
+    minItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  gpio-ranges: true
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+patternProperties:
+  '-pins$':
+    type: object
+    allOf:
+      - $ref: "pinmux-node.yaml"
+      - $ref: "pincfg-node.yaml"
+
+    properties:
+      function: true
+      pins: true
+      output-high: true
+      output-low: true
+      drive-strength: true
+
+    required:
+      - function
+      - pins
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - '#gpio-cells'
+  - gpio-ranges
+
+allOf:
+  - $ref: "pinctrl.yaml#"
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - microchip,lan966x-pinctrl
+              - microchip,sparx5-pinctrl
+    then:
+      properties:
+        reg:
+          minItems: 2
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio: pinctrl@71070034 {
+        compatible = "mscc,ocelot-pinctrl";
+        reg = <0x71070034 0x28>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&gpio 0 0 22>;
+
+        uart_pins: uart-pins {
+            pins = "GPIO_6", "GPIO_7";
+            function = "uart";
+        };
+
+        uart2_pins: uart2-pins {
+            pins = "GPIO_12", "GPIO_13";
+            function = "uart2";
+        };
+    };
+
+...
-- 
2.30.2

[PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Convert the ocelot-pinctrl device tree binding to the new YAML format.

Additionally to the original binding documentation, add interrupt
properties which are optional and already used on several SoCs like
SparX-5, Luton, Ocelot and LAN966x but were not documented before.

Also, on the sparx5 and the lan966x SoCs there are two items for the
reg property.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
 .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
 2 files changed, 108 insertions(+), 42 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
deleted file mode 100644
index 5d84fd299ccf..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Microsemi Ocelot pin controller Device Tree Bindings
-----------------------------------------------------
-
-Required properties:
- - compatible		: Should be "mscc,ocelot-pinctrl",
-			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
-			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
-			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
- - reg			: Address and length of the register set for the device
- - gpio-controller	: Indicates this device is a GPIO controller
- - #gpio-cells		: Must be 2.
-			  The first cell is the pin number and the
-			  second cell specifies GPIO flags, as defined in
-			  <dt-bindings/gpio/gpio.h>.
- - gpio-ranges		: Range of pins managed by the GPIO controller.
-
-
-The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
-configuration documented in pinctrl-bindings.txt.
-
-The following generic properties are supported:
- - function
- - pins
-
-Example:
-	gpio: pinctrl@71070034 {
-		compatible = "mscc,ocelot-pinctrl";
-		reg = <0x71070034 0x28>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-ranges = <&gpio 0 0 22>;
-
-		uart_pins: uart-pins {
-				pins = "GPIO_6", "GPIO_7";
-				function = "uart";
-		};
-
-		uart2_pins: uart2-pins {
-				pins = "GPIO_12", "GPIO_13";
-				function = "uart2";
-		};
-	};
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
new file mode 100644
index 000000000000..7149a6655623
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microsemi Ocelot pin controller
+
+maintainers:
+  - Alexandre Belloni <alexandre.belloni@bootlin.com>
+  - Lars Povlsen <lars.povlsen@microchip.com>
+
+properties:
+  compatible:
+    enum:
+      - microchip,lan966x-pinctrl
+      - microchip,sparx5-pinctrl
+      - mscc,jaguar2-pinctrl
+      - mscc,luton-pinctrl
+      - mscc,ocelot-pinctrl
+      - mscc,serval-pinctrl
+      - mscc,servalt-pinctrl
+
+  reg:
+    items:
+      - description: Base address
+      - description: Extended pin configuration registers
+    minItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  gpio-ranges: true
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+patternProperties:
+  '-pins$':
+    type: object
+    allOf:
+      - $ref: "pinmux-node.yaml"
+      - $ref: "pincfg-node.yaml"
+
+    properties:
+      function: true
+      pins: true
+      output-high: true
+      output-low: true
+      drive-strength: true
+
+    required:
+      - function
+      - pins
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - '#gpio-cells'
+  - gpio-ranges
+
+allOf:
+  - $ref: "pinctrl.yaml#"
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - microchip,lan966x-pinctrl
+              - microchip,sparx5-pinctrl
+    then:
+      properties:
+        reg:
+          minItems: 2
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio: pinctrl@71070034 {
+        compatible = "mscc,ocelot-pinctrl";
+        reg = <0x71070034 0x28>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&gpio 0 0 22>;
+
+        uart_pins: uart-pins {
+            pins = "GPIO_6", "GPIO_7";
+            function = "uart";
+        };
+
+        uart2_pins: uart2-pins {
+            pins = "GPIO_12", "GPIO_13";
+            function = "uart2";
+        };
+    };
+
+...
-- 
2.30.2


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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Krzysztof Kozlowski]

On 19/03/2022 21:46, Michael Walle wrote:
> Convert the ocelot-pinctrl device tree binding to the new YAML format.
> 
> Additionally to the original binding documentation, add interrupt
> properties which are optional and already used on several SoCs like
> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
> 
> Also, on the sparx5 and the lan966x SoCs there are two items for the
> reg property.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
>  .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
>  2 files changed, 108 insertions(+), 42 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
> deleted file mode 100644
> index 5d84fd299ccf..000000000000
> --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -Microsemi Ocelot pin controller Device Tree Bindings
> -----------------------------------------------------
> -
> -Required properties:
> - - compatible		: Should be "mscc,ocelot-pinctrl",
> -			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
> -			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
> -			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
> - - reg			: Address and length of the register set for the device
> - - gpio-controller	: Indicates this device is a GPIO controller
> - - #gpio-cells		: Must be 2.
> -			  The first cell is the pin number and the
> -			  second cell specifies GPIO flags, as defined in
> -			  <dt-bindings/gpio/gpio.h>.
> - - gpio-ranges		: Range of pins managed by the GPIO controller.
> -
> -
> -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
> -configuration documented in pinctrl-bindings.txt.
> -
> -The following generic properties are supported:
> - - function
> - - pins
> -
> -Example:
> -	gpio: pinctrl@71070034 {
> -		compatible = "mscc,ocelot-pinctrl";
> -		reg = <0x71070034 0x28>;
> -		gpio-controller;
> -		#gpio-cells = <2>;
> -		gpio-ranges = <&gpio 0 0 22>;
> -
> -		uart_pins: uart-pins {
> -				pins = "GPIO_6", "GPIO_7";
> -				function = "uart";
> -		};
> -
> -		uart2_pins: uart2-pins {
> -				pins = "GPIO_12", "GPIO_13";
> -				function = "uart2";
> -		};
> -	};
> diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> new file mode 100644
> index 000000000000..7149a6655623
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microsemi Ocelot pin controller
> +
> +maintainers:
> +  - Alexandre Belloni <alexandre.belloni@bootlin.com>
> +  - Lars Povlsen <lars.povlsen@microchip.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - microchip,lan966x-pinctrl
> +      - microchip,sparx5-pinctrl
> +      - mscc,jaguar2-pinctrl
> +      - mscc,luton-pinctrl
> +      - mscc,ocelot-pinctrl
> +      - mscc,serval-pinctrl
> +      - mscc,servalt-pinctrl
> +
> +  reg:
> +    items:
> +      - description: Base address
> +      - description: Extended pin configuration registers
> +    minItems: 1
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    const: 2
> +
> +  gpio-ranges: true
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2

Thanks for the changes in other files, but I think you did not respond
to my comments here. Can you address them?


Best regards,
Krzysztof

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Krzysztof Kozlowski]

On 19/03/2022 21:46, Michael Walle wrote:
> Convert the ocelot-pinctrl device tree binding to the new YAML format.
> 
> Additionally to the original binding documentation, add interrupt
> properties which are optional and already used on several SoCs like
> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
> 
> Also, on the sparx5 and the lan966x SoCs there are two items for the
> reg property.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
>  .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
>  2 files changed, 108 insertions(+), 42 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
> deleted file mode 100644
> index 5d84fd299ccf..000000000000
> --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -Microsemi Ocelot pin controller Device Tree Bindings
> -----------------------------------------------------
> -
> -Required properties:
> - - compatible		: Should be "mscc,ocelot-pinctrl",
> -			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
> -			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
> -			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
> - - reg			: Address and length of the register set for the device
> - - gpio-controller	: Indicates this device is a GPIO controller
> - - #gpio-cells		: Must be 2.
> -			  The first cell is the pin number and the
> -			  second cell specifies GPIO flags, as defined in
> -			  <dt-bindings/gpio/gpio.h>.
> - - gpio-ranges		: Range of pins managed by the GPIO controller.
> -
> -
> -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
> -configuration documented in pinctrl-bindings.txt.
> -
> -The following generic properties are supported:
> - - function
> - - pins
> -
> -Example:
> -	gpio: pinctrl@71070034 {
> -		compatible = "mscc,ocelot-pinctrl";
> -		reg = <0x71070034 0x28>;
> -		gpio-controller;
> -		#gpio-cells = <2>;
> -		gpio-ranges = <&gpio 0 0 22>;
> -
> -		uart_pins: uart-pins {
> -				pins = "GPIO_6", "GPIO_7";
> -				function = "uart";
> -		};
> -
> -		uart2_pins: uart2-pins {
> -				pins = "GPIO_12", "GPIO_13";
> -				function = "uart2";
> -		};
> -	};
> diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> new file mode 100644
> index 000000000000..7149a6655623
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microsemi Ocelot pin controller
> +
> +maintainers:
> +  - Alexandre Belloni <alexandre.belloni@bootlin.com>
> +  - Lars Povlsen <lars.povlsen@microchip.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - microchip,lan966x-pinctrl
> +      - microchip,sparx5-pinctrl
> +      - mscc,jaguar2-pinctrl
> +      - mscc,luton-pinctrl
> +      - mscc,ocelot-pinctrl
> +      - mscc,serval-pinctrl
> +      - mscc,servalt-pinctrl
> +
> +  reg:
> +    items:
> +      - description: Base address
> +      - description: Extended pin configuration registers
> +    minItems: 1
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    const: 2
> +
> +  gpio-ranges: true
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true
> +
> +  "#interrupt-cells":
> +    const: 2

Thanks for the changes in other files, but I think you did not respond
to my comments here. Can you address them?


Best regards,
Krzysztof

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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Am 2022-03-20 11:54, schrieb Krzysztof Kozlowski:
> On 19/03/2022 21:46, Michael Walle wrote:
>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>> 
>> Additionally to the original binding documentation, add interrupt
>> properties which are optional and already used on several SoCs like
>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>> 
>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>> reg property.
>> 
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 
>> ++++++++++++++++++
>>  2 files changed, 108 insertions(+), 42 deletions(-)
>>  delete mode 100644 
>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>  create mode 100644 
>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>> 
>> diff --git 
>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt 
>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>> deleted file mode 100644
>> index 5d84fd299ccf..000000000000
>> --- 
>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>> +++ /dev/null
>> @@ -1,42 +0,0 @@
>> -Microsemi Ocelot pin controller Device Tree Bindings
>> -----------------------------------------------------
>> -
>> -Required properties:
>> - - compatible		: Should be "mscc,ocelot-pinctrl",
>> -			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
>> -			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
>> -			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
>> - - reg			: Address and length of the register set for the device
>> - - gpio-controller	: Indicates this device is a GPIO controller
>> - - #gpio-cells		: Must be 2.
>> -			  The first cell is the pin number and the
>> -			  second cell specifies GPIO flags, as defined in
>> -			  <dt-bindings/gpio/gpio.h>.
>> - - gpio-ranges		: Range of pins managed by the GPIO controller.
>> -
>> -
>> -The ocelot-pinctrl driver uses the generic pin multiplexing and 
>> generic pin
>> -configuration documented in pinctrl-bindings.txt.
>> -
>> -The following generic properties are supported:
>> - - function
>> - - pins
>> -
>> -Example:
>> -	gpio: pinctrl@71070034 {
>> -		compatible = "mscc,ocelot-pinctrl";
>> -		reg = <0x71070034 0x28>;
>> -		gpio-controller;
>> -		#gpio-cells = <2>;
>> -		gpio-ranges = <&gpio 0 0 22>;
>> -
>> -		uart_pins: uart-pins {
>> -				pins = "GPIO_6", "GPIO_7";
>> -				function = "uart";
>> -		};
>> -
>> -		uart2_pins: uart2-pins {
>> -				pins = "GPIO_12", "GPIO_13";
>> -				function = "uart2";
>> -		};
>> -	};
>> diff --git 
>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml 
>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>> new file mode 100644
>> index 000000000000..7149a6655623
>> --- /dev/null
>> +++ 
>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>> @@ -0,0 +1,108 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Microsemi Ocelot pin controller
>> +
>> +maintainers:
>> +  - Alexandre Belloni <alexandre.belloni@bootlin.com>
>> +  - Lars Povlsen <lars.povlsen@microchip.com>
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - microchip,lan966x-pinctrl
>> +      - microchip,sparx5-pinctrl
>> +      - mscc,jaguar2-pinctrl
>> +      - mscc,luton-pinctrl
>> +      - mscc,ocelot-pinctrl
>> +      - mscc,serval-pinctrl
>> +      - mscc,servalt-pinctrl
>> +
>> +  reg:
>> +    items:
>> +      - description: Base address
>> +      - description: Extended pin configuration registers
>> +    minItems: 1
>> +
>> +  gpio-controller: true
>> +
>> +  '#gpio-cells':
>> +    const: 2
>> +
>> +  gpio-ranges: true
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  interrupt-controller: true
>> +
>> +  "#interrupt-cells":
>> +    const: 2
> 
> Thanks for the changes in other files, but I think you did not respond
> to my comments here. Can you address them?

Sorry, I might missunderstood you. They are currently used on all except
on serval and servalt SoCs like described in the updated commit message.
I thought it was clear from the commit message, so I didn't answer your
questions in v2. Or is there something else?

-michael

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Am 2022-03-20 11:54, schrieb Krzysztof Kozlowski:
> On 19/03/2022 21:46, Michael Walle wrote:
>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>> 
>> Additionally to the original binding documentation, add interrupt
>> properties which are optional and already used on several SoCs like
>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>> 
>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>> reg property.
>> 
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 
>> ++++++++++++++++++
>>  2 files changed, 108 insertions(+), 42 deletions(-)
>>  delete mode 100644 
>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>  create mode 100644 
>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>> 
>> diff --git 
>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt 
>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>> deleted file mode 100644
>> index 5d84fd299ccf..000000000000
>> --- 
>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>> +++ /dev/null
>> @@ -1,42 +0,0 @@
>> -Microsemi Ocelot pin controller Device Tree Bindings
>> -----------------------------------------------------
>> -
>> -Required properties:
>> - - compatible		: Should be "mscc,ocelot-pinctrl",
>> -			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
>> -			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
>> -			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
>> - - reg			: Address and length of the register set for the device
>> - - gpio-controller	: Indicates this device is a GPIO controller
>> - - #gpio-cells		: Must be 2.
>> -			  The first cell is the pin number and the
>> -			  second cell specifies GPIO flags, as defined in
>> -			  <dt-bindings/gpio/gpio.h>.
>> - - gpio-ranges		: Range of pins managed by the GPIO controller.
>> -
>> -
>> -The ocelot-pinctrl driver uses the generic pin multiplexing and 
>> generic pin
>> -configuration documented in pinctrl-bindings.txt.
>> -
>> -The following generic properties are supported:
>> - - function
>> - - pins
>> -
>> -Example:
>> -	gpio: pinctrl@71070034 {
>> -		compatible = "mscc,ocelot-pinctrl";
>> -		reg = <0x71070034 0x28>;
>> -		gpio-controller;
>> -		#gpio-cells = <2>;
>> -		gpio-ranges = <&gpio 0 0 22>;
>> -
>> -		uart_pins: uart-pins {
>> -				pins = "GPIO_6", "GPIO_7";
>> -				function = "uart";
>> -		};
>> -
>> -		uart2_pins: uart2-pins {
>> -				pins = "GPIO_12", "GPIO_13";
>> -				function = "uart2";
>> -		};
>> -	};
>> diff --git 
>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml 
>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>> new file mode 100644
>> index 000000000000..7149a6655623
>> --- /dev/null
>> +++ 
>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>> @@ -0,0 +1,108 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Microsemi Ocelot pin controller
>> +
>> +maintainers:
>> +  - Alexandre Belloni <alexandre.belloni@bootlin.com>
>> +  - Lars Povlsen <lars.povlsen@microchip.com>
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - microchip,lan966x-pinctrl
>> +      - microchip,sparx5-pinctrl
>> +      - mscc,jaguar2-pinctrl
>> +      - mscc,luton-pinctrl
>> +      - mscc,ocelot-pinctrl
>> +      - mscc,serval-pinctrl
>> +      - mscc,servalt-pinctrl
>> +
>> +  reg:
>> +    items:
>> +      - description: Base address
>> +      - description: Extended pin configuration registers
>> +    minItems: 1
>> +
>> +  gpio-controller: true
>> +
>> +  '#gpio-cells':
>> +    const: 2
>> +
>> +  gpio-ranges: true
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  interrupt-controller: true
>> +
>> +  "#interrupt-cells":
>> +    const: 2
> 
> Thanks for the changes in other files, but I think you did not respond
> to my comments here. Can you address them?

Sorry, I might missunderstood you. They are currently used on all except
on serval and servalt SoCs like described in the updated commit message.
I thought it was clear from the commit message, so I didn't answer your
questions in v2. Or is there something else?

-michael

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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Krzysztof Kozlowski]

On 20/03/2022 12:08, Michael Walle wrote:
> Am 2022-03-20 11:54, schrieb Krzysztof Kozlowski:
>> On 19/03/2022 21:46, Michael Walle wrote:
>>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>>>
>>> Additionally to the original binding documentation, add interrupt
>>> properties which are optional and already used on several SoCs like
>>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>>>
>>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>>> reg property.
>>>
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>> ---
>>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
>>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 
>>> ++++++++++++++++++
>>>  2 files changed, 108 insertions(+), 42 deletions(-)
>>>  delete mode 100644 
>>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>>  create mode 100644 
>>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>>
>>> diff --git 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>> deleted file mode 100644
>>> index 5d84fd299ccf..000000000000
>>> --- 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>> +++ /dev/null
>>> @@ -1,42 +0,0 @@
>>> -Microsemi Ocelot pin controller Device Tree Bindings
>>> -----------------------------------------------------
>>> -
>>> -Required properties:
>>> - - compatible		: Should be "mscc,ocelot-pinctrl",
>>> -			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
>>> -			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
>>> -			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
>>> - - reg			: Address and length of the register set for the device
>>> - - gpio-controller	: Indicates this device is a GPIO controller
>>> - - #gpio-cells		: Must be 2.
>>> -			  The first cell is the pin number and the
>>> -			  second cell specifies GPIO flags, as defined in
>>> -			  <dt-bindings/gpio/gpio.h>.
>>> - - gpio-ranges		: Range of pins managed by the GPIO controller.
>>> -
>>> -
>>> -The ocelot-pinctrl driver uses the generic pin multiplexing and 
>>> generic pin
>>> -configuration documented in pinctrl-bindings.txt.
>>> -
>>> -The following generic properties are supported:
>>> - - function
>>> - - pins
>>> -
>>> -Example:
>>> -	gpio: pinctrl@71070034 {
>>> -		compatible = "mscc,ocelot-pinctrl";
>>> -		reg = <0x71070034 0x28>;
>>> -		gpio-controller;
>>> -		#gpio-cells = <2>;
>>> -		gpio-ranges = <&gpio 0 0 22>;
>>> -
>>> -		uart_pins: uart-pins {
>>> -				pins = "GPIO_6", "GPIO_7";
>>> -				function = "uart";
>>> -		};
>>> -
>>> -		uart2_pins: uart2-pins {
>>> -				pins = "GPIO_12", "GPIO_13";
>>> -				function = "uart2";
>>> -		};
>>> -	};
>>> diff --git 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>> new file mode 100644
>>> index 000000000000..7149a6655623
>>> --- /dev/null
>>> +++ 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>> @@ -0,0 +1,108 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Microsemi Ocelot pin controller
>>> +
>>> +maintainers:
>>> +  - Alexandre Belloni <alexandre.belloni@bootlin.com>
>>> +  - Lars Povlsen <lars.povlsen@microchip.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - microchip,lan966x-pinctrl
>>> +      - microchip,sparx5-pinctrl
>>> +      - mscc,jaguar2-pinctrl
>>> +      - mscc,luton-pinctrl
>>> +      - mscc,ocelot-pinctrl
>>> +      - mscc,serval-pinctrl
>>> +      - mscc,servalt-pinctrl
>>> +
>>> +  reg:
>>> +    items:
>>> +      - description: Base address
>>> +      - description: Extended pin configuration registers
>>> +    minItems: 1
>>> +
>>> +  gpio-controller: true
>>> +
>>> +  '#gpio-cells':
>>> +    const: 2
>>> +
>>> +  gpio-ranges: true
>>> +
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>> +  interrupt-controller: true
>>> +
>>> +  "#interrupt-cells":
>>> +    const: 2
>>
>> Thanks for the changes in other files, but I think you did not respond
>> to my comments here. Can you address them?
> 
> Sorry, I might missunderstood you. They are currently used on all except
> on serval and servalt SoCs like described in the updated commit message.
> I thought it was clear from the commit message, so I didn't answer your
> questions in v2. Or is there something else?
> 

No, it's okay.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>


Best regards,
Krzysztof

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Krzysztof Kozlowski]

On 20/03/2022 12:08, Michael Walle wrote:
> Am 2022-03-20 11:54, schrieb Krzysztof Kozlowski:
>> On 19/03/2022 21:46, Michael Walle wrote:
>>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>>>
>>> Additionally to the original binding documentation, add interrupt
>>> properties which are optional and already used on several SoCs like
>>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>>>
>>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>>> reg property.
>>>
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>> ---
>>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
>>>  .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 
>>> ++++++++++++++++++
>>>  2 files changed, 108 insertions(+), 42 deletions(-)
>>>  delete mode 100644 
>>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>>  create mode 100644 
>>> Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>>
>>> diff --git 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>> deleted file mode 100644
>>> index 5d84fd299ccf..000000000000
>>> --- 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>>> +++ /dev/null
>>> @@ -1,42 +0,0 @@
>>> -Microsemi Ocelot pin controller Device Tree Bindings
>>> -----------------------------------------------------
>>> -
>>> -Required properties:
>>> - - compatible		: Should be "mscc,ocelot-pinctrl",
>>> -			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
>>> -			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
>>> -			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
>>> - - reg			: Address and length of the register set for the device
>>> - - gpio-controller	: Indicates this device is a GPIO controller
>>> - - #gpio-cells		: Must be 2.
>>> -			  The first cell is the pin number and the
>>> -			  second cell specifies GPIO flags, as defined in
>>> -			  <dt-bindings/gpio/gpio.h>.
>>> - - gpio-ranges		: Range of pins managed by the GPIO controller.
>>> -
>>> -
>>> -The ocelot-pinctrl driver uses the generic pin multiplexing and 
>>> generic pin
>>> -configuration documented in pinctrl-bindings.txt.
>>> -
>>> -The following generic properties are supported:
>>> - - function
>>> - - pins
>>> -
>>> -Example:
>>> -	gpio: pinctrl@71070034 {
>>> -		compatible = "mscc,ocelot-pinctrl";
>>> -		reg = <0x71070034 0x28>;
>>> -		gpio-controller;
>>> -		#gpio-cells = <2>;
>>> -		gpio-ranges = <&gpio 0 0 22>;
>>> -
>>> -		uart_pins: uart-pins {
>>> -				pins = "GPIO_6", "GPIO_7";
>>> -				function = "uart";
>>> -		};
>>> -
>>> -		uart2_pins: uart2-pins {
>>> -				pins = "GPIO_12", "GPIO_13";
>>> -				function = "uart2";
>>> -		};
>>> -	};
>>> diff --git 
>>> a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>> new file mode 100644
>>> index 000000000000..7149a6655623
>>> --- /dev/null
>>> +++ 
>>> b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
>>> @@ -0,0 +1,108 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Microsemi Ocelot pin controller
>>> +
>>> +maintainers:
>>> +  - Alexandre Belloni <alexandre.belloni@bootlin.com>
>>> +  - Lars Povlsen <lars.povlsen@microchip.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - microchip,lan966x-pinctrl
>>> +      - microchip,sparx5-pinctrl
>>> +      - mscc,jaguar2-pinctrl
>>> +      - mscc,luton-pinctrl
>>> +      - mscc,ocelot-pinctrl
>>> +      - mscc,serval-pinctrl
>>> +      - mscc,servalt-pinctrl
>>> +
>>> +  reg:
>>> +    items:
>>> +      - description: Base address
>>> +      - description: Extended pin configuration registers
>>> +    minItems: 1
>>> +
>>> +  gpio-controller: true
>>> +
>>> +  '#gpio-cells':
>>> +    const: 2
>>> +
>>> +  gpio-ranges: true
>>> +
>>> +  interrupts:
>>> +    maxItems: 1
>>> +
>>> +  interrupt-controller: true
>>> +
>>> +  "#interrupt-cells":
>>> +    const: 2
>>
>> Thanks for the changes in other files, but I think you did not respond
>> to my comments here. Can you address them?
> 
> Sorry, I might missunderstood you. They are currently used on all except
> on serval and servalt SoCs like described in the updated commit message.
> I thought it was clear from the commit message, so I didn't answer your
> questions in v2. Or is there something else?
> 

No, it's okay.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>


Best regards,
Krzysztof

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Re: [PATCH v3 0/6] pinctrl: ocelot: convert to YAML format

[Michael Walle]

Am 2022-03-19 21:46, schrieb Michael Walle:
> Convert the pinctrl ocelot binding to the new YAML format. Pin
> configuration nodes should have a "-pins" postfix. But unfortunately,
> there are many device trees which don't follow this. First rename
> all these nodes and then convert the binding to the YAML format so
> that the validation will pass.
> 
> Because there were no maintainers before and there is none in
> MAINTAINERS I added Alexandre Belloni and Lars Povlsen, juding by
> the commits - to the binding as maintainers. Please tell me if you
> disagree.

Linus, can this go through your pinctrl tree because there is this
series which depends on it:
https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

-michael

Re: [PATCH v3 0/6] pinctrl: ocelot: convert to YAML format

[Michael Walle]

Am 2022-03-19 21:46, schrieb Michael Walle:
> Convert the pinctrl ocelot binding to the new YAML format. Pin
> configuration nodes should have a "-pins" postfix. But unfortunately,
> there are many device trees which don't follow this. First rename
> all these nodes and then convert the binding to the YAML format so
> that the validation will pass.
> 
> Because there were no maintainers before and there is none in
> MAINTAINERS I added Alexandre Belloni and Lars Povlsen, juding by
> the commits - to the binding as maintainers. Please tell me if you
> disagree.

Linus, can this go through your pinctrl tree because there is this
series which depends on it:
https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

-michael

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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Linus Walleij]

On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote:

> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>
> Additionally to the original binding documentation, add interrupt
> properties which are optional and already used on several SoCs like
> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>
> Also, on the sparx5 and the lan966x SoCs there are two items for the
> reg property.
>
> Signed-off-by: Michael Walle <michael@walle.cc>

So is this single patch something I should apply to the pin control tree?
If you want to merge it all through ARM SoC go ahead:
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Linus Walleij]

On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote:

> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>
> Additionally to the original binding documentation, add interrupt
> properties which are optional and already used on several SoCs like
> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>
> Also, on the sparx5 and the lan966x SoCs there are two items for the
> reg property.
>
> Signed-off-by: Michael Walle <michael@walle.cc>

So is this single patch something I should apply to the pin control tree?
If you want to merge it all through ARM SoC go ahead:
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Am 2022-04-18 01:41, schrieb Linus Walleij:
> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote:
> 
>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>> 
>> Additionally to the original binding documentation, add interrupt
>> properties which are optional and already used on several SoCs like
>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>> 
>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>> reg property.
>> 
>> Signed-off-by: Michael Walle <michael@walle.cc>
> 
> So is this single patch something I should apply to the pin control 
> tree?

The first five patches will fix the validation errrors once the
binding is converted to the YAML format. So, do they need to go
through the same tree?

Also as mentioned, there is this pending series [1] which is the
reason I've converted the binding to YAML in the first place. So
at least the first patch of this series will have to go through
the same tree as the YAML conversion patch.

How can we move forward here? Krzysztof, maybe all of the dt
bindings patches can go through your tree and I'll reposting
the second patch of [1] afterwards?

-michael

[1] 
https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Am 2022-04-18 01:41, schrieb Linus Walleij:
> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote:
> 
>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>> 
>> Additionally to the original binding documentation, add interrupt
>> properties which are optional and already used on several SoCs like
>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>> 
>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>> reg property.
>> 
>> Signed-off-by: Michael Walle <michael@walle.cc>
> 
> So is this single patch something I should apply to the pin control 
> tree?

The first five patches will fix the validation errrors once the
binding is converted to the YAML format. So, do they need to go
through the same tree?

Also as mentioned, there is this pending series [1] which is the
reason I've converted the binding to YAML in the first place. So
at least the first patch of this series will have to go through
the same tree as the YAML conversion patch.

How can we move forward here? Krzysztof, maybe all of the dt
bindings patches can go through your tree and I'll reposting
the second patch of [1] afterwards?

-michael

[1] 
https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

[resend, use Krysztof's new email address]

Am 2022-04-18 01:41, schrieb Linus Walleij:
> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote:
> 
>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>> 
>> Additionally to the original binding documentation, add interrupt
>> properties which are optional and already used on several SoCs like
>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>> 
>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>> reg property.
>> 
>> Signed-off-by: Michael Walle <michael@walle.cc>
> 
> So is this single patch something I should apply to the pin control 
> tree?

The first five patches will fix the validation errrors once the
binding is converted to the YAML format. So, do they need to go
through the same tree?

Also as mentioned, there is this pending series [1] which is the
reason I've converted the binding to YAML in the first place. So
at least the first patch of this series will have to go through
the same tree as the YAML conversion patch.

How can we move forward here? Krzysztof, maybe all of the dt
bindings patches can go through your tree and I'll reposting
the second patch of [1] afterwards?

-michael

[1] 
https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

[resend, use Krysztof's new email address]

Am 2022-04-18 01:41, schrieb Linus Walleij:
> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote:
> 
>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>> 
>> Additionally to the original binding documentation, add interrupt
>> properties which are optional and already used on several SoCs like
>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>> 
>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>> reg property.
>> 
>> Signed-off-by: Michael Walle <michael@walle.cc>
> 
> So is this single patch something I should apply to the pin control 
> tree?

The first five patches will fix the validation errrors once the
binding is converted to the YAML format. So, do they need to go
through the same tree?

Also as mentioned, there is this pending series [1] which is the
reason I've converted the binding to YAML in the first place. So
at least the first patch of this series will have to go through
the same tree as the YAML conversion patch.

How can we move forward here? Krzysztof, maybe all of the dt
bindings patches can go through your tree and I'll reposting
the second patch of [1] afterwards?

-michael

[1] 
https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Krzysztof Kozlowski]

On 18/04/2022 10:19, Michael Walle wrote:
> [resend, use Krysztof's new email address]
> 
> Am 2022-04-18 01:41, schrieb Linus Walleij:
>> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote:
>>
>>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>>>
>>> Additionally to the original binding documentation, add interrupt
>>> properties which are optional and already used on several SoCs like
>>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>>>
>>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>>> reg property.
>>>
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>
>> So is this single patch something I should apply to the pin control 
>> tree?
> 
> The first five patches will fix the validation errrors once the
> binding is converted to the YAML format. So, do they need to go
> through the same tree?
> 
> Also as mentioned, there is this pending series [1] which is the
> reason I've converted the binding to YAML in the first place. So
> at least the first patch of this series will have to go through
> the same tree as the YAML conversion patch.
> 
> How can we move forward here? Krzysztof, maybe all of the dt
> bindings patches can go through your tree and I'll reposting
> the second patch of [1] afterwards?

I think you got all necessary acks for this pinctrl bindings change and
the dependency ("add reset property"), so both can go via Linus' tree.
That's preferred.

DTS patches goes through your SoC maintainer tree.

At least this is the usual scenario, but maybe I missed here something.

Best regards,
Krzysztof

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Krzysztof Kozlowski]

On 18/04/2022 10:19, Michael Walle wrote:
> [resend, use Krysztof's new email address]
> 
> Am 2022-04-18 01:41, schrieb Linus Walleij:
>> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> wrote:
>>
>>> Convert the ocelot-pinctrl device tree binding to the new YAML format.
>>>
>>> Additionally to the original binding documentation, add interrupt
>>> properties which are optional and already used on several SoCs like
>>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>>>
>>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>>> reg property.
>>>
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>
>> So is this single patch something I should apply to the pin control 
>> tree?
> 
> The first five patches will fix the validation errrors once the
> binding is converted to the YAML format. So, do they need to go
> through the same tree?
> 
> Also as mentioned, there is this pending series [1] which is the
> reason I've converted the binding to YAML in the first place. So
> at least the first patch of this series will have to go through
> the same tree as the YAML conversion patch.
> 
> How can we move forward here? Krzysztof, maybe all of the dt
> bindings patches can go through your tree and I'll reposting
> the second patch of [1] afterwards?

I think you got all necessary acks for this pinctrl bindings change and
the dependency ("add reset property"), so both can go via Linus' tree.
That's preferred.

DTS patches goes through your SoC maintainer tree.

At least this is the usual scenario, but maybe I missed here something.

Best regards,
Krzysztof

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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Am 2022-04-18 13:13, schrieb Krzysztof Kozlowski:
> On 18/04/2022 10:19, Michael Walle wrote:
>> [resend, use Krysztof's new email address]
>> 
>> Am 2022-04-18 01:41, schrieb Linus Walleij:
>>> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> 
>>> wrote:
>>> 
>>>> Convert the ocelot-pinctrl device tree binding to the new YAML 
>>>> format.
>>>> 
>>>> Additionally to the original binding documentation, add interrupt
>>>> properties which are optional and already used on several SoCs like
>>>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>>>> 
>>>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>>>> reg property.
>>>> 
>>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>> 
>>> So is this single patch something I should apply to the pin control
>>> tree?
>> 
>> The first five patches will fix the validation errrors once the
>> binding is converted to the YAML format. So, do they need to go
>> through the same tree?
>> 
>> Also as mentioned, there is this pending series [1] which is the
>> reason I've converted the binding to YAML in the first place. So
>> at least the first patch of this series will have to go through
>> the same tree as the YAML conversion patch.
>> 
>> How can we move forward here? Krzysztof, maybe all of the dt
>> bindings patches can go through your tree and I'll reposting
>> the second patch of [1] afterwards?
> 
> I think you got all necessary acks for this pinctrl bindings change and
> the dependency ("add reset property"), so both can go via Linus' tree.
> That's preferred.
> 
> DTS patches goes through your SoC maintainer tree.

Ah, ok, I wasn't aware of that. Then yes, please go ahead and
pick this and the first patch of [1] up, Linus.

Of course if you like you can pick the second patch of [1],
too. But I can also repost it without the RFC tag if that is
preferred.

-michael

[1] 
https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Am 2022-04-18 13:13, schrieb Krzysztof Kozlowski:
> On 18/04/2022 10:19, Michael Walle wrote:
>> [resend, use Krysztof's new email address]
>> 
>> Am 2022-04-18 01:41, schrieb Linus Walleij:
>>> On Sat, Mar 19, 2022 at 9:47 PM Michael Walle <michael@walle.cc> 
>>> wrote:
>>> 
>>>> Convert the ocelot-pinctrl device tree binding to the new YAML 
>>>> format.
>>>> 
>>>> Additionally to the original binding documentation, add interrupt
>>>> properties which are optional and already used on several SoCs like
>>>> SparX-5, Luton, Ocelot and LAN966x but were not documented before.
>>>> 
>>>> Also, on the sparx5 and the lan966x SoCs there are two items for the
>>>> reg property.
>>>> 
>>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>> 
>>> So is this single patch something I should apply to the pin control
>>> tree?
>> 
>> The first five patches will fix the validation errrors once the
>> binding is converted to the YAML format. So, do they need to go
>> through the same tree?
>> 
>> Also as mentioned, there is this pending series [1] which is the
>> reason I've converted the binding to YAML in the first place. So
>> at least the first patch of this series will have to go through
>> the same tree as the YAML conversion patch.
>> 
>> How can we move forward here? Krzysztof, maybe all of the dt
>> bindings patches can go through your tree and I'll reposting
>> the second patch of [1] afterwards?
> 
> I think you got all necessary acks for this pinctrl bindings change and
> the dependency ("add reset property"), so both can go via Linus' tree.
> That's preferred.
> 
> DTS patches goes through your SoC maintainer tree.

Ah, ok, I wasn't aware of that. Then yes, please go ahead and
pick this and the first patch of [1] up, Linus.

Of course if you like you can pick the second patch of [1],
too. But I can also repost it without the RFC tag if that is
preferred.

-michael

[1] 
https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

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Re: [PATCH v3 0/6] pinctrl: ocelot: convert to YAML format

[Linus Walleij]

On Sat, Mar 19, 2022 at 9:46 PM Michael Walle <michael@walle.cc> wrote:

>   dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

This patch applied to the pinctrl tree, please send the rest
through the SoC tree.

Yours,
Linus Walleij

Re: [PATCH v3 0/6] pinctrl: ocelot: convert to YAML format

[Linus Walleij]

On Sat, Mar 19, 2022 at 9:46 PM Michael Walle <michael@walle.cc> wrote:

>   dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

This patch applied to the pinctrl tree, please send the rest
through the SoC tree.

Yours,
Linus Walleij

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Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Linus Walleij]

On Mon, Apr 18, 2022 at 2:04 PM Michael Walle <michael@walle.cc> wrote:
> Am 2022-04-18 13:13, schrieb Krzysztof Kozlowski:

> > I think you got all necessary acks for this pinctrl bindings change and
> > the dependency ("add reset property"), so both can go via Linus' tree.
> > That's preferred.
> >
> > DTS patches goes through your SoC maintainer tree.
>
> Ah, ok, I wasn't aware of that. Then yes, please go ahead and
> pick this and the first patch of [1] up, Linus.

I picked up this patch but:

> [1]
> https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

These patches don't apply to my tree. Please rebase on
the pinctrl "devel" branch and resend!
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

Yours,
Linus Walleij

Re: [PATCH v3 6/6] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Linus Walleij]

On Mon, Apr 18, 2022 at 2:04 PM Michael Walle <michael@walle.cc> wrote:
> Am 2022-04-18 13:13, schrieb Krzysztof Kozlowski:

> > I think you got all necessary acks for this pinctrl bindings change and
> > the dependency ("add reset property"), so both can go via Linus' tree.
> > That's preferred.
> >
> > DTS patches goes through your SoC maintainer tree.
>
> Ah, ok, I wasn't aware of that. Then yes, please go ahead and
> pick this and the first patch of [1] up, Linus.

I picked up this patch but:

> [1]
> https://lore.kernel.org/linux-gpio/20220313154640.63813-1-michael@walle.cc/

These patches don't apply to my tree. Please rebase on
the pinctrl "devel" branch and resend!
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=devel

Yours,
Linus Walleij

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Re: [PATCH v3 5/6] ARM: dts: lan966x: rename pinctrl nodes

[Nicolas Ferre]

On 19/03/2022 at 21:46, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The pinctrl device tree binding will be converted to YAML format. Rename
> the pin nodes so they end with "-pins" to match the schema.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

For the record:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

This patch was taken by Claudiu and sent in the PR targeting 5.19 
arm-soc tree via the at91-dt branch. It's currently in linux-next.

Best regards,
   Nicolas

> ---
>   arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
> index 3281af90ac6d..3c7e3a7d6f14 100644
> --- a/arch/arm/boot/dts/lan966x-pcb8291.dts
> +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
> @@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
>                  function = "fc3_b";
>          };
> 
> -       can0_b_pins:  can0_b_pins {
> +       can0_b_pins:  can0-b-pins {
>                  /* RX, TX */
>                  pins = "GPIO_35", "GPIO_36";
>                  function = "can0_b";
> --
> 2.30.2
> 


-- 
Nicolas Ferre

Re: [PATCH v3 5/6] ARM: dts: lan966x: rename pinctrl nodes

[Nicolas Ferre]

On 19/03/2022 at 21:46, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> The pinctrl device tree binding will be converted to YAML format. Rename
> the pin nodes so they end with "-pins" to match the schema.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

For the record:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

This patch was taken by Claudiu and sent in the PR targeting 5.19 
arm-soc tree via the at91-dt branch. It's currently in linux-next.

Best regards,
   Nicolas

> ---
>   arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
> index 3281af90ac6d..3c7e3a7d6f14 100644
> --- a/arch/arm/boot/dts/lan966x-pcb8291.dts
> +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
> @@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
>                  function = "fc3_b";
>          };
> 
> -       can0_b_pins:  can0_b_pins {
> +       can0_b_pins:  can0-b-pins {
>                  /* RX, TX */
>                  pins = "GPIO_35", "GPIO_36";
>                  function = "can0_b";
> --
> 2.30.2
> 


-- 
Nicolas Ferre

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Re: (subset) [PATCH v3 4/6] arm64: dts: sparx5: rename pinctrl nodes

[Krzysztof Kozlowski]

On Sat, 19 Mar 2022 21:46:26 +0100, Michael Walle wrote:
> The pinctrl device tree binding will be converted to YAML format. Rename
> the pin nodes so they end with "-pins" to match the schema.
> 
> 

Applied, thanks!

[4/6] arm64: dts: sparx5: rename pinctrl nodes
      https://git.kernel.org/krzk/linux-dt/c/d5e64404e77c19ec5bd687b34a11eec0263f1aa8

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Re: (subset) [PATCH v3 4/6] arm64: dts: sparx5: rename pinctrl nodes

[Krzysztof Kozlowski]

On Sat, 19 Mar 2022 21:46:26 +0100, Michael Walle wrote:
> The pinctrl device tree binding will be converted to YAML format. Rename
> the pin nodes so they end with "-pins" to match the schema.
> 
> 

Applied, thanks!

[4/6] arm64: dts: sparx5: rename pinctrl nodes
      https://git.kernel.org/krzk/linux-dt/c/d5e64404e77c19ec5bd687b34a11eec0263f1aa8

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

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