* [U-Boot] [Patch V5 0/4] add mips64 cpus support
@ 2012-09-04 14:32 Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 1/4] MIPS: Don't use camel-case style Zhizhou Zhang
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Zhizhou Zhang @ 2012-09-04 14:32 UTC (permalink / raw)
To: u-boot
This patch add mips64 cpu support. In this version, I have tested it both
when configured running in ram version and running in rom version.
qemu-system-mips64 -M mips -cpu MIPS64R2-generic -bios u-boot.bin -nographic
U-Boot 2012.07-00146-g42c7773 (Sep 04 2012 - 21:56:46)
Board: Qemu -M mips CPU: unknown proc_id=0x10000
DRAM: 128 MiB
Using default environment
In: serial
Out: serial
Err: serial
Net: NE2000
qemu-mips64 #
Changes in V5:
- omit camel-case style
- avoid running "git bisect" failed
- some code style problem corrected
Changes in V4:
- Add both big-endian and little-endian support
- Remove cache probe
- Add standalone support for mips64
Changes in V3:
- merge related files into one patch, no longer one file one patch.
- add detailed commit message.
- remove standalone example. it's too complicate.
Zhizhou Zhang (4):
MIPS: Don't use camel-case style
MIPS: change address related header files
MIPS: don't define CONFIG_SYS_TEXT_BASE in config.mk
MIPS: add board qemu-mips64 support
arch/mips/cpu/mips32/cache.S | 10 +-
arch/mips/cpu/mips32/cpu.c | 8 +-
arch/mips/cpu/mips64/Makefile | 45 ++++++
arch/mips/cpu/mips64/cache.S | 229 +++++++++++++++++++++++++++++++
arch/mips/cpu/mips64/config.mk | 40 ++++++
arch/mips/cpu/mips64/cpu.c | 111 +++++++++++++++
arch/mips/cpu/mips64/interrupts.c | 34 +++++
arch/mips/cpu/mips64/start.S | 256 +++++++++++++++++++++++++++++++++++
arch/mips/cpu/mips64/time.c | 87 ++++++++++++
arch/mips/cpu/xburst/cpu.c | 12 +-
arch/mips/cpu/xburst/start.S | 4 +-
arch/mips/include/asm/addrspace.h | 2 +-
arch/mips/include/asm/asm.h | 2 +-
arch/mips/include/asm/cacheops.h | 82 +++++------
arch/mips/include/asm/io.h | 16 +++
arch/mips/include/asm/posix_types.h | 6 +
board/qemu-mips/config.mk | 10 --
board/qemu-mips/u-boot.lds | 8 ++
boards.cfg | 2 +
examples/standalone/mips64.lds | 59 ++++++++
include/configs/qemu-mips.h | 1 +
include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++
22 files changed, 1125 insertions(+), 70 deletions(-)
create mode 100644 arch/mips/cpu/mips64/Makefile
create mode 100644 arch/mips/cpu/mips64/cache.S
create mode 100644 arch/mips/cpu/mips64/config.mk
create mode 100644 arch/mips/cpu/mips64/cpu.c
create mode 100644 arch/mips/cpu/mips64/interrupts.c
create mode 100644 arch/mips/cpu/mips64/start.S
create mode 100644 arch/mips/cpu/mips64/time.c
delete mode 100644 board/qemu-mips/config.mk
create mode 100644 examples/standalone/mips64.lds
create mode 100644 include/configs/qemu-mips64.h
--
1.7.9.5
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 1/4] MIPS: Don't use camel-case style
2012-09-04 14:32 [U-Boot] [Patch V5 0/4] add mips64 cpus support Zhizhou Zhang
@ 2012-09-04 14:32 ` Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 2/4] MIPS: change address related header files Zhizhou Zhang
` (2 subsequent siblings)
3 siblings, 0 replies; 11+ messages in thread
From: Zhizhou Zhang @ 2012-09-04 14:32 UTC (permalink / raw)
To: u-boot
Replace camel-case style with upper-case style globally.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
arch/mips/cpu/mips32/cache.S | 10 ++---
arch/mips/cpu/mips32/cpu.c | 8 ++--
arch/mips/cpu/xburst/cpu.c | 12 +++---
arch/mips/cpu/xburst/start.S | 4 +-
arch/mips/include/asm/cacheops.h | 82 +++++++++++++++++++-------------------
5 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8b..64dfad0 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
-2: cache_op Fill t0
+2: cache_op FILL t0
PTR_ADDU t0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 7b49e1b..50bb248 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
return;
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += lsize;
@@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
@@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..cc190df 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
}
}
@@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
}
void flush_icache_all(void)
@@ -118,7 +118,7 @@ void flush_icache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Store_Tag_I, addr);
+ cache_op(INDEX_STORE_TAG_I, addr);
}
/* invalidate btb */
@@ -139,7 +139,7 @@ void flush_dcache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Writeback_Inv_D, addr);
+ cache_op(INDEX_WRITEBACK_INV_D, addr);
}
__asm__ __volatile__("sync");
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index d846104..3a8280c 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -96,7 +96,7 @@ relocate_code:
li t0, KSEG0
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
2:
- cache Index_Writeback_Inv_D, 0(t0)
+ cache INDEX_WRITEBACK_INV_D, 0(t0)
bne t0, t1, 2b
addi t0, CONFIG_SYS_CACHELINE_SIZE
@@ -106,7 +106,7 @@ relocate_code:
li t0, KSEG0
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
3:
- cache Index_Invalidate_I, 0(t0)
+ cache INDEX_INVALIDATE_I, 0(t0)
bne t0, t1, 3b
addi t0, CONFIG_SYS_CACHELINE_SIZE
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 70bcad7..6464250 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -14,54 +14,54 @@
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
+#define INDEX_INVALIDATE_I 0x00
+#define INDEX_WRITEBACK_INV_D 0x01
+#define INDEX_LOAD_TAG_I 0x04
+#define INDEX_LOAD_TAG_D 0x05
+#define INDEX_STORE_TAG_I 0x08
+#define INDEX_STORE_TAG_D 0x09
#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I 0x00
+#define HIT_INVALIDATE_I 0x00
#else
-#define Hit_Invalidate_I 0x10
+#define HIT_INVALIDATE_I 0x10
#endif
-#define Hit_Invalidate_D 0x11
-#define Hit_Writeback_Inv_D 0x15
+#define HIT_INVALIDATE_D 0x11
+#define HIT_WRITEBACK_INV_D 0x15
/*
* R4000-specific cacheops
*/
-#define Create_Dirty_Excl_D 0x0d
-#define Fill 0x14
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
+#define CREATE_DIRTY_EXCL_D 0x0d
+#define FILL 0x14
+#define HIT_WRITEBACK_I 0x18
+#define HIT_WRITEBACK_D 0x19
/*
* R4000SC and R4400SC-specific cacheops
*/
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_SD 0x1b
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
+#define INDEX_INVALIDATE_SI 0x02
+#define INDEX_WRITEBACK_INV_SD 0x03
+#define INDEX_LOAD_TAG_SI 0x06
+#define INDEX_LOAD_TAG_SD 0x07
+#define INDEX_STORE_TAG_SI 0x0A
+#define INDEX_STORE_TAG_SD 0x0B
+#define CREATE_DIRTY_EXCL_SD 0x0f
+#define HIT_INVALIDATE_SI 0x12
+#define HIT_INVALIDATE_SD 0x13
+#define HIT_WRITEBACK_INV_SD 0x17
+#define HIT_WRITEBACK_SD 0x1b
+#define HIT_SET_VIRTUAL_SI 0x1e
+#define HIT_SET_VIRTUAL_SD 0x1f
/*
* R5000-specific cacheops
*/
-#define R5K_Page_Invalidate_S 0x17
+#define R5K_PAGE_INVALIDATE_S 0x17
/*
* RM7000-specific cacheops
*/
-#define Page_Invalidate_T 0x16
+#define PAGE_INVALIDATE_T 0x16
/*
* R10000-specific cacheops
@@ -69,17 +69,17 @@
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
-#define Index_Writeback_Inv_S 0x03
-#define Index_Load_Tag_S 0x07
-#define Index_Store_Tag_S 0x0B
-#define Hit_Invalidate_S 0x13
-#define Cache_Barrier 0x14
-#define Hit_Writeback_Inv_S 0x17
-#define Index_Load_Data_I 0x18
-#define Index_Load_Data_D 0x19
-#define Index_Load_Data_S 0x1b
-#define Index_Store_Data_I 0x1c
-#define Index_Store_Data_D 0x1d
-#define Index_Store_Data_S 0x1f
+#define INDEX_WRITEBACK_INV_S 0x03
+#define INDEX_LOAD_TAG_S 0x07
+#define INDEX_STORE_TAG_S 0x0B
+#define HIT_INVALIDATE_S 0x13
+#define CACHE_BARRIER 0x14
+#define HIT_WRITEBACK_INV_S 0x17
+#define INDEX_LOAD_DATA_I 0x18
+#define INDEX_LOAD_DATA_D 0x19
+#define INDEX_LOAD_DATA_S 0x1b
+#define INDEX_STORE_DATA_I 0x1c
+#define INDEX_STORE_DATA_D 0x1d
+#define INDEX_STORE_DATA_S 0x1f
#endif /* __ASM_CACHEOPS_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 2/4] MIPS: change address related header files
2012-09-04 14:32 [U-Boot] [Patch V5 0/4] add mips64 cpus support Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 1/4] MIPS: Don't use camel-case style Zhizhou Zhang
@ 2012-09-04 14:32 ` Zhizhou Zhang
2012-09-04 22:25 ` Daniel Schwierzeck
2012-09-04 14:32 ` [U-Boot] [Patch V5 3/4] MIPS: don't define CONFIG_SYS_TEXT_BASE in config.mk Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support Zhizhou Zhang
3 siblings, 1 reply; 11+ messages in thread
From: Zhizhou Zhang @ 2012-09-04 14:32 UTC (permalink / raw)
To: u-boot
Prepare for upcoming mips64 support. This patch add mips64 address
space support.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
arch/mips/include/asm/addrspace.h | 2 +-
arch/mips/include/asm/asm.h | 2 +-
arch/mips/include/asm/io.h | 16 ++++++++++++++++
arch/mips/include/asm/posix_types.h | 6 ++++++
4 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 608cfcf..933ccb1 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -401,7 +401,7 @@ symbol = value
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
-#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
+#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
#else
#define R10KCBARRIER(addr)
#endif
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..80eab75 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
index 879aae2..6566ad0 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int __kernel_ipc_pid_t;
typedef int __kernel_uid_t;
typedef int __kernel_gid_t;
+#ifndef CONFIG_MIPS64
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 3/4] MIPS: don't define CONFIG_SYS_TEXT_BASE in config.mk
2012-09-04 14:32 [U-Boot] [Patch V5 0/4] add mips64 cpus support Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 1/4] MIPS: Don't use camel-case style Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 2/4] MIPS: change address related header files Zhizhou Zhang
@ 2012-09-04 14:32 ` Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support Zhizhou Zhang
3 siblings, 0 replies; 11+ messages in thread
From: Zhizhou Zhang @ 2012-09-04 14:32 UTC (permalink / raw)
To: u-boot
We define CONFIG_SYS_TEXT_BASE in board's specified header file.
So config.mk is useless, then remove it.
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
board/qemu-mips/config.mk | 10 ----------
include/configs/qemu-mips.h | 1 +
2 files changed, 1 insertion(+), 10 deletions(-)
delete mode 100644 board/qemu-mips/config.mk
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk
deleted file mode 100644
index 27cd34a..0000000
--- a/board/qemu-mips/config.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc00000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index b8b9705..f45f78b 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -137,6 +137,7 @@
*/
/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support
2012-09-04 14:32 [U-Boot] [Patch V5 0/4] add mips64 cpus support Zhizhou Zhang
` (2 preceding siblings ...)
2012-09-04 14:32 ` [U-Boot] [Patch V5 3/4] MIPS: don't define CONFIG_SYS_TEXT_BASE in config.mk Zhizhou Zhang
@ 2012-09-04 14:32 ` Zhizhou Zhang
2012-09-04 22:36 ` Daniel Schwierzeck
2012-09-04 23:12 ` Daniel Schwierzeck
3 siblings, 2 replies; 11+ messages in thread
From: Zhizhou Zhang @ 2012-09-04 14:32 UTC (permalink / raw)
To: u-boot
Both big-endian and little-endian are tested with below commands:
Rom version: (Default, Now we config it as rom version)
qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
Ram version:
qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
---
arch/mips/cpu/mips64/Makefile | 45 +++++++
arch/mips/cpu/mips64/cache.S | 229 +++++++++++++++++++++++++++++++++
arch/mips/cpu/mips64/config.mk | 40 ++++++
arch/mips/cpu/mips64/cpu.c | 111 ++++++++++++++++
arch/mips/cpu/mips64/interrupts.c | 34 +++++
arch/mips/cpu/mips64/start.S | 256 +++++++++++++++++++++++++++++++++++++
arch/mips/cpu/mips64/time.c | 87 +++++++++++++
board/qemu-mips/u-boot.lds | 8 ++
boards.cfg | 2 +
examples/standalone/mips64.lds | 59 +++++++++
include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++
11 files changed, 1042 insertions(+)
create mode 100644 arch/mips/cpu/mips64/Makefile
create mode 100644 arch/mips/cpu/mips64/cache.S
create mode 100644 arch/mips/cpu/mips64/config.mk
create mode 100644 arch/mips/cpu/mips64/cpu.c
create mode 100644 arch/mips/cpu/mips64/interrupts.c
create mode 100644 arch/mips/cpu/mips64/start.S
create mode 100644 arch/mips/cpu/mips64/time.c
create mode 100644 examples/standalone/mips64.lds
create mode 100644 include/configs/qemu-mips64.h
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile
new file mode 100644
index 0000000..be38664
--- /dev/null
+++ b/arch/mips/cpu/mips64/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).o
+
+START = start.o
+COBJS-y = cpu.o interrupts.o time.o cache.o
+
+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S
new file mode 100644
index 0000000..036f035
--- /dev/null
+++ b/arch/mips/cpu/mips64/cache.S
@@ -0,0 +1,229 @@
+/*
+ * Cache-handling routined for MIPS CPUs
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#define RA t9
+
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE 0x10000
+
+#define INDEX_BASE CKSEG0
+
+ .macro cache_op op addr
+ .set push
+ .set noreorder
+ .set mips3
+ cache \op, 0(\addr)
+ .set pop
+ .endm
+
+ .macro f_fill64 dst, offset, val
+ LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
+#if LONGSIZE == 4
+ LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
+#endif
+ .endm
+
+/*
+ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
+ */
+LEAF(mips_init_icache)
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
+ /* clear tag to invalidate */
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, a1
+1: cache_op INDEX_STORE_TAG_I t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+ /* fill once, so data field parity is correct */
+ PTR_LI t0, INDEX_BASE
+2: cache_op FILL t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 2b
+ /* invalidate again - prudent but not strictly neccessary */
+ PTR_LI t0, INDEX_BASE
+1: cache_op INDEX_STORE_TAG_I t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+9: jr ra
+ END(mips_init_icache)
+
+/*
+ * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
+ */
+LEAF(mips_init_dcache)
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, a1
+1: cache_op INDEX_STORE_TAG_D t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+ /* load from each line (in cached space) */
+ PTR_LI t0, INDEX_BASE
+2: LONG_L zero, 0(t0)
+ PTR_ADDU t0, a2
+ bne t0, t1, 2b
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+1: cache_op INDEX_STORE_TAG_D t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+9: jr ra
+ END(mips_init_dcache)
+
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity. It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ * RETURNS: N/A
+ *
+ */
+NESTED(mips_cache_reset, 0, ra)
+ move RA, ra
+ li t2, CONFIG_SYS_ICACHE_SIZE
+ li t3, CONFIG_SYS_DCACHE_SIZE
+ li t8, CONFIG_SYS_CACHELINE_SIZE
+
+ li v0, MIPS_MAX_CACHE_SIZE
+
+ /*
+ * Now clear that much memory starting from zero.
+ */
+ PTR_LI a0, CKSEG1
+ PTR_ADDU a1, a0, v0
+2: PTR_ADDIU a0, 64
+ f_fill64 a0, -64, zero
+ bne a0, a1, 2b
+
+ /*
+ * The caches are probably in an indeterminate state,
+ * so we force good parity into them by doing an
+ * invalidate, load/fill, invalidate for each line.
+ */
+
+ /*
+ * Assume bottom of RAM will generate good parity for the cache.
+ */
+
+ /*
+ * Initialize the I-cache first,
+ */
+ move a1, t2
+ move a2, t8
+ PTR_LA v1, mips_init_icache
+ jalr v1
+
+ /*
+ * then initialize D-cache.
+ */
+ move a1, t3
+ move a2, t8
+ PTR_LA v1, mips_init_dcache
+ jalr v1
+
+ jr RA
+ END(mips_cache_reset)
+
+/*
+ * dcache_status - get cache status
+ *
+ * RETURNS: 0 - cache disabled; 1 - cache enabled
+ *
+ */
+LEAF(dcache_status)
+ mfc0 t0, CP0_CONFIG
+ li t1, CONF_CM_UNCACHED
+ andi t0, t0, CONF_CM_CMASK
+ move v0, zero
+ beq t0, t1, 2f
+ li v0, 1
+2: jr ra
+ END(dcache_status)
+
+/*
+ * dcache_disable - disable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_disable)
+ mfc0 t0, CP0_CONFIG
+ li t1, -8
+ and t0, t0, t1
+ ori t0, t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_disable)
+
+/*
+ * dcache_enable - enable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_enable)
+ mfc0 t0, CP0_CONFIG
+ ori t0, CONF_CM_CMASK
+ xori t0, CONF_CM_CMASK
+ ori t0, CONF_CM_CACHABLE_NONCOHERENT
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_enable)
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk
new file mode 100644
index 0000000..ebc1ceb
--- /dev/null
+++ b/arch/mips/cpu/mips64/config.mk
@@ -0,0 +1,40 @@
+#
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Default optimization level for MIPS64
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips64
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS += -m elf64btsmip
+else
+PLATFORM_LDFLAGS += -m elf64ltsmip
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644
index 0000000..2a38d0c
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#define cache_op(op, addr) \
+ __asm__ __volatile__( \
+ " .set push\n" \
+ " .set noreorder\n" \
+ " .set mips64\n" \
+ " cache %0, %1\n" \
+ " .set pop\n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+ fprintf(stderr, "*** reset failed ***\n");
+
+ while (1)
+ /* NOP */;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(HIT_INVALIDATE_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
diff --git a/arch/mips/cpu/mips64/interrupts.c b/arch/mips/cpu/mips64/interrupts.c
new file mode 100644
index 0000000..e4e9aae
--- /dev/null
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+ return 0;
+}
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
new file mode 100644
index 0000000..dc941b8
--- /dev/null
+++ b/arch/mips/cpu/mips64/start.S
@@ -0,0 +1,256 @@
+/*
+ * Startup Code for MIPS64 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any dlater version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+ /*
+ * For the moment disable interrupts, mark the kernel mode and
+ * set ST0_KX so that the CPU does not spit fire when using
+ * 64-bit addresses.
+ */
+ .macro setup_c0_status set clr
+ .set push
+ mfc0 t0, CP0_STATUS
+ or t0, ST0_CU0 | \set | 0x1f | \clr
+ xor t0, 0x1f | \clr
+ mtc0 t0, CP0_STATUS
+ .set noreorder
+ sll zero, 3 # ehb
+ .set pop
+ .endm
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .org 0x000
+ b reset
+ nop
+ .org 0x080
+ b romReserved
+ nop
+ .org 0x100
+ b romReserved
+ nop
+ .org 0x180
+ b romReserved
+ nop
+ .org 0x200
+ b romReserved
+ nop
+ .org 0x280
+ b romReserved
+ nop
+ .org 0x300
+ b romReserved
+ nop
+ .org 0x380
+ b romReserved
+ nop
+ .org 0x480
+ b romReserved
+ nop
+
+ /*
+ * We hope there are no more reserved vectors!
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
+ .org 0x500
+ .align 4
+reset:
+
+ /* Clear watch registers */
+ dmtc0 zero, CP0_WATCHLO
+ dmtc0 zero, CP0_WATCHHI
+
+ /* WP(Watch Pending), SW0/1 should be cleared */
+ mtc0 zero, CP0_CAUSE
+
+ setup_c0_status ST0_KX 0
+
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* CONFIG0 register */
+ li t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Initialize $gp */
+ bal 1f
+ nop
+ .dword _gp
+1:
+ ld gp, 0(ra)
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
+ dla t9, lowlevel_init
+ jalr t9
+ nop
+
+ /* Initialize caches... */
+ dla t9, mips_cache_reset
+ jalr t9
+ nop
+
+ /* ... and enable them */
+ li t0, CONFIG_SYS_MIPS_CACHE_MODE
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Set up temporary stack */
+ li t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ dla sp, 0(t0)
+
+ dla t9, board_init_f
+ jr t9
+ nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+ .globl relocate_code
+ .ent relocate_code
+relocate_code:
+ move sp, a0 # set new stack pointer
+
+ li t0, CONFIG_SYS_MONITOR_BASE
+ dla t3, in_ram
+ ld t2, -24(t3) # t2 <-- uboot_end_data
+ move t1, a2
+ move s2, a2 # s2 <-- destination address
+
+ /*
+ * Fix $gp:
+ *
+ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+ */
+ move t8, gp
+ dsub gp, CONFIG_SYS_MONITOR_BASE
+ dadd gp, a2 # gp now adjusted
+ dsub s1, gp, t8 # s1 <-- relocation offset
+
+ /*
+ * t0 = source address
+ * t1 = target address
+ * t2 = source end address
+ */
+
+ /*
+ * Save destination address and size for dlater usage in flush_cache()
+ */
+ move s0, a1 # save gd in s0
+ move a0, t1 # a0 <-- destination addr
+ dsub a1, t2, t0 # a1 <-- size
+
+1:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ daddu t0, 4
+ ble t0, t2, 1b
+ daddu t1, 4
+
+ /* If caches were enabled, we would have to flush them here. */
+
+ /* a0 & a1 are already set up for flush_cache(start, size) */
+ dla t9, flush_cache
+ jalr t9
+ nop
+
+ /* Jump to where we've relocated ourselves */
+ daddi t0, s2, in_ram - _start
+ jr t0
+ nop
+
+ .dword _gp
+ .dword _GLOBAL_OFFSET_TABLE_
+ .dword uboot_end_data
+ .dword uboot_end
+ .dword num_got_entries
+
+in_ram:
+ /*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+ ld t3, -8(t0) # t3 <-- num_got_entries
+ ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ ld t9, -40(t0) # t9 <-- _gp
+ dsub t8, t9 # compute offset
+ dadd t8, t8, gp # t8 now holds relocated _G_O_T_
+ daddi t8, t8, 16 # skipping first two entries
+ li t2, 2
+1:
+ ld t1, 0(t8)
+ beqz t1, 2f
+ dadd t1, s1
+ sd t1, 0(t8)
+2:
+ daddi t2, 1
+ blt t2, t3, 1b
+ daddi t8, 8
+
+ /* Clear BSS */
+ ld t1, -24(t0) # t1 <-- uboot_end_data
+ ld t2, -16(t0) # t2 <-- uboot_end
+ dadd t1, s1 # adjust pointers
+ dadd t2, s1
+
+ dsub t1, 8
+1:
+ daddi t1, 8
+ bltl t1, t2, 1b
+ sd zero, 0(t1)
+
+ move a0, s0 # a0 <-- gd
+ dla t9, board_init_r
+ jr t9
+ move a1, s2
+
+ .end relocate_code
+
+ /* Exception handlers */
+romReserved:
+ b romReserved
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644
index 0000000..5154280
--- /dev/null
+++ b/arch/mips/cpu/mips64/time.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY \
+ (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) < 0x7fffffff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return timestamp - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
+ while ((tmo - read_c0_count()) < 0x7fffffff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..4d9580f 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
+#else
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) >> 3;
+#else
num_got_entries = (__got_end - __got_start) >> 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
diff --git a/boards.cfg b/boards.cfg
index 6b54941..ff4bb0c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -380,6 +380,8 @@ M5485HFE m68k mcf547x_8x m548xevb freescale -
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN
qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
+qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN
+qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds
new file mode 100644
index 0000000..9b27ef4
--- /dev/null
+++ b/examples/standalone/mips64.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
+*/
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
+OUTPUT_ARCH(mips)
+SECTIONS
+{
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ .sdata : { *(.sdata*) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
+
+ _end = .;
+}
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 0000000..216326d
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 /* MIPS64 CPU core */
+#define CONFIG_QEMU_MIPS1
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
+ "panic=1\0" \
+ "bootfile=/tftpboot/vmlinux\0" \
+ "load=tftp ffffffff80500000 ${u-boot}\0" \
+ ""
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#define CONFIG_DP83902A
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 115200
+#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8)
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
+#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
+#define CONFIG_SYS_ATA_DATA_OFFSET (0)
+#define CONFIG_SYS_ATA_REG_OFFSET (0)
+#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000)
+
+#define CONFIG_SYS_IDE_MAXDEVICE (4)
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT "qemu-mips64el # "
+#else
+#define CONFIG_SYS_PROMPT "qemu-mips64 # "
+#endif
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+
+#define CONFIG_SYS_MHZ 132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_HZ 1000
+
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
+
+#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
+#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_CMD_NO_FLASH
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+/* The following #defines are needed to get flash environment right */
+#undef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* ROM Version */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE 0x8000
+
+#define CONFIG_ENV_OVERWRITE
+
+#define MEM_SIZE 128
+
+#define CONFIG_LZA
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 16384
+#define CONFIG_SYS_ICACHE_SIZE 16384
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#endif /* __CONFIG_H */
--
1.7.9.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 2/4] MIPS: change address related header files
2012-09-04 14:32 ` [U-Boot] [Patch V5 2/4] MIPS: change address related header files Zhizhou Zhang
@ 2012-09-04 22:25 ` Daniel Schwierzeck
2012-09-05 11:40 ` Zhi-zhou Zhang
0 siblings, 1 reply; 11+ messages in thread
From: Daniel Schwierzeck @ 2012-09-04 22:25 UTC (permalink / raw)
To: u-boot
2012/9/4 Zhizhou Zhang <etou.zh@gmail.com>:
> Prepare for upcoming mips64 support. This patch add mips64 address
> space support.
>
> Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> ---
> arch/mips/include/asm/addrspace.h | 2 +-
> arch/mips/include/asm/asm.h | 2 +-
> arch/mips/include/asm/io.h | 16 ++++++++++++++++
> arch/mips/include/asm/posix_types.h | 6 ++++++
> 4 files changed, 24 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
> index 3a1e6d6..b768bb5 100644
> --- a/arch/mips/include/asm/addrspace.h
> +++ b/arch/mips/include/asm/addrspace.h
> @@ -136,7 +136,7 @@
> cannot access physical memory directly from core */
> #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
> #else /* !CONFIG_SOC_AU1X00 */
> -#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
> +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
> #endif /* CONFIG_SOC_AU1X00 */
> #endif /* __ASSEMBLY__ */
>
> diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
> index 608cfcf..933ccb1 100644
> --- a/arch/mips/include/asm/asm.h
> +++ b/arch/mips/include/asm/asm.h
> @@ -401,7 +401,7 @@ symbol = value
> #ifdef CONFIG_SGI_IP28
> /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
> #include <asm/cacheops.h>
> -#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
> +#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
this change is unrelated to this patch. I guess this belongs to patch 1/4
> #else
> #define R10KCBARRIER(addr)
> #endif
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 025012a..80eab75 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
> */
> extern inline phys_addr_t virt_to_phys(volatile void * address)
> {
> +#ifndef CONFIG_64BIT
> return CPHYSADDR(address);
> +#else
> + return XPHYSADDR(address);
> +#endif
> }
>
> extern inline void * phys_to_virt(unsigned long address)
> {
> +#ifndef CONFIG_64BIT
> return (void *)KSEG0ADDR(address);
> +#else
> + return (void *)CKSEG0ADDR(address);
> +#endif
> }
>
> /*
> @@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
> */
> extern inline unsigned long virt_to_bus(volatile void * address)
> {
> +#ifndef CONFIG_64BIT
> return CPHYSADDR(address);
> +#else
> + return XPHYSADDR(address);
> +#endif
> }
>
> extern inline void * bus_to_virt(unsigned long address)
> {
> +#ifndef CONFIG_64BIT
> return (void *)KSEG0ADDR(address);
> +#else
> + return (void *)CKSEG0ADDR(address);
> +#endif
> }
>
> /*
> diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
> index 879aae2..6566ad0 100644
> --- a/arch/mips/include/asm/posix_types.h
> +++ b/arch/mips/include/asm/posix_types.h
> @@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
> typedef int __kernel_ipc_pid_t;
> typedef int __kernel_uid_t;
> typedef int __kernel_gid_t;
> +#ifndef CONFIG_MIPS64
> typedef unsigned int __kernel_size_t;
> typedef int __kernel_ssize_t;
> typedef int __kernel_ptrdiff_t;
> +#else
> +typedef unsigned long __kernel_size_t;
> +typedef long __kernel_ssize_t;
> +typedef long __kernel_ptrdiff_t;
> +#endif
> typedef long __kernel_time_t;
> typedef long __kernel_suseconds_t;
> typedef long __kernel_clock_t;
> --
> 1.7.9.5
>
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support
2012-09-04 14:32 ` [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support Zhizhou Zhang
@ 2012-09-04 22:36 ` Daniel Schwierzeck
2012-09-04 23:12 ` Daniel Schwierzeck
1 sibling, 0 replies; 11+ messages in thread
From: Daniel Schwierzeck @ 2012-09-04 22:36 UTC (permalink / raw)
To: u-boot
2012/9/4 Zhizhou Zhang <etou.zh@gmail.com>:
> Both big-endian and little-endian are tested with below commands:
> Rom version: (Default, Now we config it as rom version)
> qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
> qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
> Ram version:
> qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
> qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
>
> Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> ---
> arch/mips/cpu/mips64/Makefile | 45 +++++++
> arch/mips/cpu/mips64/cache.S | 229 +++++++++++++++++++++++++++++++++
> arch/mips/cpu/mips64/config.mk | 40 ++++++
> arch/mips/cpu/mips64/cpu.c | 111 ++++++++++++++++
> arch/mips/cpu/mips64/interrupts.c | 34 +++++
> arch/mips/cpu/mips64/start.S | 256 +++++++++++++++++++++++++++++++++++++
> arch/mips/cpu/mips64/time.c | 87 +++++++++++++
> board/qemu-mips/u-boot.lds | 8 ++
> boards.cfg | 2 +
> examples/standalone/mips64.lds | 59 +++++++++
> include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++
> 11 files changed, 1042 insertions(+)
> create mode 100644 arch/mips/cpu/mips64/Makefile
> create mode 100644 arch/mips/cpu/mips64/cache.S
> create mode 100644 arch/mips/cpu/mips64/config.mk
> create mode 100644 arch/mips/cpu/mips64/cpu.c
> create mode 100644 arch/mips/cpu/mips64/interrupts.c
> create mode 100644 arch/mips/cpu/mips64/start.S
> create mode 100644 arch/mips/cpu/mips64/time.c
> create mode 100644 examples/standalone/mips64.lds
> create mode 100644 include/configs/qemu-mips64.h
>
[...]
> diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
> new file mode 100644
> index 0000000..216326d
> --- /dev/null
> +++ b/include/configs/qemu-mips64.h
> @@ -0,0 +1,171 @@
> +/*
> + * (C) Copyright 2003
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * This file contains the configuration parameters for qemu-mips64 target.
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_MIPS64 /* MIPS64 CPU core */
> +#define CONFIG_QEMU_MIPS1
#define CONFIG_QEMU_MIPS
arch/mips/lib/config.mk depends on that config option
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
> +
> +#define CONFIG_BAUDRATE 115200
> +
> +/* valid baudrates */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +
> +#define CONFIG_TIMESTAMP /* Print image info with timestamp */
> +#undef CONFIG_BOOTARGS
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "addmisc=setenv bootargs ${bootargs} " \
> + "console=ttyS0,${baudrate} " \
> + "panic=1\0" \
> + "bootfile=/tftpboot/vmlinux\0" \
> + "load=tftp ffffffff80500000 ${u-boot}\0" \
> + ""
> +
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#define CONFIG_DP83902A
> +
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_EXT2
> +#undef CONFIG_CMD_LOADB
> +#undef CONFIG_CMD_LOADS
> +#define CONFIG_CMD_DHCP
> +
> +#define CONFIG_DRIVER_NE2000
> +#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
> +
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE 1
> +#define CONFIG_SYS_NS16550_CLK 115200
> +#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8)
> +#define CONFIG_CONS_INDEX 1
> +
> +#define CONFIG_CMD_IDE
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_SYS_IDE_MAXBUS 2
> +#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
> +#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
> +#define CONFIG_SYS_ATA_DATA_OFFSET (0)
> +#define CONFIG_SYS_ATA_REG_OFFSET (0)
> +#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000)
> +
> +#define CONFIG_SYS_IDE_MAXDEVICE (4)
> +
> +#define CONFIG_CMD_RARP
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +
> +/* Monitor Command Prompt */
> +#if defined(CONFIG_SYS_LITTLE_ENDIAN)
> +#define CONFIG_SYS_PROMPT "qemu-mips64el # "
> +#else
> +#define CONFIG_SYS_PROMPT "qemu-mips64 # "
> +#endif
> +
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +
> +/* Console I/O Buffer Size */
> +#define CONFIG_SYS_CBSIZE 256
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> +/* max number of command args */
> +#define CONFIG_SYS_MAXARGS 16
> +
> +#define CONFIG_SYS_MALLOC_LEN 128*1024
> +
> +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
> +
> +#define CONFIG_SYS_MHZ 132
> +
> +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
> +
> +#define CONFIG_SYS_HZ 1000
> +
> +/* Cached addr */
> +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
> +
> +/* default load address */
> +#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
> +
> +#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
> +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
> +
> +/*-----------------------------------------------------------------------
> + * FLASH and environment organization
> + */
> +#define CONFIG_CMD_NO_FLASH
> +#define CONFIG_SYS_NO_FLASH
> +#undef CONFIG_CMD_IMLS
> +
> +/* The following #defines are needed to get flash environment right */
> +#undef CONFIG_SYS_TEXT_BASE
> +#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* ROM Version */
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
> +#define CONFIG_ENV_IS_NOWHERE
> +
> +/* Address and size of Primary Environment Sector */
> +#define CONFIG_ENV_SIZE 0x8000
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define MEM_SIZE 128
> +
> +#define CONFIG_LZA
> +
> +/*-----------------------------------------------------------------------
> + * Cache Configuration
> + */
> +#define CONFIG_SYS_DCACHE_SIZE 16384
> +#define CONFIG_SYS_ICACHE_SIZE 16384
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> +
> +#endif /* __CONFIG_H */
> --
> 1.7.9.5
>
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support
2012-09-04 14:32 ` [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support Zhizhou Zhang
2012-09-04 22:36 ` Daniel Schwierzeck
@ 2012-09-04 23:12 ` Daniel Schwierzeck
2012-09-05 11:59 ` Zhi-zhou Zhang
1 sibling, 1 reply; 11+ messages in thread
From: Daniel Schwierzeck @ 2012-09-04 23:12 UTC (permalink / raw)
To: u-boot
2012/9/4 Zhizhou Zhang <etou.zh@gmail.com>:
> Both big-endian and little-endian are tested with below commands:
> Rom version: (Default, Now we config it as rom version)
> qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
> qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic -nographic
> Ram version:
> qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
> qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic
>
> Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> ---
> arch/mips/cpu/mips64/Makefile | 45 +++++++
> arch/mips/cpu/mips64/cache.S | 229 +++++++++++++++++++++++++++++++++
> arch/mips/cpu/mips64/config.mk | 40 ++++++
> arch/mips/cpu/mips64/cpu.c | 111 ++++++++++++++++
> arch/mips/cpu/mips64/interrupts.c | 34 +++++
> arch/mips/cpu/mips64/start.S | 256 +++++++++++++++++++++++++++++++++++++
> arch/mips/cpu/mips64/time.c | 87 +++++++++++++
> board/qemu-mips/u-boot.lds | 8 ++
> boards.cfg | 2 +
> examples/standalone/mips64.lds | 59 +++++++++
> include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++
> 11 files changed, 1042 insertions(+)
> create mode 100644 arch/mips/cpu/mips64/Makefile
> create mode 100644 arch/mips/cpu/mips64/cache.S
> create mode 100644 arch/mips/cpu/mips64/config.mk
> create mode 100644 arch/mips/cpu/mips64/cpu.c
> create mode 100644 arch/mips/cpu/mips64/interrupts.c
> create mode 100644 arch/mips/cpu/mips64/start.S
> create mode 100644 arch/mips/cpu/mips64/time.c
> create mode 100644 examples/standalone/mips64.lds
> create mode 100644 include/configs/qemu-mips64.h
>
[...]
> diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
> new file mode 100644
> index 0000000..216326d
> --- /dev/null
> +++ b/include/configs/qemu-mips64.h
> @@ -0,0 +1,171 @@
> +/*
> + * (C) Copyright 2003
> + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +/*
> + * This file contains the configuration parameters for qemu-mips64 target.
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#define CONFIG_MIPS64 /* MIPS64 CPU core */
> +#define CONFIG_QEMU_MIPS1
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
> +
> +#define CONFIG_BAUDRATE 115200
> +
> +/* valid baudrates */
> +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
> +
> +#define CONFIG_TIMESTAMP /* Print image info with timestamp */
> +#undef CONFIG_BOOTARGS
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "addmisc=setenv bootargs ${bootargs} " \
> + "console=ttyS0,${baudrate} " \
> + "panic=1\0" \
> + "bootfile=/tftpboot/vmlinux\0" \
> + "load=tftp ffffffff80500000 ${u-boot}\0" \
> + ""
> +
why have you omitted this?
#define CONFIG_BOOTCOMMAND "bootp;bootelf"
#define CONFIG_CMD_ELF
> +/*
> + * BOOTP options
> + */
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#define CONFIG_DP83902A
> +
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_EXT2
> +#undef CONFIG_CMD_LOADB
> +#undef CONFIG_CMD_LOADS
> +#define CONFIG_CMD_DHCP
> +
> +#define CONFIG_DRIVER_NE2000
> +#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
> +
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE 1
> +#define CONFIG_SYS_NS16550_CLK 115200
> +#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8)
> +#define CONFIG_CONS_INDEX 1
> +
> +#define CONFIG_CMD_IDE
> +#define CONFIG_DOS_PARTITION
> +
> +#define CONFIG_SYS_IDE_MAXBUS 2
> +#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
> +#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
> +#define CONFIG_SYS_ATA_DATA_OFFSET (0)
> +#define CONFIG_SYS_ATA_REG_OFFSET (0)
> +#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000)
> +
> +#define CONFIG_SYS_IDE_MAXDEVICE (4)
> +
> +#define CONFIG_CMD_RARP
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +
> +/* Monitor Command Prompt */
> +#if defined(CONFIG_SYS_LITTLE_ENDIAN)
> +#define CONFIG_SYS_PROMPT "qemu-mips64el # "
> +#else
> +#define CONFIG_SYS_PROMPT "qemu-mips64 # "
> +#endif
> +
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_CMDLINE_EDITING
> +#define CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +
> +/* Console I/O Buffer Size */
> +#define CONFIG_SYS_CBSIZE 256
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> +/* max number of command args */
> +#define CONFIG_SYS_MAXARGS 16
> +
> +#define CONFIG_SYS_MALLOC_LEN 128*1024
> +
> +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
> +
> +#define CONFIG_SYS_MHZ 132
> +
> +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
> +
> +#define CONFIG_SYS_HZ 1000
> +
> +/* Cached addr */
> +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
> +
> +/* default load address */
> +#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
> +
> +#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
> +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
> +
> +/*-----------------------------------------------------------------------
> + * FLASH and environment organization
> + */
> +#define CONFIG_CMD_NO_FLASH
> +#define CONFIG_SYS_NO_FLASH
> +#undef CONFIG_CMD_IMLS
why have you omitted the flash support? qemu-system-mips supports
flash emulation
with the option -pflash. It already works with a qemu_mips32 U-boot.
> +
> +/* The following #defines are needed to get flash environment right */
> +#undef CONFIG_SYS_TEXT_BASE
drop this line
> +#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* ROM Version */
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +
> +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
> +#define CONFIG_ENV_IS_NOWHERE
> +
> +/* Address and size of Primary Environment Sector */
> +#define CONFIG_ENV_SIZE 0x8000
> +
> +#define CONFIG_ENV_OVERWRITE
> +
> +#define MEM_SIZE 128
> +
> +#define CONFIG_LZA
#define CONFIG_LZMA
> +
> +/*-----------------------------------------------------------------------
> + * Cache Configuration
> + */
> +#define CONFIG_SYS_DCACHE_SIZE 16384
> +#define CONFIG_SYS_ICACHE_SIZE 16384
> +#define CONFIG_SYS_CACHELINE_SIZE 32
> +
> +#endif /* __CONFIG_H */
> --
> 1.7.9.5
>
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 2/4] MIPS: change address related header files
2012-09-04 22:25 ` Daniel Schwierzeck
@ 2012-09-05 11:40 ` Zhi-zhou Zhang
0 siblings, 0 replies; 11+ messages in thread
From: Zhi-zhou Zhang @ 2012-09-05 11:40 UTC (permalink / raw)
To: u-boot
On Wed, Sep 5, 2012 at 6:25 AM, Daniel Schwierzeck <
daniel.schwierzeck@gmail.com> wrote:
> 2012/9/4 Zhizhou Zhang <etou.zh@gmail.com>:
> > Prepare for upcoming mips64 support. This patch add mips64 address
> > space support.
> >
> > Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> > ---
> > arch/mips/include/asm/addrspace.h | 2 +-
> > arch/mips/include/asm/asm.h | 2 +-
> > arch/mips/include/asm/io.h | 16 ++++++++++++++++
> > arch/mips/include/asm/posix_types.h | 6 ++++++
> > 4 files changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/mips/include/asm/addrspace.h
> b/arch/mips/include/asm/addrspace.h
> > index 3a1e6d6..b768bb5 100644
> > --- a/arch/mips/include/asm/addrspace.h
> > +++ b/arch/mips/include/asm/addrspace.h
> > @@ -136,7 +136,7 @@
> > cannot access physical memory directly from core */
> > #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
> > #else /* !CONFIG_SOC_AU1X00 */
> > -#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
> > +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
> > #endif /* CONFIG_SOC_AU1X00 */
> > #endif /* __ASSEMBLY__ */
> >
> > diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
> > index 608cfcf..933ccb1 100644
> > --- a/arch/mips/include/asm/asm.h
> > +++ b/arch/mips/include/asm/asm.h
> > @@ -401,7 +401,7 @@ symbol = value
> > #ifdef CONFIG_SGI_IP28
> > /* Inhibit speculative stores to volatile (e.g.DMA) or invalid
> addresses. */
> > #include <asm/cacheops.h>
> > -#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
> > +#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
>
> this change is unrelated to this patch. I guess this belongs to patch 1/4
>
> I'm so careless! Then what should I do now? need I resend these once
again? I think that's not good..
> > #else
> > #define R10KCBARRIER(addr)
> > #endif
> > diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> > index 025012a..80eab75 100644
> > --- a/arch/mips/include/asm/io.h
> > +++ b/arch/mips/include/asm/io.h
> > @@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long
> base)
> > */
> > extern inline phys_addr_t virt_to_phys(volatile void * address)
> > {
> > +#ifndef CONFIG_64BIT
> > return CPHYSADDR(address);
> > +#else
> > + return XPHYSADDR(address);
> > +#endif
> > }
> >
> > extern inline void * phys_to_virt(unsigned long address)
> > {
> > +#ifndef CONFIG_64BIT
> > return (void *)KSEG0ADDR(address);
> > +#else
> > + return (void *)CKSEG0ADDR(address);
> > +#endif
> > }
> >
> > /*
> > @@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long
> address)
> > */
> > extern inline unsigned long virt_to_bus(volatile void * address)
> > {
> > +#ifndef CONFIG_64BIT
> > return CPHYSADDR(address);
> > +#else
> > + return XPHYSADDR(address);
> > +#endif
> > }
> >
> > extern inline void * bus_to_virt(unsigned long address)
> > {
> > +#ifndef CONFIG_64BIT
> > return (void *)KSEG0ADDR(address);
> > +#else
> > + return (void *)CKSEG0ADDR(address);
> > +#endif
> > }
> >
> > /*
> > diff --git a/arch/mips/include/asm/posix_types.h
> b/arch/mips/include/asm/posix_types.h
> > index 879aae2..6566ad0 100644
> > --- a/arch/mips/include/asm/posix_types.h
> > +++ b/arch/mips/include/asm/posix_types.h
> > @@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
> > typedef int __kernel_ipc_pid_t;
> > typedef int __kernel_uid_t;
> > typedef int __kernel_gid_t;
> > +#ifndef CONFIG_MIPS64
> > typedef unsigned int __kernel_size_t;
> > typedef int __kernel_ssize_t;
> > typedef int __kernel_ptrdiff_t;
> > +#else
> > +typedef unsigned long __kernel_size_t;
> > +typedef long __kernel_ssize_t;
> > +typedef long __kernel_ptrdiff_t;
> > +#endif
> > typedef long __kernel_time_t;
> > typedef long __kernel_suseconds_t;
> > typedef long __kernel_clock_t;
> > --
> > 1.7.9.5
> >
>
>
>
> --
> Best regards,
> Daniel
>
--
Regards,
Zhizhou Zhang
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support
2012-09-04 23:12 ` Daniel Schwierzeck
@ 2012-09-05 11:59 ` Zhi-zhou Zhang
2012-09-05 16:48 ` Daniel Schwierzeck
0 siblings, 1 reply; 11+ messages in thread
From: Zhi-zhou Zhang @ 2012-09-05 11:59 UTC (permalink / raw)
To: u-boot
On Wed, Sep 5, 2012 at 7:12 AM, Daniel Schwierzeck <
daniel.schwierzeck@gmail.com> wrote:
> 2012/9/4 Zhizhou Zhang <etou.zh@gmail.com>:
> > Both big-endian and little-endian are tested with below commands:
> > Rom version: (Default, Now we config it as rom version)
> > qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic
> -nographic
> > qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic
> -nographic
> > Ram version:
> > qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot
> -nographic
> > qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot
> -nographic
> >
> > Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>
> > ---
> > arch/mips/cpu/mips64/Makefile | 45 +++++++
> > arch/mips/cpu/mips64/cache.S | 229
> +++++++++++++++++++++++++++++++++
> > arch/mips/cpu/mips64/config.mk | 40 ++++++
> > arch/mips/cpu/mips64/cpu.c | 111 ++++++++++++++++
> > arch/mips/cpu/mips64/interrupts.c | 34 +++++
> > arch/mips/cpu/mips64/start.S | 256
> +++++++++++++++++++++++++++++++++++++
> > arch/mips/cpu/mips64/time.c | 87 +++++++++++++
> > board/qemu-mips/u-boot.lds | 8 ++
> > boards.cfg | 2 +
> > examples/standalone/mips64.lds | 59 +++++++++
> > include/configs/qemu-mips64.h | 171 +++++++++++++++++++++++++
> > 11 files changed, 1042 insertions(+)
> > create mode 100644 arch/mips/cpu/mips64/Makefile
> > create mode 100644 arch/mips/cpu/mips64/cache.S
> > create mode 100644 arch/mips/cpu/mips64/config.mk
> > create mode 100644 arch/mips/cpu/mips64/cpu.c
> > create mode 100644 arch/mips/cpu/mips64/interrupts.c
> > create mode 100644 arch/mips/cpu/mips64/start.S
> > create mode 100644 arch/mips/cpu/mips64/time.c
> > create mode 100644 examples/standalone/mips64.lds
> > create mode 100644 include/configs/qemu-mips64.h
> >
> [...]
> > diff --git a/include/configs/qemu-mips64.h
> b/include/configs/qemu-mips64.h
> > new file mode 100644
> > index 0000000..216326d
> > --- /dev/null
> > +++ b/include/configs/qemu-mips64.h
> > @@ -0,0 +1,171 @@
> > +/*
> > + * (C) Copyright 2003
> > + * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> > +/*
> > + * This file contains the configuration parameters for qemu-mips64
> target.
> > + */
> > +
> > +#ifndef __CONFIG_H
> > +#define __CONFIG_H
> > +
> > +#define CONFIG_MIPS64 /* MIPS64 CPU core */
> > +#define CONFIG_QEMU_MIPS1
> > +#define CONFIG_MISC_INIT_R
> > +
> > +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
> > +
> > +#define CONFIG_BAUDRATE 115200
> > +
> > +/* valid baudrates */
> > +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600,
> 115200 }
> > +
> > +#define CONFIG_TIMESTAMP /* Print image info with
> timestamp */
> > +#undef CONFIG_BOOTARGS
> > +
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > + "addmisc=setenv bootargs ${bootargs} " \
> > + "console=ttyS0,${baudrate} " \
> > + "panic=1\0" \
> > + "bootfile=/tftpboot/vmlinux\0" \
> > + "load=tftp ffffffff80500000 ${u-boot}\0" \
> > + ""
> > +
>
> why have you omitted this?
>
> #define CONFIG_BOOTCOMMAND "bootp;bootelf"
>
> #define CONFIG_CMD_ELF
>
> Because I haven't tested `bootelf' command. I'm not should it work or not.
Another reason is that when I configure CONFIG_CMD_ELF I will get lots of
warning such as:
cmd_elf.c: In function 'load_elf_image_phdr':
cmd_elf.c:289:15: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
cmd_elf.c: In function 'load_elf_image_shdr':
cmd_elf.c:343:12: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
cmd_elf.c:346:12: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
> +/*
> > + * BOOTP options
> > + */
> > +#define CONFIG_BOOTP_BOOTFILESIZE
> > +#define CONFIG_BOOTP_BOOTPATH
> > +#define CONFIG_BOOTP_GATEWAY
> > +#define CONFIG_BOOTP_HOSTNAME
> > +
> > +/*
> > + * Command line configuration.
> > + */
> > +#include <config_cmd_default.h>
> > +#define CONFIG_DP83902A
> > +
> > +#define CONFIG_CMD_FAT
> > +#define CONFIG_CMD_EXT2
> > +#undef CONFIG_CMD_LOADB
> > +#undef CONFIG_CMD_LOADS
> > +#define CONFIG_CMD_DHCP
> > +
> > +#define CONFIG_DRIVER_NE2000
> > +#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
> > +
> > +#define CONFIG_SYS_NS16550
> > +#define CONFIG_SYS_NS16550_SERIAL
> > +#define CONFIG_SYS_NS16550_REG_SIZE 1
> > +#define CONFIG_SYS_NS16550_CLK 115200
> > +#define CONFIG_SYS_NS16550_COM1 (0xffffffffb40003f8)
> > +#define CONFIG_CONS_INDEX 1
> > +
> > +#define CONFIG_CMD_IDE
> > +#define CONFIG_DOS_PARTITION
> > +
> > +#define CONFIG_SYS_IDE_MAXBUS 2
> > +#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
> > +#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
> > +#define CONFIG_SYS_ATA_DATA_OFFSET (0)
> > +#define CONFIG_SYS_ATA_REG_OFFSET (0)
> > +#define CONFIG_SYS_ATA_BASE_ADDR (0xffffffffb4000000)
> > +
> > +#define CONFIG_SYS_IDE_MAXDEVICE (4)
> > +
> > +#define CONFIG_CMD_RARP
> > +
> > +/*
> > + * Miscellaneous configurable options
> > + */
> > +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> > +
> > +/* Monitor Command Prompt */
> > +#if defined(CONFIG_SYS_LITTLE_ENDIAN)
> > +#define CONFIG_SYS_PROMPT "qemu-mips64el # "
> > +#else
> > +#define CONFIG_SYS_PROMPT "qemu-mips64 # "
> > +#endif
> > +
> > +#define CONFIG_AUTO_COMPLETE
> > +#define CONFIG_CMDLINE_EDITING
> > +#define CONFIG_SYS_HUSH_PARSER
> > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> > +
> > +/* Console I/O Buffer Size */
> > +#define CONFIG_SYS_CBSIZE 256
> > +/* Print Buffer Size */
> > +#define CONFIG_SYS_PBSIZE
> (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
> > +/* max number of command args */
> > +#define CONFIG_SYS_MAXARGS 16
> > +
> > +#define CONFIG_SYS_MALLOC_LEN 128*1024
> > +
> > +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
> > +
> > +#define CONFIG_SYS_MHZ 132
> > +
> > +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
> > +
> > +#define CONFIG_SYS_HZ 1000
> > +
> > +/* Cached addr */
> > +#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
> > +
> > +/* default load address */
> > +#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
> > +
> > +#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
> > +#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
> > +
> >
> +/*-----------------------------------------------------------------------
> > + * FLASH and environment organization
> > + */
> > +#define CONFIG_CMD_NO_FLASH
> > +#define CONFIG_SYS_NO_FLASH
> > +#undef CONFIG_CMD_IMLS
>
> why have you omitted the flash support? qemu-system-mips supports
> flash emulation
> with the option -pflash. It already works with a qemu_mips32 U-boot.
>
> Yes, I have tested with -pflash in qemu_mips64 either. I have forgot why I
omit
it now. By the way, which commit should I base on of my next patch?
> > +
> > +/* The following #defines are needed to get flash environment right */
> > +#undef CONFIG_SYS_TEXT_BASE
>
> drop this line
>
> > +#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* ROM
> Version */
> > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> > +
> > +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
> > +#define CONFIG_ENV_IS_NOWHERE
> > +
> > +/* Address and size of Primary Environment Sector */
> > +#define CONFIG_ENV_SIZE 0x8000
> > +
> > +#define CONFIG_ENV_OVERWRITE
> > +
> > +#define MEM_SIZE 128
> > +
> > +#define CONFIG_LZA
>
> #define CONFIG_LZMA
>
> Thanks, I will put more attention on checking this file.
> > +
> >
> +/*-----------------------------------------------------------------------
> > + * Cache Configuration
> > + */
> > +#define CONFIG_SYS_DCACHE_SIZE 16384
> > +#define CONFIG_SYS_ICACHE_SIZE 16384
> > +#define CONFIG_SYS_CACHELINE_SIZE 32
> > +
> > +#endif /* __CONFIG_H */
> > --
> > 1.7.9.5
> >
>
>
>
> --
> Best regards,
> Daniel
>
--
Regards,
Zhizhou Zhang
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support
2012-09-05 11:59 ` Zhi-zhou Zhang
@ 2012-09-05 16:48 ` Daniel Schwierzeck
0 siblings, 0 replies; 11+ messages in thread
From: Daniel Schwierzeck @ 2012-09-05 16:48 UTC (permalink / raw)
To: u-boot
2012/9/5 Zhi-zhou Zhang <etou.zh@gmail.com>:
[...]
>>
>> why have you omitted this?
>>
>> #define CONFIG_BOOTCOMMAND "bootp;bootelf"
>>
>> #define CONFIG_CMD_ELF
>>
> Because I haven't tested `bootelf' command. I'm not should it work or not.
> Another reason is that when I configure CONFIG_CMD_ELF I will get lots of
> warning such as:
> cmd_elf.c: In function 'load_elf_image_phdr':
> cmd_elf.c:289:15: warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
> cmd_elf.c: In function 'load_elf_image_shdr':
> cmd_elf.c:343:12: warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
> cmd_elf.c:346:12: warning: cast to pointer from integer of different size
> [-Wint-to-pointer-cast]
ok but there are similar warnings in other files too. We can fix those
files later.
My point is that all qemu_mips variants should be configured with the
same options.
[...]
>>
>> why have you omitted the flash support? qemu-system-mips supports
>> flash emulation
>> with the option -pflash. It already works with a qemu_mips32 U-boot.
>>
> Yes, I have tested with -pflash in qemu_mips64 either. I have forgot why I
> omit
> it now. By the way, which commit should I base on of my next patch?
it is still git://git.denx.de/u-boot-mips.git master
--
Best regards,
Daniel
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2012-09-05 16:48 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-09-04 14:32 [U-Boot] [Patch V5 0/4] add mips64 cpus support Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 1/4] MIPS: Don't use camel-case style Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 2/4] MIPS: change address related header files Zhizhou Zhang
2012-09-04 22:25 ` Daniel Schwierzeck
2012-09-05 11:40 ` Zhi-zhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 3/4] MIPS: don't define CONFIG_SYS_TEXT_BASE in config.mk Zhizhou Zhang
2012-09-04 14:32 ` [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support Zhizhou Zhang
2012-09-04 22:36 ` Daniel Schwierzeck
2012-09-04 23:12 ` Daniel Schwierzeck
2012-09-05 11:59 ` Zhi-zhou Zhang
2012-09-05 16:48 ` Daniel Schwierzeck
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.