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* [PATCH V5 0/5]  clk: Samsung: audss: Register audio subsytem clocks using common clk framework
@ 2013-06-04 12:28 ` Padmavathi Venna
  0 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, padma.v, padma.kvr
  Cc: sbkim73, broonie, kgene.kim, mturquette

Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem
has a internal clock controller which controls i2s0 and pcm0 clocks. This patch
series adds the Samsung audio subsytem clock to the common clock framework and
provides the I2S controllers clock information in the dtsi file.

This patch series is made based on Kukjin Kim for-next branch

Changes since V4:
        - Reworked on the nits given by Doug.
        - Removed mout_audss and mout_i2s from i2s nodes as we are not
          getting these clocks in the i2s driver.
        - Modified the I2S binding documentation for clocks and pinmux.

Changes since V3:
        - Replaced samsung with exynos in the macro prefixes and function names
          as this driver supports mainly exynos and s5p family.
        - Added Reviewed-by:Sylwester Nawrocki <s.nawrocki@samsung.com>

Changes since V2:
        - Removed s5pv210 compatible name from driver as it is
          not yet supported which is different from Exynos series
          audio subsystem clock conroller.
        - Removed clkdev lookup support and added alias names in
          the i2s0 controller node.
Changes since V1:
        - Reworked on all review comments by Sylwester Nawrocki
        - Added a header file for all clock indexes as requested by Sylwester
        - Added different compatible names for s5pv210, exynos4 and exynos5
        - Registered the pcm clocks with common clock framework

Padmavathi Venna (5):
  ARM: samsung: use #include for all device trees
  clk: samsung: register audio subsystem clocks using common clock
    framework
  ARM: dts: add Exynos audio subsystem clock controller node
  ARM: dts: add clock provider information for i2s controllers in
    Exynos5250
  ARM: dts: Update Samsung I2S documentation

 .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
 .../devicetree/bindings/sound/samsung-i2s.txt      |   40 ++----
 arch/arm/boot/dts/exynos4.dtsi                     |    2 +-
 arch/arm/boot/dts/exynos4210-origen.dts            |    2 +-
 arch/arm/boot/dts/exynos4210-smdkv310.dts          |    2 +-
 arch/arm/boot/dts/exynos4210-trats.dts             |    2 +-
 arch/arm/boot/dts/exynos4210-universal_c210.dts    |    2 +-
 arch/arm/boot/dts/exynos4210.dtsi                  |    4 +-
 arch/arm/boot/dts/exynos4212.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4412-odroidx.dts           |    2 +-
 arch/arm/boot/dts/exynos4412-origen.dts            |    2 +-
 arch/arm/boot/dts/exynos4412-smdk4412.dts          |    2 +-
 arch/arm/boot/dts/exynos4412.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4x12.dtsi                  |    4 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 +-
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 +-
 arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
 arch/arm/boot/dts/exynos5250.dtsi                  |   20 +++-
 arch/arm/boot/dts/exynos5440-sd5v1.dts             |    2 +-
 arch/arm/boot/dts/exynos5440-ssdk5440.dts          |    2 +-
 arch/arm/boot/dts/exynos5440.dtsi                  |    2 +-
 arch/arm/boot/dts/s3c2416-smdk2416.dts             |    2 +-
 arch/arm/boot/dts/s3c2416.dtsi                     |    4 +-
 arch/arm/boot/dts/s3c24xx.dtsi                     |    2 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
 include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
 27 files changed, 279 insertions(+), 54 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
 create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
 create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h

-- 
1.7.4.4

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 0/5]  clk: Samsung: audss: Register audio subsytem clocks using common clk framework
@ 2013-06-04 12:28 ` Padmavathi Venna
  0 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-arm-kernel

Samsung S5PV210 and Exynos SoC has a separate subsystem for audio. This subsystem
has a internal clock controller which controls i2s0 and pcm0 clocks. This patch
series adds the Samsung audio subsytem clock to the common clock framework and
provides the I2S controllers clock information in the dtsi file.

This patch series is made based on Kukjin Kim for-next branch

Changes since V4:
        - Reworked on the nits given by Doug.
        - Removed mout_audss and mout_i2s from i2s nodes as we are not
          getting these clocks in the i2s driver.
        - Modified the I2S binding documentation for clocks and pinmux.

Changes since V3:
        - Replaced samsung with exynos in the macro prefixes and function names
          as this driver supports mainly exynos and s5p family.
        - Added Reviewed-by:Sylwester Nawrocki <s.nawrocki@samsung.com>

Changes since V2:
        - Removed s5pv210 compatible name from driver as it is
          not yet supported which is different from Exynos series
          audio subsystem clock conroller.
        - Removed clkdev lookup support and added alias names in
          the i2s0 controller node.
Changes since V1:
        - Reworked on all review comments by Sylwester Nawrocki
        - Added a header file for all clock indexes as requested by Sylwester
        - Added different compatible names for s5pv210, exynos4 and exynos5
        - Registered the pcm clocks with common clock framework

Padmavathi Venna (5):
  ARM: samsung: use #include for all device trees
  clk: samsung: register audio subsystem clocks using common clock
    framework
  ARM: dts: add Exynos audio subsystem clock controller node
  ARM: dts: add clock provider information for i2s controllers in
    Exynos5250
  ARM: dts: Update Samsung I2S documentation

 .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
 .../devicetree/bindings/sound/samsung-i2s.txt      |   40 ++----
 arch/arm/boot/dts/exynos4.dtsi                     |    2 +-
 arch/arm/boot/dts/exynos4210-origen.dts            |    2 +-
 arch/arm/boot/dts/exynos4210-smdkv310.dts          |    2 +-
 arch/arm/boot/dts/exynos4210-trats.dts             |    2 +-
 arch/arm/boot/dts/exynos4210-universal_c210.dts    |    2 +-
 arch/arm/boot/dts/exynos4210.dtsi                  |    4 +-
 arch/arm/boot/dts/exynos4212.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4412-odroidx.dts           |    2 +-
 arch/arm/boot/dts/exynos4412-origen.dts            |    2 +-
 arch/arm/boot/dts/exynos4412-smdk4412.dts          |    2 +-
 arch/arm/boot/dts/exynos4412.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4x12.dtsi                  |    4 +-
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 +-
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 +-
 arch/arm/boot/dts/exynos5250-snow.dts              |    4 +-
 arch/arm/boot/dts/exynos5250.dtsi                  |   20 +++-
 arch/arm/boot/dts/exynos5440-sd5v1.dts             |    2 +-
 arch/arm/boot/dts/exynos5440-ssdk5440.dts          |    2 +-
 arch/arm/boot/dts/exynos5440.dtsi                  |    2 +-
 arch/arm/boot/dts/s3c2416-smdk2416.dts             |    2 +-
 arch/arm/boot/dts/s3c2416.dtsi                     |    4 +-
 arch/arm/boot/dts/s3c24xx.dtsi                     |    2 +-
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
 include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
 27 files changed, 279 insertions(+), 54 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
 create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
 create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h

-- 
1.7.4.4

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 1/5] ARM: samsung: use #include for all device trees
  2013-06-04 12:28 ` Padmavathi Venna
@ 2013-06-04 12:28   ` Padmavathi Venna
  -1 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, padma.v, padma.kvr
  Cc: sbkim73, broonie, kgene.kim, mturquette

Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 arch/arm/boot/dts/exynos4.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4210-origen.dts         |    2 +-
 arch/arm/boot/dts/exynos4210-smdkv310.dts       |    2 +-
 arch/arm/boot/dts/exynos4210-trats.dts          |    2 +-
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    2 +-
 arch/arm/boot/dts/exynos4210.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos4212.dtsi               |    2 +-
 arch/arm/boot/dts/exynos4412-odroidx.dts        |    2 +-
 arch/arm/boot/dts/exynos4412-origen.dts         |    2 +-
 arch/arm/boot/dts/exynos4412-smdk4412.dts       |    2 +-
 arch/arm/boot/dts/exynos4412.dtsi               |    2 +-
 arch/arm/boot/dts/exynos4x12.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts        |    2 +-
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    2 +-
 arch/arm/boot/dts/exynos5250-snow.dts           |    4 ++--
 arch/arm/boot/dts/exynos5250.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos5440-sd5v1.dts          |    2 +-
 arch/arm/boot/dts/exynos5440-ssdk5440.dts       |    2 +-
 arch/arm/boot/dts/exynos5440.dtsi               |    2 +-
 arch/arm/boot/dts/s3c2416-smdk2416.dts          |    2 +-
 arch/arm/boot/dts/s3c2416.dtsi                  |    4 ++--
 arch/arm/boot/dts/s3c24xx.dtsi                  |    2 +-
 22 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Universal C210 based on Exynos4210 rev0";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 366795a..75c2756 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4210-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4210-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
 	compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..7bb8d48 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Hardkernel ODROID-X board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 790a999..df097b5 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index c52b01f..1e816fa 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Samsung SMDK evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389..e743e67 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
 	compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7..8896bb5 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4x12-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 02cfc76..8e27120 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "Insignal Arndale evaluation board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e0c792..f2a025e 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index d449feb..fd711e2 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
-/include/ "cros5250-common.dtsi"
+#include "exynos5250.dtsi"
+#include "cros5250-common.dtsi"
 
 / {
 	model = "Google Snow";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9dfc6de..bccda67 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
-/include/ "exynos5250-pinctrl.dtsi"
+#include "skeleton.dtsi"
+#include "exynos5250-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos5250";
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b5..5e84c5f 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
 	model = "SAMSUNG SD5v1 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..2fd6646 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
 	model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..13b40b3 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "samsung,exynos5440";
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index ad1dd09..59594cf 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "s3c2416.dtsi"
+#include "s3c2416.dtsi"
 
 / {
 	model = "SMDK2416";
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 6809324..e6555bd 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "s3c24xx.dtsi"
-/include/ "s3c2416-pinctrl.dtsi"
+#include "s3c24xx.dtsi"
+#include "s3c2416-pinctrl.dtsi"
 
 / {
 	model = "Samsung S3C2416 SoC";
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
index cab46ff..2d1d7dc 100644
--- a/arch/arm/boot/dts/s3c24xx.dtsi
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "samsung,s3c24xx";
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 1/5] ARM: samsung: use #include for all device trees
@ 2013-06-04 12:28   ` Padmavathi Venna
  0 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-arm-kernel

Replace /include/ (dtc) with #include (C pre-processor) for all
Samsung DT files

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 arch/arm/boot/dts/exynos4.dtsi                  |    2 +-
 arch/arm/boot/dts/exynos4210-origen.dts         |    2 +-
 arch/arm/boot/dts/exynos4210-smdkv310.dts       |    2 +-
 arch/arm/boot/dts/exynos4210-trats.dts          |    2 +-
 arch/arm/boot/dts/exynos4210-universal_c210.dts |    2 +-
 arch/arm/boot/dts/exynos4210.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos4212.dtsi               |    2 +-
 arch/arm/boot/dts/exynos4412-odroidx.dts        |    2 +-
 arch/arm/boot/dts/exynos4412-origen.dts         |    2 +-
 arch/arm/boot/dts/exynos4412-smdk4412.dts       |    2 +-
 arch/arm/boot/dts/exynos4412.dtsi               |    2 +-
 arch/arm/boot/dts/exynos4x12.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts        |    2 +-
 arch/arm/boot/dts/exynos5250-smdk5250.dts       |    2 +-
 arch/arm/boot/dts/exynos5250-snow.dts           |    4 ++--
 arch/arm/boot/dts/exynos5250.dtsi               |    4 ++--
 arch/arm/boot/dts/exynos5440-sd5v1.dts          |    2 +-
 arch/arm/boot/dts/exynos5440-ssdk5440.dts       |    2 +-
 arch/arm/boot/dts/exynos5440.dtsi               |    2 +-
 arch/arm/boot/dts/s3c2416-smdk2416.dts          |    2 +-
 arch/arm/boot/dts/s3c2416.dtsi                  |    4 ++--
 arch/arm/boot/dts/s3c24xx.dtsi                  |    2 +-
 22 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bed40ee..3f94fe8 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index bcf8079..5f851d7 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b7..9c01b71 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484..94eebff 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb5..889cdad 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
 	model = "Samsung Universal C210 based on Exynos4210 rev0";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 366795a..75c2756 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4210-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4210-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos4210";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f4..6f34d7f 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
 	compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf..7bb8d48 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Hardkernel ODROID-X board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 790a999..df097b5 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Insignal Origen evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index c52b01f..1e816fa 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
 	model = "Samsung SMDK evaluation board based on Exynos4412";
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389..e743e67 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
 	compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7..8896bb5 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4x12-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
 
 / {
 	aliases {
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 02cfc76..8e27120 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "Insignal Arndale evaluation board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e0c792..f2a025e 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
 	model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index d449feb..fd711e2 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
-/include/ "cros5250-common.dtsi"
+#include "exynos5250.dtsi"
+#include "cros5250-common.dtsi"
 
 / {
 	model = "Google Snow";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 9dfc6de..bccda67 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
-/include/ "exynos5250-pinctrl.dtsi"
+#include "skeleton.dtsi"
+#include "exynos5250-pinctrl.dtsi"
 
 / {
 	compatible = "samsung,exynos5250";
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b5..5e84c5f 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
 	model = "SAMSUNG SD5v1 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042b..2fd6646 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
 	model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c89..13b40b3 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "samsung,exynos5440";
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index ad1dd09..59594cf 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -9,7 +9,7 @@
  */
 
 /dts-v1/;
-/include/ "s3c2416.dtsi"
+#include "s3c2416.dtsi"
 
 / {
 	model = "SMDK2416";
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index 6809324..e6555bd 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "s3c24xx.dtsi"
-/include/ "s3c2416-pinctrl.dtsi"
+#include "s3c24xx.dtsi"
+#include "s3c2416-pinctrl.dtsi"
 
 / {
 	model = "Samsung S3C2416 SoC";
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
index cab46ff..2d1d7dc 100644
--- a/arch/arm/boot/dts/s3c24xx.dtsi
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -8,7 +8,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
 	compatible = "samsung,s3c24xx";
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
  2013-06-04 12:28 ` Padmavathi Venna
@ 2013-06-04 12:28   ` Padmavathi Venna
  -1 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, padma.v, padma.kvr
  Cc: sbkim73, broonie, kgene.kim, mturquette

Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
 include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
 4 files changed, 223 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
 create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
 create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h

diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 0000000..a120180
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
+  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock           ID      SoC (if specific)
+-----------------------------------------------
+
+mout_audss      0
+mout_i2s        1
+dout_srp        2
+dout_aud_bus    3
+dout_i2s        4
+srp_clk         5
+i2s_bus         6
+sclk_i2s        7
+pcm_bus         8
+sclk_pcm        9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller@3810000 {
+	compatible = "samsung,exynos5250-audss-clock";
+	reg = <0x03810000 0x0C>;
+	#clock-cells = <1>;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+
+i2s0: i2s@03830000 {
+	compatible = "samsung,i2s-v5";
+	reg = <0x03830000 0x100>;
+	dmas = <&pdma0 10
+		&pdma0 9
+		&pdma0 8>;
+	dma-names = "tx", "rx", "tx-sec";
+	clocks = <&clock_audss EXYNOS_I2S_BUS>,
+		<&clock_audss EXYNOS_I2S_BUS>,
+		<&clock_audss EXYNOS_SCLK_I2S>,
+		<&clock_audss EXYNOS_MOUT_AUDSS>,
+		<&clock_audss EXYNOS_MOUT_I2S>;
+	clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
+	"mout_audss", "mout_i2s";
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..1876810 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
+obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
new file mode 100644
index 0000000..9b1bbd5
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clk/exynos-audss-clk.h>
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+	{ASS_CLK_SRC,  0},
+	{ASS_CLK_DIV,  0},
+	{ASS_CLK_GATE, 0},
+};
+
+/* list of all parent clock list */
+static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
+static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_audss_clk_suspend(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+		reg_save[i][1] = readl(reg_base + reg_save[i][0]);
+
+	return 0;
+}
+
+static void exynos_audss_clk_resume(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+		writel(reg_save[i][1], reg_base + reg_save[i][0]);
+}
+
+static struct syscore_ops exynos_audss_clk_syscore_ops = {
+	.suspend	= exynos_audss_clk_suspend,
+	.resume		= exynos_audss_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* register exynos_audss clocks */
+void __init exynos_audss_clk_init(struct device_node *np)
+{
+	reg_base = of_iomap(np, 0);
+	if (!reg_base) {
+		pr_err("%s: failed to map audss registers\n", __func__);
+		return;
+	}
+
+	clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+				GFP_KERNEL);
+	if (!clk_table) {
+		pr_err("%s: could not allocate clk lookup table\n", __func__);
+		return;
+	}
+
+	clk_data.clks = clk_table;
+	clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+				mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
+				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+
+	clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
+				mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
+				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
+
+	clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
+				"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
+				0, &lock);
+
+	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
+				"dout_aud_bus", "dout_srp", 0,
+				reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
+
+	clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
+				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
+				&lock);
+
+	clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
+				"dout_srp", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 0, 0, &lock);
+
+	clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
+				"dout_aud_bus", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 2, 0, &lock);
+
+	clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
+				"dout_i2s", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 3, 0, &lock);
+
+	clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
+				 "sclk_pcm", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 4, 0, &lock);
+
+	clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
+				"div_pcm0", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 5, 0, &lock);
+
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&exynos_audss_clk_syscore_ops);
+#endif
+
+	pr_info("Exynos: Audss: clock setup completed\n");
+}
+CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
+		exynos_audss_clk_init);
+CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
+		exynos_audss_clk_init);
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
new file mode 100644
index 0000000..8279f42
--- /dev/null
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and exynos audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+
+#define EXYNOS_MOUT_AUDSS	0
+#define EXYNOS_MOUT_I2S	1
+#define EXYNOS_DOUT_SRP	2
+#define EXYNOS_DOUT_AUD_BUS	3
+#define EXYNOS_DOUT_I2S	4
+#define EXYNOS_SRP_CLK		5
+#define EXYNOS_I2S_BUS		6
+#define EXYNOS_SCLK_I2S	7
+#define EXYNOS_PCM_BUS		8
+#define EXYNOS_SCLK_PCM	9
+
+#define EXYNOS_AUDSS_MAX_CLKS	10
+
+#endif
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
@ 2013-06-04 12:28   ` Padmavathi Venna
  0 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-arm-kernel

Audio subsystem is introduced in s5pv210 and exynos platforms.
This has seperate clock controller which can control i2s0 and
pcm0 clocks. This patch registers the audio subsystem clocks
with the common clock framework on Exynos family.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
 drivers/clk/samsung/Makefile                       |    1 +
 drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
 include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
 4 files changed, 223 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
 create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
 create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h

diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
new file mode 100644
index 0000000..a120180
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -0,0 +1,64 @@
+* Samsung Audio Subsystem Clock Controller
+
+The Samsung Audio Subsystem clock controller generates and supplies clocks
+to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
+binding described here is applicable to all SoC's in Exynos family.
+
+Required Properties:
+
+- compatible: should be one of the following:
+  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
+  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
+
+- reg: physical base address and length of the controller's register set.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume. Some of the clocks are available only on a particular
+Exynos4 SoC and this is specified where applicable.
+
+Provided clocks:
+
+Clock           ID      SoC (if specific)
+-----------------------------------------------
+
+mout_audss      0
+mout_i2s        1
+dout_srp        2
+dout_aud_bus    3
+dout_i2s        4
+srp_clk         5
+i2s_bus         6
+sclk_i2s        7
+pcm_bus         8
+sclk_pcm        9
+
+Example 1: An example of a clock controller node is listed below.
+
+clock_audss: audss-clock-controller at 3810000 {
+	compatible = "samsung,exynos5250-audss-clock";
+	reg = <0x03810000 0x0C>;
+	#clock-cells = <1>;
+};
+
+Example 2: I2S controller node that consumes the clock generated by the clock
+           controller. Refer to the standard clock bindings for information
+           about 'clocks' and 'clock-names' property.
+
+i2s0: i2s at 03830000 {
+	compatible = "samsung,i2s-v5";
+	reg = <0x03830000 0x100>;
+	dmas = <&pdma0 10
+		&pdma0 9
+		&pdma0 8>;
+	dma-names = "tx", "rx", "tx-sec";
+	clocks = <&clock_audss EXYNOS_I2S_BUS>,
+		<&clock_audss EXYNOS_I2S_BUS>,
+		<&clock_audss EXYNOS_SCLK_I2S>,
+		<&clock_audss EXYNOS_MOUT_AUDSS>,
+		<&clock_audss EXYNOS_MOUT_I2S>;
+	clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
+	"mout_audss", "mout_i2s";
+};
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index b7c232e..1876810 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)	+= clk.o clk-pll.o
 obj-$(CONFIG_ARCH_EXYNOS4)	+= clk-exynos4.o
 obj-$(CONFIG_SOC_EXYNOS5250)	+= clk-exynos5250.o
 obj-$(CONFIG_SOC_EXYNOS5440)	+= clk-exynos5440.o
+obj-$(CONFIG_ARCH_EXYNOS)	+= clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
new file mode 100644
index 0000000..9b1bbd5
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Padmavathi Venna <padma.v@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Audio Subsystem Clock Controller.
+*/
+
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#include <dt-bindings/clk/exynos-audss-clk.h>
+
+static DEFINE_SPINLOCK(lock);
+static struct clk **clk_table;
+static void __iomem *reg_base;
+static struct clk_onecell_data clk_data;
+
+#define ASS_CLK_SRC 0x0
+#define ASS_CLK_DIV 0x4
+#define ASS_CLK_GATE 0x8
+
+static unsigned long reg_save[][2] = {
+	{ASS_CLK_SRC,  0},
+	{ASS_CLK_DIV,  0},
+	{ASS_CLK_GATE, 0},
+};
+
+/* list of all parent clock list */
+static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
+static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos_audss_clk_suspend(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+		reg_save[i][1] = readl(reg_base + reg_save[i][0]);
+
+	return 0;
+}
+
+static void exynos_audss_clk_resume(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(reg_save); i++)
+		writel(reg_save[i][1], reg_base + reg_save[i][0]);
+}
+
+static struct syscore_ops exynos_audss_clk_syscore_ops = {
+	.suspend	= exynos_audss_clk_suspend,
+	.resume		= exynos_audss_clk_resume,
+};
+#endif /* CONFIG_PM_SLEEP */
+
+/* register exynos_audss clocks */
+void __init exynos_audss_clk_init(struct device_node *np)
+{
+	reg_base = of_iomap(np, 0);
+	if (!reg_base) {
+		pr_err("%s: failed to map audss registers\n", __func__);
+		return;
+	}
+
+	clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
+				GFP_KERNEL);
+	if (!clk_table) {
+		pr_err("%s: could not allocate clk lookup table\n", __func__);
+		return;
+	}
+
+	clk_data.clks = clk_table;
+	clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
+	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
+				mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
+				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
+
+	clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
+				mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
+				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
+
+	clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
+				"mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
+				0, &lock);
+
+	clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
+				"dout_aud_bus", "dout_srp", 0,
+				reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
+
+	clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
+				"mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
+				&lock);
+
+	clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
+				"dout_srp", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 0, 0, &lock);
+
+	clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
+				"dout_aud_bus", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 2, 0, &lock);
+
+	clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
+				"dout_i2s", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 3, 0, &lock);
+
+	clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
+				 "sclk_pcm", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 4, 0, &lock);
+
+	clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
+				"div_pcm0", CLK_SET_RATE_PARENT,
+				reg_base + ASS_CLK_GATE, 5, 0, &lock);
+
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&exynos_audss_clk_syscore_ops);
+#endif
+
+	pr_info("Exynos: Audss: clock setup completed\n");
+}
+CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
+		exynos_audss_clk_init);
+CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
+		exynos_audss_clk_init);
diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
new file mode 100644
index 0000000..8279f42
--- /dev/null
+++ b/include/dt-bindings/clk/exynos-audss-clk.h
@@ -0,0 +1,25 @@
+/*
+ * This header provides constants for Samsung audio subsystem
+ * clock controller.
+ *
+ * The constants defined in this header are being used in dts
+ * and exynos audss driver.
+ */
+
+#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
+
+#define EXYNOS_MOUT_AUDSS	0
+#define EXYNOS_MOUT_I2S	1
+#define EXYNOS_DOUT_SRP	2
+#define EXYNOS_DOUT_AUD_BUS	3
+#define EXYNOS_DOUT_I2S	4
+#define EXYNOS_SRP_CLK		5
+#define EXYNOS_I2S_BUS		6
+#define EXYNOS_SCLK_I2S	7
+#define EXYNOS_PCM_BUS		8
+#define EXYNOS_SCLK_PCM	9
+
+#define EXYNOS_AUDSS_MAX_CLKS	10
+
+#endif
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 3/5] ARM: dts: add Exynos audio subsystem clock controller node
  2013-06-04 12:28 ` Padmavathi Venna
@ 2013-06-04 12:28   ` Padmavathi Venna
  -1 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, padma.v, padma.kvr
  Cc: sbkim73, broonie, kgene.kim, mturquette

Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index bccda67..388983e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
 		#clock-cells = <1>;
 	};
 
+	clock_audss: audss-clock-controller@3810000 {
+		compatible = "samsung,exynos5250-audss-clock";
+		reg = <0x03810000 0x0C>;
+		#clock-cells = <1>;
+	};
+
 	gic:interrupt-controller@10481000 {
 		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 3/5] ARM: dts: add Exynos audio subsystem clock controller node
@ 2013-06-04 12:28   ` Padmavathi Venna
  0 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-arm-kernel

Audio subsystem introduced in s5pv210 and exynos platforms
which has a internal clock controller. This patch adds a node
for the same on exynos5250.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index bccda67..388983e 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,12 @@
 		#clock-cells = <1>;
 	};
 
+	clock_audss: audss-clock-controller at 3810000 {
+		compatible = "samsung,exynos5250-audss-clock";
+		reg = <0x03810000 0x0C>;
+		#clock-cells = <1>;
+	};
+
 	gic:interrupt-controller at 10481000 {
 		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 		#interrupt-cells = <3>;
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
  2013-06-04 12:28 ` Padmavathi Venna
@ 2013-06-04 12:28   ` Padmavathi Venna
  -1 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, padma.v, padma.kvr
  Cc: sbkim73, broonie, kgene.kim, mturquette

Add clock lookup information for i2s controllers on exynos5250 SoC.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 388983e..1e62ca9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
 #include "skeleton.dtsi"
 #include "exynos5250-pinctrl.dtsi"
 
+#include <dt-bindings/clk/exynos-audss-clk.h>
+
 / {
 	compatible = "samsung,exynos5250";
 	interrupt-parent = <&gic>;
@@ -457,6 +459,10 @@
 			&pdma0 9
 			&pdma0 8>;
 		dma-names = "tx", "rx", "tx-sec";
+		clocks = <&clock_audss EXYNOS_I2S_BUS>,
+			<&clock_audss EXYNOS_I2S_BUS>,
+			<&clock_audss EXYNOS_SCLK_I2S>;
+		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 		samsung,supports-6ch;
 		samsung,supports-rstclr;
 		samsung,supports-secdai;
@@ -471,6 +477,8 @@
 		dmas = <&pdma1 12
 			&pdma1 11>;
 		dma-names = "tx", "rx";
+		clocks = <&clock 307>;
+		clock-names = "iis";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s1_bus>;
 	};
@@ -481,6 +489,8 @@
 		dmas = <&pdma0 12
 			&pdma0 11>;
 		dma-names = "tx", "rx";
+		clocks = <&clock 308>;
+		clock-names = "iis";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s2_bus>;
 	};
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
@ 2013-06-04 12:28   ` Padmavathi Venna
  0 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-arm-kernel

Add clock lookup information for i2s controllers on exynos5250 SoC.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
 arch/arm/boot/dts/exynos5250.dtsi |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 388983e..1e62ca9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -20,6 +20,8 @@
 #include "skeleton.dtsi"
 #include "exynos5250-pinctrl.dtsi"
 
+#include <dt-bindings/clk/exynos-audss-clk.h>
+
 / {
 	compatible = "samsung,exynos5250";
 	interrupt-parent = <&gic>;
@@ -457,6 +459,10 @@
 			&pdma0 9
 			&pdma0 8>;
 		dma-names = "tx", "rx", "tx-sec";
+		clocks = <&clock_audss EXYNOS_I2S_BUS>,
+			<&clock_audss EXYNOS_I2S_BUS>,
+			<&clock_audss EXYNOS_SCLK_I2S>;
+		clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 		samsung,supports-6ch;
 		samsung,supports-rstclr;
 		samsung,supports-secdai;
@@ -471,6 +477,8 @@
 		dmas = <&pdma1 12
 			&pdma1 11>;
 		dma-names = "tx", "rx";
+		clocks = <&clock 307>;
+		clock-names = "iis";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s1_bus>;
 	};
@@ -481,6 +489,8 @@
 		dmas = <&pdma0 12
 			&pdma0 11>;
 		dma-names = "tx", "rx";
+		clocks = <&clock 308>;
+		clock-names = "iis";
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s2_bus>;
 	};
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 5/5] ARM: dts: Update Samsung I2S documentation
  2013-06-04 12:28 ` Padmavathi Venna
@ 2013-06-04 12:28   ` Padmavathi Venna
  -1 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, padma.v, padma.kvr
  Cc: sbkim73, broonie, kgene.kim, mturquette

This patch updates the samsung i2s documentation for pinmux and
clock entries.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
 .../devicetree/bindings/sound/samsung-i2s.txt      |   40 ++++++-------------
 1 files changed, 13 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 3070046..6f9d29f 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -8,6 +8,10 @@ Required SoC Specific Properties:
 - dmas: list of DMA controller phandle and DMA request line ordered pairs.
 - dma-names: identifier string for each DMA request line in the dmas property.
   These strings correspond 1:1 with the ordered pairs in dmas.
+- clocks: from common clock binding. Handle to iis clock and RCLK src clk.
+- clock-names: from common clock binding: Should be "iis","i2s_opclk0" and
+  "i2s_opclk1". "iis" is the i2s bus clock and i2s_opclk selects the src of
+  RCLK which is a mux inside i2s controller.
 
 Optional SoC Specific Properties:
 
@@ -20,44 +24,26 @@ Optional SoC Specific Properties:
   then this flag is enabled.
 - samsung,idma-addr: Internal DMA register base address of the audio
   sub system(used in secondary sound source).
-
-Required Board Specific Properties:
-
-- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
-  interface lines. The format of the gpio specifier depends on the gpio
-  controller.
-  The syntax of samsung gpio specifier is
-	<[phandle of the gpio controller node]
-	 [pin number within the gpio controller]
-	 [mux function]
-	 [flags and pull up/down]
-	 [drive strength]>
+- pinctrl-0: Should specify pin control groups used for this controller.
+- pinctrl-names: Should contain only one value - "default".
 
 Example:
 
-- SoC Specific Portion:
-
-i2s@03830000 {
+i2s0: i2s@03830000 {
 	compatible = "samsung,i2s-v5";
 	reg = <0x03830000 0x100>;
 	dmas = <&pdma0 10
 		&pdma0 9
 		&pdma0 8>;
 	dma-names = "tx", "rx", "tx-sec";
+	clocks = <&clock_audss EXYNOS_I2S_BUS>,
+		<&clock_audss EXYNOS_I2S_BUS>,
+		<&clock_audss EXYNOS_SCLK_I2S>;
+	clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 	samsung,supports-6ch;
 	samsung,supports-rstclr;
 	samsung,supports-secdai;
 	samsung,idma-addr = <0x03000000>;
-};
-
-- Board Specific Portion:
-
-i2s@03830000 {
-	gpios = <&gpz 0 2 0 0>, /* I2S_0_SCLK */
-		<&gpz 1 2 0 0>, /* I2S_0_CDCLK */
-		<&gpz 2 2 0 0>, /* I2S_0_LRCK */
-		<&gpz 3 2 0 0>, /* I2S_0_SDI */
-		<&gpz 4 2 0 0>, /* I2S_0_SDO[1] */
-		<&gpz 5 2 0 0>, /* I2S_0_SDO[2] */
-		<&gpz 6 2 0 0>; /* I2S_0_SDO[3] */
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_bus>;
 };
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* [PATCH V5 5/5] ARM: dts: Update Samsung I2S documentation
@ 2013-06-04 12:28   ` Padmavathi Venna
  0 siblings, 0 replies; 28+ messages in thread
From: Padmavathi Venna @ 2013-06-04 12:28 UTC (permalink / raw)
  To: linux-arm-kernel

This patch updates the samsung i2s documentation for pinmux and
clock entries.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
 .../devicetree/bindings/sound/samsung-i2s.txt      |   40 ++++++-------------
 1 files changed, 13 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
index 3070046..6f9d29f 100644
--- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
+++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
@@ -8,6 +8,10 @@ Required SoC Specific Properties:
 - dmas: list of DMA controller phandle and DMA request line ordered pairs.
 - dma-names: identifier string for each DMA request line in the dmas property.
   These strings correspond 1:1 with the ordered pairs in dmas.
+- clocks: from common clock binding. Handle to iis clock and RCLK src clk.
+- clock-names: from common clock binding: Should be "iis","i2s_opclk0" and
+  "i2s_opclk1". "iis" is the i2s bus clock and i2s_opclk selects the src of
+  RCLK which is a mux inside i2s controller.
 
 Optional SoC Specific Properties:
 
@@ -20,44 +24,26 @@ Optional SoC Specific Properties:
   then this flag is enabled.
 - samsung,idma-addr: Internal DMA register base address of the audio
   sub system(used in secondary sound source).
-
-Required Board Specific Properties:
-
-- gpios: The gpio specifier for data out,data in, LRCLK, CDCLK and SCLK
-  interface lines. The format of the gpio specifier depends on the gpio
-  controller.
-  The syntax of samsung gpio specifier is
-	<[phandle of the gpio controller node]
-	 [pin number within the gpio controller]
-	 [mux function]
-	 [flags and pull up/down]
-	 [drive strength]>
+- pinctrl-0: Should specify pin control groups used for this controller.
+- pinctrl-names: Should contain only one value - "default".
 
 Example:
 
-- SoC Specific Portion:
-
-i2s at 03830000 {
+i2s0: i2s at 03830000 {
 	compatible = "samsung,i2s-v5";
 	reg = <0x03830000 0x100>;
 	dmas = <&pdma0 10
 		&pdma0 9
 		&pdma0 8>;
 	dma-names = "tx", "rx", "tx-sec";
+	clocks = <&clock_audss EXYNOS_I2S_BUS>,
+		<&clock_audss EXYNOS_I2S_BUS>,
+		<&clock_audss EXYNOS_SCLK_I2S>;
+	clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 	samsung,supports-6ch;
 	samsung,supports-rstclr;
 	samsung,supports-secdai;
 	samsung,idma-addr = <0x03000000>;
-};
-
-- Board Specific Portion:
-
-i2s at 03830000 {
-	gpios = <&gpz 0 2 0 0>, /* I2S_0_SCLK */
-		<&gpz 1 2 0 0>, /* I2S_0_CDCLK */
-		<&gpz 2 2 0 0>, /* I2S_0_LRCK */
-		<&gpz 3 2 0 0>, /* I2S_0_SDI */
-		<&gpz 4 2 0 0>, /* I2S_0_SDO[1] */
-		<&gpz 5 2 0 0>, /* I2S_0_SDO[2] */
-		<&gpz 6 2 0 0>; /* I2S_0_SDO[3] */
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2s0_bus>;
 };
-- 
1.7.4.4

^ permalink raw reply related	[flat|nested] 28+ messages in thread
* Re: [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
  2013-06-04 12:28   ` Padmavathi Venna
@ 2013-06-04 17:09     ` Doug Anderson
  -1 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:09 UTC (permalink / raw)
  To: Padmavathi Venna
  Cc: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, padma.kvr, sbkim73, Kukjin Kim, broonie,
	Mike Turquette

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> Audio subsystem is introduced in s5pv210 and exynos platforms.
> This has seperate clock controller which can control i2s0 and
> pcm0 clocks. This patch registers the audio subsystem clocks
> with the common clock framework on Exynos family.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
>  drivers/clk/samsung/Makefile                       |    1 +
>  drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
>  include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
>  4 files changed, 223 insertions(+), 0 deletions(-)

Thanks for fixing up my nits.  This looks good to me.

Reviewed-by: Doug Anderson <dianders@chromium.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
@ 2013-06-04 17:09     ` Doug Anderson
  0 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:09 UTC (permalink / raw)
  To: linux-arm-kernel

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> Audio subsystem is introduced in s5pv210 and exynos platforms.
> This has seperate clock controller which can control i2s0 and
> pcm0 clocks. This patch registers the audio subsystem clocks
> with the common clock framework on Exynos family.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
>  drivers/clk/samsung/Makefile                       |    1 +
>  drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
>  include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
>  4 files changed, 223 insertions(+), 0 deletions(-)

Thanks for fixing up my nits.  This looks good to me.

Reviewed-by: Doug Anderson <dianders@chromium.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread
* Re: [PATCH V5 3/5] ARM: dts: add Exynos audio subsystem clock controller node
  2013-06-04 12:28   ` Padmavathi Venna
@ 2013-06-04 17:10     ` Doug Anderson
  -1 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:10 UTC (permalink / raw)
  To: Padmavathi Venna
  Cc: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, Padma Venkat, sbkim73, Kukjin Kim, broonie,
	Mike Turquette

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> Audio subsystem introduced in s5pv210 and exynos platforms
> which has a internal clock controller. This patch adds a node
> for the same on exynos5250.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)

Responded on patch set 4 already, but this is the same.  I'm happy with this.

Reviewed-by: Doug Anderson <dianders@chromium.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 3/5] ARM: dts: add Exynos audio subsystem clock controller node
@ 2013-06-04 17:10     ` Doug Anderson
  0 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:10 UTC (permalink / raw)
  To: linux-arm-kernel

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> Audio subsystem introduced in s5pv210 and exynos platforms
> which has a internal clock controller. This patch adds a node
> for the same on exynos5250.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)

Responded on patch set 4 already, but this is the same.  I'm happy with this.

Reviewed-by: Doug Anderson <dianders@chromium.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread
* Re: [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
  2013-06-04 12:28   ` Padmavathi Venna
@ 2013-06-04 17:12     ` Doug Anderson
  -1 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:12 UTC (permalink / raw)
  To: Padmavathi Venna
  Cc: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, Padma Venkat, sbkim73, Kukjin Kim, broonie,
	Mike Turquette

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> Add clock lookup information for i2s controllers on exynos5250 SoC.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |   10 ++++++++++

Would still like to see a separate patch documenting these clocks in
"Documentation/devicetree/bindings/sound/samsung-i2s.txt".  ...but
what's here looks good, thanks!

Reviewed-by: Doug Anderson <dianders@chromium.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
@ 2013-06-04 17:12     ` Doug Anderson
  0 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:12 UTC (permalink / raw)
  To: linux-arm-kernel

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> Add clock lookup information for i2s controllers on exynos5250 SoC.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
>  arch/arm/boot/dts/exynos5250.dtsi |   10 ++++++++++

Would still like to see a separate patch documenting these clocks in
"Documentation/devicetree/bindings/sound/samsung-i2s.txt".  ...but
what's here looks good, thanks!

Reviewed-by: Doug Anderson <dianders@chromium.org>

^ permalink raw reply	[flat|nested] 28+ messages in thread
* Re: [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
  2013-06-04 12:28   ` Padmavathi Venna
@ 2013-06-04 17:19     ` Doug Anderson
  -1 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:19 UTC (permalink / raw)
  To: Padmavathi Venna
  Cc: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, Padma Venkat, sbkim73, Kukjin Kim, broonie,
	Mike Turquette

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> @@ -471,6 +477,8 @@
>                 dmas = <&pdma1 12
>                         &pdma1 11>;
>                 dma-names = "tx", "rx";
> +               clocks = <&clock 307>;
> +               clock-names = "iis";

...actually, glancing at the driver I'm a little surprised that you
don't need to list "i2s_opclk0".  Did you test i2s1?

>                 pinctrl-names = "default";
>                 pinctrl-0 = <&i2s1_bus>;
>         };
> @@ -481,6 +489,8 @@
>                 dmas = <&pdma0 12
>                         &pdma0 11>;
>                 dma-names = "tx", "rx";
> +               clocks = <&clock 308>;
> +               clock-names = "iis";

...and here.


-Doug

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
@ 2013-06-04 17:19     ` Doug Anderson
  0 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:19 UTC (permalink / raw)
  To: linux-arm-kernel

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> @@ -471,6 +477,8 @@
>                 dmas = <&pdma1 12
>                         &pdma1 11>;
>                 dma-names = "tx", "rx";
> +               clocks = <&clock 307>;
> +               clock-names = "iis";

...actually, glancing at the driver I'm a little surprised that you
don't need to list "i2s_opclk0".  Did you test i2s1?

>                 pinctrl-names = "default";
>                 pinctrl-0 = <&i2s1_bus>;
>         };
> @@ -481,6 +489,8 @@
>                 dmas = <&pdma0 12
>                         &pdma0 11>;
>                 dma-names = "tx", "rx";
> +               clocks = <&clock 308>;
> +               clock-names = "iis";

...and here.


-Doug

^ permalink raw reply	[flat|nested] 28+ messages in thread
* Re: [PATCH V5 5/5] ARM: dts: Update Samsung I2S documentation
  2013-06-04 12:28   ` Padmavathi Venna
@ 2013-06-04 17:25     ` Doug Anderson
  -1 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:25 UTC (permalink / raw)
  To: Padmavathi Venna
  Cc: linux-samsung-soc, devicetree-discuss, linux-arm-kernel,
	alsa-devel, Padma Venkat, sbkim73, Kukjin Kim, broonie,
	Mike Turquette

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> This patch updates the samsung i2s documentation for pinmux and
> clock entries.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> ---
>  .../devicetree/bindings/sound/samsung-i2s.txt      |   40 ++++++-------------
>  1 files changed, 13 insertions(+), 27 deletions(-)

Whoops, just asked for this and now saw it.  Thanks for posting!

One note: don't use the "dts" tag for this commit.  That should be
only for things that are touching dts / dtsi files, not for updating
docs.


> diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
> index 3070046..6f9d29f 100644
> --- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
> @@ -8,6 +8,10 @@ Required SoC Specific Properties:
>  - dmas: list of DMA controller phandle and DMA request line ordered pairs.
>  - dma-names: identifier string for each DMA request line in the dmas property.
>    These strings correspond 1:1 with the ordered pairs in dmas.
> +- clocks: from common clock binding. Handle to iis clock and RCLK src clk.
> +- clock-names: from common clock binding: Should be "iis","i2s_opclk0" and
> +  "i2s_opclk1". "iis" is the i2s bus clock and i2s_opclk selects the src of
> +  RCLK which is a mux inside i2s controller.

>From your other patch apparently opclk0 and/or opclk1 are not
required.  Two of your i2c nodes don't have either, though I suspect
that you at least need opclk0.  See my comments there.

-Doug

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 5/5] ARM: dts: Update Samsung I2S documentation
@ 2013-06-04 17:25     ` Doug Anderson
  0 siblings, 0 replies; 28+ messages in thread
From: Doug Anderson @ 2013-06-04 17:25 UTC (permalink / raw)
  To: linux-arm-kernel

Padmavathi,

On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
> This patch updates the samsung i2s documentation for pinmux and
> clock entries.
>
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> ---
>  .../devicetree/bindings/sound/samsung-i2s.txt      |   40 ++++++-------------
>  1 files changed, 13 insertions(+), 27 deletions(-)

Whoops, just asked for this and now saw it.  Thanks for posting!

One note: don't use the "dts" tag for this commit.  That should be
only for things that are touching dts / dtsi files, not for updating
docs.


> diff --git a/Documentation/devicetree/bindings/sound/samsung-i2s.txt b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
> index 3070046..6f9d29f 100644
> --- a/Documentation/devicetree/bindings/sound/samsung-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/samsung-i2s.txt
> @@ -8,6 +8,10 @@ Required SoC Specific Properties:
>  - dmas: list of DMA controller phandle and DMA request line ordered pairs.
>  - dma-names: identifier string for each DMA request line in the dmas property.
>    These strings correspond 1:1 with the ordered pairs in dmas.
> +- clocks: from common clock binding. Handle to iis clock and RCLK src clk.
> +- clock-names: from common clock binding: Should be "iis","i2s_opclk0" and
> +  "i2s_opclk1". "iis" is the i2s bus clock and i2s_opclk selects the src of
> +  RCLK which is a mux inside i2s controller.

>From your other patch apparently opclk0 and/or opclk1 are not
required.  Two of your i2c nodes don't have either, though I suspect
that you at least need opclk0.  See my comments there.

-Doug

^ permalink raw reply	[flat|nested] 28+ messages in thread
* Re: [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
  2013-06-04 17:19     ` Doug Anderson
@ 2013-06-06  3:54       ` Padma Venkat
  -1 siblings, 0 replies; 28+ messages in thread
From: Padma Venkat @ 2013-06-06  3:54 UTC (permalink / raw)
  To: Doug Anderson
  Cc: Padmavathi Venna, linux-samsung-soc, devicetree-discuss,
	linux-arm-kernel, alsa-devel, sbkim73, Kukjin Kim, broonie,
	Mike Turquette

Hi Doug,

On Tue, Jun 4, 2013 at 10:49 PM, Doug Anderson <dianders@chromium.org> wrote:
> Padmavathi,
>
> On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
>> @@ -471,6 +477,8 @@
>>                 dmas = <&pdma1 12
>>                         &pdma1 11>;
>>                 dma-names = "tx", "rx";
>> +               clocks = <&clock 307>;
>> +               clock-names = "iis";
>
> ...actually, glancing at the driver I'm a little surprised that you
> don't need to list "i2s_opclk0".  Did you test i2s1?

I didn't test i2s1 but i2s_opclk0 is also required. I will resubmit the patch.

>
>>                 pinctrl-names = "default";
>>                 pinctrl-0 = <&i2s1_bus>;
>>         };
>> @@ -481,6 +489,8 @@
>>                 dmas = <&pdma0 12
>>                         &pdma0 11>;
>>                 dma-names = "tx", "rx";
>> +               clocks = <&clock 308>;
>> +               clock-names = "iis";
>
> ...and here.
>
>
> -Doug

Thanks
Padma

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250
@ 2013-06-06  3:54       ` Padma Venkat
  0 siblings, 0 replies; 28+ messages in thread
From: Padma Venkat @ 2013-06-06  3:54 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Doug,

On Tue, Jun 4, 2013 at 10:49 PM, Doug Anderson <dianders@chromium.org> wrote:
> Padmavathi,
>
> On Tue, Jun 4, 2013 at 5:28 AM, Padmavathi Venna <padma.v@samsung.com> wrote:
>> @@ -471,6 +477,8 @@
>>                 dmas = <&pdma1 12
>>                         &pdma1 11>;
>>                 dma-names = "tx", "rx";
>> +               clocks = <&clock 307>;
>> +               clock-names = "iis";
>
> ...actually, glancing at the driver I'm a little surprised that you
> don't need to list "i2s_opclk0".  Did you test i2s1?

I didn't test i2s1 but i2s_opclk0 is also required. I will resubmit the patch.

>
>>                 pinctrl-names = "default";
>>                 pinctrl-0 = <&i2s1_bus>;
>>         };
>> @@ -481,6 +489,8 @@
>>                 dmas = <&pdma0 12
>>                         &pdma0 11>;
>>                 dma-names = "tx", "rx";
>> +               clocks = <&clock 308>;
>> +               clock-names = "iis";
>
> ...and here.
>
>
> -Doug

Thanks
Padma

^ permalink raw reply	[flat|nested] 28+ messages in thread
* Re: [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
  2013-06-04 12:28   ` Padmavathi Venna
@ 2013-06-11 22:13     ` Mike Turquette
  -1 siblings, 0 replies; 28+ messages in thread
From: Mike Turquette @ 2013-06-11 22:13 UTC (permalink / raw)
  To: Padmavathi Venna, linux-samsung-soc, devicetree-discuss,
	linux-arm-kernel, alsa-devel
  Cc: sbkim73, broonie, kgene.kim

Quoting Padmavathi Venna (2013-06-04 05:28:07)
> Audio subsystem is introduced in s5pv210 and exynos platforms.
> This has seperate clock controller which can control i2s0 and
> pcm0 clocks. This patch registers the audio subsystem clocks
> with the common clock framework on Exynos family.
> 
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

This looks good to me.  You have my Ack, or I can take this patch
through clk-next.  Let me know what works for you.

Regards,
Mike

> ---
>  .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
>  drivers/clk/samsung/Makefile                       |    1 +
>  drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
>  include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
>  4 files changed, 223 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>  create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
>  create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> new file mode 100644
> index 0000000..a120180
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> @@ -0,0 +1,64 @@
> +* Samsung Audio Subsystem Clock Controller
> +
> +The Samsung Audio Subsystem clock controller generates and supplies clocks
> +to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
> +binding described here is applicable to all SoC's in Exynos family.
> +
> +Required Properties:
> +
> +- compatible: should be one of the following:
> +  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
> +  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
> +
> +- reg: physical base address and length of the controller's register set.
> +
> +- #clock-cells: should be 1.
> +
> +The following is the list of clocks generated by the controller. Each clock is
> +assigned an identifier and client nodes use this identifier to specify the
> +clock which they consume. Some of the clocks are available only on a particular
> +Exynos4 SoC and this is specified where applicable.
> +
> +Provided clocks:
> +
> +Clock           ID      SoC (if specific)
> +-----------------------------------------------
> +
> +mout_audss      0
> +mout_i2s        1
> +dout_srp        2
> +dout_aud_bus    3
> +dout_i2s        4
> +srp_clk         5
> +i2s_bus         6
> +sclk_i2s        7
> +pcm_bus         8
> +sclk_pcm        9
> +
> +Example 1: An example of a clock controller node is listed below.
> +
> +clock_audss: audss-clock-controller@3810000 {
> +       compatible = "samsung,exynos5250-audss-clock";
> +       reg = <0x03810000 0x0C>;
> +       #clock-cells = <1>;
> +};
> +
> +Example 2: I2S controller node that consumes the clock generated by the clock
> +           controller. Refer to the standard clock bindings for information
> +           about 'clocks' and 'clock-names' property.
> +
> +i2s0: i2s@03830000 {
> +       compatible = "samsung,i2s-v5";
> +       reg = <0x03830000 0x100>;
> +       dmas = <&pdma0 10
> +               &pdma0 9
> +               &pdma0 8>;
> +       dma-names = "tx", "rx", "tx-sec";
> +       clocks = <&clock_audss EXYNOS_I2S_BUS>,
> +               <&clock_audss EXYNOS_I2S_BUS>,
> +               <&clock_audss EXYNOS_SCLK_I2S>,
> +               <&clock_audss EXYNOS_MOUT_AUDSS>,
> +               <&clock_audss EXYNOS_MOUT_I2S>;
> +       clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
> +       "mout_audss", "mout_i2s";
> +};
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index b7c232e..1876810 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)        += clk.o clk-pll.o
>  obj-$(CONFIG_ARCH_EXYNOS4)     += clk-exynos4.o
>  obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
>  obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
> +obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-audss.o
> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
> new file mode 100644
> index 0000000..9b1bbd5
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos-audss.c
> @@ -0,0 +1,133 @@
> +/*
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Padmavathi Venna <padma.v@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Common Clock Framework support for Audio Subsystem Clock Controller.
> +*/
> +
> +#include <linux/clkdev.h>
> +#include <linux/io.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/syscore_ops.h>
> +
> +#include <dt-bindings/clk/exynos-audss-clk.h>
> +
> +static DEFINE_SPINLOCK(lock);
> +static struct clk **clk_table;
> +static void __iomem *reg_base;
> +static struct clk_onecell_data clk_data;
> +
> +#define ASS_CLK_SRC 0x0
> +#define ASS_CLK_DIV 0x4
> +#define ASS_CLK_GATE 0x8
> +
> +static unsigned long reg_save[][2] = {
> +       {ASS_CLK_SRC,  0},
> +       {ASS_CLK_DIV,  0},
> +       {ASS_CLK_GATE, 0},
> +};
> +
> +/* list of all parent clock list */
> +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
> +static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int exynos_audss_clk_suspend(void)
> +{
> +       int i;
> +
> +       for (i = 0; i < ARRAY_SIZE(reg_save); i++)
> +               reg_save[i][1] = readl(reg_base + reg_save[i][0]);
> +
> +       return 0;
> +}
> +
> +static void exynos_audss_clk_resume(void)
> +{
> +       int i;
> +
> +       for (i = 0; i < ARRAY_SIZE(reg_save); i++)
> +               writel(reg_save[i][1], reg_base + reg_save[i][0]);
> +}
> +
> +static struct syscore_ops exynos_audss_clk_syscore_ops = {
> +       .suspend        = exynos_audss_clk_suspend,
> +       .resume         = exynos_audss_clk_resume,
> +};
> +#endif /* CONFIG_PM_SLEEP */
> +
> +/* register exynos_audss clocks */
> +void __init exynos_audss_clk_init(struct device_node *np)
> +{
> +       reg_base = of_iomap(np, 0);
> +       if (!reg_base) {
> +               pr_err("%s: failed to map audss registers\n", __func__);
> +               return;
> +       }
> +
> +       clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
> +                               GFP_KERNEL);
> +       if (!clk_table) {
> +               pr_err("%s: could not allocate clk lookup table\n", __func__);
> +               return;
> +       }
> +
> +       clk_data.clks = clk_table;
> +       clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
> +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +
> +       clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
> +                               mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
> +                               reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
> +
> +       clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
> +                               mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
> +                               reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
> +
> +       clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
> +                               "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
> +                               0, &lock);
> +
> +       clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
> +                               "dout_aud_bus", "dout_srp", 0,
> +                               reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
> +
> +       clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
> +                               "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
> +                               &lock);
> +
> +       clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
> +                               "dout_srp", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 0, 0, &lock);
> +
> +       clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
> +                               "dout_aud_bus", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 2, 0, &lock);
> +
> +       clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
> +                               "dout_i2s", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 3, 0, &lock);
> +
> +       clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
> +                                "sclk_pcm", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 4, 0, &lock);
> +
> +       clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
> +                               "div_pcm0", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 5, 0, &lock);
> +
> +#ifdef CONFIG_PM_SLEEP
> +       register_syscore_ops(&exynos_audss_clk_syscore_ops);
> +#endif
> +
> +       pr_info("Exynos: Audss: clock setup completed\n");
> +}
> +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
> +               exynos_audss_clk_init);
> +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
> +               exynos_audss_clk_init);
> diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
> new file mode 100644
> index 0000000..8279f42
> --- /dev/null
> +++ b/include/dt-bindings/clk/exynos-audss-clk.h
> @@ -0,0 +1,25 @@
> +/*
> + * This header provides constants for Samsung audio subsystem
> + * clock controller.
> + *
> + * The constants defined in this header are being used in dts
> + * and exynos audss driver.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
> +#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
> +
> +#define EXYNOS_MOUT_AUDSS      0
> +#define EXYNOS_MOUT_I2S        1
> +#define EXYNOS_DOUT_SRP        2
> +#define EXYNOS_DOUT_AUD_BUS    3
> +#define EXYNOS_DOUT_I2S        4
> +#define EXYNOS_SRP_CLK         5
> +#define EXYNOS_I2S_BUS         6
> +#define EXYNOS_SCLK_I2S        7
> +#define EXYNOS_PCM_BUS         8
> +#define EXYNOS_SCLK_PCM        9
> +
> +#define EXYNOS_AUDSS_MAX_CLKS  10
> +
> +#endif
> -- 
> 1.7.4.4

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
@ 2013-06-11 22:13     ` Mike Turquette
  0 siblings, 0 replies; 28+ messages in thread
From: Mike Turquette @ 2013-06-11 22:13 UTC (permalink / raw)
  To: linux-arm-kernel

Quoting Padmavathi Venna (2013-06-04 05:28:07)
> Audio subsystem is introduced in s5pv210 and exynos platforms.
> This has seperate clock controller which can control i2s0 and
> pcm0 clocks. This patch registers the audio subsystem clocks
> with the common clock framework on Exynos family.
> 
> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

This looks good to me.  You have my Ack, or I can take this patch
through clk-next.  Let me know what works for you.

Regards,
Mike

> ---
>  .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
>  drivers/clk/samsung/Makefile                       |    1 +
>  drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
>  include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
>  4 files changed, 223 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>  create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
>  create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> new file mode 100644
> index 0000000..a120180
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> @@ -0,0 +1,64 @@
> +* Samsung Audio Subsystem Clock Controller
> +
> +The Samsung Audio Subsystem clock controller generates and supplies clocks
> +to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
> +binding described here is applicable to all SoC's in Exynos family.
> +
> +Required Properties:
> +
> +- compatible: should be one of the following:
> +  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
> +  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
> +
> +- reg: physical base address and length of the controller's register set.
> +
> +- #clock-cells: should be 1.
> +
> +The following is the list of clocks generated by the controller. Each clock is
> +assigned an identifier and client nodes use this identifier to specify the
> +clock which they consume. Some of the clocks are available only on a particular
> +Exynos4 SoC and this is specified where applicable.
> +
> +Provided clocks:
> +
> +Clock           ID      SoC (if specific)
> +-----------------------------------------------
> +
> +mout_audss      0
> +mout_i2s        1
> +dout_srp        2
> +dout_aud_bus    3
> +dout_i2s        4
> +srp_clk         5
> +i2s_bus         6
> +sclk_i2s        7
> +pcm_bus         8
> +sclk_pcm        9
> +
> +Example 1: An example of a clock controller node is listed below.
> +
> +clock_audss: audss-clock-controller at 3810000 {
> +       compatible = "samsung,exynos5250-audss-clock";
> +       reg = <0x03810000 0x0C>;
> +       #clock-cells = <1>;
> +};
> +
> +Example 2: I2S controller node that consumes the clock generated by the clock
> +           controller. Refer to the standard clock bindings for information
> +           about 'clocks' and 'clock-names' property.
> +
> +i2s0: i2s at 03830000 {
> +       compatible = "samsung,i2s-v5";
> +       reg = <0x03830000 0x100>;
> +       dmas = <&pdma0 10
> +               &pdma0 9
> +               &pdma0 8>;
> +       dma-names = "tx", "rx", "tx-sec";
> +       clocks = <&clock_audss EXYNOS_I2S_BUS>,
> +               <&clock_audss EXYNOS_I2S_BUS>,
> +               <&clock_audss EXYNOS_SCLK_I2S>,
> +               <&clock_audss EXYNOS_MOUT_AUDSS>,
> +               <&clock_audss EXYNOS_MOUT_I2S>;
> +       clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
> +       "mout_audss", "mout_i2s";
> +};
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index b7c232e..1876810 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)        += clk.o clk-pll.o
>  obj-$(CONFIG_ARCH_EXYNOS4)     += clk-exynos4.o
>  obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
>  obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
> +obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-audss.o
> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
> new file mode 100644
> index 0000000..9b1bbd5
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos-audss.c
> @@ -0,0 +1,133 @@
> +/*
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Padmavathi Venna <padma.v@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Common Clock Framework support for Audio Subsystem Clock Controller.
> +*/
> +
> +#include <linux/clkdev.h>
> +#include <linux/io.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/syscore_ops.h>
> +
> +#include <dt-bindings/clk/exynos-audss-clk.h>
> +
> +static DEFINE_SPINLOCK(lock);
> +static struct clk **clk_table;
> +static void __iomem *reg_base;
> +static struct clk_onecell_data clk_data;
> +
> +#define ASS_CLK_SRC 0x0
> +#define ASS_CLK_DIV 0x4
> +#define ASS_CLK_GATE 0x8
> +
> +static unsigned long reg_save[][2] = {
> +       {ASS_CLK_SRC,  0},
> +       {ASS_CLK_DIV,  0},
> +       {ASS_CLK_GATE, 0},
> +};
> +
> +/* list of all parent clock list */
> +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
> +static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int exynos_audss_clk_suspend(void)
> +{
> +       int i;
> +
> +       for (i = 0; i < ARRAY_SIZE(reg_save); i++)
> +               reg_save[i][1] = readl(reg_base + reg_save[i][0]);
> +
> +       return 0;
> +}
> +
> +static void exynos_audss_clk_resume(void)
> +{
> +       int i;
> +
> +       for (i = 0; i < ARRAY_SIZE(reg_save); i++)
> +               writel(reg_save[i][1], reg_base + reg_save[i][0]);
> +}
> +
> +static struct syscore_ops exynos_audss_clk_syscore_ops = {
> +       .suspend        = exynos_audss_clk_suspend,
> +       .resume         = exynos_audss_clk_resume,
> +};
> +#endif /* CONFIG_PM_SLEEP */
> +
> +/* register exynos_audss clocks */
> +void __init exynos_audss_clk_init(struct device_node *np)
> +{
> +       reg_base = of_iomap(np, 0);
> +       if (!reg_base) {
> +               pr_err("%s: failed to map audss registers\n", __func__);
> +               return;
> +       }
> +
> +       clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
> +                               GFP_KERNEL);
> +       if (!clk_table) {
> +               pr_err("%s: could not allocate clk lookup table\n", __func__);
> +               return;
> +       }
> +
> +       clk_data.clks = clk_table;
> +       clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
> +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +
> +       clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
> +                               mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
> +                               reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
> +
> +       clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
> +                               mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
> +                               reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
> +
> +       clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
> +                               "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
> +                               0, &lock);
> +
> +       clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
> +                               "dout_aud_bus", "dout_srp", 0,
> +                               reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
> +
> +       clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
> +                               "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
> +                               &lock);
> +
> +       clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
> +                               "dout_srp", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 0, 0, &lock);
> +
> +       clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
> +                               "dout_aud_bus", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 2, 0, &lock);
> +
> +       clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
> +                               "dout_i2s", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 3, 0, &lock);
> +
> +       clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
> +                                "sclk_pcm", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 4, 0, &lock);
> +
> +       clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
> +                               "div_pcm0", CLK_SET_RATE_PARENT,
> +                               reg_base + ASS_CLK_GATE, 5, 0, &lock);
> +
> +#ifdef CONFIG_PM_SLEEP
> +       register_syscore_ops(&exynos_audss_clk_syscore_ops);
> +#endif
> +
> +       pr_info("Exynos: Audss: clock setup completed\n");
> +}
> +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
> +               exynos_audss_clk_init);
> +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
> +               exynos_audss_clk_init);
> diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
> new file mode 100644
> index 0000000..8279f42
> --- /dev/null
> +++ b/include/dt-bindings/clk/exynos-audss-clk.h
> @@ -0,0 +1,25 @@
> +/*
> + * This header provides constants for Samsung audio subsystem
> + * clock controller.
> + *
> + * The constants defined in this header are being used in dts
> + * and exynos audss driver.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
> +#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
> +
> +#define EXYNOS_MOUT_AUDSS      0
> +#define EXYNOS_MOUT_I2S        1
> +#define EXYNOS_DOUT_SRP        2
> +#define EXYNOS_DOUT_AUD_BUS    3
> +#define EXYNOS_DOUT_I2S        4
> +#define EXYNOS_SRP_CLK         5
> +#define EXYNOS_I2S_BUS         6
> +#define EXYNOS_SCLK_I2S        7
> +#define EXYNOS_PCM_BUS         8
> +#define EXYNOS_SCLK_PCM        9
> +
> +#define EXYNOS_AUDSS_MAX_CLKS  10
> +
> +#endif
> -- 
> 1.7.4.4

^ permalink raw reply	[flat|nested] 28+ messages in thread
* Re: [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
  2013-06-11 22:13     ` Mike Turquette
@ 2013-06-12  5:35       ` Padma Venkat
  -1 siblings, 0 replies; 28+ messages in thread
From: Padma Venkat @ 2013-06-12  5:35 UTC (permalink / raw)
  To: Mike Turquette
  Cc: Padmavathi Venna, linux-samsung-soc, devicetree-discuss,
	linux-arm-kernel, alsa-devel, sbkim73, broonie, kgene.kim

Hi Mike,

On Wed, Jun 12, 2013 at 3:43 AM, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Padmavathi Venna (2013-06-04 05:28:07)
>> Audio subsystem is introduced in s5pv210 and exynos platforms.
>> This has seperate clock controller which can control i2s0 and
>> pcm0 clocks. This patch registers the audio subsystem clocks
>> with the common clock framework on Exynos family.
>>
>> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
>> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>
> This looks good to me.  You have my Ack, or I can take this patch
> through clk-next.  Let me know what works for you.

I have to rework for one small change in one of the patch in the set.
So I will do that and put your ack and will repost the patches. After
that you can take the patches through clk-next.

Thanks
Padma

>
> Regards,
> Mike
>
>> ---
>>  .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
>>  drivers/clk/samsung/Makefile                       |    1 +
>>  drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
>>  include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
>>  4 files changed, 223 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>>  create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
>>  create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> new file mode 100644
>> index 0000000..a120180
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> @@ -0,0 +1,64 @@
>> +* Samsung Audio Subsystem Clock Controller
>> +
>> +The Samsung Audio Subsystem clock controller generates and supplies clocks
>> +to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
>> +binding described here is applicable to all SoC's in Exynos family.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following:
>> +  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
>> +  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
>> +
>> +- reg: physical base address and length of the controller's register set.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +The following is the list of clocks generated by the controller. Each clock is
>> +assigned an identifier and client nodes use this identifier to specify the
>> +clock which they consume. Some of the clocks are available only on a particular
>> +Exynos4 SoC and this is specified where applicable.
>> +
>> +Provided clocks:
>> +
>> +Clock           ID      SoC (if specific)
>> +-----------------------------------------------
>> +
>> +mout_audss      0
>> +mout_i2s        1
>> +dout_srp        2
>> +dout_aud_bus    3
>> +dout_i2s        4
>> +srp_clk         5
>> +i2s_bus         6
>> +sclk_i2s        7
>> +pcm_bus         8
>> +sclk_pcm        9
>> +
>> +Example 1: An example of a clock controller node is listed below.
>> +
>> +clock_audss: audss-clock-controller@3810000 {
>> +       compatible = "samsung,exynos5250-audss-clock";
>> +       reg = <0x03810000 0x0C>;
>> +       #clock-cells = <1>;
>> +};
>> +
>> +Example 2: I2S controller node that consumes the clock generated by the clock
>> +           controller. Refer to the standard clock bindings for information
>> +           about 'clocks' and 'clock-names' property.
>> +
>> +i2s0: i2s@03830000 {
>> +       compatible = "samsung,i2s-v5";
>> +       reg = <0x03830000 0x100>;
>> +       dmas = <&pdma0 10
>> +               &pdma0 9
>> +               &pdma0 8>;
>> +       dma-names = "tx", "rx", "tx-sec";
>> +       clocks = <&clock_audss EXYNOS_I2S_BUS>,
>> +               <&clock_audss EXYNOS_I2S_BUS>,
>> +               <&clock_audss EXYNOS_SCLK_I2S>,
>> +               <&clock_audss EXYNOS_MOUT_AUDSS>,
>> +               <&clock_audss EXYNOS_MOUT_I2S>;
>> +       clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
>> +       "mout_audss", "mout_i2s";
>> +};
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> index b7c232e..1876810 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)        += clk.o clk-pll.o
>>  obj-$(CONFIG_ARCH_EXYNOS4)     += clk-exynos4.o
>>  obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
>>  obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
>> +obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-audss.o
>> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
>> new file mode 100644
>> index 0000000..9b1bbd5
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos-audss.c
>> @@ -0,0 +1,133 @@
>> +/*
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * Author: Padmavathi Venna <padma.v@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for Audio Subsystem Clock Controller.
>> +*/
>> +
>> +#include <linux/clkdev.h>
>> +#include <linux/io.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of_address.h>
>> +#include <linux/syscore_ops.h>
>> +
>> +#include <dt-bindings/clk/exynos-audss-clk.h>
>> +
>> +static DEFINE_SPINLOCK(lock);
>> +static struct clk **clk_table;
>> +static void __iomem *reg_base;
>> +static struct clk_onecell_data clk_data;
>> +
>> +#define ASS_CLK_SRC 0x0
>> +#define ASS_CLK_DIV 0x4
>> +#define ASS_CLK_GATE 0x8
>> +
>> +static unsigned long reg_save[][2] = {
>> +       {ASS_CLK_SRC,  0},
>> +       {ASS_CLK_DIV,  0},
>> +       {ASS_CLK_GATE, 0},
>> +};
>> +
>> +/* list of all parent clock list */
>> +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
>> +static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int exynos_audss_clk_suspend(void)
>> +{
>> +       int i;
>> +
>> +       for (i = 0; i < ARRAY_SIZE(reg_save); i++)
>> +               reg_save[i][1] = readl(reg_base + reg_save[i][0]);
>> +
>> +       return 0;
>> +}
>> +
>> +static void exynos_audss_clk_resume(void)
>> +{
>> +       int i;
>> +
>> +       for (i = 0; i < ARRAY_SIZE(reg_save); i++)
>> +               writel(reg_save[i][1], reg_base + reg_save[i][0]);
>> +}
>> +
>> +static struct syscore_ops exynos_audss_clk_syscore_ops = {
>> +       .suspend        = exynos_audss_clk_suspend,
>> +       .resume         = exynos_audss_clk_resume,
>> +};
>> +#endif /* CONFIG_PM_SLEEP */
>> +
>> +/* register exynos_audss clocks */
>> +void __init exynos_audss_clk_init(struct device_node *np)
>> +{
>> +       reg_base = of_iomap(np, 0);
>> +       if (!reg_base) {
>> +               pr_err("%s: failed to map audss registers\n", __func__);
>> +               return;
>> +       }
>> +
>> +       clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
>> +                               GFP_KERNEL);
>> +       if (!clk_table) {
>> +               pr_err("%s: could not allocate clk lookup table\n", __func__);
>> +               return;
>> +       }
>> +
>> +       clk_data.clks = clk_table;
>> +       clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
>> +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
>> +
>> +       clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
>> +                               mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
>> +                               reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
>> +
>> +       clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
>> +                               mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
>> +                               reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
>> +
>> +       clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
>> +                               "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
>> +                               0, &lock);
>> +
>> +       clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
>> +                               "dout_aud_bus", "dout_srp", 0,
>> +                               reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
>> +
>> +       clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
>> +                               "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
>> +                               &lock);
>> +
>> +       clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
>> +                               "dout_srp", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 0, 0, &lock);
>> +
>> +       clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
>> +                               "dout_aud_bus", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 2, 0, &lock);
>> +
>> +       clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
>> +                               "dout_i2s", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 3, 0, &lock);
>> +
>> +       clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
>> +                                "sclk_pcm", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 4, 0, &lock);
>> +
>> +       clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
>> +                               "div_pcm0", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 5, 0, &lock);
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +       register_syscore_ops(&exynos_audss_clk_syscore_ops);
>> +#endif
>> +
>> +       pr_info("Exynos: Audss: clock setup completed\n");
>> +}
>> +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
>> +               exynos_audss_clk_init);
>> +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
>> +               exynos_audss_clk_init);
>> diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
>> new file mode 100644
>> index 0000000..8279f42
>> --- /dev/null
>> +++ b/include/dt-bindings/clk/exynos-audss-clk.h
>> @@ -0,0 +1,25 @@
>> +/*
>> + * This header provides constants for Samsung audio subsystem
>> + * clock controller.
>> + *
>> + * The constants defined in this header are being used in dts
>> + * and exynos audss driver.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
>> +#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
>> +
>> +#define EXYNOS_MOUT_AUDSS      0
>> +#define EXYNOS_MOUT_I2S        1
>> +#define EXYNOS_DOUT_SRP        2
>> +#define EXYNOS_DOUT_AUD_BUS    3
>> +#define EXYNOS_DOUT_I2S        4
>> +#define EXYNOS_SRP_CLK         5
>> +#define EXYNOS_I2S_BUS         6
>> +#define EXYNOS_SCLK_I2S        7
>> +#define EXYNOS_PCM_BUS         8
>> +#define EXYNOS_SCLK_PCM        9
>> +
>> +#define EXYNOS_AUDSS_MAX_CLKS  10
>> +
>> +#endif
>> --
>> 1.7.4.4

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework
@ 2013-06-12  5:35       ` Padma Venkat
  0 siblings, 0 replies; 28+ messages in thread
From: Padma Venkat @ 2013-06-12  5:35 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Mike,

On Wed, Jun 12, 2013 at 3:43 AM, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Padmavathi Venna (2013-06-04 05:28:07)
>> Audio subsystem is introduced in s5pv210 and exynos platforms.
>> This has seperate clock controller which can control i2s0 and
>> pcm0 clocks. This patch registers the audio subsystem clocks
>> with the common clock framework on Exynos family.
>>
>> Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
>> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>
> This looks good to me.  You have my Ack, or I can take this patch
> through clk-next.  Let me know what works for you.

I have to rework for one small change in one of the patch in the set.
So I will do that and put your ack and will repost the patches. After
that you can take the patches through clk-next.

Thanks
Padma

>
> Regards,
> Mike
>
>> ---
>>  .../devicetree/bindings/clock/clk-exynos-audss.txt |   64 ++++++++++
>>  drivers/clk/samsung/Makefile                       |    1 +
>>  drivers/clk/samsung/clk-exynos-audss.c             |  133 ++++++++++++++++++++
>>  include/dt-bindings/clk/exynos-audss-clk.h         |   25 ++++
>>  4 files changed, 223 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>>  create mode 100644 drivers/clk/samsung/clk-exynos-audss.c
>>  create mode 100644 include/dt-bindings/clk/exynos-audss-clk.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> new file mode 100644
>> index 0000000..a120180
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> @@ -0,0 +1,64 @@
>> +* Samsung Audio Subsystem Clock Controller
>> +
>> +The Samsung Audio Subsystem clock controller generates and supplies clocks
>> +to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
>> +binding described here is applicable to all SoC's in Exynos family.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be one of the following:
>> +  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
>> +  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.
>> +
>> +- reg: physical base address and length of the controller's register set.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +The following is the list of clocks generated by the controller. Each clock is
>> +assigned an identifier and client nodes use this identifier to specify the
>> +clock which they consume. Some of the clocks are available only on a particular
>> +Exynos4 SoC and this is specified where applicable.
>> +
>> +Provided clocks:
>> +
>> +Clock           ID      SoC (if specific)
>> +-----------------------------------------------
>> +
>> +mout_audss      0
>> +mout_i2s        1
>> +dout_srp        2
>> +dout_aud_bus    3
>> +dout_i2s        4
>> +srp_clk         5
>> +i2s_bus         6
>> +sclk_i2s        7
>> +pcm_bus         8
>> +sclk_pcm        9
>> +
>> +Example 1: An example of a clock controller node is listed below.
>> +
>> +clock_audss: audss-clock-controller at 3810000 {
>> +       compatible = "samsung,exynos5250-audss-clock";
>> +       reg = <0x03810000 0x0C>;
>> +       #clock-cells = <1>;
>> +};
>> +
>> +Example 2: I2S controller node that consumes the clock generated by the clock
>> +           controller. Refer to the standard clock bindings for information
>> +           about 'clocks' and 'clock-names' property.
>> +
>> +i2s0: i2s at 03830000 {
>> +       compatible = "samsung,i2s-v5";
>> +       reg = <0x03830000 0x100>;
>> +       dmas = <&pdma0 10
>> +               &pdma0 9
>> +               &pdma0 8>;
>> +       dma-names = "tx", "rx", "tx-sec";
>> +       clocks = <&clock_audss EXYNOS_I2S_BUS>,
>> +               <&clock_audss EXYNOS_I2S_BUS>,
>> +               <&clock_audss EXYNOS_SCLK_I2S>,
>> +               <&clock_audss EXYNOS_MOUT_AUDSS>,
>> +               <&clock_audss EXYNOS_MOUT_I2S>;
>> +       clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
>> +       "mout_audss", "mout_i2s";
>> +};
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> index b7c232e..1876810 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_COMMON_CLK)        += clk.o clk-pll.o
>>  obj-$(CONFIG_ARCH_EXYNOS4)     += clk-exynos4.o
>>  obj-$(CONFIG_SOC_EXYNOS5250)   += clk-exynos5250.o
>>  obj-$(CONFIG_SOC_EXYNOS5440)   += clk-exynos5440.o
>> +obj-$(CONFIG_ARCH_EXYNOS)      += clk-exynos-audss.o
>> diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
>> new file mode 100644
>> index 0000000..9b1bbd5
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos-audss.c
>> @@ -0,0 +1,133 @@
>> +/*
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * Author: Padmavathi Venna <padma.v@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for Audio Subsystem Clock Controller.
>> +*/
>> +
>> +#include <linux/clkdev.h>
>> +#include <linux/io.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of_address.h>
>> +#include <linux/syscore_ops.h>
>> +
>> +#include <dt-bindings/clk/exynos-audss-clk.h>
>> +
>> +static DEFINE_SPINLOCK(lock);
>> +static struct clk **clk_table;
>> +static void __iomem *reg_base;
>> +static struct clk_onecell_data clk_data;
>> +
>> +#define ASS_CLK_SRC 0x0
>> +#define ASS_CLK_DIV 0x4
>> +#define ASS_CLK_GATE 0x8
>> +
>> +static unsigned long reg_save[][2] = {
>> +       {ASS_CLK_SRC,  0},
>> +       {ASS_CLK_DIV,  0},
>> +       {ASS_CLK_GATE, 0},
>> +};
>> +
>> +/* list of all parent clock list */
>> +static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
>> +static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +static int exynos_audss_clk_suspend(void)
>> +{
>> +       int i;
>> +
>> +       for (i = 0; i < ARRAY_SIZE(reg_save); i++)
>> +               reg_save[i][1] = readl(reg_base + reg_save[i][0]);
>> +
>> +       return 0;
>> +}
>> +
>> +static void exynos_audss_clk_resume(void)
>> +{
>> +       int i;
>> +
>> +       for (i = 0; i < ARRAY_SIZE(reg_save); i++)
>> +               writel(reg_save[i][1], reg_base + reg_save[i][0]);
>> +}
>> +
>> +static struct syscore_ops exynos_audss_clk_syscore_ops = {
>> +       .suspend        = exynos_audss_clk_suspend,
>> +       .resume         = exynos_audss_clk_resume,
>> +};
>> +#endif /* CONFIG_PM_SLEEP */
>> +
>> +/* register exynos_audss clocks */
>> +void __init exynos_audss_clk_init(struct device_node *np)
>> +{
>> +       reg_base = of_iomap(np, 0);
>> +       if (!reg_base) {
>> +               pr_err("%s: failed to map audss registers\n", __func__);
>> +               return;
>> +       }
>> +
>> +       clk_table = kzalloc(sizeof(struct clk *) * EXYNOS_AUDSS_MAX_CLKS,
>> +                               GFP_KERNEL);
>> +       if (!clk_table) {
>> +               pr_err("%s: could not allocate clk lookup table\n", __func__);
>> +               return;
>> +       }
>> +
>> +       clk_data.clks = clk_table;
>> +       clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
>> +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
>> +
>> +       clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
>> +                               mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
>> +                               reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
>> +
>> +       clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
>> +                               mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
>> +                               reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
>> +
>> +       clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
>> +                               "mout_audss", 0, reg_base + ASS_CLK_DIV, 0, 4,
>> +                               0, &lock);
>> +
>> +       clk_table[EXYNOS_DOUT_AUD_BUS] = clk_register_divider(NULL,
>> +                               "dout_aud_bus", "dout_srp", 0,
>> +                               reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
>> +
>> +       clk_table[EXYNOS_DOUT_I2S] = clk_register_divider(NULL, "dout_i2s",
>> +                               "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
>> +                               &lock);
>> +
>> +       clk_table[EXYNOS_SRP_CLK] = clk_register_gate(NULL, "srp_clk",
>> +                               "dout_srp", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 0, 0, &lock);
>> +
>> +       clk_table[EXYNOS_I2S_BUS] = clk_register_gate(NULL, "i2s_bus",
>> +                               "dout_aud_bus", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 2, 0, &lock);
>> +
>> +       clk_table[EXYNOS_SCLK_I2S] = clk_register_gate(NULL, "sclk_i2s",
>> +                               "dout_i2s", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 3, 0, &lock);
>> +
>> +       clk_table[EXYNOS_PCM_BUS] = clk_register_gate(NULL, "pcm_bus",
>> +                                "sclk_pcm", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 4, 0, &lock);
>> +
>> +       clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm",
>> +                               "div_pcm0", CLK_SET_RATE_PARENT,
>> +                               reg_base + ASS_CLK_GATE, 5, 0, &lock);
>> +
>> +#ifdef CONFIG_PM_SLEEP
>> +       register_syscore_ops(&exynos_audss_clk_syscore_ops);
>> +#endif
>> +
>> +       pr_info("Exynos: Audss: clock setup completed\n");
>> +}
>> +CLK_OF_DECLARE(exynos4210_audss_clk, "samsung,exynos4210-audss-clock",
>> +               exynos_audss_clk_init);
>> +CLK_OF_DECLARE(exynos5250_audss_clk, "samsung,exynos5250-audss-clock",
>> +               exynos_audss_clk_init);
>> diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h
>> new file mode 100644
>> index 0000000..8279f42
>> --- /dev/null
>> +++ b/include/dt-bindings/clk/exynos-audss-clk.h
>> @@ -0,0 +1,25 @@
>> +/*
>> + * This header provides constants for Samsung audio subsystem
>> + * clock controller.
>> + *
>> + * The constants defined in this header are being used in dts
>> + * and exynos audss driver.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
>> +#define _DT_BINDINGS_CLK_EXYNOS_AUDSS_H
>> +
>> +#define EXYNOS_MOUT_AUDSS      0
>> +#define EXYNOS_MOUT_I2S        1
>> +#define EXYNOS_DOUT_SRP        2
>> +#define EXYNOS_DOUT_AUD_BUS    3
>> +#define EXYNOS_DOUT_I2S        4
>> +#define EXYNOS_SRP_CLK         5
>> +#define EXYNOS_I2S_BUS         6
>> +#define EXYNOS_SCLK_I2S        7
>> +#define EXYNOS_PCM_BUS         8
>> +#define EXYNOS_SCLK_PCM        9
>> +
>> +#define EXYNOS_AUDSS_MAX_CLKS  10
>> +
>> +#endif
>> --
>> 1.7.4.4

^ permalink raw reply	[flat|nested] 28+ messages in thread
end of thread, other threads:[~2013-06-12  5:35 UTC | newest]

Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2013-06-04 12:28 [PATCH V5 0/5] clk: Samsung: audss: Register audio subsytem clocks using common clk framework Padmavathi Venna
2013-06-04 12:28 ` Padmavathi Venna
2013-06-04 12:28 ` [PATCH V5 1/5] ARM: samsung: use #include for all device trees Padmavathi Venna
2013-06-04 12:28   ` Padmavathi Venna
2013-06-04 12:28 ` [PATCH V5 2/5] clk: samsung: register audio subsystem clocks using common clock framework Padmavathi Venna
2013-06-04 12:28   ` Padmavathi Venna
2013-06-04 17:09   ` Doug Anderson
2013-06-04 17:09     ` Doug Anderson
2013-06-11 22:13   ` Mike Turquette
2013-06-11 22:13     ` Mike Turquette
2013-06-12  5:35     ` Padma Venkat
2013-06-12  5:35       ` Padma Venkat
2013-06-04 12:28 ` [PATCH V5 3/5] ARM: dts: add Exynos audio subsystem clock controller node Padmavathi Venna
2013-06-04 12:28   ` Padmavathi Venna
2013-06-04 17:10   ` Doug Anderson
2013-06-04 17:10     ` Doug Anderson
2013-06-04 12:28 ` [PATCH V5 4/5] ARM: dts: add clock provider information for i2s controllers in Exynos5250 Padmavathi Venna
2013-06-04 12:28   ` Padmavathi Venna
2013-06-04 17:12   ` Doug Anderson
2013-06-04 17:12     ` Doug Anderson
2013-06-04 17:19   ` Doug Anderson
2013-06-04 17:19     ` Doug Anderson
2013-06-06  3:54     ` Padma Venkat
2013-06-06  3:54       ` Padma Venkat
2013-06-04 12:28 ` [PATCH V5 5/5] ARM: dts: Update Samsung I2S documentation Padmavathi Venna
2013-06-04 12:28   ` Padmavathi Venna
2013-06-04 17:25   ` Doug Anderson
2013-06-04 17:25     ` Doug Anderson

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