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From: Doug Anderson <dianders@chromium.org>
To: Arun Kumar K <arun.kk@samsung.com>
Cc: linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
	Kukjin Kim <kgene.kim@samsung.com>,
	Thomas Abraham <thomas.abraham@linaro.org>,
	arunkk.samsung@gmail.com
Subject: Re: clk: Exynos5250: Add clocks for G3D
Date: Tue, 21 May 2013 15:43:43 -0700	[thread overview]
Message-ID: <CAD=FV=XCzcY4-dN=2OYkrkTU9HYxykSUPnm++RVQ6a6g4t-XUA@mail.gmail.com> (raw)
In-Reply-To: <1369139801-1889-1-git-send-email-arun.kk@samsung.com>

Arun,

On Tue, May 21, 2013 at 5:36 AM, Arun Kumar K <arun.kk@samsung.com> wrote:
> @@ -262,6 +270,7 @@ struct samsung_div_clock exynos5250_div_clks[] __initdata = {
>         DIV(none, "aclk166", "mout_aclk166", DIV_TOP0, 8, 3),
>         DIV(none, "aclk333", "mout_aclk333", DIV_TOP0, 20, 3),
>         DIV(none, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
> +       DIV(aclk_400_g3d, "aclk_400_g3d", "mout_aclk400", DIV_TOP0, 24, 3),

Doh!  I looked at this more and it looks like I missed something.
You've added this clock to the range assigned for "[Peripheral Clock
Gates]".  This is not a gate clock but is a div clock.

Perhaps it should be in a different range?  Could make IDs that start
at 512 or something?

-Doug

  parent reply	other threads:[~2013-05-21 22:43 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-05-21 12:36 [PATCH] clk: Exynos5250: Add clocks for G3D Arun Kumar K
2013-05-21 20:10 ` Doug Anderson
2013-05-21 22:43 ` Doug Anderson [this message]
2013-05-24  4:35   ` Arun Kumar K
2013-05-21 22:50 ` [PATCH] " Tomasz Figa
2013-05-24  4:34   ` Arun Kumar K

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