Re: [PATCH] clk: Exynos5250: Add clocks for G3D

[Arun Kumar K <arunkk.samsung@gmail.com>]

Hi Tomasz,

Thanks for your review.

>> +     DIV(aclk_400_g3d, "aclk_400_g3d", "mout_aclk400", DIV_TOP0, 24,
> 3),
>
> Do you need to export this div clock? If it's a parent of a gate clock,
> then you can simply add CLK_SET_RATE_PARENT flag to the gate clock and
> calling set_rate on it will reconfigure the divider.
>

Yes this clock doesnt need to exported. But the current driver gets this clock
and will fail if its not exported. So that will need some changes from the
driver side also.


>>       DIV(none, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),
>>       DIV(none, "div_cam0", "mout_cam0", DIV_GSCL, 16, 4),
>>       DIV(none, "div_cam1", "mout_cam1", DIV_GSCL, 20, 4),
>> @@ -462,6 +471,7 @@ struct samsung_gate_clock exynos5250_gate_clks[]
>> __initdata = { GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0),
>>       GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0),
>>       GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0),
>> +     GATE(g3d, "g3d", "aclk_400_g3d", GATE_IP_G3D, 0, 0, 0),
>
> This would be then:
>
>         GATE(g3d, "g3d", "aclk_400_g3d", GATE_IP_G3D, 0,
>                                         CLK_SET_RATE_PARENT, 0),
>

Yes this would work. I will change it accordingly.

Thanks
Arun