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From: Duc Dang <dhdang@apm.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: "David Daney" <ddaney.cavm@gmail.com>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Mark Rutland" <mark.rutland@arm.com>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Krzysztof Kozlowski" <k.kozlowski@samsung.com>,
	"Liu Gang" <Gang.Liu@nxp.com>,
	"Masahiro Yamada" <yamada.masahiro@socionext.com>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"Kevin Hilman" <khilman@baylibre.com>,
	"Hou Zhiqiang" <B48286@freescale.com>,
	"Michal Simek" <michal.simek@xilinx.com>,
	"Kukjin Kim" <kgene@kernel.org>,
	bcm-kernel-feedback-list@broadcom.com,
	linux-arm <linux-arm-kernel@lists.infradead.org>,
	"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
	"Jason Cooper" <jason@lakedaemon.net>,
	"Ray Jui" <rjui@broadcom.com>,
	"Tirumalesh Chalamarla" <tchalamarla@cavium.com>,
	linux-samsung-soc@vger.kernel.org, "Yuan Yao" <yao.yuan@nxp.com>,
	"Wenbin Song" <Wenbin.Song@freescale.com>,
	"Jan Glauber" <jglauber@cavium.com>,
	"Gregory Clement" <gregory.clement@free-electrons.com>,
	linux-amlogic@lists.infradead.org,
	"Mingkai Hu" <Mingkai.Hu@freescale.com>,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
	"Rajesh Bhagat" <rajesh.bhagat@freescale.com>,
	"Scott Branden" <sbranden@broadcom.com>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	"Carlo Caione" <carlo@caione.org>,
	"Dinh Nguyen" <dinguyen@opensource.altera.com>
Subject: Re: [PATCH v3 1/2] clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered
Date: Fri, 10 Jun 2016 14:51:45 -0700	[thread overview]
Message-ID: <CADaLND=gft2NEsoAHKBOUkK=ufDf7=xyqgwk-30+0C8Ui6iZRw@mail.gmail.com> (raw)
In-Reply-To: <20160610082952.4f20d732@arm.com>

On Fri, Jun 10, 2016 at 12:29 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On Thu, 09 Jun 2016 14:10:48 -0700
> David Daney <ddaney.cavm@gmail.com> wrote:
>
>> On 06/06/2016 10:56 AM, Marc Zyngier wrote:
>> > The ARM architected timer produces level-triggered interrupts (this
>> > is mandated by the architecture). Unfortunately, most device-trees
>> > get this wrong, and expose an edge-triggered interrupt.
>> >
>> > Until now, this wasn't too much an issue, as the programming of the
>> > trigger would fail (the corresponding PPI cannot be reconfigured),
>> > and the kernel would be happy with this. But we're about to change
>> > this, and trust DT a lot if the driver doesn't provide its own
>> > trigger information. In that context, the timer breaks badly.
>> >
>> > While we do need to fix the DTs, there is also some userspace out
>> > there (kvmtool) that generates the same kind of broken DT on the
>> > fly, and that will completely break with newer kernels.
>> >
>> > As a safety measure, and to keep buggy software alive as well as
>> > buying us some time to fix DTs all over the place, let's check
>> > what trigger configuration has been given us by the firmware.
>> > If this is not a level configuration, then we know that the
>> > DT/ACPI configuration is bust, and we pick some defaults which
>> > won't be worse than the existing setup.
>> >
>> > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>>
>>
>> I tried to test this patch, but there is a problem somewhere that I have
>> not yet tracked down.  On Cavium Thunder (gic-v3 based) I have tested
>> with the device tree interrupt type of both 4 and 8 and get the same result:
>>
>>
>> [    0.000000] arm_arch_timer: WARNING: Invalid trigger for IRQ2,
>> assuming level low
>> [    0.000000] arm_arch_timer: WARNING: Please fix your firmware
>> [    0.000000] arm_arch_timer: WARNING: Invalid trigger for IRQ3,
>> assuming level low
>> [    0.000000] arm_arch_timer: WARNING: Please fix your firmware
>> [    0.000000] arm_arch_timer: Architected cp15 timer(s) running at
>> 100.00MHz (phys).
>> [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff
>> max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
>> [    0.000002] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps
>> every 4398046511100ns
>>
>> It could be that the gic-v3 irq mapping code is broken.  I will try to
>> look into it, but there may be other fixes needed before we would
>> consider this patch to be an improvement.
>
> That's because the core kernel has other bugs which are going to be
> addressed in 4.8. So far, we cannot set the trigger of a per-cpu
> interrupt from the device tree, and we end-up with whatever is the
> default (edge). You can put whatever you want in the DT, it will be
> ignored.
>
> This series in preparation of these fixes landing in 4.8, where we'll
> be able to do the right thing, and will start noticing stupid things
> coming from the DT.
Hi Marc,

I also see the same warning that David saw. Can you please cc me when
the bug fix series
is available? I will test it out for X-Gene 1 and will need to change
the interrupt setting for timer
events on X-Gene 2 as well.

Regards,
Duc Dang.

>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny.

WARNING: multiple messages have this Message-ID (diff)
From: Duc Dang <dhdang@apm.com>
To: Marc Zyngier <marc.zyngier@arm.com>
Cc: "Mark Rutland" <mark.rutland@arm.com>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Krzysztof Kozlowski" <k.kozlowski@samsung.com>,
	"Hou Zhiqiang" <B48286@freescale.com>,
	"Wenbin Song" <Wenbin.Song@freescale.com>,
	"Liu Gang" <Gang.Liu@nxp.com>,
	"Masahiro Yamada" <yamada.masahiro@socionext.com>,
	"Mingkai Hu" <Mingkai.Hu@freescale.com>,
	"Florian Fainelli" <f.fainelli@gmail.com>,
	"Kevin Hilman" <khilman@baylibre.com>,
	"Daniel Lezcano" <daniel.lezcano@linaro.org>,
	"Michal Simek" <michal.simek@xilinx.com>,
	linux-samsung-soc@vger.kernel.org,
	"Kukjin Kim" <kgene@kernel.org>,
	bcm-kernel-feedback-list@broadcom.com,
	"Sören Brinkmann" <soren.brinkmann@xilinx.com>,
	"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
	"Jason Cooper" <jason@lakedaemon.net>,
	"Ray Jui" <rjui@broadcom.com>,
	"Tirumalesh Chalamarla" <tchalamarla@cavium.com>,
	"Rob Herring" <robh+dt@kernel.org>, "Yuan Yao" <yao.yuan@nxp.com>
Subject: Re: [PATCH v3 1/2] clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered
Date: Fri, 10 Jun 2016 14:51:45 -0700	[thread overview]
Message-ID: <CADaLND=gft2NEsoAHKBOUkK=ufDf7=xyqgwk-30+0C8Ui6iZRw@mail.gmail.com> (raw)
In-Reply-To: <20160610082952.4f20d732@arm.com>

On Fri, Jun 10, 2016 at 12:29 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On Thu, 09 Jun 2016 14:10:48 -0700
> David Daney <ddaney.cavm@gmail.com> wrote:
>
>> On 06/06/2016 10:56 AM, Marc Zyngier wrote:
>> > The ARM architected timer produces level-triggered interrupts (this
>> > is mandated by the architecture). Unfortunately, most device-trees
>> > get this wrong, and expose an edge-triggered interrupt.
>> >
>> > Until now, this wasn't too much an issue, as the programming of the
>> > trigger would fail (the corresponding PPI cannot be reconfigured),
>> > and the kernel would be happy with this. But we're about to change
>> > this, and trust DT a lot if the driver doesn't provide its own
>> > trigger information. In that context, the timer breaks badly.
>> >
>> > While we do need to fix the DTs, there is also some userspace out
>> > there (kvmtool) that generates the same kind of broken DT on the
>> > fly, and that will completely break with newer kernels.
>> >
>> > As a safety measure, and to keep buggy software alive as well as
>> > buying us some time to fix DTs all over the place, let's check
>> > what trigger configuration has been given us by the firmware.
>> > If this is not a level configuration, then we know that the
>> > DT/ACPI configuration is bust, and we pick some defaults which
>> > won't be worse than the existing setup.
>> >
>> > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>>
>>
>> I tried to test this patch, but there is a problem somewhere that I have
>> not yet tracked down.  On Cavium Thunder (gic-v3 based) I have tested
>> with the device tree interrupt type of both 4 and 8 and get the same result:
>>
>>
>> [    0.000000] arm_arch_timer: WARNING: Invalid trigger for IRQ2,
>> assuming level low
>> [    0.000000] arm_arch_timer: WARNING: Please fix your firmware
>> [    0.000000] arm_arch_timer: WARNING: Invalid trigger for IRQ3,
>> assuming level low
>> [    0.000000] arm_arch_timer: WARNING: Please fix your firmware
>> [    0.000000] arm_arch_timer: Architected cp15 timer(s) running at
>> 100.00MHz (phys).
>> [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff
>> max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
>> [    0.000002] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps
>> every 4398046511100ns
>>
>> It could be that the gic-v3 irq mapping code is broken.  I will try to
>> look into it, but there may be other fixes needed before we would
>> consider this patch to be an improvement.
>
> That's because the core kernel has other bugs which are going to be
> addressed in 4.8. So far, we cannot set the trigger of a per-cpu
> interrupt from the device tree, and we end-up with whatever is the
> default (edge). You can put whatever you want in the DT, it will be
> ignored.
>
> This series in preparation of these fixes landing in 4.8, where we'll
> be able to do the right thing, and will start noticing stupid things
> coming from the DT.
Hi Marc,

I also see the same warning that David saw. Can you please cc me when
the bug fix series
is available? I will test it out for X-Gene 1 and will need to change
the interrupt setting for timer
events on X-Gene 2 as well.

Regards,
Duc Dang.

>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny.

WARNING: multiple messages have this Message-ID (diff)
From: dhdang@apm.com (Duc Dang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 1/2] clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered
Date: Tue, 05 Jul 2016 04:37:14 -0000	[thread overview]
Message-ID: <CADaLND=gft2NEsoAHKBOUkK=ufDf7=xyqgwk-30+0C8Ui6iZRw@mail.gmail.com> (raw)
In-Reply-To: <20160610082952.4f20d732@arm.com>

On Fri, Jun 10, 2016 at 12:29 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On Thu, 09 Jun 2016 14:10:48 -0700
> David Daney <ddaney.cavm@gmail.com> wrote:
>
>> On 06/06/2016 10:56 AM, Marc Zyngier wrote:
>> > The ARM architected timer produces level-triggered interrupts (this
>> > is mandated by the architecture). Unfortunately, most device-trees
>> > get this wrong, and expose an edge-triggered interrupt.
>> >
>> > Until now, this wasn't too much an issue, as the programming of the
>> > trigger would fail (the corresponding PPI cannot be reconfigured),
>> > and the kernel would be happy with this. But we're about to change
>> > this, and trust DT a lot if the driver doesn't provide its own
>> > trigger information. In that context, the timer breaks badly.
>> >
>> > While we do need to fix the DTs, there is also some userspace out
>> > there (kvmtool) that generates the same kind of broken DT on the
>> > fly, and that will completely break with newer kernels.
>> >
>> > As a safety measure, and to keep buggy software alive as well as
>> > buying us some time to fix DTs all over the place, let's check
>> > what trigger configuration has been given us by the firmware.
>> > If this is not a level configuration, then we know that the
>> > DT/ACPI configuration is bust, and we pick some defaults which
>> > won't be worse than the existing setup.
>> >
>> > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>>
>>
>> I tried to test this patch, but there is a problem somewhere that I have
>> not yet tracked down.  On Cavium Thunder (gic-v3 based) I have tested
>> with the device tree interrupt type of both 4 and 8 and get the same result:
>>
>>
>> [    0.000000] arm_arch_timer: WARNING: Invalid trigger for IRQ2,
>> assuming level low
>> [    0.000000] arm_arch_timer: WARNING: Please fix your firmware
>> [    0.000000] arm_arch_timer: WARNING: Invalid trigger for IRQ3,
>> assuming level low
>> [    0.000000] arm_arch_timer: WARNING: Please fix your firmware
>> [    0.000000] arm_arch_timer: Architected cp15 timer(s) running at
>> 100.00MHz (phys).
>> [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff
>> max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
>> [    0.000002] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps
>> every 4398046511100ns
>>
>> It could be that the gic-v3 irq mapping code is broken.  I will try to
>> look into it, but there may be other fixes needed before we would
>> consider this patch to be an improvement.
>
> That's because the core kernel has other bugs which are going to be
> addressed in 4.8. So far, we cannot set the trigger of a per-cpu
> interrupt from the device tree, and we end-up with whatever is the
> default (edge). You can put whatever you want in the DT, it will be
> ignored.
>
> This series in preparation of these fixes landing in 4.8, where we'll
> be able to do the right thing, and will start noticing stupid things
> coming from the DT.
Hi Marc,

I also see the same warning that David saw. Can you please cc me when
the bug fix series
is available? I will test it out for X-Gene 1 and will need to change
the interrupt setting for timer
events on X-Gene 2 as well.

Regards,
Duc Dang.

>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny.

WARNING: multiple messages have this Message-ID (diff)
From: dhdang@apm.com (Duc Dang)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH v3 1/2] clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered
Date: Tue, 05 Jul 2016 04:37:15 -0000	[thread overview]
Message-ID: <CADaLND=gft2NEsoAHKBOUkK=ufDf7=xyqgwk-30+0C8Ui6iZRw@mail.gmail.com> (raw)
In-Reply-To: <20160610082952.4f20d732@arm.com>

On Fri, Jun 10, 2016 at 12:29 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On Thu, 09 Jun 2016 14:10:48 -0700
> David Daney <ddaney.cavm@gmail.com> wrote:
>
>> On 06/06/2016 10:56 AM, Marc Zyngier wrote:
>> > The ARM architected timer produces level-triggered interrupts (this
>> > is mandated by the architecture). Unfortunately, most device-trees
>> > get this wrong, and expose an edge-triggered interrupt.
>> >
>> > Until now, this wasn't too much an issue, as the programming of the
>> > trigger would fail (the corresponding PPI cannot be reconfigured),
>> > and the kernel would be happy with this. But we're about to change
>> > this, and trust DT a lot if the driver doesn't provide its own
>> > trigger information. In that context, the timer breaks badly.
>> >
>> > While we do need to fix the DTs, there is also some userspace out
>> > there (kvmtool) that generates the same kind of broken DT on the
>> > fly, and that will completely break with newer kernels.
>> >
>> > As a safety measure, and to keep buggy software alive as well as
>> > buying us some time to fix DTs all over the place, let's check
>> > what trigger configuration has been given us by the firmware.
>> > If this is not a level configuration, then we know that the
>> > DT/ACPI configuration is bust, and we pick some defaults which
>> > won't be worse than the existing setup.
>> >
>> > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>>
>>
>> I tried to test this patch, but there is a problem somewhere that I have
>> not yet tracked down.  On Cavium Thunder (gic-v3 based) I have tested
>> with the device tree interrupt type of both 4 and 8 and get the same result:
>>
>>
>> [    0.000000] arm_arch_timer: WARNING: Invalid trigger for IRQ2,
>> assuming level low
>> [    0.000000] arm_arch_timer: WARNING: Please fix your firmware
>> [    0.000000] arm_arch_timer: WARNING: Invalid trigger for IRQ3,
>> assuming level low
>> [    0.000000] arm_arch_timer: WARNING: Please fix your firmware
>> [    0.000000] arm_arch_timer: Architected cp15 timer(s) running at
>> 100.00MHz (phys).
>> [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff
>> max_cycles: 0x171024e7e0, max_idle_ns: 440795205315 ns
>> [    0.000002] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps
>> every 4398046511100ns
>>
>> It could be that the gic-v3 irq mapping code is broken.  I will try to
>> look into it, but there may be other fixes needed before we would
>> consider this patch to be an improvement.
>
> That's because the core kernel has other bugs which are going to be
> addressed in 4.8. So far, we cannot set the trigger of a per-cpu
> interrupt from the device tree, and we end-up with whatever is the
> default (edge). You can put whatever you want in the DT, it will be
> ignored.
>
> This series in preparation of these fixes landing in 4.8, where we'll
> be able to do the right thing, and will start noticing stupid things
> coming from the DT.
Hi Marc,

I also see the same warning that David saw. Can you please cc me when
the bug fix series
is available? I will test it out for X-Gene 1 and will need to change
the interrupt setting for timer
events on X-Gene 2 as well.

Regards,
Duc Dang.

>
> Thanks,
>
>         M.
> --
> Jazz is not dead. It just smells funny.

  parent reply	other threads:[~2016-06-10 21:52 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-06-06 17:56 [PATCH v3 0/2] arm/arm64: Fix architected timer interrupt trigger Marc Zyngier
2016-06-06 17:56 ` Marc Zyngier
2016-06-06 17:56 ` Marc Zyngier
2016-06-06 17:56 ` Marc Zyngier
2016-06-06 17:56 ` [PATCH v3 1/2] clocksource/arm_arch_timer: Force per-CPU interrupt to be level-triggered Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-09 21:10   ` David Daney
2016-06-09 21:10     ` David Daney
2016-06-09 21:10     ` David Daney
2016-06-09 21:10     ` David Daney
2016-06-10  7:29     ` Marc Zyngier
2016-06-10  7:29       ` Marc Zyngier
2016-06-10  7:29       ` Marc Zyngier
2016-06-10  7:29       ` Marc Zyngier
2016-06-10 17:39       ` David Daney
2016-06-10 17:39         ` David Daney
2016-06-10 17:39         ` David Daney
2016-06-10 17:39         ` David Daney
2016-06-11  9:41         ` Marc Zyngier
2016-06-11  9:41           ` Marc Zyngier
2016-06-11  9:41           ` Marc Zyngier
2016-06-11  9:41           ` Marc Zyngier
     [not found]           ` <CANe6Qb_sx8_rRHZG1PR=A+cgxqYTzreZ0rD01X-gtEDb=h1cVQ@mail.gmail.com>
2016-06-12 10:12             ` Marc Zyngier
2016-06-12 10:12               ` Marc Zyngier
2016-06-12 10:12               ` Marc Zyngier
2016-06-12 10:12               ` Marc Zyngier
2016-06-10 21:51       ` Duc Dang [this message]
2016-07-05  4:37         ` Duc Dang
2016-07-05  4:37         ` Duc Dang
2016-06-10 21:51         ` Duc Dang
2016-06-06 17:56 ` [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-06 17:56   ` Marc Zyngier
2016-06-07  7:08   ` Krzysztof Kozlowski
2016-06-07  7:08     ` Krzysztof Kozlowski
2016-06-07  7:08     ` Krzysztof Kozlowski
2016-06-07  7:08     ` Krzysztof Kozlowski
2016-06-07  7:19   ` Michal Simek
2016-06-07  7:19     ` Michal Simek
2016-06-07  7:19     ` Michal Simek
2016-06-07  7:19     ` Michal Simek
2016-06-09 15:05   ` Dinh Nguyen
2016-06-09 15:05     ` Dinh Nguyen
2016-06-09 15:05     ` Dinh Nguyen
2016-06-09 15:05     ` Dinh Nguyen
2016-06-09 15:23   ` Carlo Caione
2016-06-09 15:23     ` Carlo Caione
2016-06-09 15:23     ` Carlo Caione
2016-06-09 15:23     ` Carlo Caione
2016-06-09 18:11   ` David Daney
2016-06-09 18:11     ` David Daney
2016-06-09 18:11     ` David Daney
2016-06-09 18:11     ` David Daney
2016-06-09 21:06     ` David Daney
2016-06-09 21:06       ` David Daney
2016-06-09 21:06       ` David Daney
2016-06-09 21:06       ` David Daney
2016-06-10  7:23       ` Marc Zyngier
2016-06-10  7:23         ` Marc Zyngier
2016-06-10  7:23         ` Marc Zyngier
2016-06-10  7:23         ` Marc Zyngier
2016-06-10 16:50         ` David Daney
2016-06-10 16:50           ` David Daney
2016-06-10 16:50           ` David Daney
2016-06-10 16:50           ` David Daney
2016-06-10 16:56           ` Marc Zyngier
2016-06-10 16:56             ` Marc Zyngier
2016-06-10 16:56             ` Marc Zyngier
2016-06-10 16:56             ` Marc Zyngier
2016-06-10 17:32             ` David Daney
2016-06-10 17:32               ` David Daney
2016-06-10 17:32               ` David Daney
2016-06-10 17:32               ` David Daney
2016-06-11 10:04               ` Marc Zyngier
2016-06-11 10:04                 ` Marc Zyngier
2016-06-11 10:04                 ` Marc Zyngier
2016-06-11 10:04                 ` Marc Zyngier
2016-06-10 21:48   ` Duc Dang
2016-07-05  4:37     ` Duc Dang
2016-07-05  4:37     ` Duc Dang
2016-06-10 21:48     ` Duc Dang

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