* [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10
@ 2017-01-09 11:25 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 02/29] arm: socfpga: arria10: add sdram defines " Chee Tien Fong
` (16 more replies)
0 siblings, 17 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add remaining 3 I2C base addresses for the Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index a7056d4..902c321 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -29,6 +29,9 @@
#define SOCFPGA_MPUL2_ADDRESS 0xfffff000
#define SOCFPGA_I2C0_ADDRESS 0xffc02200
#define SOCFPGA_I2C1_ADDRESS 0xffc02300
+#define SOCFPGA_I2C2_ADDRESS 0xffc02400
+#define SOCFPGA_I2C3_ADDRESS 0xffc02500
+#define SOCFPGA_I2C4_ADDRESS 0xffc02600
#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 02/29] arm: socfpga: arria10: add sdram defines for Arria10
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 03/29] arm: socfpga: arria10: add board files for the Arria10 SoCDK Chee Tien Fong
` (15 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add the structures for the SDRAM controller on Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 ++++++++++++++++++++++++
1 files changed, 380 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
new file mode 100644
index 0000000..0403531
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h
@@ -0,0 +1,380 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _SOCFPGA_SDRAM_A10_H_
+#define _SOCFPGA_SDRAM_A10_H_
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_ecc_hmc {
+ u32 ip_rev_id;
+ u32 _pad_0x4_0x7;
+ u32 ddrioctrl;
+ u32 ddrcalstat;
+ u32 mpr_0beat1;
+ u32 mpr_1beat1;
+ u32 mpr_2beat1;
+ u32 mpr_3beat1;
+ u32 mpr_4beat1;
+ u32 mpr_5beat1;
+ u32 mpr_6beat1;
+ u32 mpr_7beat1;
+ u32 mpr_8beat1;
+ u32 mpr_0beat2;
+ u32 mpr_1beat2;
+ u32 mpr_2beat2;
+ u32 mpr_3beat2;
+ u32 mpr_4beat2;
+ u32 mpr_5beat2;
+ u32 mpr_6beat2;
+ u32 mpr_7beat2;
+ u32 mpr_8beat2;
+ u32 _pad_0x58_0x5f[2];
+ u32 auto_precharge;
+ u32 _pad_0x64_0xff[39];
+ u32 eccctrl;
+ u32 eccctrl2;
+ u32 _pad_0x108_0x10f[2];
+ u32 errinten;
+ u32 errintens;
+ u32 errintenr;
+ u32 intmode;
+ u32 intstat;
+ u32 diaginttest;
+ u32 modstat;
+ u32 derraddra;
+ u32 serraddra;
+ u32 _pad_0x134_0x137;
+ u32 autowb_corraddr;
+ u32 serrcntreg;
+ u32 autowb_drop_cntreg;
+ u32 _pad_0x144_0x147;
+ u32 ecc_reg2wreccdatabus;
+ u32 ecc_rdeccdata2regbus;
+ u32 ecc_reg2rdeccdatabus;
+ u32 _pad_0x154_0x15f[3];
+ u32 ecc_diagon;
+ u32 ecc_decstat;
+ u32 _pad_0x168_0x16f[2];
+ u32 ecc_errgenaddr_0;
+ u32 ecc_errgenaddr_1;
+ u32 ecc_errgenaddr_2;
+ u32 ecc_errgenaddr_3;
+};
+
+struct socfpga_noc_ddr_scheduler {
+ u32 ddr_t_main_scheduler_id_coreid;
+ u32 ddr_t_main_scheduler_id_revisionid;
+ u32 ddr_t_main_scheduler_ddrconf;
+ u32 ddr_t_main_scheduler_ddrtiming;
+ u32 ddr_t_main_scheduler_ddrmode;
+ u32 ddr_t_main_scheduler_readlatency;
+ u32 _pad_0x20_0x34[8];
+ u32 ddr_t_main_scheduler_activate;
+ u32 ddr_t_main_scheduler_devtodev;
+};
+
+/*
+ * OCRAM firewall
+ */
+struct socfpga_noc_fw_ocram {
+ u32 enable;
+ u32 enable_set;
+ u32 enable_clear;
+ u32 region0;
+ u32 region1;
+ u32 region2;
+ u32 region3;
+ u32 region4;
+ u32 region5;
+};
+
+/* for master such as MPU and FPGA */
+struct socfpga_noc_fw_ddr_mpu_fpga2sdram {
+ u32 enable;
+ u32 enable_set;
+ u32 enable_clear;
+ u32 _pad_0xc_0xf;
+ u32 mpuregion0addr;
+ u32 mpuregion1addr;
+ u32 mpuregion2addr;
+ u32 mpuregion3addr;
+ u32 fpga2sdram0region0addr;
+ u32 fpga2sdram0region1addr;
+ u32 fpga2sdram0region2addr;
+ u32 fpga2sdram0region3addr;
+ u32 fpga2sdram1region0addr;
+ u32 fpga2sdram1region1addr;
+ u32 fpga2sdram1region2addr;
+ u32 fpga2sdram1region3addr;
+ u32 fpga2sdram2region0addr;
+ u32 fpga2sdram2region1addr;
+ u32 fpga2sdram2region2addr;
+ u32 fpga2sdram2region3addr;
+};
+
+/* for L3 master */
+struct socfpga_noc_fw_ddr_l3 {
+ u32 enable;
+ u32 enable_set;
+ u32 enable_clear;
+ u32 hpsregion0addr;
+ u32 hpsregion1addr;
+ u32 hpsregion2addr;
+ u32 hpsregion3addr;
+ u32 hpsregion4addr;
+ u32 hpsregion5addr;
+ u32 hpsregion6addr;
+ u32 hpsregion7addr;
+};
+
+struct socfpga_io48_mmr {
+ u32 dbgcfg0;
+ u32 dbgcfg1;
+ u32 dbgcfg2;
+ u32 dbgcfg3;
+ u32 dbgcfg4;
+ u32 dbgcfg5;
+ u32 dbgcfg6;
+ u32 reserve0;
+ u32 reserve1;
+ u32 reserve2;
+ u32 ctrlcfg0;
+ u32 ctrlcfg1;
+ u32 ctrlcfg2;
+ u32 ctrlcfg3;
+ u32 ctrlcfg4;
+ u32 ctrlcfg5;
+ u32 ctrlcfg6;
+ u32 ctrlcfg7;
+ u32 ctrlcfg8;
+ u32 ctrlcfg9;
+ u32 dramtiming0;
+ u32 dramodt0;
+ u32 dramodt1;
+ u32 sbcfg0;
+ u32 sbcfg1;
+ u32 sbcfg2;
+ u32 sbcfg3;
+ u32 sbcfg4;
+ u32 sbcfg5;
+ u32 sbcfg6;
+ u32 sbcfg7;
+ u32 caltiming0;
+ u32 caltiming1;
+ u32 caltiming2;
+ u32 caltiming3;
+ u32 caltiming4;
+ u32 caltiming5;
+ u32 caltiming6;
+ u32 caltiming7;
+ u32 caltiming8;
+ u32 caltiming9;
+ u32 caltiming10;
+ u32 dramaddrw;
+ u32 sideband0;
+ u32 sideband1;
+ u32 sideband2;
+ u32 sideband3;
+ u32 sideband4;
+ u32 sideband5;
+ u32 sideband6;
+ u32 sideband7;
+ u32 sideband8;
+ u32 sideband9;
+ u32 sideband10;
+ u32 sideband11;
+ u32 sideband12;
+ u32 sideband13;
+ u32 sideband14;
+ u32 sideband15;
+ u32 dramsts;
+ u32 dbgdone;
+ u32 dbgsignals;
+ u32 dbgreset;
+ u32 dbgmatch;
+ u32 counter0mask;
+ u32 counter1mask;
+ u32 counter0match;
+ u32 counter1match;
+ u32 niosreserve0;
+ u32 niosreserve1;
+ u32 niosreserve2;
+};
+#endif /*__ASSEMBLY__*/
+
+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F000000
+#define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_SHIFT 24
+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_MASK 0x00F80000
+#define IO48_MMR_CTRLCFG0_DB1_BURST_LENGTH_SHIFT 19
+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_MASK 0x0007C000
+#define IO48_MMR_CTRLCFG0_DB0_BURST_LENGTH_SHIFT 14
+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK 0x00003E00
+#define IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT 9
+#define IO48_MMR_CTRLCFG0_AC_POS_MASK 0x00000180
+#define IO48_MMR_CTRLCFG0_AC_POS_SHIFT 7
+#define IO48_MMR_CTRLCFG0_DIMM_TYPE_MASK 0x00000070
+#define IO48_MMR_CTRLCFG0_DIM_TYPE_SHIFT 4
+#define IO48_MMR_CTRLCFG0_MEM_TYPE_MASK 0x0000000F
+#define IO48_MMR_CTRLCFG0_MEM_TYPE_SHIFT 0
+
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM (1 << 30)
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM (1 << 29)
+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM (1 << 28)
+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM (1 << 27)
+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_DM (1 << 26)
+#define IO48_MMR_CTRLCFG1_DQSTRK_EN (1 << 25)
+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_MASK 0x01F80000
+#define IO48_MMR_CTRLCFG1_STARVE_LIMIT_SHIFT 19
+#define IO48_MMR_CTRLCFG1_REORDER_READ (1 << 18)
+#define IO48_MMR_CTRLCFG1_DBC3_REORDER_RDATA (1 << 17)
+#define IO48_MMR_CTRLCFG1_DBC2_REORDER_RDATA (1 << 16)
+#define IO48_MMR_CTRLCFG1_DBC1_REORDER_RDATA (1 << 15)
+#define IO48_MMR_CTRLCFG1_DBC0_REORDER_RDATA (1 << 14)
+#define IO48_MMR_CTRLCFG1_CTRL_REORDER_RDATA (1 << 13)
+#define IO48_MMR_CTRLCFG1_REORDER_DATA (1 << 12)
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_ECC (1 << 11)
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_ECC (1 << 10)
+#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_ECC (1 << 9)
+#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_ECC (1 << 8)
+#define IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC (1 << 7)
+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK 0x00000060
+#define IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT 5
+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_MASK 0x0000001F
+#define IO48_MMR_CTRLCFG1_DBC3_BURST_LENGTH_SHIFT 0
+
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_MASK 0x3F000000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BG_SHIFT 24
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK 0x00FC0000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT 18
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK 0x0003F000
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT 12
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_MASK 0x00000FC0
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_PCH_SHIFT 6
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK 0x0000003F
+#define IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_SHIFT 0
+
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK 0x3F000000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT 24
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK 0x00FC0000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT 18
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_MASK 0x0003F000
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DB_SHIFT 12
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK 0x00000FC0
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT 6
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_MASK 0x0000003F
+#define IO48_MMR_CALTIMING1_CFG_RD_TO_RD_SHIFT 0
+
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_MASK 0x3F000000
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_DIFF_CHIP_SHIFT 24
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_MASK 0x00FC0000
+#define IO48_MMR_CALTIMING2_CFG_WR_TO_WR_SHIFT 18
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_MASK 0x0003F000
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_AP_VALID_SHIFT 12
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK 0x00000FC0
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT 6
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_MASK 0x0000003F
+#define IO48_MMR_CALTIMING2_CFG_RD_TO_WR_DIFF_BG_SHIFT 0
+
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_MASK 0x3F000000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_PCH_SHIFT 24
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_MASK 0x00FC0000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_BG_SHIFT 18
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK 0x0003F000
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT 12
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK 0x00000FC0
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT 6
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_MASK 0x0000003F
+#define IO48_MMR_CALTIMING3_CFG_WR_TO_WR_DIFF_BG_SHIFT 0
+
+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_MASK 0xFC000000
+#define IO48_MMR_CALTIMING4_CFG_PDN_TO_VALID_SHIFT 26
+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_MASK 0x03FC0000
+#define IO48_MMR_CALTIMING4_CFG_ARF_TO_VALID_SHIFT 18
+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_MASK 0x0003F000
+#define IO48_MMR_CALTIMING4_CFG_PCH_ALL_TO_VALID_SHIFT 12
+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK 0x00000FC0
+#define IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT 6
+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_MASK 0x0000003F
+#define IO48_MMR_CALTIMING4_CFG_WR_AP_TO_VALID_SHIFT 0
+
+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK 0x000000FF
+#define IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_SHIFT 0
+
+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK 0x00070000
+#define IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT 16
+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK 0x0000C000
+#define IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT 14
+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK 0x00003C00
+#define IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT 10
+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK 0x000003E0
+#define IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT 5
+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK 0x0000001F
+#define IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SHIFT 0
+
+#define ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
+
+#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK 0x00000001
+#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK 0x00000002
+#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
+#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK 0x00000002
+#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK 0x00010000
+#define ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK 0x00010000
+#define ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK 0x00000100
+#define ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK 0x00000001
+#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK 0x00000100
+#define ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK 0x00000001
+
+#define ALT_ECC_HMC_OCP_SERRCNTREG_VALUE 8
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
+#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1
+
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4
+#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10
+
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2
+#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4
+
+#define ALT_NOC_FW_DDR_END_ADDR_LSB 16
+#define ALT_NOC_FW_DDR_ADDR_MASK 0xFFFF
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK 0x00000001
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK 0x00000002
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK 0x00000004
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK 0x00000008
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK 0x00000010
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK 0x00000020
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK 0x00000040
+#define ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK 0x00000080
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK 0x00000001
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK 0x00000002
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK 0x00000004
+#define ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK 0x00000008
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK 0x00000010
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK 0x00000020
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK 0x00000040
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK 0x00000080
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK 0x00000100
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK 0x00000200
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK 0x00000400
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK 0x00000800
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK 0x00001000
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK 0x00002000
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK 0x00004000
+#define ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK 0x00008000
+
+#define ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK 0x0000003F
+#endif /* _SOCFPGA_SDRAM_A10_H_ */
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 03/29] arm: socfpga: arria10: add board files for the Arria10 SoCDK
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 02/29] arm: socfpga: arria10: add sdram defines " Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 04/29] arm: socfpga: arria10: add system manager defines Chee Tien Fong
` (14 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add minimal support for the Arria10 SoCDK.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
board/altera/arria10-socdk/Kconfig | 18 ++++++++++++++++++
board/altera/arria10-socdk/Makefile | 7 +++++++
board/altera/arria10-socdk/socfpga.c | 24 ++++++++++++++++++++++++
3 files changed, 49 insertions(+), 0 deletions(-)
create mode 100644 board/altera/arria10-socdk/Kconfig
create mode 100644 board/altera/arria10-socdk/Makefile
create mode 100644 board/altera/arria10-socdk/socfpga.c
diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig
new file mode 100644
index 0000000..b80cc6d
--- /dev/null
+++ b/board/altera/arria10-socdk/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_SOCFPGA_ARRIA10
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_BOARD
+ default "socfpga_arria10"
+
+config SYS_VENDOR
+ default "altera"
+
+config SYS_SOC
+ default "socfpga_arria10"
+
+config SYS_CONFIG_NAME
+ default "socfpga_arria10"
+
+endif
diff --git a/board/altera/arria10-socdk/Makefile b/board/altera/arria10-socdk/Makefile
new file mode 100644
index 0000000..1d885ce
--- /dev/null
+++ b/board/altera/arria10-socdk/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y := socfpga.o
diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c
new file mode 100644
index 0000000..abedc22
--- /dev/null
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+ /* Address of boot parameters for ATAG (if ATAG is used) */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 04/29] arm: socfpga: arria10: add system manager defines
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 02/29] arm: socfpga: arria10: add sdram defines " Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 03/29] arm: socfpga: arria10: add board files for the Arria10 SoCDK Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 05/29] arm: socfpga: arria10: add misc functions for Arria10 Chee Tien Fong
` (13 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add system manager defines for Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
.../arm/mach-socfpga/include/mach/system_manager.h | 122 ++++++++++++++++++++
1 files changed, 122 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index c45edea..e688c50 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
#endif
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
u32 _pad_0x734;
u32 spim0usefpga; /* 0x738 */
};
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+ u32 siliconid1;
+ u32 siliconid2;
+ u32 wddbg;
+ u32 bootinfo;
+ u32 mpu_ctrl_l2_ecc;
+ u32 _pad_0x14_0x1f[3];
+ u32 dma;
+ u32 dma_periph;
+ u32 sdmmcgrp_ctrl;
+ u32 sdmmc_l3master;
+ u32 nand_bootstrap;
+ u32 nand_l3master;
+ u32 usb0_l3master;
+ u32 usb1_l3master;
+ u32 emac_global;
+ u32 emac0;
+ u32 emac1;
+ u32 emac2;
+ u32 _pad_0x50_0x5f[4];
+ u32 fpgaintf_en_global;
+ u32 fpgaintf_en_0;
+ u32 fpgaintf_en_1;
+ u32 fpgaintf_en_2;
+ u32 fpgaintf_en_3;
+ u32 _pad_0x74_0x7f[3];
+ u32 noc_addr_remap_value;
+ u32 noc_addr_remap_set;
+ u32 noc_addr_remap_clear;
+ u32 _pad_0x8c_0x8f;
+ u32 ecc_intmask_value;
+ u32 ecc_intmask_set;
+ u32 ecc_intmask_clr;
+ u32 ecc_intstatus_serr;
+ u32 ecc_intstatus_derr;
+ u32 mpu_status_l2_ecc;
+ u32 mpu_clear_l2_ecc;
+ u32 mpu_status_l1_parity;
+ u32 mpu_clear_l1_parity;
+ u32 mpu_set_l1_parity;
+ u32 _pad_0xb8_0xbf[2];
+ u32 noc_timeout;
+ u32 noc_idlereq_set;
+ u32 noc_idlereq_clr;
+ u32 noc_idlereq_value;
+ u32 noc_idleack;
+ u32 noc_idlestatus;
+ u32 fpga2soc_ctrl;
+ u32 _pad_0xdc_0xff[9];
+ u32 tsmc_tsel_0;
+ u32 tsmc_tsel_1;
+ u32 tsmc_tsel_2;
+ u32 tsmc_tsel_3;
+ u32 _pad_0x110_0x200[60];
+ u32 romhw_ctrl;
+ u32 romcode_ctrl;
+ u32 romcode_cpu1startaddr;
+ u32 romcode_initswstate;
+ u32 romcode_initswlastld;
+ u32 _pad_0x214_0x217;
+ u32 warmram_enable;
+ u32 warmram_datastart;
+ u32 warmram_length;
+ u32 warmram_execution;
+ u32 warmram_crc;
+ u32 _pad_0x22c_0x22f;
+ u32 isw_handoff[8];
+ u32 romcode_bootromswstate[8];
+};
+#endif
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0)
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1)
@@ -146,4 +218,54 @@ struct socfpga_system_manager {
#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V 0x0
+#define VOLTAGE_SEL_1P8V 0x1
+#define VOLTAGE_SEL_2P5V 0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE 0
+#define INPUT_BUF_1P8V 1
+#define INPUT_BUF_2P5V3V 2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE 0
+#define WK_PU_ENABLE 1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW 0
+#define PU_SLW_RT_FAST 1
+#define PU_SLW_RT_DEFAULT PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW 0
+#define PD_SLW_RT_FAST 1
+#define PD_SLW_RT_DEFAULT PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT 0x10
+#define PD_DRV_STRG_DEFAULT 0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB 0
+#define PD_SLW_RT_LSB 5
+#define PU_DRV_STRG_LSB 8
+#define PU_SLW_RT_LSB 13
+#define WK_PU_LSB 16
+#define INPUT_BUF_LSB 17
+#define BIAS_TRIM_LSB 19
+#define VOLTAGE_SEL_LSB 0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK 0x00000001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK 0x00000010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK 0x00000100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK 0x00010000
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK 0x00100000
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK 0x01000000
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x00000001
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x00000002
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x00000002
+
#endif /* _SYSTEM_MANAGER_H_ */
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 05/29] arm: socfpga: arria10: add misc functions for Arria10
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (2 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 04/29] arm: socfpga: arria10: add system manager defines Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 06/29] arm: socfpga: arria10: add socfpga_arria10_socdk config Chee Tien Fong
` (12 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
arch/arm/mach-socfpga/misc.c | 51 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 51 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index dd6b53b..c1e5969 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
#include <watchdog.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram_a10.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
@@ -30,8 +31,15 @@ static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct socfpga_reset_manager *reset_manager_base =
(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#else
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+ (void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+ (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
@@ -253,9 +261,14 @@ static int socfpga_fpga_id(const bool print_id)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
puts("CPU: Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
+#else
+ const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> 12) & 0x7;
+ puts("CPU: Altera SoCFPGA Arria 10\n");
+#endif
printf("BOOT: %s\n", bsel_str[bsel].name);
return 0;
}
@@ -338,6 +351,7 @@ int arch_cpu_init(void)
return 0;
}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/*
* Convert all NIC-301 AMBA slaves from secure to non-secure
*/
@@ -461,6 +475,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
}
+#else
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+ /* Put OCRAM in non-secure */
+ writel(0x003f0000, &noc_fw_ocram_base->region0);
+ writel(0x1, &noc_fw_ocram_base->enable);
+
+ /* Put DDR in non-secure */
+ writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr);
+ writel(0x1, &noc_fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+ initialize_security_policies();
+
+ /* Configure the L2 controller to make SDRAM start at 0 */
+ writel(0x1, &pl310->pl310_addr_filter_start);
+
+ /* assert reset to all except L4WD0 and L4TIMER0 */
+ socfpga_per_reset_all();
+
+ /* configuring the clock based on handoff */
+ /* TODO: Add call to cm_basic_init() */
+
+ /* Add device descriptor to FPGA device table */
+ socfpga_fpga_add();
+ return 0;
+}
+#endif
U_BOOT_CMD(
bridge, 2, 1, do_bridge,
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 06/29] arm: socfpga: arria10: add socfpga_arria10_socdk config
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (3 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 05/29] arm: socfpga: arria10: add misc functions for Arria10 Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 07/29] arm: socfpga: arria10: add socfpga_arria10_defconfig Chee Tien Fong
` (11 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add config for the Arria10 SoC Development Kit.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
include/configs/socfpga_arria10_socdk.h | 94 +++++++++++++++++++++++++++++++
1 files changed, 94 insertions(+), 0 deletions(-)
create mode 100644 include/configs/socfpga_arria10_socdk.h
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 0000000..577f60f
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include <asm/arch/base_addr_a10.h>
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE 0x2000000
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "zImage"
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR 0x01000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
+#define CONFIG_ENV_OFFSET 512/* just after the MBR */
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "verify=n\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "bootimage=zImage\0" \
+ "fdt_addr=100\0" \
+ "fdtimage=socfpga.dtb\0" \
+ "fsloadcmd=ext2load\0" \
+ "bootm ${loadaddr} - ${fdt_addr}\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootz ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootimage};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "qspiroot=/dev/mtdblock0\0" \
+ "qspirootfstype=jffs2\0" \
+ "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+ "bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+#endif /* __CONFIG_H */
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 07/29] arm: socfpga: arria10: add socfpga_arria10_defconfig
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (4 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 06/29] arm: socfpga: arria10: add socfpga_arria10_socdk config Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 08/29] arm: socfpga: arria10: add config option build for arria10 Chee Tien Fong
` (10 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add a defconfig file for Arria10, which does not include enabling SPL.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
configs/socfpga_arria10_defconfig | 24 ++++++++++++++++++++++++
1 files changed, 24 insertions(+), 0 deletions(-)
create mode 100644 configs/socfpga_arria10_defconfig
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
new file mode 100644
index 0000000..755bb66
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,24 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SYS_NS16550=y
+CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 08/29] arm: socfpga: arria10: add config option build for arria10
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (5 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 07/29] arm: socfpga: arria10: add socfpga_arria10_defconfig Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 09/29] arm: socfpga: add define for bootinfo bsel bit shift Chee Tien Fong
` (9 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
arch/arm/Kconfig | 4 ++--
arch/arm/mach-socfpga/Kconfig | 10 ++++++++++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0ed36cd..80c5992 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,9 +561,9 @@ config ARCH_SNAPDRAGON
config ARCH_SOCFPGA
bool "Altera SOCFPGA family"
select CPU_V7
- select SUPPORT_SPL
+ select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
select OF_CONTROL
- select SPL_OF_CONTROL
+ select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
select DM
select DM_SPI_FLASH
select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 6991af8..d9a5178 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -31,6 +31,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
+config TARGET_SOCFPGA_ARRIA10
+ bool
+
config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -50,6 +53,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+ bool "Altera SOCFPGA SoCDK (Arria 10)"
+ select TARGET_SOCFPGA_ARRIA10
+
config TARGET_SOCFPGA_DENX_MCVEVK
bool "DENX MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -86,6 +93,7 @@ endchoice
config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -98,6 +106,7 @@ config SYS_BOARD
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -111,6 +120,7 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 09/29] arm: socfpga: add define for bootinfo bsel bit shift
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (6 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 08/29] arm: socfpga: arria10: add config option build for arria10 Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 10/29] arm: socfpga: arria10: add reset manager for Arria10 Chee Tien Fong
` (8 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
.../arm/mach-socfpga/include/mach/system_manager.h | 2 ++
arch/arm/mach-socfpga/misc.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e688c50..9ca889a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -203,8 +203,10 @@ struct socfpga_system_manager {
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
#else
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
#endif
#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c1e5969..2645129 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -261,12 +261,12 @@ static int socfpga_fpga_id(const bool print_id)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
+ const u32 bsel = (readl(&sysmgr_regs->bootinfo) >>
+ SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
- const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
puts("CPU: Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
#else
- const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> 12) & 0x7;
puts("CPU: Altera SoCFPGA Arria 10\n");
#endif
printf("BOOT: %s\n", bsel_str[bsel].name);
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 10/29] arm: socfpga: arria10: add reset manager for Arria10
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (7 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 09/29] arm: socfpga: add define for bootinfo bsel bit shift Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 11/29] arm: socfpga: wrap system manager functions for A5/C5 devices Chee Tien Fong
` (7 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++++++++++++++++++++
arch/arm/mach-socfpga/reset_manager.c | 24 +++++++-
2 files changed, 88 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 2f070f2..6225118 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
};
+#else
+struct socfpga_reset_manager {
+ u32 stat;
+ u32 ramstat;
+ u32 miscstat;
+ u32 ctrl;
+ u32 hdsken;
+ u32 hdskreq;
+ u32 hdskack;
+ u32 counts;
+ u32 mpu_mod_reset;
+ u32 per_mod_reset; /* stated as per0_mod_reset in A10 datasheet */
+ u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+ u32 brg_mod_reset;
+ u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+ u32 coldmodrst;
+ u32 nrstmodrst;
+ u32 dbgmodrst;
+ u32 mpuwarmmask;
+ u32 per0warmmask;
+ u32 per1warmmask;
+ u32 brgwarmmask;
+ u32 syswarmmask;
+ u32 nrstwarmmask;
+ u32 l3warmmask;
+ u32 tststa;
+ u32 tstscratch;
+ u32 hdsktimeout;
+ u32 hmcintr;
+ u32 hmcintren;
+ u32 hmcintrens;
+ u32 hmcintrenr;
+ u32 hmcgpout;
+ u32 hmcgpin;
+};
+#endif
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
#define RSTMGR_BANK(_reset) \
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/*
* SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
* 0 ... mpumodrst
@@ -75,6 +113,33 @@ struct socfpga_reset_manager {
#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
+#endif
/* Create a human-readable reference to SoCFPGA reset. */
#define SOCFPGA_RESET(_name) RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base =
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
void socfpga_per_reset(u32 reset, int set)
{
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
* Assert reset on every peripheral but L4WD0.
* Watchdog must be kept intact to prevent glitches
* and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
*/
void socfpga_per_reset_all(void)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
writel(~l4wd0, &reset_manager_base->per_mod_reset);
writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+#else
+ const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
+ (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
+
+ unsigned mask_ecc_ocp = 0x0000FF00;
+
+ /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+ writel(~l4wd0, &reset_manager_base->per1_mod_reset);
+ setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp);
+
+ /* Finally disable the ECC_OCP */
+ setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp);
+#endif
}
/*
@@ -71,6 +89,7 @@ void reset_cpu(ulong addr)
;
}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/*
* Release peripherals from reset based on handoff
*/
@@ -78,6 +97,7 @@ void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per_mod_reset);
}
+#endif
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
void socfpga_bridges_reset(int enable)
@@ -92,6 +112,7 @@ void socfpga_bridges_reset(int enable)
void socfpga_bridges_reset(int enable)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
L3REGS_REMAP_HPS2FPGA_MASK |
L3REGS_REMAP_OCRAM_MASK;
@@ -116,5 +137,6 @@ void socfpga_bridges_reset(int enable)
/* Remap the bridges into memory map */
writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
}
+#endif
}
#endif
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 11/29] arm: socfpga: wrap system manager functions for A5/C5 devices
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (8 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 10/29] arm: socfpga: arria10: add reset manager for Arria10 Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 12/29] arm: socfpga: arria10: don't build GEN5 sdram for arria10 Chee Tien Fong
` (6 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
The system manager on Arria10 is not used for pin muxing duties, so wrap
these functions for GEN5 devices only.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
arch/arm/mach-socfpga/system_manager.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c
index 75a65f3..9e1c3fd 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -19,6 +19,7 @@ static struct socfpga_system_manager *sysmgr_regs =
* The value is not wrote to SYSMGR.FPGAINTF.MODULE but
* CONFIG_SYSMGR_ISWGRP_HANDOFF.
*/
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
static void populate_sysmgr_fpgaintf_module(void)
{
uint32_t handoff_val = 0;
@@ -83,3 +84,4 @@ void sysmgr_config_warmrstcfgio(int enable)
clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
}
+#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 12/29] arm: socfpga: arria10: don't build GEN5 sdram for arria10
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (9 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 11/29] arm: socfpga: wrap system manager functions for A5/C5 devices Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 13/29] arm: socfpga: arria10 fpga does not have bridges mapped Chee Tien Fong
` (5 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
The Arria10 device will not be able to re-use the GEN5 SDRAM controller,
so we shouldn't build the driver. Move CONFIG_ALTERA_SDRAM to Kconfig
option in drivers/ddr/altera/Kconfig.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
drivers/Kconfig | 2 ++
drivers/ddr/Kconfig | 1 +
drivers/ddr/altera/Kconfig | 6 ++++++
include/configs/socfpga_common.h | 5 -----
4 files changed, 9 insertions(+), 5 deletions(-)
create mode 100644 drivers/ddr/Kconfig
create mode 100644 drivers/ddr/altera/Kconfig
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 0e5d97d..3e6bbac 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
source "drivers/crypto/Kconfig"
+source "drivers/ddr/Kconfig"
+
source "drivers/demo/Kconfig"
source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644
index 0000000..b764add
--- /dev/null
+++ b/drivers/ddr/Kconfig
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644
index 0000000..9554da7
--- /dev/null
+++ b/drivers/ddr/altera/Kconfig
@@ -0,0 +1,6 @@
+config ALTERA_SDRAM
+ bool "SoCFPGA SDRAM for Arria5/Cyclone5 devices"
+ default y if TARGET_SOCFPGA_GEN5
+ help
+ This is for building the SDRAM controller for the Arria5/Cyclone5
+ devices.
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 31f1338..bbbde1e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -77,11 +77,6 @@
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
-/*
* EPCS/EPCQx1 Serial Flash Controller
*/
#ifdef CONFIG_ALTERA_SPI
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 13/29] arm: socfpga: arria10 fpga does not have bridges mapped
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (10 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 12/29] arm: socfpga: arria10: don't build GEN5 sdram for arria10 Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 14/29] arm: socfpga: arria10: remove board_init and s_init Chee Tien Fong
` (4 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
On the Arria10 device, the bridges are not mapped through the interconnect.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
drivers/fpga/socfpga.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index f1b2f2c..bfefafd 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -278,8 +278,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset(1);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Unmap the bridges from NIC-301 */
writel(0x1, SOCFPGA_L3REGS_ADDRESS);
+#endif
/* Initialize the FPGA Manager */
status = fpgamgr_program_init();
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 14/29] arm: socfpga: arria10: remove board_init and s_init
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (11 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 13/29] arm: socfpga: arria10 fpga does not have bridges mapped Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 15/29] arm: socfpga: combine clrbits/setbits into a single clrsetbits Chee Tien Fong
` (3 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
These functions are already in arch/arm/mach-socfpga/board.c
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
board/altera/arria10-socdk/socfpga.c | 17 -----------------
1 files changed, 0 insertions(+), 17 deletions(-)
diff --git a/board/altera/arria10-socdk/socfpga.c b/board/altera/arria10-socdk/socfpga.c
index abedc22..8516633 100644
--- a/board/altera/arria10-socdk/socfpga.c
+++ b/board/altera/arria10-socdk/socfpga.c
@@ -5,20 +5,3 @@
*/
#include <common.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void s_init(void)
-{
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-int board_init(void)
-{
- /* Address of boot parameters for ATAG (if ATAG is used) */
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- return 0;
-}
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 15/29] arm: socfpga: combine clrbits/setbits into a single clrsetbits
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (12 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 14/29] arm: socfpga: arria10: remove board_init and s_init Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 16/29] arm: socfpga: add reset manager defines for Arria10 Chee Tien Fong
` (2 subsequent siblings)
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
There is no dependency on doing a separate clrbits first in the
dwmac_deassert_reset function. Combine them into a single
clrsetbits call.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
arch/arm/mach-socfpga/misc.c | 9 +++------
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 2645129..c97caea 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id,
return;
}
- /* Clearing emac0 PHY interface select to 0 */
- clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
-
/* configure to PHY interface select choosed */
- setbits_le32(&sysmgr_regs->emacgrp_ctrl,
- phymode << physhift);
+ clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
+ SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
+ phymode << physhift);
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 16/29] arm: socfpga: add reset manager defines for Arria10
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (13 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 15/29] arm: socfpga: combine clrbits/setbits into a single clrsetbits Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 17/29] arm: socfpga: arria10: update dwmac reset function to support Arria10 Chee Tien Fong
2017-01-09 12:43 ` [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Marek Vasut
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add the Arria10 reset manager defines that is used in Linux. Change the
license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 ++++++++++++++++++++++++++
1 files changed, 103 insertions(+), 0 deletions(-)
create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h
diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 0000000..7619ca2
--- /dev/null
+++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET 2
+#define SCUPER_RESET 3
+
+/* PER0MODRST */
+#define EMAC0_RESET 32
+#define EMAC1_RESET 33
+#define EMAC2_RESET 34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET 39
+#define EMAC0_OCP_RESET 40
+#define EMAC1_OCP_RESET 41
+#define EMAC2_OCP_RESET 42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET 47
+#define DMA_RESET 48
+#define SPIM0_RESET 49
+#define SPIM1_RESET 50
+#define SPIS0_RESET 51
+#define SPIS1_RESET 52
+#define DMA_OCP_RESET 53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET 56
+#define DMAIF1_RESET 57
+#define DMAIF2_RESET 58
+#define DMAIF3_RESET 59
+#define DMAIF4_RESET 60
+#define DMAIF5_RESET 61
+#define DMAIF6_RESET 62
+#define DMAIF7_RESET 63
+
+/* PER1MODRST */
+#define L4WD0_RESET 64
+#define L4WD1_RESET 65
+#define L4SYSTIMER0_RESET 66
+#define L4SYSTIMER1_RESET 67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET 80
+#define UART1_RESET 81
+/* 82-87 is reserved */
+#define GPIO0_RESET 88
+#define GPIO1_RESET 89
+#define GPIO2_RESET 90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET 97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET 99
+#define F2SSDRAM1_RESET 100
+#define F2SSDRAM2_RESET 101
+#define DDRSCH_RESET 102
+
+/* SYSMODRST*/
+#define ROM_RESET 128
+#define OCRAM_RESET 129
+/* 130 is reserved */
+#define FPGAMGR_RESET 131
+#define S2F_RESET 132
+#define SYSDBG_RESET 133
+#define OCRAM_OCP_RESET 134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET 160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET 163
+#define TIMESTAMPCOLD_RESET 164
+#define TAPCOLD_RESET 165
+#define HMCCOLD_RESET 166
+#define IOMGRCOLD_RESET 167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET 192
+
+/* DBGMODRST */
+#define DBG_RESET 224
+#endif
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 17/29] arm: socfpga: arria10: update dwmac reset function to support Arria10
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (14 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 16/29] arm: socfpga: add reset manager defines for Arria10 Chee Tien Fong
@ 2017-01-09 11:25 ` Chee Tien Fong
2017-01-09 12:43 ` [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Marek Vasut
16 siblings, 0 replies; 21+ messages in thread
From: Chee Tien Fong @ 2017-01-09 11:25 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
On the Arria10, the EMAC phy mode configuration for each EMACs is located
in separate registers versus being in 1 register for the GEN5 devices. The
Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset function to support both GEN5 and Arria10
devices.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
.../arm/mach-socfpga/include/mach/system_manager.h | 4 +---
arch/arm/mach-socfpga/misc.c | 14 ++++++++++++++
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 9ca889a..831ba4a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -133,9 +133,7 @@ struct socfpga_system_manager {
u32 usb0_l3master;
u32 usb1_l3master;
u32 emac_global;
- u32 emac0;
- u32 emac1;
- u32 emac2;
+ u32 emac[3];
u32 _pad_0x50_0x5f[4];
u32 fpgaintf_en_global;
u32 fpgaintf_en_0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index c97caea..510aa1d 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -21,7 +21,11 @@
#include <asm/arch/scu.h>
#include <asm/pl310.h>
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <dt-bindings/reset/altr,rst-mgr.h>
+#else
+#include <dt-bindings/reset/altr,rst-mgr-a10.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id,
} else if (of_reset_id == EMAC1_RESET) {
physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
reset = SOCFPGA_RESET(EMAC1);
+#ifndef CONFIG_TARGET_SOCFPGA_GEN5
+ } else if (of_reset_id == EMAC2_RESET) {
+ reset = SOCFPGA_RESET(EMAC2);
+#endif
} else {
printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
return;
}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* configure to PHY interface select choosed */
clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl,
SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift,
phymode << physhift);
+#else
+ clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET],
+ SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
+ phymode);
+#endif
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
--
1.7.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
` (15 preceding siblings ...)
2017-01-09 11:25 ` [U-Boot] [v4 17/29] arm: socfpga: arria10: update dwmac reset function to support Arria10 Chee Tien Fong
@ 2017-01-09 12:43 ` Marek Vasut
2017-01-09 16:54 ` Dinh Nguyen
2017-01-10 3:37 ` Chee, Tien Fong
16 siblings, 2 replies; 21+ messages in thread
From: Marek Vasut @ 2017-01-09 12:43 UTC (permalink / raw)
To: u-boot
On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> Add remaining 3 I2C base addresses for the Arria10.
>
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Reviewed-by: Stefan Roese <sr@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Tien Fong <skywindctf@gmail.com>
Please, just use git send-email to send the whole series. Don't drop the
PATCH from the subject or anything. I am ignoring this series until it's
sent properly.
> ---
> arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> index a7056d4..902c321 100644
> --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> @@ -29,6 +29,9 @@
> #define SOCFPGA_MPUL2_ADDRESS 0xfffff000
> #define SOCFPGA_I2C0_ADDRESS 0xffc02200
> #define SOCFPGA_I2C1_ADDRESS 0xffc02300
> +#define SOCFPGA_I2C2_ADDRESS 0xffc02400
> +#define SOCFPGA_I2C3_ADDRESS 0xffc02500
> +#define SOCFPGA_I2C4_ADDRESS 0xffc02600
>
> #define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
> #define SOCFPGA_UART0_ADDRESS 0xffc02000
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10
2017-01-09 12:43 ` [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Marek Vasut
@ 2017-01-09 16:54 ` Dinh Nguyen
2017-01-10 3:05 ` Chee, Tien Fong
2017-01-10 3:37 ` Chee, Tien Fong
1 sibling, 1 reply; 21+ messages in thread
From: Dinh Nguyen @ 2017-01-09 16:54 UTC (permalink / raw)
To: u-boot
On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut <marex@denx.de> wrote:
> On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>
>> Add remaining 3 I2C base addresses for the Arria10.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> Reviewed-by: Stefan Roese <sr@denx.de>
>> Cc: Marek Vasut <marex@denx.de>
>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>> Cc: Chin Liang See <chin.liang.see@intel.com>
>> Cc: Tien Fong <skywindctf@gmail.com>
>
> Please, just use git send-email to send the whole series. Don't drop the
> PATCH from the subject or anything. I am ignoring this series until it's
> sent properly.
>
Also, can I ask why the revision bump to v4? Please give reviewers time to
review such a big change set before bumping the rev when most of the
patches haven't been reviewed yet.
Dinh
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10
2017-01-09 16:54 ` Dinh Nguyen
@ 2017-01-10 3:05 ` Chee, Tien Fong
0 siblings, 0 replies; 21+ messages in thread
From: Chee, Tien Fong @ 2017-01-10 3:05 UTC (permalink / raw)
To: u-boot
On Isn, 2017-01-09 at 10:54 -0600, Dinh Nguyen wrote:
> On Mon, Jan 9, 2017 at 6:43 AM, Marek Vasut <marex@denx.de> wrote:
> >
> > On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> > >
> > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > >
> > > Add remaining 3 I2C base addresses for the Arria10.
> > >
> > > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > Reviewed-by: Stefan Roese <sr@denx.de>
> > > Cc: Marek Vasut <marex@denx.de>
> > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > Cc: Tien Fong <skywindctf@gmail.com>
> > Please, just use git send-email to send the whole series. Don't
> > drop the
> > PATCH from the subject or anything. I am ignoring this series until
> > it's
> > sent properly.
> >
Hi, i dind't drop any patch, this is rev4 with changes suggested from
Dinh which is merging the patch21 into patch7.
> Also, can I ask why the revision bump to v4? Please give reviewers
> time to
> review such a big change set before bumping the rev when most of the
> patches haven't been reviewed yet.
>
> Dinh
Ohh....we thought that if reviewer has comment on any patch, some
reviewers might waiting next revision then only review.
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10
2017-01-09 12:43 ` [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Marek Vasut
2017-01-09 16:54 ` Dinh Nguyen
@ 2017-01-10 3:37 ` Chee, Tien Fong
1 sibling, 0 replies; 21+ messages in thread
From: Chee, Tien Fong @ 2017-01-10 3:37 UTC (permalink / raw)
To: u-boot
On Isn, 2017-01-09 at 13:43 +0100, Marek Vasut wrote:
> On 01/09/2017 12:25 PM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Add remaining 3 I2C base addresses for the Arria10.
> >
> > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > Reviewed-by: Stefan Roese <sr@denx.de>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > Cc: Chin Liang See <chin.liang.see@intel.com>
> > Cc: Tien Fong <skywindctf@gmail.com>
> Please, just use git send-email to send the whole series. Don't drop
> the
> PATCH from the subject or anything. I am ignoring this series until
> it's
> sent properly.
>
Ahh....i catched what you means. I was used --subject-prefix when -v
was not working. Well, i would try again.
> >
> > ---
> > ?arch/arm/mach-socfpga/include/mach/base_addr_a10.h |????3 +++
> > ?1 files changed, 3 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > index a7056d4..902c321 100644
> > --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > @@ -29,6 +29,9 @@
> > ?#define SOCFPGA_MPUL2_ADDRESS 0xfffff000
> > ?#define SOCFPGA_I2C0_ADDRESS 0xffc02200
> > ?#define SOCFPGA_I2C1_ADDRESS 0xffc02300
> > +#define SOCFPGA_I2C2_ADDRESS 0xffc02400
> > +#define SOCFPGA_I2C3_ADDRESS 0xffc02500
> > +#define SOCFPGA_I2C4_ADDRESS 0xffc02600
> > ?
> > ?#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
> > ?#define SOCFPGA_UART0_ADDRESS 0xffc02000
> >
>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2017-01-10 3:37 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-09 11:25 [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 02/29] arm: socfpga: arria10: add sdram defines " Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 03/29] arm: socfpga: arria10: add board files for the Arria10 SoCDK Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 04/29] arm: socfpga: arria10: add system manager defines Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 05/29] arm: socfpga: arria10: add misc functions for Arria10 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 06/29] arm: socfpga: arria10: add socfpga_arria10_socdk config Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 07/29] arm: socfpga: arria10: add socfpga_arria10_defconfig Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 08/29] arm: socfpga: arria10: add config option build for arria10 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 09/29] arm: socfpga: add define for bootinfo bsel bit shift Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 10/29] arm: socfpga: arria10: add reset manager for Arria10 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 11/29] arm: socfpga: wrap system manager functions for A5/C5 devices Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 12/29] arm: socfpga: arria10: don't build GEN5 sdram for arria10 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 13/29] arm: socfpga: arria10 fpga does not have bridges mapped Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 14/29] arm: socfpga: arria10: remove board_init and s_init Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 15/29] arm: socfpga: combine clrbits/setbits into a single clrsetbits Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 16/29] arm: socfpga: add reset manager defines for Arria10 Chee Tien Fong
2017-01-09 11:25 ` [U-Boot] [v4 17/29] arm: socfpga: arria10: update dwmac reset function to support Arria10 Chee Tien Fong
2017-01-09 12:43 ` [U-Boot] [v4 01/29] arm: socfpga: arria10: add additional i2c nodes for Arria10 Marek Vasut
2017-01-09 16:54 ` Dinh Nguyen
2017-01-10 3:05 ` Chee, Tien Fong
2017-01-10 3:37 ` Chee, Tien Fong
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