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* [PATCH 1/3] drm/amdgpu: refine vce2.0 dpm sequence
@ 2017-03-13  8:51 Rex Zhu
       [not found] ` <1489395082-30583-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  0 siblings, 1 reply; 4+ messages in thread
From: Rex Zhu @ 2017-03-13  8:51 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

first start vce then enable vce dpm.

Change-Id: I8f5da7caca3184ce65962df9bb3d3162b5a0528a
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index adaa9ca..716c22d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1315,11 +1315,11 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 			/* XXX select vce level based on ring/task */
 			adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
 			mutex_unlock(&adev->pm.mutex);
-			amdgpu_pm_compute_clocks(adev);
-			amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
-							AMD_PG_STATE_UNGATE);
 			amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 							AMD_CG_STATE_UNGATE);
+			amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
+							AMD_PG_STATE_UNGATE);
+			amdgpu_pm_compute_clocks(adev);
 		} else {
 			amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
 							AMD_PG_STATE_GATE);
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 2/3] drm/amd/powerplay: fix copy error in smu7_clockpoweragting.c
       [not found] ` <1489395082-30583-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-03-13  8:51   ` Rex Zhu
  2017-03-13  8:51   ` [PATCH 3/3] drm/amdgpu: refine vce_3.0 code Rex Zhu
  1 sibling, 0 replies; 4+ messages in thread
From: Rex Zhu @ 2017-03-13  8:51 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

Change-Id: I0e41fdb2df794dcbe4c508e9a71dd60612430482
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
index 8cf71f3..261b828 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c
@@ -178,7 +178,7 @@ int smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
 	if (bgate) {
 		cgs_set_powergating_state(hwmgr->device,
 						AMD_IP_BLOCK_TYPE_VCE,
-						AMD_PG_STATE_UNGATE);
+						AMD_PG_STATE_GATE);
 		cgs_set_clockgating_state(hwmgr->device,
 				AMD_IP_BLOCK_TYPE_VCE,
 				AMD_CG_STATE_GATE);
-- 
1.9.1

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH 3/3] drm/amdgpu: refine vce_3.0 code.
       [not found] ` <1489395082-30583-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  2017-03-13  8:51   ` [PATCH 2/3] drm/amd/powerplay: fix copy error in smu7_clockpoweragting.c Rex Zhu
@ 2017-03-13  8:51   ` Rex Zhu
       [not found]     ` <1489395082-30583-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
  1 sibling, 1 reply; 4+ messages in thread
From: Rex Zhu @ 2017-03-13  8:51 UTC (permalink / raw)
  To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Rex Zhu

fix logic error in hw_fini and
set_clockgating_state functions.

Change-Id: I1e3f241f300b3c561df695b38b19c7a89160db25
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 5705e81..97ff9ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -65,7 +65,8 @@
 static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
 static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
 static int vce_v3_0_wait_for_idle(void *handle);
-
+static int vce_v3_0_set_clockgating_state(void *handle,
+					  enum amd_clockgating_state state);
 /**
  * vce_v3_0_ring_get_rptr - get read pointer
  *
@@ -305,12 +306,8 @@ static int vce_v3_0_stop(struct amdgpu_device *adev)
 		/* hold on ECPU */
 		WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
 
-		/* clear BUSY flag */
-		WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);
-
-		/* Set Clock-Gating off */
-		if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
-			vce_v3_0_set_vce_sw_clock_gating(adev, false);
+		/* clear VCE STATUS */
+		WREG32(mmVCE_STATUS, 0);
 	}
 
 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
@@ -461,7 +458,8 @@ static int vce_v3_0_hw_fini(void *handle)
 	if (r)
 		return r;
 
-	return vce_v3_0_stop(adev);
+	vce_v3_0_stop(adev);
+	return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
 }
 
 static int vce_v3_0_suspend(void *handle)
@@ -728,7 +726,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
 
 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));
 
-		if (enable) {
+		if (!enable) {
 			/* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */
 			uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);
 			data &= ~(0xf | 0xff0);
-- 
1.9.1

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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH 3/3] drm/amdgpu: refine vce_3.0 code.
       [not found]     ` <1489395082-30583-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2017-03-13 14:54       ` Alex Deucher
  0 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2017-03-13 14:54 UTC (permalink / raw)
  To: Rex Zhu; +Cc: amd-gfx list

On Mon, Mar 13, 2017 at 4:51 AM, Rex Zhu <Rex.Zhu@amd.com> wrote:
> fix logic error in hw_fini and
> set_clockgating_state functions.
>
> Change-Id: I1e3f241f300b3c561df695b38b19c7a89160db25
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>


> ---
>  drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 16 +++++++---------
>  1 file changed, 7 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 5705e81..97ff9ad 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -65,7 +65,8 @@
>  static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
>  static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
>  static int vce_v3_0_wait_for_idle(void *handle);
> -
> +static int vce_v3_0_set_clockgating_state(void *handle,
> +                                         enum amd_clockgating_state state);
>  /**
>   * vce_v3_0_ring_get_rptr - get read pointer
>   *
> @@ -305,12 +306,8 @@ static int vce_v3_0_stop(struct amdgpu_device *adev)
>                 /* hold on ECPU */
>                 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1);
>
> -               /* clear BUSY flag */
> -               WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0);
> -
> -               /* Set Clock-Gating off */
> -               if (adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)
> -                       vce_v3_0_set_vce_sw_clock_gating(adev, false);
> +               /* clear VCE STATUS */
> +               WREG32(mmVCE_STATUS, 0);
>         }
>
>         WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
> @@ -461,7 +458,8 @@ static int vce_v3_0_hw_fini(void *handle)
>         if (r)
>                 return r;
>
> -       return vce_v3_0_stop(adev);
> +       vce_v3_0_stop(adev);
> +       return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
>  }
>
>  static int vce_v3_0_suspend(void *handle)
> @@ -728,7 +726,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
>
>                 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));
>
> -               if (enable) {
> +               if (!enable) {
>                         /* initialize VCE_CLOCK_GATING_A: Clock ON/OFF delay */
>                         uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);
>                         data &= ~(0xf | 0xff0);
> --
> 1.9.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-03-13 14:54 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2017-03-13  8:51 [PATCH 1/3] drm/amdgpu: refine vce2.0 dpm sequence Rex Zhu
     [not found] ` <1489395082-30583-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-03-13  8:51   ` [PATCH 2/3] drm/amd/powerplay: fix copy error in smu7_clockpoweragting.c Rex Zhu
2017-03-13  8:51   ` [PATCH 3/3] drm/amdgpu: refine vce_3.0 code Rex Zhu
     [not found]     ` <1489395082-30583-3-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2017-03-13 14:54       ` Alex Deucher

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