* Re: [PATCH] drm/amdgpu: Fix inconsistent indenting
@ 2021-05-21 13:35 ` Christian König
0 siblings, 0 replies; 9+ messages in thread
From: Christian König @ 2021-05-21 13:35 UTC (permalink / raw)
To: Jiapeng Chong, alexander.deucher
Cc: airlied, Xinhui.Pan, linux-kernel, amd-gfx, christian.koenig,
linaro-mm-sig, dri-devel, daniel, sumit.semwal, linux-media
Am 21.05.21 um 11:50 schrieb Jiapeng Chong:
> Eliminate the follow smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
> sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
>
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 75d7310..c45e1b0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
> */
> static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
> {
> - uint32_t gcr_cntl =
> - SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> - SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> - SDMA_GCR_GLI_INV(1);
> + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> + SDMA_GCR_GLI_INV(1);
>
> /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
> amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
> amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
> amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> - SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> + SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> - SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> + SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> - SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> + SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> }
>
> /**
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/amdgpu: Fix inconsistent indenting
@ 2021-05-21 13:35 ` Christian König
0 siblings, 0 replies; 9+ messages in thread
From: Christian König @ 2021-05-21 13:35 UTC (permalink / raw)
To: Jiapeng Chong, alexander.deucher
Cc: airlied, Xinhui.Pan, linux-kernel, amd-gfx, christian.koenig,
linaro-mm-sig, dri-devel, linux-media
Am 21.05.21 um 11:50 schrieb Jiapeng Chong:
> Eliminate the follow smatch warning:
>
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
> sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
>
> Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 75d7310..c45e1b0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
> */
> static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
> {
> - uint32_t gcr_cntl =
> - SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> - SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> - SDMA_GCR_GLI_INV(1);
> + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> + SDMA_GCR_GLI_INV(1);
>
> /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
> amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
> amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
> amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> - SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> + SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> - SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> + SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> - SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> + SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> }
>
> /**
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/amdgpu: Fix inconsistent indenting
2021-05-21 13:35 ` Christian König
(?)
@ 2021-05-21 20:57 ` Alex Deucher
-1 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2021-05-21 20:57 UTC (permalink / raw)
To: Christian König
Cc: Jiapeng Chong, Deucher, Alexander, Dave Airlie, xinhui pan, LKML,
amd-gfx list, Christian Koenig,
moderated list:DMA BUFFER SHARING FRAMEWORK,
Maling list - DRI developers, Daniel Vetter, Sumit Semwal,
linux-media
Applied. Thanks!
Alex
On Fri, May 21, 2021 at 9:35 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 21.05.21 um 11:50 schrieb Jiapeng Chong:
> > Eliminate the follow smatch warning:
> >
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
> > sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
> >
> > Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> > Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
>
> Reviewed-by: Christian König <christian.koenig@amd.com>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++++++-------
> > 1 file changed, 6 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > index 75d7310..c45e1b0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > @@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
> > */
> > static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
> > {
> > - uint32_t gcr_cntl =
> > - SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> > - SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> > - SDMA_GCR_GLI_INV(1);
> > + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> > + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> > + SDMA_GCR_GLI_INV(1);
> >
> > /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
> > amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> > + SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> > + SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> > + SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> > }
> >
> > /**
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/amdgpu: Fix inconsistent indenting
@ 2021-05-21 20:57 ` Alex Deucher
0 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2021-05-21 20:57 UTC (permalink / raw)
To: Christian König
Cc: Jiapeng Chong, Dave Airlie, xinhui pan, LKML, amd-gfx list,
Sumit Semwal, moderated list:DMA BUFFER SHARING FRAMEWORK,
Maling list - DRI developers, Daniel Vetter, Deucher, Alexander,
Christian Koenig, linux-media
Applied. Thanks!
Alex
On Fri, May 21, 2021 at 9:35 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 21.05.21 um 11:50 schrieb Jiapeng Chong:
> > Eliminate the follow smatch warning:
> >
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
> > sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
> >
> > Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> > Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
>
> Reviewed-by: Christian König <christian.koenig@amd.com>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++++++-------
> > 1 file changed, 6 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > index 75d7310..c45e1b0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > @@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
> > */
> > static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
> > {
> > - uint32_t gcr_cntl =
> > - SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> > - SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> > - SDMA_GCR_GLI_INV(1);
> > + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> > + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> > + SDMA_GCR_GLI_INV(1);
> >
> > /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
> > amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> > + SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> > + SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> > + SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> > }
> >
> > /**
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH] drm/amdgpu: Fix inconsistent indenting
@ 2021-05-21 20:57 ` Alex Deucher
0 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2021-05-21 20:57 UTC (permalink / raw)
To: Christian König
Cc: Jiapeng Chong, Dave Airlie, xinhui pan, LKML, amd-gfx list,
moderated list:DMA BUFFER SHARING FRAMEWORK,
Maling list - DRI developers, Deucher, Alexander,
Christian Koenig, linux-media
Applied. Thanks!
Alex
On Fri, May 21, 2021 at 9:35 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Am 21.05.21 um 11:50 schrieb Jiapeng Chong:
> > Eliminate the follow smatch warning:
> >
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449
> > sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting.
> >
> > Reported-by: Abaci Robot <abaci@linux.alibaba.com>
> > Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
>
> Reviewed-by: Christian König <christian.koenig@amd.com>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++++++-------
> > 1 file changed, 6 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > index 75d7310..c45e1b0 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> > @@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
> > */
> > static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
> > {
> > - uint32_t gcr_cntl =
> > - SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> > - SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> > - SDMA_GCR_GLI_INV(1);
> > + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> > + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> > + SDMA_GCR_GLI_INV(1);
> >
> > /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
> > amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> > + SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> > + SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
> > amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
> > - SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> > + SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
> > }
> >
> > /**
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread